?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86/topology: Fix function name in documentation
[cris-mirror.git] / drivers / usb / dwc3 / core.c
blobade2ab00d37ab1255a168b5f5e8d0911c1051a2f
1 // SPDX-License-Identifier: GPL-2.0
2 /**
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/version.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/spinlock.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/interrupt.h>
19 #include <linux/ioport.h>
20 #include <linux/io.h>
21 #include <linux/list.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/of.h>
25 #include <linux/acpi.h>
26 #include <linux/pinctrl/consumer.h>
27
28 #include <linux/usb/ch9.h>
29 #include <linux/usb/gadget.h>
30 #include <linux/usb/of.h>
31 #include <linux/usb/otg.h>
32
33 #include "core.h"
34 #include "gadget.h"
35 #include "io.h"
36
37 #include "debug.h"
38
39 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
40
41 /**
42 * dwc3_get_dr_mode - Validates and sets dr_mode
43 * @dwc: pointer to our context structure
44 */
45 static int dwc3_get_dr_mode(struct dwc3 *dwc)
46 {
47 enum usb_dr_mode mode;
48 struct device *dev = dwc->dev;
49 unsigned int hw_mode;
50
51 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
52 dwc->dr_mode = USB_DR_MODE_OTG;
53
54 mode = dwc->dr_mode;
55 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
56
57 switch (hw_mode) {
58 case DWC3_GHWPARAMS0_MODE_GADGET:
59 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
60 dev_err(dev,
61 "Controller does not support host mode.\n");
62 return -EINVAL;
63 }
64 mode = USB_DR_MODE_PERIPHERAL;
65 break;
66 case DWC3_GHWPARAMS0_MODE_HOST:
67 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
68 dev_err(dev,
69 "Controller does not support device mode.\n");
70 return -EINVAL;
71 }
72 mode = USB_DR_MODE_HOST;
73 break;
74 default:
75 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
76 mode = USB_DR_MODE_HOST;
77 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
78 mode = USB_DR_MODE_PERIPHERAL;
79 }
80
81 if (mode != dwc->dr_mode) {
82 dev_warn(dev,
83 "Configuration mismatch. dr_mode forced to %s\n",
84 mode == USB_DR_MODE_HOST ? "host" : "gadget");
85
86 dwc->dr_mode = mode;
87 }
88
89 return 0;
90 }
91
92 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
93 static int dwc3_event_buffers_setup(struct dwc3 *dwc);
94
95 static void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
96 {
97 u32 reg;
98
99 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
100 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
101 reg |= DWC3_GCTL_PRTCAPDIR(mode);
102 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
103 }
104
105 static void __dwc3_set_mode(struct work_struct *work)
106 {
107 struct dwc3 *dwc = work_to_dwc(work);
108 unsigned long flags;
109 int ret;
110
111 if (!dwc->desired_dr_role)
112 return;
113
114 if (dwc->desired_dr_role == dwc->current_dr_role)
115 return;
116
117 if (dwc->dr_mode != USB_DR_MODE_OTG)
118 return;
119
120 switch (dwc->current_dr_role) {
121 case DWC3_GCTL_PRTCAP_HOST:
122 dwc3_host_exit(dwc);
123 break;
124 case DWC3_GCTL_PRTCAP_DEVICE:
125 dwc3_gadget_exit(dwc);
126 dwc3_event_buffers_cleanup(dwc);
127 break;
128 default:
129 break;
130 }
131
132 spin_lock_irqsave(&dwc->lock, flags);
133
134 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
135
136 dwc->current_dr_role = dwc->desired_dr_role;
137
138 spin_unlock_irqrestore(&dwc->lock, flags);
139
140 switch (dwc->desired_dr_role) {
141 case DWC3_GCTL_PRTCAP_HOST:
142 ret = dwc3_host_init(dwc);
143 if (ret) {
144 dev_err(dwc->dev, "failed to initialize host\n");
145 } else {
146 if (dwc->usb2_phy)
147 otg_set_vbus(dwc->usb2_phy->otg, true);
148 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
149 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
150 phy_calibrate(dwc->usb2_generic_phy);
151 }
152 break;
153 case DWC3_GCTL_PRTCAP_DEVICE:
154 dwc3_event_buffers_setup(dwc);
155
156 if (dwc->usb2_phy)
157 otg_set_vbus(dwc->usb2_phy->otg, false);
158 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
159 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
160
161 ret = dwc3_gadget_init(dwc);
162 if (ret)
163 dev_err(dwc->dev, "failed to initialize peripheral\n");
164 break;
165 default:
166 break;
167 }
168 }
169
170 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
171 {
172 unsigned long flags;
173
174 spin_lock_irqsave(&dwc->lock, flags);
175 dwc->desired_dr_role = mode;
176 spin_unlock_irqrestore(&dwc->lock, flags);
177
178 queue_work(system_power_efficient_wq, &dwc->drd_work);
179 }
180
181 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
182 {
183 struct dwc3 *dwc = dep->dwc;
184 u32 reg;
185
186 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
187 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
188 DWC3_GDBGFIFOSPACE_TYPE(type));
189
190 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
191
192 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
193 }
194
195 /**
196 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
197 * @dwc: pointer to our context structure
198 */
199 static int dwc3_core_soft_reset(struct dwc3 *dwc)
200 {
201 u32 reg;
202 int retries = 1000;
203 int ret;
204
205 usb_phy_init(dwc->usb2_phy);
206 usb_phy_init(dwc->usb3_phy);
207 ret = phy_init(dwc->usb2_generic_phy);
208 if (ret < 0)
209 return ret;
210
211 ret = phy_init(dwc->usb3_generic_phy);
212 if (ret < 0) {
213 phy_exit(dwc->usb2_generic_phy);
214 return ret;
215 }
216
217 /*
218 * We're resetting only the device side because, if we're in host mode,
219 * XHCI driver will reset the host block. If dwc3 was configured for
220 * host-only mode, then we can return early.
221 */
222 if (dwc->dr_mode == USB_DR_MODE_HOST)
223 return 0;
224
225 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
226 reg |= DWC3_DCTL_CSFTRST;
227 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
228
229 do {
230 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
231 if (!(reg & DWC3_DCTL_CSFTRST))
232 return 0;
233
234 udelay(1);
235 } while (--retries);
236
237 return -ETIMEDOUT;
238 }
239
240 /*
241 * dwc3_frame_length_adjustment - Adjusts frame length if required
242 * @dwc3: Pointer to our controller context structure
243 */
244 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
245 {
246 u32 reg;
247 u32 dft;
248
249 if (dwc->revision < DWC3_REVISION_250A)
250 return;
251
252 if (dwc->fladj == 0)
253 return;
254
255 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
256 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
257 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
258 "request value same as default, ignoring\n")) {
259 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
260 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
261 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
262 }
263 }
264
265 /**
266 * dwc3_free_one_event_buffer - Frees one event buffer
267 * @dwc: Pointer to our controller context structure
268 * @evt: Pointer to event buffer to be freed
269 */
270 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
271 struct dwc3_event_buffer *evt)
272 {
273 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
274 }
275
276 /**
277 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
278 * @dwc: Pointer to our controller context structure
279 * @length: size of the event buffer
280 *
281 * Returns a pointer to the allocated event buffer structure on success
282 * otherwise ERR_PTR(errno).
283 */
284 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
285 unsigned length)
286 {
287 struct dwc3_event_buffer *evt;
288
289 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
290 if (!evt)
291 return ERR_PTR(-ENOMEM);
292
293 evt->dwc = dwc;
294 evt->length = length;
295 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
296 if (!evt->cache)
297 return ERR_PTR(-ENOMEM);
298
299 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
300 &evt->dma, GFP_KERNEL);
301 if (!evt->buf)
302 return ERR_PTR(-ENOMEM);
303
304 return evt;
305 }
306
307 /**
308 * dwc3_free_event_buffers - frees all allocated event buffers
309 * @dwc: Pointer to our controller context structure
310 */
311 static void dwc3_free_event_buffers(struct dwc3 *dwc)
312 {
313 struct dwc3_event_buffer *evt;
314
315 evt = dwc->ev_buf;
316 if (evt)
317 dwc3_free_one_event_buffer(dwc, evt);
318 }
319
320 /**
321 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
322 * @dwc: pointer to our controller context structure
323 * @length: size of event buffer
324 *
325 * Returns 0 on success otherwise negative errno. In the error case, dwc
326 * may contain some buffers allocated but not all which were requested.
327 */
328 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
329 {
330 struct dwc3_event_buffer *evt;
331
332 evt = dwc3_alloc_one_event_buffer(dwc, length);
333 if (IS_ERR(evt)) {
334 dev_err(dwc->dev, "can't allocate event buffer\n");
335 return PTR_ERR(evt);
336 }
337 dwc->ev_buf = evt;
338
339 return 0;
340 }
341
342 /**
343 * dwc3_event_buffers_setup - setup our allocated event buffers
344 * @dwc: pointer to our controller context structure
345 *
346 * Returns 0 on success otherwise negative errno.
347 */
348 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
349 {
350 struct dwc3_event_buffer *evt;
351
352 evt = dwc->ev_buf;
353 evt->lpos = 0;
354 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
355 lower_32_bits(evt->dma));
356 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
357 upper_32_bits(evt->dma));
358 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
359 DWC3_GEVNTSIZ_SIZE(evt->length));
360 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
361
362 return 0;
363 }
364
365 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
366 {
367 struct dwc3_event_buffer *evt;
368
369 evt = dwc->ev_buf;
370
371 evt->lpos = 0;
372
373 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
374 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
375 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
376 | DWC3_GEVNTSIZ_SIZE(0));
377 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
378 }
379
380 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
381 {
382 if (!dwc->has_hibernation)
383 return 0;
384
385 if (!dwc->nr_scratch)
386 return 0;
387
388 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
389 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
390 if (!dwc->scratchbuf)
391 return -ENOMEM;
392
393 return 0;
394 }
395
396 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
397 {
398 dma_addr_t scratch_addr;
399 u32 param;
400 int ret;
401
402 if (!dwc->has_hibernation)
403 return 0;
404
405 if (!dwc->nr_scratch)
406 return 0;
407
408 /* should never fall here */
409 if (!WARN_ON(dwc->scratchbuf))
410 return 0;
411
412 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
413 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
414 DMA_BIDIRECTIONAL);
415 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
416 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
417 ret = -EFAULT;
418 goto err0;
419 }
420
421 dwc->scratch_addr = scratch_addr;
422
423 param = lower_32_bits(scratch_addr);
424
425 ret = dwc3_send_gadget_generic_command(dwc,
426 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
427 if (ret < 0)
428 goto err1;
429
430 param = upper_32_bits(scratch_addr);
431
432 ret = dwc3_send_gadget_generic_command(dwc,
433 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
434 if (ret < 0)
435 goto err1;
436
437 return 0;
438
439 err1:
440 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
441 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
442
443 err0:
444 return ret;
445 }
446
447 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
448 {
449 if (!dwc->has_hibernation)
450 return;
451
452 if (!dwc->nr_scratch)
453 return;
454
455 /* should never fall here */
456 if (!WARN_ON(dwc->scratchbuf))
457 return;
458
459 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
460 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
461 kfree(dwc->scratchbuf);
462 }
463
464 static void dwc3_core_num_eps(struct dwc3 *dwc)
465 {
466 struct dwc3_hwparams *parms = &dwc->hwparams;
467
468 dwc->num_eps = DWC3_NUM_EPS(parms);
469 }
470
471 static void dwc3_cache_hwparams(struct dwc3 *dwc)
472 {
473 struct dwc3_hwparams *parms = &dwc->hwparams;
474
475 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
476 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
477 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
478 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
479 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
480 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
481 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
482 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
483 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
484 }
485
486 /**
487 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
488 * @dwc: Pointer to our controller context structure
489 *
490 * Returns 0 on success. The USB PHY interfaces are configured but not
491 * initialized. The PHY interfaces and the PHYs get initialized together with
492 * the core in dwc3_core_init.
493 */
494 static int dwc3_phy_setup(struct dwc3 *dwc)
495 {
496 u32 reg;
497 int ret;
498
499 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
500
501 /*
502 * Make sure UX_EXIT_PX is cleared as that causes issues with some
503 * PHYs. Also, this bit is not supposed to be used in normal operation.
504 */
505 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
506
507 /*
508 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
509 * to '0' during coreConsultant configuration. So default value
510 * will be '0' when the core is reset. Application needs to set it
511 * to '1' after the core initialization is completed.
512 */
513 if (dwc->revision > DWC3_REVISION_194A)
514 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
515
516 if (dwc->u2ss_inp3_quirk)
517 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
518
519 if (dwc->dis_rxdet_inp3_quirk)
520 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
521
522 if (dwc->req_p1p2p3_quirk)
523 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
524
525 if (dwc->del_p1p2p3_quirk)
526 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
527
528 if (dwc->del_phy_power_chg_quirk)
529 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
530
531 if (dwc->lfps_filter_quirk)
532 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
533
534 if (dwc->rx_detect_poll_quirk)
535 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
536
537 if (dwc->tx_de_emphasis_quirk)
538 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
539
540 if (dwc->dis_u3_susphy_quirk)
541 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
542
543 if (dwc->dis_del_phy_power_chg_quirk)
544 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
545
546 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
547
548 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
549
550 /* Select the HS PHY interface */
551 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
552 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
553 if (dwc->hsphy_interface &&
554 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
555 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
556 break;
557 } else if (dwc->hsphy_interface &&
558 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
559 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
560 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
561 } else {
562 /* Relying on default value. */
563 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
564 break;
565 }
566 /* FALLTHROUGH */
567 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
568 ret = dwc3_ulpi_init(dwc);
569 if (ret)
570 return ret;
571 /* FALLTHROUGH */
572 default:
573 break;
574 }
575
576 switch (dwc->hsphy_mode) {
577 case USBPHY_INTERFACE_MODE_UTMI:
578 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
579 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
580 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
581 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
582 break;
583 case USBPHY_INTERFACE_MODE_UTMIW:
584 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
585 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
586 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
587 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
588 break;
589 default:
590 break;
591 }
592
593 /*
594 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
595 * '0' during coreConsultant configuration. So default value will
596 * be '0' when the core is reset. Application needs to set it to
597 * '1' after the core initialization is completed.
598 */
599 if (dwc->revision > DWC3_REVISION_194A)
600 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
601
602 if (dwc->dis_u2_susphy_quirk)
603 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
604
605 if (dwc->dis_enblslpm_quirk)
606 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
607
608 if (dwc->dis_u2_freeclk_exists_quirk)
609 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
610
611 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
612
613 return 0;
614 }
615
616 static void dwc3_core_exit(struct dwc3 *dwc)
617 {
618 dwc3_event_buffers_cleanup(dwc);
619
620 usb_phy_shutdown(dwc->usb2_phy);
621 usb_phy_shutdown(dwc->usb3_phy);
622 phy_exit(dwc->usb2_generic_phy);
623 phy_exit(dwc->usb3_generic_phy);
624
625 usb_phy_set_suspend(dwc->usb2_phy, 1);
626 usb_phy_set_suspend(dwc->usb3_phy, 1);
627 phy_power_off(dwc->usb2_generic_phy);
628 phy_power_off(dwc->usb3_generic_phy);
629 }
630
631 static bool dwc3_core_is_valid(struct dwc3 *dwc)
632 {
633 u32 reg;
634
635 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
636
637 /* This should read as U3 followed by revision number */
638 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
639 /* Detected DWC_usb3 IP */
640 dwc->revision = reg;
641 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
642 /* Detected DWC_usb31 IP */
643 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
644 dwc->revision |= DWC3_REVISION_IS_DWC31;
645 } else {
646 return false;
647 }
648
649 return true;
650 }
651
652 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
653 {
654 u32 hwparams4 = dwc->hwparams.hwparams4;
655 u32 reg;
656
657 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
658 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
659
660 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
661 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
662 /**
663 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
664 * issue which would cause xHCI compliance tests to fail.
665 *
666 * Because of that we cannot enable clock gating on such
667 * configurations.
668 *
669 * Refers to:
670 *
671 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
672 * SOF/ITP Mode Used
673 */
674 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
675 dwc->dr_mode == USB_DR_MODE_OTG) &&
676 (dwc->revision >= DWC3_REVISION_210A &&
677 dwc->revision <= DWC3_REVISION_250A))
678 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
679 else
680 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
681 break;
682 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
683 /* enable hibernation here */
684 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
685
686 /*
687 * REVISIT Enabling this bit so that host-mode hibernation
688 * will work. Device-mode hibernation is not yet implemented.
689 */
690 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
691 break;
692 default:
693 /* nothing */
694 break;
695 }
696
697 /* check if current dwc3 is on simulation board */
698 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
699 dev_info(dwc->dev, "Running with FPGA optmizations\n");
700 dwc->is_fpga = true;
701 }
702
703 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
704 "disable_scramble cannot be used on non-FPGA builds\n");
705
706 if (dwc->disable_scramble_quirk && dwc->is_fpga)
707 reg |= DWC3_GCTL_DISSCRAMBLE;
708 else
709 reg &= ~DWC3_GCTL_DISSCRAMBLE;
710
711 if (dwc->u2exit_lfps_quirk)
712 reg |= DWC3_GCTL_U2EXIT_LFPS;
713
714 /*
715 * WORKAROUND: DWC3 revisions <1.90a have a bug
716 * where the device can fail to connect at SuperSpeed
717 * and falls back to high-speed mode which causes
718 * the device to enter a Connect/Disconnect loop
719 */
720 if (dwc->revision < DWC3_REVISION_190A)
721 reg |= DWC3_GCTL_U2RSTECN;
722
723 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
724 }
725
726 static int dwc3_core_get_phy(struct dwc3 *dwc);
727
728 /**
729 * dwc3_core_init - Low-level initialization of DWC3 Core
730 * @dwc: Pointer to our controller context structure
731 *
732 * Returns 0 on success otherwise negative errno.
733 */
734 static int dwc3_core_init(struct dwc3 *dwc)
735 {
736 u32 reg;
737 int ret;
738
739 if (!dwc3_core_is_valid(dwc)) {
740 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
741 ret = -ENODEV;
742 goto err0;
743 }
744
745 /*
746 * Write Linux Version Code to our GUID register so it's easy to figure
747 * out which kernel version a bug was found.
748 */
749 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
750
751 /* Handle USB2.0-only core configuration */
752 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
753 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
754 if (dwc->maximum_speed == USB_SPEED_SUPER)
755 dwc->maximum_speed = USB_SPEED_HIGH;
756 }
757
758 ret = dwc3_core_get_phy(dwc);
759 if (ret)
760 goto err0;
761
762 ret = dwc3_core_soft_reset(dwc);
763 if (ret)
764 goto err0;
765
766 ret = dwc3_phy_setup(dwc);
767 if (ret)
768 goto err0;
769
770 dwc3_core_setup_global_control(dwc);
771 dwc3_core_num_eps(dwc);
772
773 ret = dwc3_setup_scratch_buffers(dwc);
774 if (ret)
775 goto err1;
776
777 /* Adjust Frame Length */
778 dwc3_frame_length_adjustment(dwc);
779
780 usb_phy_set_suspend(dwc->usb2_phy, 0);
781 usb_phy_set_suspend(dwc->usb3_phy, 0);
782 ret = phy_power_on(dwc->usb2_generic_phy);
783 if (ret < 0)
784 goto err2;
785
786 ret = phy_power_on(dwc->usb3_generic_phy);
787 if (ret < 0)
788 goto err3;
789
790 ret = dwc3_event_buffers_setup(dwc);
791 if (ret) {
792 dev_err(dwc->dev, "failed to setup event buffers\n");
793 goto err4;
794 }
795
796 /*
797 * ENDXFER polling is available on version 3.10a and later of
798 * the DWC_usb3 controller. It is NOT available in the
799 * DWC_usb31 controller.
800 */
801 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
802 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
803 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
804 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
805 }
806
807 if (dwc->revision >= DWC3_REVISION_250A) {
808 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
809
810 /*
811 * Enable hardware control of sending remote wakeup
812 * in HS when the device is in the L1 state.
813 */
814 if (dwc->revision >= DWC3_REVISION_290A)
815 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
816
817 if (dwc->dis_tx_ipgap_linecheck_quirk)
818 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
819
820 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
821 }
822
823 return 0;
824
825 err4:
826 phy_power_off(dwc->usb3_generic_phy);
827
828 err3:
829 phy_power_off(dwc->usb2_generic_phy);
830
831 err2:
832 usb_phy_set_suspend(dwc->usb2_phy, 1);
833 usb_phy_set_suspend(dwc->usb3_phy, 1);
834
835 err1:
836 usb_phy_shutdown(dwc->usb2_phy);
837 usb_phy_shutdown(dwc->usb3_phy);
838 phy_exit(dwc->usb2_generic_phy);
839 phy_exit(dwc->usb3_generic_phy);
840
841 err0:
842 return ret;
843 }
844
845 static int dwc3_core_get_phy(struct dwc3 *dwc)
846 {
847 struct device *dev = dwc->dev;
848 struct device_node *node = dev->of_node;
849 int ret;
850
851 if (node) {
852 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
853 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
854 } else {
855 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
856 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
857 }
858
859 if (IS_ERR(dwc->usb2_phy)) {
860 ret = PTR_ERR(dwc->usb2_phy);
861 if (ret == -ENXIO || ret == -ENODEV) {
862 dwc->usb2_phy = NULL;
863 } else if (ret == -EPROBE_DEFER) {
864 return ret;
865 } else {
866 dev_err(dev, "no usb2 phy configured\n");
867 return ret;
868 }
869 }
870
871 if (IS_ERR(dwc->usb3_phy)) {
872 ret = PTR_ERR(dwc->usb3_phy);
873 if (ret == -ENXIO || ret == -ENODEV) {
874 dwc->usb3_phy = NULL;
875 } else if (ret == -EPROBE_DEFER) {
876 return ret;
877 } else {
878 dev_err(dev, "no usb3 phy configured\n");
879 return ret;
880 }
881 }
882
883 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
884 if (IS_ERR(dwc->usb2_generic_phy)) {
885 ret = PTR_ERR(dwc->usb2_generic_phy);
886 if (ret == -ENOSYS || ret == -ENODEV) {
887 dwc->usb2_generic_phy = NULL;
888 } else if (ret == -EPROBE_DEFER) {
889 return ret;
890 } else {
891 dev_err(dev, "no usb2 phy configured\n");
892 return ret;
893 }
894 }
895
896 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
897 if (IS_ERR(dwc->usb3_generic_phy)) {
898 ret = PTR_ERR(dwc->usb3_generic_phy);
899 if (ret == -ENOSYS || ret == -ENODEV) {
900 dwc->usb3_generic_phy = NULL;
901 } else if (ret == -EPROBE_DEFER) {
902 return ret;
903 } else {
904 dev_err(dev, "no usb3 phy configured\n");
905 return ret;
906 }
907 }
908
909 return 0;
910 }
911
912 static int dwc3_core_init_mode(struct dwc3 *dwc)
913 {
914 struct device *dev = dwc->dev;
915 int ret;
916
917 switch (dwc->dr_mode) {
918 case USB_DR_MODE_PERIPHERAL:
919 dwc->current_dr_role = DWC3_GCTL_PRTCAP_DEVICE;
920 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
921
922 if (dwc->usb2_phy)
923 otg_set_vbus(dwc->usb2_phy->otg, false);
924 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
925 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
926
927 ret = dwc3_gadget_init(dwc);
928 if (ret) {
929 if (ret != -EPROBE_DEFER)
930 dev_err(dev, "failed to initialize gadget\n");
931 return ret;
932 }
933 break;
934 case USB_DR_MODE_HOST:
935 dwc->current_dr_role = DWC3_GCTL_PRTCAP_HOST;
936 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
937
938 if (dwc->usb2_phy)
939 otg_set_vbus(dwc->usb2_phy->otg, true);
940 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
941 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
942
943 ret = dwc3_host_init(dwc);
944 if (ret) {
945 if (ret != -EPROBE_DEFER)
946 dev_err(dev, "failed to initialize host\n");
947 return ret;
948 }
949 phy_calibrate(dwc->usb2_generic_phy);
950 break;
951 case USB_DR_MODE_OTG:
952 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
953 ret = dwc3_drd_init(dwc);
954 if (ret) {
955 if (ret != -EPROBE_DEFER)
956 dev_err(dev, "failed to initialize dual-role\n");
957 return ret;
958 }
959 break;
960 default:
961 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
962 return -EINVAL;
963 }
964
965 return 0;
966 }
967
968 static void dwc3_core_exit_mode(struct dwc3 *dwc)
969 {
970 switch (dwc->dr_mode) {
971 case USB_DR_MODE_PERIPHERAL:
972 dwc3_gadget_exit(dwc);
973 break;
974 case USB_DR_MODE_HOST:
975 dwc3_host_exit(dwc);
976 break;
977 case USB_DR_MODE_OTG:
978 dwc3_drd_exit(dwc);
979 break;
980 default:
981 /* do nothing */
982 break;
983 }
984 }
985
986 static void dwc3_get_properties(struct dwc3 *dwc)
987 {
988 struct device *dev = dwc->dev;
989 u8 lpm_nyet_threshold;
990 u8 tx_de_emphasis;
991 u8 hird_threshold;
992
993 /* default to highest possible threshold */
994 lpm_nyet_threshold = 0xff;
995
996 /* default to -3.5dB de-emphasis */
997 tx_de_emphasis = 1;
998
999 /*
1000 * default to assert utmi_sleep_n and use maximum allowed HIRD
1001 * threshold value of 0b1100
1002 */
1003 hird_threshold = 12;
1004
1005 dwc->maximum_speed = usb_get_maximum_speed(dev);
1006 dwc->dr_mode = usb_get_dr_mode(dev);
1007 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1008
1009 dwc->sysdev_is_parent = device_property_read_bool(dev,
1010 "linux,sysdev_is_parent");
1011 if (dwc->sysdev_is_parent)
1012 dwc->sysdev = dwc->dev->parent;
1013 else
1014 dwc->sysdev = dwc->dev;
1015
1016 dwc->has_lpm_erratum = device_property_read_bool(dev,
1017 "snps,has-lpm-erratum");
1018 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1019 &lpm_nyet_threshold);
1020 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1021 "snps,is-utmi-l1-suspend");
1022 device_property_read_u8(dev, "snps,hird-threshold",
1023 &hird_threshold);
1024 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1025 "snps,usb3_lpm_capable");
1026
1027 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1028 "snps,disable_scramble_quirk");
1029 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1030 "snps,u2exit_lfps_quirk");
1031 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1032 "snps,u2ss_inp3_quirk");
1033 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1034 "snps,req_p1p2p3_quirk");
1035 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1036 "snps,del_p1p2p3_quirk");
1037 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1038 "snps,del_phy_power_chg_quirk");
1039 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1040 "snps,lfps_filter_quirk");
1041 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1042 "snps,rx_detect_poll_quirk");
1043 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1044 "snps,dis_u3_susphy_quirk");
1045 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1046 "snps,dis_u2_susphy_quirk");
1047 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1048 "snps,dis_enblslpm_quirk");
1049 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1050 "snps,dis_rxdet_inp3_quirk");
1051 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1052 "snps,dis-u2-freeclk-exists-quirk");
1053 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1054 "snps,dis-del-phy-power-chg-quirk");
1055 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1056 "snps,dis-tx-ipgap-linecheck-quirk");
1057
1058 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1059 "snps,tx_de_emphasis_quirk");
1060 device_property_read_u8(dev, "snps,tx_de_emphasis",
1061 &tx_de_emphasis);
1062 device_property_read_string(dev, "snps,hsphy_interface",
1063 &dwc->hsphy_interface);
1064 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1065 &dwc->fladj);
1066
1067 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1068 "snps,dis_metastability_quirk");
1069
1070 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1071 dwc->tx_de_emphasis = tx_de_emphasis;
1072
1073 dwc->hird_threshold = hird_threshold
1074 | (dwc->is_utmi_l1_suspend << 4);
1075
1076 dwc->imod_interval = 0;
1077 }
1078
1079 /* check whether the core supports IMOD */
1080 bool dwc3_has_imod(struct dwc3 *dwc)
1081 {
1082 return ((dwc3_is_usb3(dwc) &&
1083 dwc->revision >= DWC3_REVISION_300A) ||
1084 (dwc3_is_usb31(dwc) &&
1085 dwc->revision >= DWC3_USB31_REVISION_120A));
1086 }
1087
1088 static void dwc3_check_params(struct dwc3 *dwc)
1089 {
1090 struct device *dev = dwc->dev;
1091
1092 /* Check for proper value of imod_interval */
1093 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1094 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1095 dwc->imod_interval = 0;
1096 }
1097
1098 /*
1099 * Workaround for STAR 9000961433 which affects only version
1100 * 3.00a of the DWC_usb3 core. This prevents the controller
1101 * interrupt from being masked while handling events. IMOD
1102 * allows us to work around this issue. Enable it for the
1103 * affected version.
1104 */
1105 if (!dwc->imod_interval &&
1106 (dwc->revision == DWC3_REVISION_300A))
1107 dwc->imod_interval = 1;
1108
1109 /* Check the maximum_speed parameter */
1110 switch (dwc->maximum_speed) {
1111 case USB_SPEED_LOW:
1112 case USB_SPEED_FULL:
1113 case USB_SPEED_HIGH:
1114 case USB_SPEED_SUPER:
1115 case USB_SPEED_SUPER_PLUS:
1116 break;
1117 default:
1118 dev_err(dev, "invalid maximum_speed parameter %d\n",
1119 dwc->maximum_speed);
1120 /* fall through */
1121 case USB_SPEED_UNKNOWN:
1122 /* default to superspeed */
1123 dwc->maximum_speed = USB_SPEED_SUPER;
1124
1125 /*
1126 * default to superspeed plus if we are capable.
1127 */
1128 if (dwc3_is_usb31(dwc) &&
1129 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1130 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1131 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1132
1133 break;
1134 }
1135 }
1136
1137 static int dwc3_probe(struct platform_device *pdev)
1138 {
1139 struct device *dev = &pdev->dev;
1140 struct resource *res;
1141 struct dwc3 *dwc;
1142
1143 int ret;
1144
1145 void __iomem *regs;
1146
1147 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1148 if (!dwc)
1149 return -ENOMEM;
1150
1151 dwc->dev = dev;
1152
1153 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1154 if (!res) {
1155 dev_err(dev, "missing memory resource\n");
1156 return -ENODEV;
1157 }
1158
1159 dwc->xhci_resources[0].start = res->start;
1160 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1161 DWC3_XHCI_REGS_END;
1162 dwc->xhci_resources[0].flags = res->flags;
1163 dwc->xhci_resources[0].name = res->name;
1164
1165 res->start += DWC3_GLOBALS_REGS_START;
1166
1167 /*
1168 * Request memory region but exclude xHCI regs,
1169 * since it will be requested by the xhci-plat driver.
1170 */
1171 regs = devm_ioremap_resource(dev, res);
1172 if (IS_ERR(regs)) {
1173 ret = PTR_ERR(regs);
1174 goto err0;
1175 }
1176
1177 dwc->regs = regs;
1178 dwc->regs_size = resource_size(res);
1179
1180 dwc3_get_properties(dwc);
1181
1182 platform_set_drvdata(pdev, dwc);
1183 dwc3_cache_hwparams(dwc);
1184
1185 spin_lock_init(&dwc->lock);
1186
1187 pm_runtime_set_active(dev);
1188 pm_runtime_use_autosuspend(dev);
1189 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1190 pm_runtime_enable(dev);
1191 ret = pm_runtime_get_sync(dev);
1192 if (ret < 0)
1193 goto err1;
1194
1195 pm_runtime_forbid(dev);
1196
1197 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1198 if (ret) {
1199 dev_err(dwc->dev, "failed to allocate event buffers\n");
1200 ret = -ENOMEM;
1201 goto err2;
1202 }
1203
1204 ret = dwc3_get_dr_mode(dwc);
1205 if (ret)
1206 goto err3;
1207
1208 ret = dwc3_alloc_scratch_buffers(dwc);
1209 if (ret)
1210 goto err3;
1211
1212 ret = dwc3_core_init(dwc);
1213 if (ret) {
1214 dev_err(dev, "failed to initialize core\n");
1215 goto err4;
1216 }
1217
1218 dwc3_check_params(dwc);
1219
1220 ret = dwc3_core_init_mode(dwc);
1221 if (ret)
1222 goto err5;
1223
1224 dwc3_debugfs_init(dwc);
1225 pm_runtime_put(dev);
1226
1227 return 0;
1228
1229 err5:
1230 dwc3_event_buffers_cleanup(dwc);
1231
1232 err4:
1233 dwc3_free_scratch_buffers(dwc);
1234
1235 err3:
1236 dwc3_free_event_buffers(dwc);
1237 dwc3_ulpi_exit(dwc);
1238
1239 err2:
1240 pm_runtime_allow(&pdev->dev);
1241
1242 err1:
1243 pm_runtime_put_sync(&pdev->dev);
1244 pm_runtime_disable(&pdev->dev);
1245
1246 err0:
1247 /*
1248 * restore res->start back to its original value so that, in case the
1249 * probe is deferred, we don't end up getting error in request the
1250 * memory region the next time probe is called.
1251 */
1252 res->start -= DWC3_GLOBALS_REGS_START;
1253
1254 return ret;
1255 }
1256
1257 static int dwc3_remove(struct platform_device *pdev)
1258 {
1259 struct dwc3 *dwc = platform_get_drvdata(pdev);
1260 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1261
1262 pm_runtime_get_sync(&pdev->dev);
1263 /*
1264 * restore res->start back to its original value so that, in case the
1265 * probe is deferred, we don't end up getting error in request the
1266 * memory region the next time probe is called.
1267 */
1268 res->start -= DWC3_GLOBALS_REGS_START;
1269
1270 dwc3_debugfs_exit(dwc);
1271 dwc3_core_exit_mode(dwc);
1272
1273 dwc3_core_exit(dwc);
1274 dwc3_ulpi_exit(dwc);
1275
1276 pm_runtime_put_sync(&pdev->dev);
1277 pm_runtime_allow(&pdev->dev);
1278 pm_runtime_disable(&pdev->dev);
1279
1280 dwc3_free_event_buffers(dwc);
1281 dwc3_free_scratch_buffers(dwc);
1282
1283 return 0;
1284 }
1285
1286 #ifdef CONFIG_PM
1287 static int dwc3_suspend_common(struct dwc3 *dwc)
1288 {
1289 unsigned long flags;
1290
1291 switch (dwc->current_dr_role) {
1292 case DWC3_GCTL_PRTCAP_DEVICE:
1293 spin_lock_irqsave(&dwc->lock, flags);
1294 dwc3_gadget_suspend(dwc);
1295 spin_unlock_irqrestore(&dwc->lock, flags);
1296 dwc3_core_exit(dwc);
1297 break;
1298 case DWC3_GCTL_PRTCAP_HOST:
1299 default:
1300 /* do nothing */
1301 break;
1302 }
1303
1304 return 0;
1305 }
1306
1307 static int dwc3_resume_common(struct dwc3 *dwc)
1308 {
1309 unsigned long flags;
1310 int ret;
1311
1312 switch (dwc->current_dr_role) {
1313 case DWC3_GCTL_PRTCAP_DEVICE:
1314 ret = dwc3_core_init(dwc);
1315 if (ret)
1316 return ret;
1317
1318 spin_lock_irqsave(&dwc->lock, flags);
1319 dwc3_gadget_resume(dwc);
1320 spin_unlock_irqrestore(&dwc->lock, flags);
1321 break;
1322 case DWC3_GCTL_PRTCAP_HOST:
1323 default:
1324 /* do nothing */
1325 break;
1326 }
1327
1328 return 0;
1329 }
1330
1331 static int dwc3_runtime_checks(struct dwc3 *dwc)
1332 {
1333 switch (dwc->current_dr_role) {
1334 case USB_DR_MODE_PERIPHERAL:
1335 case USB_DR_MODE_OTG:
1336 if (dwc->connected)
1337 return -EBUSY;
1338 break;
1339 case USB_DR_MODE_HOST:
1340 default:
1341 /* do nothing */
1342 break;
1343 }
1344
1345 return 0;
1346 }
1347
1348 static int dwc3_runtime_suspend(struct device *dev)
1349 {
1350 struct dwc3 *dwc = dev_get_drvdata(dev);
1351 int ret;
1352
1353 if (dwc3_runtime_checks(dwc))
1354 return -EBUSY;
1355
1356 ret = dwc3_suspend_common(dwc);
1357 if (ret)
1358 return ret;
1359
1360 device_init_wakeup(dev, true);
1361
1362 return 0;
1363 }
1364
1365 static int dwc3_runtime_resume(struct device *dev)
1366 {
1367 struct dwc3 *dwc = dev_get_drvdata(dev);
1368 int ret;
1369
1370 device_init_wakeup(dev, false);
1371
1372 ret = dwc3_resume_common(dwc);
1373 if (ret)
1374 return ret;
1375
1376 switch (dwc->current_dr_role) {
1377 case DWC3_GCTL_PRTCAP_DEVICE:
1378 dwc3_gadget_process_pending_events(dwc);
1379 break;
1380 case DWC3_GCTL_PRTCAP_HOST:
1381 default:
1382 /* do nothing */
1383 break;
1384 }
1385
1386 pm_runtime_mark_last_busy(dev);
1387
1388 return 0;
1389 }
1390
1391 static int dwc3_runtime_idle(struct device *dev)
1392 {
1393 struct dwc3 *dwc = dev_get_drvdata(dev);
1394
1395 switch (dwc->current_dr_role) {
1396 case DWC3_GCTL_PRTCAP_DEVICE:
1397 if (dwc3_runtime_checks(dwc))
1398 return -EBUSY;
1399 break;
1400 case DWC3_GCTL_PRTCAP_HOST:
1401 default:
1402 /* do nothing */
1403 break;
1404 }
1405
1406 pm_runtime_mark_last_busy(dev);
1407 pm_runtime_autosuspend(dev);
1408
1409 return 0;
1410 }
1411 #endif /* CONFIG_PM */
1412
1413 #ifdef CONFIG_PM_SLEEP
1414 static int dwc3_suspend(struct device *dev)
1415 {
1416 struct dwc3 *dwc = dev_get_drvdata(dev);
1417 int ret;
1418
1419 ret = dwc3_suspend_common(dwc);
1420 if (ret)
1421 return ret;
1422
1423 pinctrl_pm_select_sleep_state(dev);
1424
1425 return 0;
1426 }
1427
1428 static int dwc3_resume(struct device *dev)
1429 {
1430 struct dwc3 *dwc = dev_get_drvdata(dev);
1431 int ret;
1432
1433 pinctrl_pm_select_default_state(dev);
1434
1435 ret = dwc3_resume_common(dwc);
1436 if (ret)
1437 return ret;
1438
1439 pm_runtime_disable(dev);
1440 pm_runtime_set_active(dev);
1441 pm_runtime_enable(dev);
1442
1443 return 0;
1444 }
1445 #endif /* CONFIG_PM_SLEEP */
1446
1447 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1448 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1449 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1450 dwc3_runtime_idle)
1451 };
1452
1453 #ifdef CONFIG_OF
1454 static const struct of_device_id of_dwc3_match[] = {
1455 {
1456 .compatible = "snps,dwc3"
1457 },
1458 {
1459 .compatible = "synopsys,dwc3"
1460 },
1461 { },
1462 };
1463 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1464 #endif
1465
1466 #ifdef CONFIG_ACPI
1467
1468 #define ACPI_ID_INTEL_BSW "808622B7"
1469
1470 static const struct acpi_device_id dwc3_acpi_match[] = {
1471 { ACPI_ID_INTEL_BSW, 0 },
1472 { },
1473 };
1474 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1475 #endif
1476
1477 static struct platform_driver dwc3_driver = {
1478 .probe = dwc3_probe,
1479 .remove = dwc3_remove,
1480 .driver = {
1481 .name = "dwc3",
1482 .of_match_table = of_match_ptr(of_dwc3_match),
1483 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1484 .pm = &dwc3_dev_pm_ops,
1485 },
1486 };
1487
1488 module_platform_driver(dwc3_driver);
1489
1490 MODULE_ALIAS("platform:dwc3");
1491 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1492 MODULE_LICENSE("GPL v2");
1493 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
CRIS linux kernel tree