drivers/usb/dwc3/ep0.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/slab.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/list.h>
  19 #include <linux/dma-mapping.h>
  20
  21 #include <linux/usb/ch9.h>
  22 #include <linux/usb/gadget.h>
  23 #include <linux/usb/composite.h>
  24
  25 #include "core.h"
  26 #include "debug.h"
  27 #include "gadget.h"
  28 #include "io.h"
  29
  30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  32                 struct dwc3_ep *dep, struct dwc3_request *req);
  33
  34 static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
  35                 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
  36 {
  37         struct dwc3_trb                 *trb;
  38         struct dwc3                     *dwc;
  39
  40         dwc = dep->dwc;
  41         trb = &dwc->ep0_trb[dep->trb_enqueue];
  42
  43         if (chain)
  44                 dep->trb_enqueue++;
  45
  46         trb->bpl = lower_32_bits(buf_dma);
  47         trb->bph = upper_32_bits(buf_dma);
  48         trb->size = len;
  49         trb->ctrl = type;
  50
  51         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  52                         | DWC3_TRB_CTRL_ISP_IMI);
  53
  54         if (chain)
  55                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
  56         else
  57                 trb->ctrl |= (DWC3_TRB_CTRL_IOC
  58                                 | DWC3_TRB_CTRL_LST);
  59
  60         trace_dwc3_prepare_trb(dep, trb);
  61 }
  62
  63 static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
  64 {
  65         struct dwc3_gadget_ep_cmd_params params;
  66         struct dwc3                     *dwc;
  67         int                             ret;
  68
  69         if (dep->flags & DWC3_EP_BUSY)
  70                 return 0;
  71
  72         dwc = dep->dwc;
  73
  74         memset(&params, 0, sizeof(params));
  75         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  76         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  77
  78         ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, &params);
  79         if (ret < 0)
  80                 return ret;
  81
  82         dep->flags |= DWC3_EP_BUSY;
  83         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
  84         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
  85
  86         return 0;
  87 }
  88
  89 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
  90                 struct dwc3_request *req)
  91 {
  92         struct dwc3             *dwc = dep->dwc;
  93
  94         req->request.actual     = 0;
  95         req->request.status     = -EINPROGRESS;
  96         req->epnum              = dep->number;
  97
  98         list_add_tail(&req->list, &dep->pending_list);
  99
 100         /*
 101          * Gadget driver might not be quick enough to queue a request
 102          * before we get a Transfer Not Ready event on this endpoint.
 103          *
 104          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 105          * flag is set, it's telling us that as soon as Gadget queues the
 106          * required request, we should kick the transfer here because the
 107          * IRQ we were waiting for is long gone.
 108          */
 109         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 110                 unsigned        direction;
 111
 112                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 113
 114                 if (dwc->ep0state != EP0_DATA_PHASE) {
 115                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 116                         return 0;
 117                 }
 118
 119                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 120
 121                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 122                                 DWC3_EP0_DIR_IN);
 123
 124                 return 0;
 125         }
 126
 127         /*
 128          * In case gadget driver asked us to delay the STATUS phase,
 129          * handle it here.
 130          */
 131         if (dwc->delayed_status) {
 132                 unsigned        direction;
 133
 134                 direction = !dwc->ep0_expect_in;
 135                 dwc->delayed_status = false;
 136                 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
 137
 138                 if (dwc->ep0state == EP0_STATUS_PHASE)
 139                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 140
 141                 return 0;
 142         }
 143
 144         /*
 145          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 146          *
 147          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 148          * come before issueing Start Transfer command, but if we do, we will
 149          * miss situations where the host starts another SETUP phase instead of
 150          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 151          * Layer Compliance Suite.
 152          *
 153          * The problem surfaces due to the fact that in case of back-to-back
 154          * SETUP packets there will be no XferNotReady(DATA) generated and we
 155          * will be stuck waiting for XferNotReady(DATA) forever.
 156          *
 157          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 158          * it tells us to start Data Phase right away. It also mentions that if
 159          * we receive a SETUP phase instead of the DATA phase, core will issue
 160          * XferComplete for the DATA phase, before actually initiating it in
 161          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 162          * can only be used to print some debugging logs, as the core expects
 163          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 164          * just so it completes right away, without transferring anything and,
 165          * only then, we can go back to the SETUP phase.
 166          *
 167          * Because of this scenario, SNPS decided to change the programming
 168          * model of control transfers and support on-demand transfers only for
 169          * the STATUS phase. To fix the issue we have now, we will always wait
 170          * for gadget driver to queue the DATA phase's struct usb_request, then
 171          * start it right away.
 172          *
 173          * If we're actually in a 2-stage transfer, we will wait for
 174          * XferNotReady(STATUS).
 175          */
 176         if (dwc->three_stage_setup) {
 177                 unsigned        direction;
 178
 179                 direction = dwc->ep0_expect_in;
 180                 dwc->ep0state = EP0_DATA_PHASE;
 181
 182                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 183
 184                 dep->flags &= ~DWC3_EP0_DIR_IN;
 185         }
 186
 187         return 0;
 188 }
 189
 190 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 191                 gfp_t gfp_flags)
 192 {
 193         struct dwc3_request             *req = to_dwc3_request(request);
 194         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 195         struct dwc3                     *dwc = dep->dwc;
 196
 197         unsigned long                   flags;
 198
 199         int                             ret;
 200
 201         spin_lock_irqsave(&dwc->lock, flags);
 202         if (!dep->endpoint.desc) {
 203                 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
 204                                 dep->name);
 205                 ret = -ESHUTDOWN;
 206                 goto out;
 207         }
 208
 209         /* we share one TRB for ep0/1 */
 210         if (!list_empty(&dep->pending_list)) {
 211                 ret = -EBUSY;
 212                 goto out;
 213         }
 214
 215         ret = __dwc3_gadget_ep0_queue(dep, req);
 216
 217 out:
 218         spin_unlock_irqrestore(&dwc->lock, flags);
 219
 220         return ret;
 221 }
 222
 223 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 224 {
 225         struct dwc3_ep          *dep;
 226
 227         /* reinitialize physical ep1 */
 228         dep = dwc->eps[1];
 229         dep->flags = DWC3_EP_ENABLED;
 230
 231         /* stall is always issued on EP0 */
 232         dep = dwc->eps[0];
 233         __dwc3_gadget_ep_set_halt(dep, 1, false);
 234         dep->flags = DWC3_EP_ENABLED;
 235         dwc->delayed_status = false;
 236
 237         if (!list_empty(&dep->pending_list)) {
 238                 struct dwc3_request     *req;
 239
 240                 req = next_request(&dep->pending_list);
 241                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 242         }
 243
 244         dwc->ep0state = EP0_SETUP_PHASE;
 245         dwc3_ep0_out_start(dwc);
 246 }
 247
 248 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 249 {
 250         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 251         struct dwc3                     *dwc = dep->dwc;
 252
 253         dwc3_ep0_stall_and_restart(dwc);
 254
 255         return 0;
 256 }
 257
 258 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 259 {
 260         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 261         struct dwc3                     *dwc = dep->dwc;
 262         unsigned long                   flags;
 263         int                             ret;
 264
 265         spin_lock_irqsave(&dwc->lock, flags);
 266         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 267         spin_unlock_irqrestore(&dwc->lock, flags);
 268
 269         return ret;
 270 }
 271
 272 void dwc3_ep0_out_start(struct dwc3 *dwc)
 273 {
 274         struct dwc3_ep                  *dep;
 275         int                             ret;
 276
 277         complete(&dwc->ep0_in_setup);
 278
 279         dep = dwc->eps[0];
 280         dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
 281                         DWC3_TRBCTL_CONTROL_SETUP, false);
 282         ret = dwc3_ep0_start_trans(dep);
 283         WARN_ON(ret < 0);
 284 }
 285
 286 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 287 {
 288         struct dwc3_ep          *dep;
 289         u32                     windex = le16_to_cpu(wIndex_le);
 290         u32                     epnum;
 291
 292         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 293         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 294                 epnum |= 1;
 295
 296         dep = dwc->eps[epnum];
 297         if (dep->flags & DWC3_EP_ENABLED)
 298                 return dep;
 299
 300         return NULL;
 301 }
 302
 303 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 304 {
 305 }
 306 /*
 307  * ch 9.4.5
 308  */
 309 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 310                 struct usb_ctrlrequest *ctrl)
 311 {
 312         struct dwc3_ep          *dep;
 313         u32                     recip;
 314         u32                     value;
 315         u32                     reg;
 316         u16                     usb_status = 0;
 317         __le16                  *response_pkt;
 318
 319         /* We don't support PTM_STATUS */
 320         value = le16_to_cpu(ctrl->wValue);
 321         if (value != 0)
 322                 return -EINVAL;
 323
 324         recip = ctrl->bRequestType & USB_RECIP_MASK;
 325         switch (recip) {
 326         case USB_RECIP_DEVICE:
 327                 /*
 328                  * LTM will be set once we know how to set this in HW.
 329                  */
 330                 usb_status |= dwc->gadget.is_selfpowered;
 331
 332                 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
 333                     (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
 334                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 335                         if (reg & DWC3_DCTL_INITU1ENA)
 336                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 337                         if (reg & DWC3_DCTL_INITU2ENA)
 338                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 339                 }
 340
 341                 break;
 342
 343         case USB_RECIP_INTERFACE:
 344                 /*
 345                  * Function Remote Wake Capable D0
 346                  * Function Remote Wakeup       D1
 347                  */
 348                 break;
 349
 350         case USB_RECIP_ENDPOINT:
 351                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 352                 if (!dep)
 353                         return -EINVAL;
 354
 355                 if (dep->flags & DWC3_EP_STALL)
 356                         usb_status = 1 << USB_ENDPOINT_HALT;
 357                 break;
 358         default:
 359                 return -EINVAL;
 360         }
 361
 362         response_pkt = (__le16 *) dwc->setup_buf;
 363         *response_pkt = cpu_to_le16(usb_status);
 364
 365         dep = dwc->eps[0];
 366         dwc->ep0_usb_req.dep = dep;
 367         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 368         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 369         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 370
 371         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 372 }
 373
 374 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
 375                 int set)
 376 {
 377         u32 reg;
 378
 379         if (state != USB_STATE_CONFIGURED)
 380                 return -EINVAL;
 381         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 382                         (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 383                 return -EINVAL;
 384
 385         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 386         if (set)
 387                 reg |= DWC3_DCTL_INITU1ENA;
 388         else
 389                 reg &= ~DWC3_DCTL_INITU1ENA;
 390         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 391
 392         return 0;
 393 }
 394
 395 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
 396                 int set)
 397 {
 398         u32 reg;
 399
 400
 401         if (state != USB_STATE_CONFIGURED)
 402                 return -EINVAL;
 403         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 404                         (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 405                 return -EINVAL;
 406
 407         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 408         if (set)
 409                 reg |= DWC3_DCTL_INITU2ENA;
 410         else
 411                 reg &= ~DWC3_DCTL_INITU2ENA;
 412         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 413
 414         return 0;
 415 }
 416
 417 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
 418                 u32 wIndex, int set)
 419 {
 420         if ((wIndex & 0xff) != 0)
 421                 return -EINVAL;
 422         if (!set)
 423                 return -EINVAL;
 424
 425         switch (wIndex >> 8) {
 426         case TEST_J:
 427         case TEST_K:
 428         case TEST_SE0_NAK:
 429         case TEST_PACKET:
 430         case TEST_FORCE_EN:
 431                 dwc->test_mode_nr = wIndex >> 8;
 432                 dwc->test_mode = true;
 433                 break;
 434         default:
 435                 return -EINVAL;
 436         }
 437
 438         return 0;
 439 }
 440
 441 static int dwc3_ep0_handle_device(struct dwc3 *dwc,
 442                 struct usb_ctrlrequest *ctrl, int set)
 443 {
 444         enum usb_device_state   state;
 445         u32                     wValue;
 446         u32                     wIndex;
 447         int                     ret = 0;
 448
 449         wValue = le16_to_cpu(ctrl->wValue);
 450         wIndex = le16_to_cpu(ctrl->wIndex);
 451         state = dwc->gadget.state;
 452
 453         switch (wValue) {
 454         case USB_DEVICE_REMOTE_WAKEUP:
 455                 break;
 456         /*
 457          * 9.4.1 says only only for SS, in AddressState only for
 458          * default control pipe
 459          */
 460         case USB_DEVICE_U1_ENABLE:
 461                 ret = dwc3_ep0_handle_u1(dwc, state, set);
 462                 break;
 463         case USB_DEVICE_U2_ENABLE:
 464                 ret = dwc3_ep0_handle_u2(dwc, state, set);
 465                 break;
 466         case USB_DEVICE_LTM_ENABLE:
 467                 ret = -EINVAL;
 468                 break;
 469         case USB_DEVICE_TEST_MODE:
 470                 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
 471                 break;
 472         default:
 473                 ret = -EINVAL;
 474         }
 475
 476         return ret;
 477 }
 478
 479 static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
 480                 struct usb_ctrlrequest *ctrl, int set)
 481 {
 482         u32                     wValue;
 483         int                     ret = 0;
 484
 485         wValue = le16_to_cpu(ctrl->wValue);
 486
 487         switch (wValue) {
 488         case USB_INTRF_FUNC_SUSPEND:
 489                 /*
 490                  * REVISIT: Ideally we would enable some low power mode here,
 491                  * however it's unclear what we should be doing here.
 492                  *
 493                  * For now, we're not doing anything, just making sure we return
 494                  * 0 so USB Command Verifier tests pass without any errors.
 495                  */
 496                 break;
 497         default:
 498                 ret = -EINVAL;
 499         }
 500
 501         return ret;
 502 }
 503
 504 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
 505                 struct usb_ctrlrequest *ctrl, int set)
 506 {
 507         struct dwc3_ep          *dep;
 508         u32                     wValue;
 509         int                     ret;
 510
 511         wValue = le16_to_cpu(ctrl->wValue);
 512
 513         switch (wValue) {
 514         case USB_ENDPOINT_HALT:
 515                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 516                 if (!dep)
 517                         return -EINVAL;
 518
 519                 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 520                         break;
 521
 522                 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 523                 if (ret)
 524                         return -EINVAL;
 525                 break;
 526         default:
 527                 return -EINVAL;
 528         }
 529
 530         return 0;
 531 }
 532
 533 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 534                 struct usb_ctrlrequest *ctrl, int set)
 535 {
 536         u32                     recip;
 537         int                     ret;
 538
 539         recip = ctrl->bRequestType & USB_RECIP_MASK;
 540
 541         switch (recip) {
 542         case USB_RECIP_DEVICE:
 543                 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
 544                 break;
 545         case USB_RECIP_INTERFACE:
 546                 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
 547                 break;
 548         case USB_RECIP_ENDPOINT:
 549                 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
 550                 break;
 551         default:
 552                 ret = -EINVAL;
 553         }
 554
 555         return ret;
 556 }
 557
 558 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 559 {
 560         enum usb_device_state state = dwc->gadget.state;
 561         u32 addr;
 562         u32 reg;
 563
 564         addr = le16_to_cpu(ctrl->wValue);
 565         if (addr > 127) {
 566                 dev_err(dwc->dev, "invalid device address %d\n", addr);
 567                 return -EINVAL;
 568         }
 569
 570         if (state == USB_STATE_CONFIGURED) {
 571                 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
 572                 return -EINVAL;
 573         }
 574
 575         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 576         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 577         reg |= DWC3_DCFG_DEVADDR(addr);
 578         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 579
 580         if (addr)
 581                 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
 582         else
 583                 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
 584
 585         return 0;
 586 }
 587
 588 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 589 {
 590         int ret;
 591
 592         spin_unlock(&dwc->lock);
 593         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 594         spin_lock(&dwc->lock);
 595         return ret;
 596 }
 597
 598 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 599 {
 600         enum usb_device_state state = dwc->gadget.state;
 601         u32 cfg;
 602         int ret;
 603         u32 reg;
 604
 605         cfg = le16_to_cpu(ctrl->wValue);
 606
 607         switch (state) {
 608         case USB_STATE_DEFAULT:
 609                 return -EINVAL;
 610
 611         case USB_STATE_ADDRESS:
 612                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 613                 /* if the cfg matches and the cfg is non zero */
 614                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 615
 616                         /*
 617                          * only change state if set_config has already
 618                          * been processed. If gadget driver returns
 619                          * USB_GADGET_DELAYED_STATUS, we will wait
 620                          * to change the state on the next usb_ep_queue()
 621                          */
 622                         if (ret == 0)
 623                                 usb_gadget_set_state(&dwc->gadget,
 624                                                 USB_STATE_CONFIGURED);
 625
 626                         /*
 627                          * Enable transition to U1/U2 state when
 628                          * nothing is pending from application.
 629                          */
 630                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 631                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
 632                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 633                 }
 634                 break;
 635
 636         case USB_STATE_CONFIGURED:
 637                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 638                 if (!cfg && !ret)
 639                         usb_gadget_set_state(&dwc->gadget,
 640                                         USB_STATE_ADDRESS);
 641                 break;
 642         default:
 643                 ret = -EINVAL;
 644         }
 645         return ret;
 646 }
 647
 648 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 649 {
 650         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 651         struct dwc3     *dwc = dep->dwc;
 652
 653         u32             param = 0;
 654         u32             reg;
 655
 656         struct timing {
 657                 u8      u1sel;
 658                 u8      u1pel;
 659                 __le16  u2sel;
 660                 __le16  u2pel;
 661         } __packed timing;
 662
 663         int             ret;
 664
 665         memcpy(&timing, req->buf, sizeof(timing));
 666
 667         dwc->u1sel = timing.u1sel;
 668         dwc->u1pel = timing.u1pel;
 669         dwc->u2sel = le16_to_cpu(timing.u2sel);
 670         dwc->u2pel = le16_to_cpu(timing.u2pel);
 671
 672         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 673         if (reg & DWC3_DCTL_INITU2ENA)
 674                 param = dwc->u2pel;
 675         if (reg & DWC3_DCTL_INITU1ENA)
 676                 param = dwc->u1pel;
 677
 678         /*
 679          * According to Synopsys Databook, if parameter is
 680          * greater than 125, a value of zero should be
 681          * programmed in the register.
 682          */
 683         if (param > 125)
 684                 param = 0;
 685
 686         /* now that we have the time, issue DGCMD Set Sel */
 687         ret = dwc3_send_gadget_generic_command(dwc,
 688                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 689         WARN_ON(ret < 0);
 690 }
 691
 692 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 693 {
 694         struct dwc3_ep  *dep;
 695         enum usb_device_state state = dwc->gadget.state;
 696         u16             wLength;
 697
 698         if (state == USB_STATE_DEFAULT)
 699                 return -EINVAL;
 700
 701         wLength = le16_to_cpu(ctrl->wLength);
 702
 703         if (wLength != 6) {
 704                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 705                                 wLength);
 706                 return -EINVAL;
 707         }
 708
 709         /*
 710          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 711          * queue a usb_request for 6 bytes.
 712          *
 713          * Remember, though, this controller can't handle non-wMaxPacketSize
 714          * aligned transfers on the OUT direction, so we queue a request for
 715          * wMaxPacketSize instead.
 716          */
 717         dep = dwc->eps[0];
 718         dwc->ep0_usb_req.dep = dep;
 719         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 720         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 721         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 722
 723         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 724 }
 725
 726 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 727 {
 728         u16             wLength;
 729         u16             wValue;
 730         u16             wIndex;
 731
 732         wValue = le16_to_cpu(ctrl->wValue);
 733         wLength = le16_to_cpu(ctrl->wLength);
 734         wIndex = le16_to_cpu(ctrl->wIndex);
 735
 736         if (wIndex || wLength)
 737                 return -EINVAL;
 738
 739         dwc->gadget.isoch_delay = wValue;
 740
 741         return 0;
 742 }
 743
 744 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 745 {
 746         int ret;
 747
 748         switch (ctrl->bRequest) {
 749         case USB_REQ_GET_STATUS:
 750                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 751                 break;
 752         case USB_REQ_CLEAR_FEATURE:
 753                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 754                 break;
 755         case USB_REQ_SET_FEATURE:
 756                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 757                 break;
 758         case USB_REQ_SET_ADDRESS:
 759                 ret = dwc3_ep0_set_address(dwc, ctrl);
 760                 break;
 761         case USB_REQ_SET_CONFIGURATION:
 762                 ret = dwc3_ep0_set_config(dwc, ctrl);
 763                 break;
 764         case USB_REQ_SET_SEL:
 765                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 766                 break;
 767         case USB_REQ_SET_ISOCH_DELAY:
 768                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 769                 break;
 770         default:
 771                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 772                 break;
 773         }
 774
 775         return ret;
 776 }
 777
 778 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 779                 const struct dwc3_event_depevt *event)
 780 {
 781         struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
 782         int ret = -EINVAL;
 783         u32 len;
 784
 785         if (!dwc->gadget_driver)
 786                 goto out;
 787
 788         trace_dwc3_ctrl_req(ctrl);
 789
 790         len = le16_to_cpu(ctrl->wLength);
 791         if (!len) {
 792                 dwc->three_stage_setup = false;
 793                 dwc->ep0_expect_in = false;
 794                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 795         } else {
 796                 dwc->three_stage_setup = true;
 797                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 798                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 799         }
 800
 801         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 802                 ret = dwc3_ep0_std_request(dwc, ctrl);
 803         else
 804                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 805
 806         if (ret == USB_GADGET_DELAYED_STATUS)
 807                 dwc->delayed_status = true;
 808
 809 out:
 810         if (ret < 0)
 811                 dwc3_ep0_stall_and_restart(dwc);
 812 }
 813
 814 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 815                 const struct dwc3_event_depevt *event)
 816 {
 817         struct dwc3_request     *r = NULL;
 818         struct usb_request      *ur;
 819         struct dwc3_trb         *trb;
 820         struct dwc3_ep          *ep0;
 821         u32                     transferred = 0;
 822         u32                     status;
 823         u32                     length;
 824         u8                      epnum;
 825
 826         epnum = event->endpoint_number;
 827         ep0 = dwc->eps[0];
 828
 829         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 830         trb = dwc->ep0_trb;
 831         trace_dwc3_complete_trb(ep0, trb);
 832
 833         r = next_request(&ep0->pending_list);
 834         if (!r)
 835                 return;
 836
 837         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 838         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 839                 dwc->setup_packet_pending = true;
 840                 if (r)
 841                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 842
 843                 return;
 844         }
 845
 846         ur = &r->request;
 847
 848         length = trb->size & DWC3_TRB_SIZE_MASK;
 849         transferred = ur->length - length;
 850         ur->actual += transferred;
 851
 852         if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 853              ur->length && ur->zero) || dwc->ep0_bounced) {
 854                 trb++;
 855                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
 856                 trace_dwc3_complete_trb(ep0, trb);
 857                 ep0->trb_enqueue = 0;
 858                 dwc->ep0_bounced = false;
 859         }
 860
 861         if ((epnum & 1) && ur->actual < ur->length)
 862                 dwc3_ep0_stall_and_restart(dwc);
 863         else
 864                 dwc3_gadget_giveback(ep0, r, 0);
 865 }
 866
 867 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 868                 const struct dwc3_event_depevt *event)
 869 {
 870         struct dwc3_request     *r;
 871         struct dwc3_ep          *dep;
 872         struct dwc3_trb         *trb;
 873         u32                     status;
 874
 875         dep = dwc->eps[0];
 876         trb = dwc->ep0_trb;
 877
 878         trace_dwc3_complete_trb(dep, trb);
 879
 880         if (!list_empty(&dep->pending_list)) {
 881                 r = next_request(&dep->pending_list);
 882
 883                 dwc3_gadget_giveback(dep, r, 0);
 884         }
 885
 886         if (dwc->test_mode) {
 887                 int ret;
 888
 889                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 890                 if (ret < 0) {
 891                         dev_err(dwc->dev, "invalid test #%d\n",
 892                                         dwc->test_mode_nr);
 893                         dwc3_ep0_stall_and_restart(dwc);
 894                         return;
 895                 }
 896         }
 897
 898         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 899         if (status == DWC3_TRBSTS_SETUP_PENDING)
 900                 dwc->setup_packet_pending = true;
 901
 902         dwc->ep0state = EP0_SETUP_PHASE;
 903         dwc3_ep0_out_start(dwc);
 904 }
 905
 906 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 907                         const struct dwc3_event_depevt *event)
 908 {
 909         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 910
 911         dep->flags &= ~DWC3_EP_BUSY;
 912         dep->resource_index = 0;
 913         dwc->setup_packet_pending = false;
 914
 915         switch (dwc->ep0state) {
 916         case EP0_SETUP_PHASE:
 917                 dwc3_ep0_inspect_setup(dwc, event);
 918                 break;
 919
 920         case EP0_DATA_PHASE:
 921                 dwc3_ep0_complete_data(dwc, event);
 922                 break;
 923
 924         case EP0_STATUS_PHASE:
 925                 dwc3_ep0_complete_status(dwc, event);
 926                 break;
 927         default:
 928                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 929         }
 930 }
 931
 932 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 933                 struct dwc3_ep *dep, struct dwc3_request *req)
 934 {
 935         int                     ret;
 936
 937         req->direction = !!dep->number;
 938
 939         if (req->request.length == 0) {
 940                 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0,
 941                                 DWC3_TRBCTL_CONTROL_DATA, false);
 942                 ret = dwc3_ep0_start_trans(dep);
 943         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 944                         && (dep->number == 0)) {
 945                 u32     maxpacket;
 946                 u32     rem;
 947
 948                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
 949                                 &req->request, dep->number);
 950                 if (ret)
 951                         return;
 952
 953                 maxpacket = dep->endpoint.maxpacket;
 954                 rem = req->request.length % maxpacket;
 955                 dwc->ep0_bounced = true;
 956
 957                 /* prepare normal TRB */
 958                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
 959                                          req->request.length,
 960                                          DWC3_TRBCTL_CONTROL_DATA,
 961                                          true);
 962
 963                 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
 964
 965                 /* Now prepare one extra TRB to align transfer size */
 966                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
 967                                          maxpacket - rem,
 968                                          DWC3_TRBCTL_CONTROL_DATA,
 969                                          false);
 970                 ret = dwc3_ep0_start_trans(dep);
 971         } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
 972                    req->request.length && req->request.zero) {
 973                 u32     maxpacket;
 974
 975                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
 976                                 &req->request, dep->number);
 977                 if (ret)
 978                         return;
 979
 980                 maxpacket = dep->endpoint.maxpacket;
 981
 982                 /* prepare normal TRB */
 983                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
 984                                          req->request.length,
 985                                          DWC3_TRBCTL_CONTROL_DATA,
 986                                          true);
 987
 988                 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
 989
 990                 /* Now prepare one extra TRB to align transfer size */
 991                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
 992                                          0, DWC3_TRBCTL_CONTROL_DATA,
 993                                          false);
 994                 ret = dwc3_ep0_start_trans(dep);
 995         } else {
 996                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
 997                                 &req->request, dep->number);
 998                 if (ret)
 999                         return;
1000
1001                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1002                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1003                                 false);
1004
1005                 req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1006
1007                 ret = dwc3_ep0_start_trans(dep);
1008         }
1009
1010         WARN_ON(ret < 0);
1011 }
1012
1013 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1014 {
1015         struct dwc3             *dwc = dep->dwc;
1016         u32                     type;
1017
1018         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1019                 : DWC3_TRBCTL_CONTROL_STATUS2;
1020
1021         dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1022         return dwc3_ep0_start_trans(dep);
1023 }
1024
1025 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1026 {
1027         WARN_ON(dwc3_ep0_start_control_status(dep));
1028 }
1029
1030 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1031                 const struct dwc3_event_depevt *event)
1032 {
1033         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1034
1035         __dwc3_ep0_do_control_status(dwc, dep);
1036 }
1037
1038 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1039 {
1040         struct dwc3_gadget_ep_cmd_params params;
1041         u32                     cmd;
1042         int                     ret;
1043
1044         if (!dep->resource_index)
1045                 return;
1046
1047         cmd = DWC3_DEPCMD_ENDTRANSFER;
1048         cmd |= DWC3_DEPCMD_CMDIOC;
1049         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1050         memset(&params, 0, sizeof(params));
1051         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1052         WARN_ON_ONCE(ret);
1053         dep->resource_index = 0;
1054 }
1055
1056 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1057                 const struct dwc3_event_depevt *event)
1058 {
1059         switch (event->status) {
1060         case DEPEVT_STATUS_CONTROL_DATA:
1061                 /*
1062                  * We already have a DATA transfer in the controller's cache,
1063                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1064                  * it's for the wrong direction.
1065                  *
1066                  * In that case, we must issue END_TRANSFER command to the Data
1067                  * Phase we already have started and issue SetStall on the
1068                  * control endpoint.
1069                  */
1070                 if (dwc->ep0_expect_in != event->endpoint_number) {
1071                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1072
1073                         dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1074                         dwc3_ep0_end_control_data(dwc, dep);
1075                         dwc3_ep0_stall_and_restart(dwc);
1076                         return;
1077                 }
1078
1079                 break;
1080
1081         case DEPEVT_STATUS_CONTROL_STATUS:
1082                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1083                         return;
1084
1085                 dwc->ep0state = EP0_STATUS_PHASE;
1086
1087                 if (dwc->delayed_status) {
1088                         struct dwc3_ep *dep = dwc->eps[0];
1089
1090                         WARN_ON_ONCE(event->endpoint_number != 1);
1091                         /*
1092                          * We should handle the delay STATUS phase here if the
1093                          * request for handling delay STATUS has been queued
1094                          * into the list.
1095                          */
1096                         if (!list_empty(&dep->pending_list)) {
1097                                 dwc->delayed_status = false;
1098                                 usb_gadget_set_state(&dwc->gadget,
1099                                                      USB_STATE_CONFIGURED);
1100                                 dwc3_ep0_do_control_status(dwc, event);
1101                         }
1102
1103                         return;
1104                 }
1105
1106                 dwc3_ep0_do_control_status(dwc, event);
1107         }
1108 }
1109
1110 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1111                 const struct dwc3_event_depevt *event)
1112 {
1113         switch (event->endpoint_event) {
1114         case DWC3_DEPEVT_XFERCOMPLETE:
1115                 dwc3_ep0_xfer_complete(dwc, event);
1116                 break;
1117
1118         case DWC3_DEPEVT_XFERNOTREADY:
1119                 dwc3_ep0_xfernotready(dwc, event);
1120                 break;
1121
1122         case DWC3_DEPEVT_XFERINPROGRESS:
1123         case DWC3_DEPEVT_RXTXFIFOEVT:
1124         case DWC3_DEPEVT_STREAMEVT:
1125         case DWC3_DEPEVT_EPCMDCMPLT:
1126                 break;
1127         }
1128 }