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x86/topology: Fix function name in documentation
[cris-mirror.git] / drivers / usb / mtu3 / mtu3_core.c
blobb1b99a8f6a7a01f54d4bbfb5f4edee060b411a32
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * mtu3_core.c - hardware access layer and gadget init/exit of
4 * MediaTek usb3 Dual-Role Controller Driver
5 *
6 * Copyright (C) 2016 MediaTek Inc.
7 *
8 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
9 */
10
11 #include <linux/dma-mapping.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/platform_device.h>
17
18 #include "mtu3.h"
19
20 static int ep_fifo_alloc(struct mtu3_ep *mep, u32 seg_size)
21 {
22 struct mtu3_fifo_info *fifo = mep->fifo;
23 u32 num_bits = DIV_ROUND_UP(seg_size, MTU3_EP_FIFO_UNIT);
24 u32 start_bit;
25
26 /* ensure that @mep->fifo_seg_size is power of two */
27 num_bits = roundup_pow_of_two(num_bits);
28 if (num_bits > fifo->limit)
29 return -EINVAL;
30
31 mep->fifo_seg_size = num_bits * MTU3_EP_FIFO_UNIT;
32 num_bits = num_bits * (mep->slot + 1);
33 start_bit = bitmap_find_next_zero_area(fifo->bitmap,
34 fifo->limit, 0, num_bits, 0);
35 if (start_bit >= fifo->limit)
36 return -EOVERFLOW;
37
38 bitmap_set(fifo->bitmap, start_bit, num_bits);
39 mep->fifo_size = num_bits * MTU3_EP_FIFO_UNIT;
40 mep->fifo_addr = fifo->base + MTU3_EP_FIFO_UNIT * start_bit;
41
42 dev_dbg(mep->mtu->dev, "%s fifo:%#x/%#x, start_bit: %d\n",
43 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
44
45 return mep->fifo_addr;
46 }
47
48 static void ep_fifo_free(struct mtu3_ep *mep)
49 {
50 struct mtu3_fifo_info *fifo = mep->fifo;
51 u32 addr = mep->fifo_addr;
52 u32 bits = mep->fifo_size / MTU3_EP_FIFO_UNIT;
53 u32 start_bit;
54
55 if (unlikely(addr < fifo->base || bits > fifo->limit))
56 return;
57
58 start_bit = (addr - fifo->base) / MTU3_EP_FIFO_UNIT;
59 bitmap_clear(fifo->bitmap, start_bit, bits);
60 mep->fifo_size = 0;
61 mep->fifo_seg_size = 0;
62
63 dev_dbg(mep->mtu->dev, "%s size:%#x/%#x, start_bit: %d\n",
64 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
65 }
66
67 /* enable/disable U3D SS function */
68 static inline void mtu3_ss_func_set(struct mtu3 *mtu, bool enable)
69 {
70 /* If usb3_en==0, LTSSM will go to SS.Disable state */
71 if (enable)
72 mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
73 else
74 mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
75
76 dev_dbg(mtu->dev, "USB3_EN = %d\n", !!enable);
77 }
78
79 /* set/clear U3D HS device soft connect */
80 static inline void mtu3_hs_softconn_set(struct mtu3 *mtu, bool enable)
81 {
82 if (enable) {
83 mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
84 SOFT_CONN | SUSPENDM_ENABLE);
85 } else {
86 mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
87 SOFT_CONN | SUSPENDM_ENABLE);
88 }
89 dev_dbg(mtu->dev, "SOFTCONN = %d\n", !!enable);
90 }
91
92 /* only port0 of U2/U3 supports device mode */
93 static int mtu3_device_enable(struct mtu3 *mtu)
94 {
95 void __iomem *ibase = mtu->ippc_base;
96 u32 check_clk = 0;
97
98 mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
99
100 if (mtu->is_u3_ip) {
101 check_clk = SSUSB_U3_MAC_RST_B_STS;
102 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
103 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN |
104 SSUSB_U3_PORT_HOST_SEL));
105 }
106 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
107 (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
108 SSUSB_U2_PORT_HOST_SEL));
109
110 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
111 mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
112
113 return ssusb_check_clocks(mtu->ssusb, check_clk);
114 }
115
116 static void mtu3_device_disable(struct mtu3 *mtu)
117 {
118 void __iomem *ibase = mtu->ippc_base;
119
120 if (mtu->is_u3_ip)
121 mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
122 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN));
123
124 mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
125 SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
126
127 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
128 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
129
130 mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
131 }
132
133 /* reset U3D's device module. */
134 static void mtu3_device_reset(struct mtu3 *mtu)
135 {
136 void __iomem *ibase = mtu->ippc_base;
137
138 mtu3_setbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
139 udelay(1);
140 mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
141 }
142
143 /* disable all interrupts */
144 static void mtu3_intr_disable(struct mtu3 *mtu)
145 {
146 void __iomem *mbase = mtu->mac_base;
147
148 /* Disable level 1 interrupts */
149 mtu3_writel(mbase, U3D_LV1IECR, ~0x0);
150 /* Disable endpoint interrupts */
151 mtu3_writel(mbase, U3D_EPIECR, ~0x0);
152 }
153
154 static void mtu3_intr_status_clear(struct mtu3 *mtu)
155 {
156 void __iomem *mbase = mtu->mac_base;
157
158 /* Clear EP0 and Tx/Rx EPn interrupts status */
159 mtu3_writel(mbase, U3D_EPISR, ~0x0);
160 /* Clear U2 USB common interrupts status */
161 mtu3_writel(mbase, U3D_COMMON_USB_INTR, ~0x0);
162 /* Clear U3 LTSSM interrupts status */
163 mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0);
164 /* Clear speed change interrupt status */
165 mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0);
166 }
167
168 /* enable system global interrupt */
169 static void mtu3_intr_enable(struct mtu3 *mtu)
170 {
171 void __iomem *mbase = mtu->mac_base;
172 u32 value;
173
174 /*Enable level 1 interrupts (BMU, QMU, MAC3, DMA, MAC2, EPCTL) */
175 value = BMU_INTR | QMU_INTR | MAC3_INTR | MAC2_INTR | EP_CTRL_INTR;
176 mtu3_writel(mbase, U3D_LV1IESR, value);
177
178 /* Enable U2 common USB interrupts */
179 value = SUSPEND_INTR | RESUME_INTR | RESET_INTR;
180 mtu3_writel(mbase, U3D_COMMON_USB_INTR_ENABLE, value);
181
182 if (mtu->is_u3_ip) {
183 /* Enable U3 LTSSM interrupts */
184 value = HOT_RST_INTR | WARM_RST_INTR | VBUS_RISE_INTR |
185 VBUS_FALL_INTR | ENTER_U3_INTR | EXIT_U3_INTR;
186 mtu3_writel(mbase, U3D_LTSSM_INTR_ENABLE, value);
187 }
188
189 /* Enable QMU interrupts. */
190 value = TXQ_CSERR_INT | TXQ_LENERR_INT | RXQ_CSERR_INT |
191 RXQ_LENERR_INT | RXQ_ZLPERR_INT;
192 mtu3_writel(mbase, U3D_QIESR1, value);
193
194 /* Enable speed change interrupt */
195 mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR);
196 }
197
198 /* set/clear the stall and toggle bits for non-ep0 */
199 void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set)
200 {
201 struct mtu3 *mtu = mep->mtu;
202 void __iomem *mbase = mtu->mac_base;
203 u8 epnum = mep->epnum;
204 u32 csr;
205
206 if (mep->is_in) { /* TX */
207 csr = mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)) & TX_W1C_BITS;
208 if (set)
209 csr |= TX_SENDSTALL;
210 else
211 csr = (csr & (~TX_SENDSTALL)) | TX_SENTSTALL;
212 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr);
213 } else { /* RX */
214 csr = mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)) & RX_W1C_BITS;
215 if (set)
216 csr |= RX_SENDSTALL;
217 else
218 csr = (csr & (~RX_SENDSTALL)) | RX_SENTSTALL;
219 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr);
220 }
221
222 if (!set) {
223 mtu3_setbits(mbase, U3D_EP_RST, EP_RST(mep->is_in, epnum));
224 mtu3_clrbits(mbase, U3D_EP_RST, EP_RST(mep->is_in, epnum));
225 mep->flags &= ~MTU3_EP_STALL;
226 } else {
227 mep->flags |= MTU3_EP_STALL;
228 }
229
230 dev_dbg(mtu->dev, "%s: %s\n", mep->name,
231 set ? "SEND STALL" : "CLEAR STALL, with EP RESET");
232 }
233
234 void mtu3_dev_on_off(struct mtu3 *mtu, int is_on)
235 {
236 if (mtu->is_u3_ip && mtu->max_speed >= USB_SPEED_SUPER)
237 mtu3_ss_func_set(mtu, is_on);
238 else
239 mtu3_hs_softconn_set(mtu, is_on);
240
241 dev_info(mtu->dev, "gadget (%s) pullup D%s\n",
242 usb_speed_string(mtu->max_speed), is_on ? "+" : "-");
243 }
244
245 void mtu3_start(struct mtu3 *mtu)
246 {
247 void __iomem *mbase = mtu->mac_base;
248
249 dev_dbg(mtu->dev, "%s devctl 0x%x\n", __func__,
250 mtu3_readl(mbase, U3D_DEVICE_CONTROL));
251
252 mtu3_clrbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
253
254 /*
255 * When disable U2 port, USB2_CSR's register will be reset to
256 * default value after re-enable it again(HS is enabled by default).
257 * So if force mac to work as FS, disable HS function.
258 */
259 if (mtu->max_speed == USB_SPEED_FULL)
260 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
261
262 /* Initialize the default interrupts */
263 mtu3_intr_enable(mtu);
264 mtu->is_active = 1;
265
266 if (mtu->softconnect)
267 mtu3_dev_on_off(mtu, 1);
268 }
269
270 void mtu3_stop(struct mtu3 *mtu)
271 {
272 dev_dbg(mtu->dev, "%s\n", __func__);
273
274 mtu3_intr_disable(mtu);
275 mtu3_intr_status_clear(mtu);
276
277 if (mtu->softconnect)
278 mtu3_dev_on_off(mtu, 0);
279
280 mtu->is_active = 0;
281 mtu3_setbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
282 }
283
284 /* for non-ep0 */
285 int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
286 int interval, int burst, int mult)
287 {
288 void __iomem *mbase = mtu->mac_base;
289 int epnum = mep->epnum;
290 u32 csr0, csr1, csr2;
291 int fifo_sgsz, fifo_addr;
292 int num_pkts;
293
294 fifo_addr = ep_fifo_alloc(mep, mep->maxp);
295 if (fifo_addr < 0) {
296 dev_err(mtu->dev, "alloc ep fifo failed(%d)\n", mep->maxp);
297 return -ENOMEM;
298 }
299 fifo_sgsz = ilog2(mep->fifo_seg_size);
300 dev_dbg(mtu->dev, "%s fifosz: %x(%x/%x)\n", __func__, fifo_sgsz,
301 mep->fifo_seg_size, mep->fifo_size);
302
303 if (mep->is_in) {
304 csr0 = TX_TXMAXPKTSZ(mep->maxp);
305 csr0 |= TX_DMAREQEN;
306
307 num_pkts = (burst + 1) * (mult + 1) - 1;
308 csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot);
309 csr1 |= TX_MAX_PKT(num_pkts) | TX_MULT(mult);
310
311 csr2 = TX_FIFOADDR(fifo_addr >> 4);
312 csr2 |= TX_FIFOSEGSIZE(fifo_sgsz);
313
314 switch (mep->type) {
315 case USB_ENDPOINT_XFER_BULK:
316 csr1 |= TX_TYPE(TYPE_BULK);
317 break;
318 case USB_ENDPOINT_XFER_ISOC:
319 csr1 |= TX_TYPE(TYPE_ISO);
320 csr2 |= TX_BINTERVAL(interval);
321 break;
322 case USB_ENDPOINT_XFER_INT:
323 csr1 |= TX_TYPE(TYPE_INT);
324 csr2 |= TX_BINTERVAL(interval);
325 break;
326 }
327
328 /* Enable QMU Done interrupt */
329 mtu3_setbits(mbase, U3D_QIESR0, QMU_TX_DONE_INT(epnum));
330
331 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr0);
332 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), csr1);
333 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), csr2);
334
335 dev_dbg(mtu->dev, "U3D_TX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
336 epnum, mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)),
337 mtu3_readl(mbase, MU3D_EP_TXCR1(epnum)),
338 mtu3_readl(mbase, MU3D_EP_TXCR2(epnum)));
339 } else {
340 csr0 = RX_RXMAXPKTSZ(mep->maxp);
341 csr0 |= RX_DMAREQEN;
342
343 num_pkts = (burst + 1) * (mult + 1) - 1;
344 csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot);
345 csr1 |= RX_MAX_PKT(num_pkts) | RX_MULT(mult);
346
347 csr2 = RX_FIFOADDR(fifo_addr >> 4);
348 csr2 |= RX_FIFOSEGSIZE(fifo_sgsz);
349
350 switch (mep->type) {
351 case USB_ENDPOINT_XFER_BULK:
352 csr1 |= RX_TYPE(TYPE_BULK);
353 break;
354 case USB_ENDPOINT_XFER_ISOC:
355 csr1 |= RX_TYPE(TYPE_ISO);
356 csr2 |= RX_BINTERVAL(interval);
357 break;
358 case USB_ENDPOINT_XFER_INT:
359 csr1 |= RX_TYPE(TYPE_INT);
360 csr2 |= RX_BINTERVAL(interval);
361 break;
362 }
363
364 /*Enable QMU Done interrupt */
365 mtu3_setbits(mbase, U3D_QIESR0, QMU_RX_DONE_INT(epnum));
366
367 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr0);
368 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), csr1);
369 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), csr2);
370
371 dev_dbg(mtu->dev, "U3D_RX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
372 epnum, mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)),
373 mtu3_readl(mbase, MU3D_EP_RXCR1(epnum)),
374 mtu3_readl(mbase, MU3D_EP_RXCR2(epnum)));
375 }
376
377 dev_dbg(mtu->dev, "csr0:%#x, csr1:%#x, csr2:%#x\n", csr0, csr1, csr2);
378 dev_dbg(mtu->dev, "%s: %s, fifo-addr:%#x, fifo-size:%#x(%#x/%#x)\n",
379 __func__, mep->name, mep->fifo_addr, mep->fifo_size,
380 fifo_sgsz, mep->fifo_seg_size);
381
382 return 0;
383 }
384
385 /* for non-ep0 */
386 void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep)
387 {
388 void __iomem *mbase = mtu->mac_base;
389 int epnum = mep->epnum;
390
391 if (mep->is_in) {
392 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), 0);
393 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), 0);
394 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), 0);
395 mtu3_setbits(mbase, U3D_QIECR0, QMU_TX_DONE_INT(epnum));
396 } else {
397 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), 0);
398 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), 0);
399 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), 0);
400 mtu3_setbits(mbase, U3D_QIECR0, QMU_RX_DONE_INT(epnum));
401 }
402
403 ep_fifo_free(mep);
404
405 dev_dbg(mtu->dev, "%s: %s\n", __func__, mep->name);
406 }
407
408 /*
409 * Two scenarios:
410 * 1. when device IP supports SS, the fifo of EP0, TX EPs, RX EPs
411 * are separated;
412 * 2. when supports only HS, the fifo is shared for all EPs, and
413 * the capability registers of @EPNTXFFSZ or @EPNRXFFSZ indicate
414 * the total fifo size of non-ep0, and ep0's is fixed to 64B,
415 * so the total fifo size is 64B + @EPNTXFFSZ;
416 * Due to the first 64B should be reserved for EP0, non-ep0's fifo
417 * starts from offset 64 and are divided into two equal parts for
418 * TX or RX EPs for simplification.
419 */
420 static void get_ep_fifo_config(struct mtu3 *mtu)
421 {
422 struct mtu3_fifo_info *tx_fifo;
423 struct mtu3_fifo_info *rx_fifo;
424 u32 fifosize;
425
426 if (mtu->is_u3_ip) {
427 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
428 tx_fifo = &mtu->tx_fifo;
429 tx_fifo->base = 0;
430 tx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
431 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
432
433 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNRXFFSZ);
434 rx_fifo = &mtu->rx_fifo;
435 rx_fifo->base = 0;
436 rx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
437 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
438 mtu->slot = MTU3_U3_IP_SLOT_DEFAULT;
439 } else {
440 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
441 tx_fifo = &mtu->tx_fifo;
442 tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE;
443 tx_fifo->limit = (fifosize / MTU3_EP_FIFO_UNIT) >> 1;
444 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
445
446 rx_fifo = &mtu->rx_fifo;
447 rx_fifo->base =
448 tx_fifo->base + tx_fifo->limit * MTU3_EP_FIFO_UNIT;
449 rx_fifo->limit = tx_fifo->limit;
450 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
451 mtu->slot = MTU3_U2_IP_SLOT_DEFAULT;
452 }
453
454 dev_dbg(mtu->dev, "%s, TX: base-%d, limit-%d; RX: base-%d, limit-%d\n",
455 __func__, tx_fifo->base, tx_fifo->limit,
456 rx_fifo->base, rx_fifo->limit);
457 }
458
459 void mtu3_ep0_setup(struct mtu3 *mtu)
460 {
461 u32 maxpacket = mtu->g.ep0->maxpacket;
462 u32 csr;
463
464 dev_dbg(mtu->dev, "%s maxpacket: %d\n", __func__, maxpacket);
465
466 csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR);
467 csr &= ~EP0_MAXPKTSZ_MSK;
468 csr |= EP0_MAXPKTSZ(maxpacket);
469 csr &= EP0_W1C_BITS;
470 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);
471
472 /* Enable EP0 interrupt */
473 mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR);
474 }
475
476 static int mtu3_mem_alloc(struct mtu3 *mtu)
477 {
478 void __iomem *mbase = mtu->mac_base;
479 struct mtu3_ep *ep_array;
480 int in_ep_num, out_ep_num;
481 u32 cap_epinfo;
482 int ret;
483 int i;
484
485 cap_epinfo = mtu3_readl(mbase, U3D_CAP_EPINFO);
486 in_ep_num = CAP_TX_EP_NUM(cap_epinfo);
487 out_ep_num = CAP_RX_EP_NUM(cap_epinfo);
488
489 dev_info(mtu->dev, "fifosz/epnum: Tx=%#x/%d, Rx=%#x/%d\n",
490 mtu3_readl(mbase, U3D_CAP_EPNTXFFSZ), in_ep_num,
491 mtu3_readl(mbase, U3D_CAP_EPNRXFFSZ), out_ep_num);
492
493 /* one for ep0, another is reserved */
494 mtu->num_eps = min(in_ep_num, out_ep_num) + 1;
495 ep_array = kcalloc(mtu->num_eps * 2, sizeof(*ep_array), GFP_KERNEL);
496 if (ep_array == NULL)
497 return -ENOMEM;
498
499 mtu->ep_array = ep_array;
500 mtu->in_eps = ep_array;
501 mtu->out_eps = &ep_array[mtu->num_eps];
502 /* ep0 uses in_eps[0], out_eps[0] is reserved */
503 mtu->ep0 = mtu->in_eps;
504 mtu->ep0->mtu = mtu;
505 mtu->ep0->epnum = 0;
506
507 for (i = 1; i < mtu->num_eps; i++) {
508 struct mtu3_ep *mep = mtu->in_eps + i;
509
510 mep->fifo = &mtu->tx_fifo;
511 mep = mtu->out_eps + i;
512 mep->fifo = &mtu->rx_fifo;
513 }
514
515 get_ep_fifo_config(mtu);
516
517 ret = mtu3_qmu_init(mtu);
518 if (ret)
519 kfree(mtu->ep_array);
520
521 return ret;
522 }
523
524 static void mtu3_mem_free(struct mtu3 *mtu)
525 {
526 mtu3_qmu_exit(mtu);
527 kfree(mtu->ep_array);
528 }
529
530 static void mtu3_set_speed(struct mtu3 *mtu)
531 {
532 void __iomem *mbase = mtu->mac_base;
533
534 if (!mtu->is_u3_ip && (mtu->max_speed > USB_SPEED_HIGH))
535 mtu->max_speed = USB_SPEED_HIGH;
536
537 if (mtu->max_speed == USB_SPEED_FULL) {
538 /* disable U3 SS function */
539 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
540 /* disable HS function */
541 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
542 } else if (mtu->max_speed == USB_SPEED_HIGH) {
543 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
544 /* HS/FS detected by HW */
545 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
546 } else if (mtu->max_speed == USB_SPEED_SUPER) {
547 mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
548 SSUSB_U3_PORT_SSP_SPEED);
549 }
550
551 dev_info(mtu->dev, "max_speed: %s\n",
552 usb_speed_string(mtu->max_speed));
553 }
554
555 static void mtu3_regs_init(struct mtu3 *mtu)
556 {
557
558 void __iomem *mbase = mtu->mac_base;
559
560 /* be sure interrupts are disabled before registration of ISR */
561 mtu3_intr_disable(mtu);
562 mtu3_intr_status_clear(mtu);
563
564 if (mtu->is_u3_ip) {
565 /* disable LGO_U1/U2 by default */
566 mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL,
567 SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE |
568 SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE);
569 /* device responses to u3_exit from host automatically */
570 mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
571 /* automatically build U2 link when U3 detect fail */
572 mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH);
573 }
574
575 mtu3_set_speed(mtu);
576
577 /* delay about 0.1us from detecting reset to send chirp-K */
578 mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK);
579 /* U2/U3 detected by HW */
580 mtu3_writel(mbase, U3D_DEVICE_CONF, 0);
581 /* enable QMU 16B checksum */
582 mtu3_setbits(mbase, U3D_QCR0, QMU_CS16B_EN);
583 /* vbus detected by HW */
584 mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON);
585 }
586
587 static irqreturn_t mtu3_link_isr(struct mtu3 *mtu)
588 {
589 void __iomem *mbase = mtu->mac_base;
590 enum usb_device_speed udev_speed;
591 u32 maxpkt = 64;
592 u32 link;
593 u32 speed;
594
595 link = mtu3_readl(mbase, U3D_DEV_LINK_INTR);
596 link &= mtu3_readl(mbase, U3D_DEV_LINK_INTR_ENABLE);
597 mtu3_writel(mbase, U3D_DEV_LINK_INTR, link); /* W1C */
598 dev_dbg(mtu->dev, "=== LINK[%x] ===\n", link);
599
600 if (!(link & SSUSB_DEV_SPEED_CHG_INTR))
601 return IRQ_NONE;
602
603 speed = SSUSB_DEV_SPEED(mtu3_readl(mbase, U3D_DEVICE_CONF));
604
605 switch (speed) {
606 case MTU3_SPEED_FULL:
607 udev_speed = USB_SPEED_FULL;
608 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
609 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
610 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
611 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
612 LPM_BESL_STALL | LPM_BESLD_STALL);
613 break;
614 case MTU3_SPEED_HIGH:
615 udev_speed = USB_SPEED_HIGH;
616 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
617 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
618 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
619 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
620 LPM_BESL_STALL | LPM_BESLD_STALL);
621 break;
622 case MTU3_SPEED_SUPER:
623 udev_speed = USB_SPEED_SUPER;
624 maxpkt = 512;
625 break;
626 case MTU3_SPEED_SUPER_PLUS:
627 udev_speed = USB_SPEED_SUPER_PLUS;
628 maxpkt = 512;
629 break;
630 default:
631 udev_speed = USB_SPEED_UNKNOWN;
632 break;
633 }
634 dev_dbg(mtu->dev, "%s: %s\n", __func__, usb_speed_string(udev_speed));
635
636 mtu->g.speed = udev_speed;
637 mtu->g.ep0->maxpacket = maxpkt;
638 mtu->ep0_state = MU3D_EP0_STATE_SETUP;
639
640 if (udev_speed == USB_SPEED_UNKNOWN)
641 mtu3_gadget_disconnect(mtu);
642 else
643 mtu3_ep0_setup(mtu);
644
645 return IRQ_HANDLED;
646 }
647
648 static irqreturn_t mtu3_u3_ltssm_isr(struct mtu3 *mtu)
649 {
650 void __iomem *mbase = mtu->mac_base;
651 u32 ltssm;
652
653 ltssm = mtu3_readl(mbase, U3D_LTSSM_INTR);
654 ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE);
655 mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm); /* W1C */
656 dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm);
657
658 if (ltssm & (HOT_RST_INTR | WARM_RST_INTR))
659 mtu3_gadget_reset(mtu);
660
661 if (ltssm & VBUS_FALL_INTR)
662 mtu3_ss_func_set(mtu, false);
663
664 if (ltssm & VBUS_RISE_INTR)
665 mtu3_ss_func_set(mtu, true);
666
667 if (ltssm & EXIT_U3_INTR)
668 mtu3_gadget_resume(mtu);
669
670 if (ltssm & ENTER_U3_INTR)
671 mtu3_gadget_suspend(mtu);
672
673 return IRQ_HANDLED;
674 }
675
676 static irqreturn_t mtu3_u2_common_isr(struct mtu3 *mtu)
677 {
678 void __iomem *mbase = mtu->mac_base;
679 u32 u2comm;
680
681 u2comm = mtu3_readl(mbase, U3D_COMMON_USB_INTR);
682 u2comm &= mtu3_readl(mbase, U3D_COMMON_USB_INTR_ENABLE);
683 mtu3_writel(mbase, U3D_COMMON_USB_INTR, u2comm); /* W1C */
684 dev_dbg(mtu->dev, "=== U2COMM[%x] ===\n", u2comm);
685
686 if (u2comm & SUSPEND_INTR)
687 mtu3_gadget_suspend(mtu);
688
689 if (u2comm & RESUME_INTR)
690 mtu3_gadget_resume(mtu);
691
692 if (u2comm & RESET_INTR)
693 mtu3_gadget_reset(mtu);
694
695 return IRQ_HANDLED;
696 }
697
698 static irqreturn_t mtu3_irq(int irq, void *data)
699 {
700 struct mtu3 *mtu = (struct mtu3 *)data;
701 unsigned long flags;
702 u32 level1;
703
704 spin_lock_irqsave(&mtu->lock, flags);
705
706 /* U3D_LV1ISR is RU */
707 level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR);
708 level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER);
709
710 if (level1 & EP_CTRL_INTR)
711 mtu3_link_isr(mtu);
712
713 if (level1 & MAC2_INTR)
714 mtu3_u2_common_isr(mtu);
715
716 if (level1 & MAC3_INTR)
717 mtu3_u3_ltssm_isr(mtu);
718
719 if (level1 & BMU_INTR)
720 mtu3_ep0_isr(mtu);
721
722 if (level1 & QMU_INTR)
723 mtu3_qmu_isr(mtu);
724
725 spin_unlock_irqrestore(&mtu->lock, flags);
726
727 return IRQ_HANDLED;
728 }
729
730 static int mtu3_hw_init(struct mtu3 *mtu)
731 {
732 u32 cap_dev;
733 int ret;
734
735 mtu->hw_version = mtu3_readl(mtu->ippc_base, U3D_SSUSB_HW_ID);
736
737 cap_dev = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP);
738 mtu->is_u3_ip = !!SSUSB_IP_DEV_U3_PORT_NUM(cap_dev);
739
740 dev_info(mtu->dev, "IP version 0x%x(%s IP)\n", mtu->hw_version,
741 mtu->is_u3_ip ? "U3" : "U2");
742
743 mtu3_device_reset(mtu);
744
745 ret = mtu3_device_enable(mtu);
746 if (ret) {
747 dev_err(mtu->dev, "device enable failed %d\n", ret);
748 return ret;
749 }
750
751 ret = mtu3_mem_alloc(mtu);
752 if (ret)
753 return -ENOMEM;
754
755 mtu3_regs_init(mtu);
756
757 return 0;
758 }
759
760 static void mtu3_hw_exit(struct mtu3 *mtu)
761 {
762 mtu3_device_disable(mtu);
763 mtu3_mem_free(mtu);
764 }
765
766 /**
767 * we set 32-bit DMA mask by default, here check whether the controller
768 * supports 36-bit DMA or not, if it does, set 36-bit DMA mask.
769 */
770 static int mtu3_set_dma_mask(struct mtu3 *mtu)
771 {
772 struct device *dev = mtu->dev;
773 bool is_36bit = false;
774 int ret = 0;
775 u32 value;
776
777 value = mtu3_readl(mtu->mac_base, U3D_MISC_CTRL);
778 if (value & DMA_ADDR_36BIT) {
779 is_36bit = true;
780 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
781 /* If set 36-bit DMA mask fails, fall back to 32-bit DMA mask */
782 if (ret) {
783 is_36bit = false;
784 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
785 }
786 }
787 dev_info(dev, "dma mask: %s bits\n", is_36bit ? "36" : "32");
788
789 return ret;
790 }
791
792 int ssusb_gadget_init(struct ssusb_mtk *ssusb)
793 {
794 struct device *dev = ssusb->dev;
795 struct platform_device *pdev = to_platform_device(dev);
796 struct mtu3 *mtu = NULL;
797 struct resource *res;
798 int ret = -ENOMEM;
799
800 mtu = devm_kzalloc(dev, sizeof(struct mtu3), GFP_KERNEL);
801 if (mtu == NULL)
802 return -ENOMEM;
803
804 mtu->irq = platform_get_irq(pdev, 0);
805 if (mtu->irq < 0) {
806 dev_err(dev, "fail to get irq number\n");
807 return mtu->irq;
808 }
809 dev_info(dev, "irq %d\n", mtu->irq);
810
811 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
812 mtu->mac_base = devm_ioremap_resource(dev, res);
813 if (IS_ERR(mtu->mac_base)) {
814 dev_err(dev, "error mapping memory for dev mac\n");
815 return PTR_ERR(mtu->mac_base);
816 }
817
818 spin_lock_init(&mtu->lock);
819 mtu->dev = dev;
820 mtu->ippc_base = ssusb->ippc_base;
821 ssusb->mac_base = mtu->mac_base;
822 ssusb->u3d = mtu;
823 mtu->ssusb = ssusb;
824 mtu->max_speed = usb_get_maximum_speed(dev);
825
826 /* check the max_speed parameter */
827 switch (mtu->max_speed) {
828 case USB_SPEED_FULL:
829 case USB_SPEED_HIGH:
830 case USB_SPEED_SUPER:
831 case USB_SPEED_SUPER_PLUS:
832 break;
833 default:
834 dev_err(dev, "invalid max_speed: %s\n",
835 usb_speed_string(mtu->max_speed));
836 /* fall through */
837 case USB_SPEED_UNKNOWN:
838 /* default as SSP */
839 mtu->max_speed = USB_SPEED_SUPER_PLUS;
840 break;
841 }
842
843 dev_dbg(dev, "mac_base=0x%p, ippc_base=0x%p\n",
844 mtu->mac_base, mtu->ippc_base);
845
846 ret = mtu3_hw_init(mtu);
847 if (ret) {
848 dev_err(dev, "mtu3 hw init failed:%d\n", ret);
849 return ret;
850 }
851
852 ret = mtu3_set_dma_mask(mtu);
853 if (ret) {
854 dev_err(dev, "mtu3 set dma_mask failed:%d\n", ret);
855 goto dma_mask_err;
856 }
857
858 ret = devm_request_irq(dev, mtu->irq, mtu3_irq, 0, dev_name(dev), mtu);
859 if (ret) {
860 dev_err(dev, "request irq %d failed!\n", mtu->irq);
861 goto irq_err;
862 }
863
864 device_init_wakeup(dev, true);
865
866 ret = mtu3_gadget_setup(mtu);
867 if (ret) {
868 dev_err(dev, "mtu3 gadget init failed:%d\n", ret);
869 goto gadget_err;
870 }
871
872 /* init as host mode, power down device IP for power saving */
873 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
874 mtu3_stop(mtu);
875
876 dev_dbg(dev, " %s() done...\n", __func__);
877
878 return 0;
879
880 gadget_err:
881 device_init_wakeup(dev, false);
882
883 dma_mask_err:
884 irq_err:
885 mtu3_hw_exit(mtu);
886 ssusb->u3d = NULL;
887 dev_err(dev, " %s() fail...\n", __func__);
888
889 return ret;
890 }
891
892 void ssusb_gadget_exit(struct ssusb_mtk *ssusb)
893 {
894 struct mtu3 *mtu = ssusb->u3d;
895
896 mtu3_gadget_cleanup(mtu);
897 device_init_wakeup(ssusb->dev, false);
898 mtu3_hw_exit(mtu);
899 }
CRIS linux kernel tree