2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 * DMA Coherent API Notes
12 * I/O is inherently non-coherent on ARC. So a coherent DMA buffer is
13 * implemented by accessintg it using a kernel virtual address, with
14 * Cache bit off in the TLB entry.
16 * The default DMA address == Phy address which is 0x8000_0000 based.
19 #include <linux/dma-mapping.h>
20 #include <linux/dma-debug.h>
21 #include <linux/export.h>
22 #include <asm/cache.h>
23 #include <asm/cacheflush.h>
26 * Helpers for Coherent DMA API.
28 void *dma_alloc_noncoherent(struct device
*dev
, size_t size
,
29 dma_addr_t
*dma_handle
, gfp_t gfp
)
33 /* This is linear addr (0x8000_0000 based) */
34 paddr
= alloc_pages_exact(size
, gfp
);
38 /* This is bus address, platform dependent */
39 *dma_handle
= (dma_addr_t
)paddr
;
43 EXPORT_SYMBOL(dma_alloc_noncoherent
);
45 void dma_free_noncoherent(struct device
*dev
, size_t size
, void *vaddr
,
46 dma_addr_t dma_handle
)
48 free_pages_exact((void *)dma_handle
, size
);
50 EXPORT_SYMBOL(dma_free_noncoherent
);
52 void *dma_alloc_coherent(struct device
*dev
, size_t size
,
53 dma_addr_t
*dma_handle
, gfp_t gfp
)
58 * IOC relies on all data (even coherent DMA data) being in cache
59 * Thus allocate normal cached memory
61 * The gains with IOC are two pronged:
62 * -For streaming data, elides needs for cache maintenance, saving
63 * cycles in flush code, and bus bandwidth as all the lines of a
64 * buffer need to be flushed out to memory
65 * -For coherent data, Read/Write to buffers terminate early in cache
66 * (vs. always going to memory - thus are faster)
68 if (is_isa_arcv2() && ioc_exists
)
69 return dma_alloc_noncoherent(dev
, size
, dma_handle
, gfp
);
71 /* This is linear addr (0x8000_0000 based) */
72 paddr
= alloc_pages_exact(size
, gfp
);
76 /* This is kernel Virtual address (0x7000_0000 based) */
77 kvaddr
= ioremap_nocache((unsigned long)paddr
, size
);
81 /* This is bus address, platform dependent */
82 *dma_handle
= (dma_addr_t
)paddr
;
85 * Evict any existing L1 and/or L2 lines for the backing page
86 * in case it was used earlier as a normal "cached" page.
87 * Yeah this bit us - STAR 9000898266
89 * Although core does call flush_cache_vmap(), it gets kvaddr hence
90 * can't be used to efficiently flush L1 and/or L2 which need paddr
91 * Currently flush_cache_vmap nukes the L1 cache completely which
92 * will be optimized as a separate commit
94 dma_cache_wback_inv((unsigned long)paddr
, size
);
98 EXPORT_SYMBOL(dma_alloc_coherent
);
100 void dma_free_coherent(struct device
*dev
, size_t size
, void *kvaddr
,
101 dma_addr_t dma_handle
)
103 if (is_isa_arcv2() && ioc_exists
)
104 return dma_free_noncoherent(dev
, size
, kvaddr
, dma_handle
);
106 iounmap((void __force __iomem
*)kvaddr
);
108 free_pages_exact((void *)dma_handle
, size
);
110 EXPORT_SYMBOL(dma_free_coherent
);
113 * Helper for streaming DMA...
115 void __arc_dma_cache_sync(unsigned long paddr
, size_t size
,
116 enum dma_data_direction dir
)
118 __inline_dma_cache_sync(paddr
, size
, dir
);
120 EXPORT_SYMBOL(__arc_dma_cache_sync
);