2 * Device Tree file for Marvell Armada 388 evaluation board
5 * Copyright (C) 2014 Marvell
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
14 * a) This file is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of the
17 * License, or (at your option) any later version.
19 * This file is distributed in the hope that it will be useful
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
38 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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49 #include "armada-388.dtsi"
52 model = "Marvell Armada 385 Development Board";
53 compatible = "marvell,a385-db", "marvell,armada388",
54 "marvell,armada385", "marvell,armada380";
57 stdout-path = "serial0:115200n8";
61 device_type = "memory";
62 reg = <0x00000000 0x10000000>; /* 256 MB */
66 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
67 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
76 compatible = "w25q32", "jedec,spi-nor";
77 reg = <0>; /* Chip select 0 */
78 spi-max-frequency = <108000000>;
84 clock-frequency = <100000>;
89 clock-frequency = <100000>;
99 phy-mode = "rgmii-id";
109 phy-mode = "rgmii-id";
113 phy0: ethernet-phy@0 {
117 phy1: ethernet-phy@1 {
133 marvell,nand-keep-config;
134 marvell,nand-enable-arbiter;
136 nand-ecc-strength = <4>;
137 nand-ecc-step-size = <512>;
145 reg = <0x800000 0x800000>;
148 label = "Filesystem";
149 reg = <0x1000000 0x3f000000>;
173 * The two PCIe units are accessible through
174 * standard PCIe slots on the board.