| blob | 63a48490e2f9653ff83f7f6202fd993d101b6ec9 |
1 /*
2 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 *
13 * Or, alternatively,
14 *
15 * b) Permission is hereby granted, free of charge, to any person
16 * obtaining a copy of this software and associated documentation
17 * files (the "Software"), to deal in the Software without
18 * restriction, including without limitation the rights to use,
19 * copy, modify, merge, publish, distribute, sublicense, and/or
20 * sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following
22 * conditions:
23 *
24 * The above copyright notice and this permission notice shall be
25 * included in all copies or substantial portions of the Software.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
29 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
31 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
32 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
33 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
34 * OTHER DEALINGS IN THE SOFTWARE.
35 */
37 #include <dt-bindings/clock/berlin2q.h>
38 #include <dt-bindings/interrupt-controller/arm-gic.h>
40 #include "skeleton.dtsi"
42 / {
43 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
44 compatible = "marvell,berlin2q", "marvell,berlin";
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49 enable-method = "marvell,berlin-smp";
51 cpu@0 {
52 compatible = "arm,cortex-a9";
53 device_type = "cpu";
54 next-level-cache = <&l2>;
55 reg = <0>;
56 };
58 cpu@1 {
59 compatible = "arm,cortex-a9";
60 device_type = "cpu";
61 next-level-cache = <&l2>;
62 reg = <1>;
63 };
65 cpu@2 {
66 compatible = "arm,cortex-a9";
67 device_type = "cpu";
68 next-level-cache = <&l2>;
69 reg = <2>;
70 };
72 cpu@3 {
73 compatible = "arm,cortex-a9";
74 device_type = "cpu";
75 next-level-cache = <&l2>;
76 reg = <3>;
77 };
78 };
80 refclk: oscillator {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <25000000>;
84 };
86 soc {
87 compatible = "simple-bus";
88 #address-cells = <1>;
89 #size-cells = <1>;
91 ranges = <0 0xf7000000 0x1000000>;
92 interrupt-parent = <&gic>;
94 pmu {
95 compatible = "arm,cortex-a9-pmu";
96 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
100 };
102 sdhci0: sdhci@ab0000 {
103 compatible = "mrvl,pxav3-mmc";
104 reg = <0xab0000 0x200>;
105 clocks = <&chip_clk CLKID_SDIO1XIN>;
106 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
107 status = "disabled";
108 };
110 sdhci1: sdhci@ab0800 {
111 compatible = "mrvl,pxav3-mmc";
112 reg = <0xab0800 0x200>;
113 clocks = <&chip_clk CLKID_SDIO1XIN>;
114 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
115 status = "disabled";
116 };
118 sdhci2: sdhci@ab1000 {
119 compatible = "mrvl,pxav3-mmc";
120 reg = <0xab1000 0x200>;
121 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
122 clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;
123 clock-names = "io", "core";
124 status = "disabled";
125 };
127 l2: l2-cache-controller@ac0000 {
128 compatible = "arm,pl310-cache";
129 reg = <0xac0000 0x1000>;
130 cache-level = <2>;
131 arm,data-latency = <2 2 2>;
132 arm,tag-latency = <2 2 2>;
133 };
135 scu: snoop-control-unit@ad0000 {
136 compatible = "arm,cortex-a9-scu";
137 reg = <0xad0000 0x58>;
138 };
140 local-timer@ad0600 {
141 compatible = "arm,cortex-a9-twd-timer";
142 reg = <0xad0600 0x20>;
143 clocks = <&chip_clk CLKID_TWD>;
144 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
145 };
147 gic: interrupt-controller@ad1000 {
148 compatible = "arm,cortex-a9-gic";
149 reg = <0xad1000 0x1000>, <0xad0100 0x100>;
150 interrupt-controller;
151 #interrupt-cells = <3>;
152 };
154 usb_phy2: phy@a2f400 {
155 compatible = "marvell,berlin2-usb-phy";
156 reg = <0xa2f400 0x128>;
157 #phy-cells = <0>;
158 resets = <&chip_rst 0x104 14>;
159 status = "disabled";
160 };
162 usb2: usb@a30000 {
163 compatible = "chipidea,usb2";
164 reg = <0xa30000 0x10000>;
165 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
166 clocks = <&chip_clk CLKID_USB2>;
167 phys = <&usb_phy2>;
168 phy-names = "usb-phy";
169 status = "disabled";
170 };
172 usb_phy0: phy@b74000 {
173 compatible = "marvell,berlin2-usb-phy";
174 reg = <0xb74000 0x128>;
175 #phy-cells = <0>;
176 resets = <&chip_rst 0x104 12>;
177 status = "disabled";
178 };
180 usb_phy1: phy@b78000 {
181 compatible = "marvell,berlin2-usb-phy";
182 reg = <0xb78000 0x128>;
183 #phy-cells = <0>;
184 resets = <&chip_rst 0x104 13>;
185 status = "disabled";
186 };
188 eth0: ethernet@b90000 {
189 compatible = "marvell,pxa168-eth";
190 reg = <0xb90000 0x10000>;
191 clocks = <&chip_clk CLKID_GETH0>;
192 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
193 /* set by bootloader */
194 local-mac-address = [00 00 00 00 00 00];
195 #address-cells = <1>;
196 #size-cells = <0>;
197 phy-connection-type = "mii";
198 phy-handle = <ðphy0>;
199 status = "disabled";
201 ethphy0: ethernet-phy@0 {
202 reg = <0>;
203 };
204 };
206 cpu-ctrl@dd0000 {
207 compatible = "marvell,berlin-cpu-ctrl";
208 reg = <0xdd0000 0x10000>;
209 };
211 apb@e80000 {
212 compatible = "simple-bus";
213 #address-cells = <1>;
214 #size-cells = <1>;
216 ranges = <0 0xe80000 0x10000>;
217 interrupt-parent = <&aic>;
219 gpio0: gpio@0400 {
220 compatible = "snps,dw-apb-gpio";
221 reg = <0x0400 0x400>;
222 #address-cells = <1>;
223 #size-cells = <0>;
225 porta: gpio-port@0 {
226 compatible = "snps,dw-apb-gpio-port";
227 gpio-controller;
228 #gpio-cells = <2>;
229 snps,nr-gpios = <32>;
230 reg = <0>;
231 interrupt-controller;
232 #interrupt-cells = <2>;
233 interrupts = <0>;
234 };
235 };
237 gpio1: gpio@0800 {
238 compatible = "snps,dw-apb-gpio";
239 reg = <0x0800 0x400>;
240 #address-cells = <1>;
241 #size-cells = <0>;
243 portb: gpio-port@1 {
244 compatible = "snps,dw-apb-gpio-port";
245 gpio-controller;
246 #gpio-cells = <2>;
247 snps,nr-gpios = <32>;
248 reg = <0>;
249 interrupt-controller;
250 #interrupt-cells = <2>;
251 interrupts = <1>;
252 };
253 };
255 gpio2: gpio@0c00 {
256 compatible = "snps,dw-apb-gpio";
257 reg = <0x0c00 0x400>;
258 #address-cells = <1>;
259 #size-cells = <0>;
261 portc: gpio-port@2 {
262 compatible = "snps,dw-apb-gpio-port";
263 gpio-controller;
264 #gpio-cells = <2>;
265 snps,nr-gpios = <32>;
266 reg = <0>;
267 interrupt-controller;
268 #interrupt-cells = <2>;
269 interrupts = <2>;
270 };
271 };
273 gpio3: gpio@1000 {
274 compatible = "snps,dw-apb-gpio";
275 reg = <0x1000 0x400>;
276 #address-cells = <1>;
277 #size-cells = <0>;
279 portd: gpio-port@3 {
280 compatible = "snps,dw-apb-gpio-port";
281 gpio-controller;
282 #gpio-cells = <2>;
283 snps,nr-gpios = <32>;
284 reg = <0>;
285 interrupt-controller;
286 #interrupt-cells = <2>;
287 interrupts = <3>;
288 };
289 };
291 i2c0: i2c@1400 {
292 compatible = "snps,designware-i2c";
293 #address-cells = <1>;
294 #size-cells = <0>;
295 reg = <0x1400 0x100>;
296 interrupt-parent = <&aic>;
297 interrupts = <4>;
298 clocks = <&chip_clk CLKID_CFG>;
299 pinctrl-0 = <&twsi0_pmux>;
300 pinctrl-names = "default";
301 status = "disabled";
302 };
304 i2c1: i2c@1800 {
305 compatible = "snps,designware-i2c";
306 #address-cells = <1>;
307 #size-cells = <0>;
308 reg = <0x1800 0x100>;
309 interrupt-parent = <&aic>;
310 interrupts = <5>;
311 clocks = <&chip_clk CLKID_CFG>;
312 pinctrl-0 = <&twsi1_pmux>;
313 pinctrl-names = "default";
314 status = "disabled";
315 };
317 timer0: timer@2c00 {
318 compatible = "snps,dw-apb-timer";
319 reg = <0x2c00 0x14>;
320 clocks = <&chip_clk CLKID_CFG>;
321 clock-names = "timer";
322 interrupts = <8>;
323 };
325 timer1: timer@2c14 {
326 compatible = "snps,dw-apb-timer";
327 reg = <0x2c14 0x14>;
328 clocks = <&chip_clk CLKID_CFG>;
329 clock-names = "timer";
330 };
332 timer2: timer@2c28 {
333 compatible = "snps,dw-apb-timer";
334 reg = <0x2c28 0x14>;
335 clocks = <&chip_clk CLKID_CFG>;
336 clock-names = "timer";
337 status = "disabled";
338 };
340 timer3: timer@2c3c {
341 compatible = "snps,dw-apb-timer";
342 reg = <0x2c3c 0x14>;
343 clocks = <&chip_clk CLKID_CFG>;
344 clock-names = "timer";
345 status = "disabled";
346 };
348 timer4: timer@2c50 {
349 compatible = "snps,dw-apb-timer";
350 reg = <0x2c50 0x14>;
351 clocks = <&chip_clk CLKID_CFG>;
352 clock-names = "timer";
353 status = "disabled";
354 };
356 timer5: timer@2c64 {
357 compatible = "snps,dw-apb-timer";
358 reg = <0x2c64 0x14>;
359 clocks = <&chip_clk CLKID_CFG>;
360 clock-names = "timer";
361 status = "disabled";
362 };
364 timer6: timer@2c78 {
365 compatible = "snps,dw-apb-timer";
366 reg = <0x2c78 0x14>;
367 clocks = <&chip_clk CLKID_CFG>;
368 clock-names = "timer";
369 status = "disabled";
370 };
372 timer7: timer@2c8c {
373 compatible = "snps,dw-apb-timer";
374 reg = <0x2c8c 0x14>;
375 clocks = <&chip_clk CLKID_CFG>;
376 clock-names = "timer";
377 status = "disabled";
378 };
380 aic: interrupt-controller@3800 {
381 compatible = "snps,dw-apb-ictl";
382 reg = <0x3800 0x30>;
383 interrupt-controller;
384 #interrupt-cells = <1>;
385 interrupt-parent = <&gic>;
386 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
387 };
388 };
390 chip: chip-control@ea0000 {
391 compatible = "simple-mfd", "syscon";
392 reg = <0xea0000 0x400>, <0xdd0170 0x10>;
394 chip_clk: clock {
395 compatible = "marvell,berlin2q-clk";
396 #clock-cells = <1>;
397 clocks = <&refclk>;
398 clock-names = "refclk";
399 };
401 soc_pinctrl: pin-controller {
402 compatible = "marvell,berlin2q-soc-pinctrl";
404 twsi0_pmux: twsi0-pmux {
405 groups = "G6";
406 function = "twsi0";
407 };
409 twsi1_pmux: twsi1-pmux {
410 groups = "G7";
411 function = "twsi1";
412 };
413 };
415 chip_rst: reset {
416 compatible = "marvell,berlin2-reset";
417 #reset-cells = <2>;
418 };
419 };
421 ahci: sata@e90000 {
422 compatible = "marvell,berlin2q-ahci", "generic-ahci";
423 reg = <0xe90000 0x1000>;
424 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&chip_clk CLKID_SATA>;
426 #address-cells = <1>;
427 #size-cells = <0>;
429 sata0: sata-port@0 {
430 reg = <0>;
431 phys = <&sata_phy 0>;
432 status = "disabled";
433 };
435 sata1: sata-port@1 {
436 reg = <1>;
437 phys = <&sata_phy 1>;
438 status = "disabled";
439 };
440 };
442 sata_phy: phy@e900a0 {
443 compatible = "marvell,berlin2q-sata-phy";
444 reg = <0xe900a0 0x200>;
445 clocks = <&chip_clk CLKID_SATA>;
446 #address-cells = <1>;
447 #size-cells = <0>;
448 #phy-cells = <1>;
449 status = "disabled";
451 sata-phy@0 {
452 reg = <0>;
453 };
455 sata-phy@1 {
456 reg = <1>;
457 };
458 };
460 usb0: usb@ed0000 {
461 compatible = "chipidea,usb2";
462 reg = <0xed0000 0x10000>;
463 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&chip_clk CLKID_USB0>;
465 phys = <&usb_phy0>;
466 phy-names = "usb-phy";
467 status = "disabled";
468 };
470 usb1: usb@ee0000 {
471 compatible = "chipidea,usb2";
472 reg = <0xee0000 0x10000>;
473 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&chip_clk CLKID_USB1>;
475 phys = <&usb_phy1>;
476 phy-names = "usb-phy";
477 status = "disabled";
478 };
480 apb@fc0000 {
481 compatible = "simple-bus";
482 #address-cells = <1>;
483 #size-cells = <1>;
485 ranges = <0 0xfc0000 0x10000>;
486 interrupt-parent = <&sic>;
488 sm_gpio1: gpio@5000 {
489 compatible = "snps,dw-apb-gpio";
490 reg = <0x5000 0x400>;
491 #address-cells = <1>;
492 #size-cells = <0>;
494 portf: gpio-port@5 {
495 compatible = "snps,dw-apb-gpio-port";
496 gpio-controller;
497 #gpio-cells = <2>;
498 snps,nr-gpios = <32>;
499 reg = <0>;
500 };
501 };
503 i2c2: i2c@7000 {
504 compatible = "snps,designware-i2c";
505 #address-cells = <1>;
506 #size-cells = <0>;
507 reg = <0x7000 0x100>;
508 interrupt-parent = <&sic>;
509 interrupts = <6>;
510 clocks = <&refclk>;
511 pinctrl-0 = <&twsi2_pmux>;
512 pinctrl-names = "default";
513 status = "disabled";
514 };
516 i2c3: i2c@8000 {
517 compatible = "snps,designware-i2c";
518 #address-cells = <1>;
519 #size-cells = <0>;
520 reg = <0x8000 0x100>;
521 interrupt-parent = <&sic>;
522 interrupts = <7>;
523 clocks = <&refclk>;
524 pinctrl-0 = <&twsi3_pmux>;
525 pinctrl-names = "default";
526 status = "disabled";
527 };
529 uart0: uart@9000 {
530 compatible = "snps,dw-apb-uart";
531 reg = <0x9000 0x100>;
532 interrupt-parent = <&sic>;
533 interrupts = <8>;
534 clocks = <&refclk>;
535 reg-shift = <2>;
536 pinctrl-0 = <&uart0_pmux>;
537 pinctrl-names = "default";
538 status = "disabled";
539 };
541 uart1: uart@a000 {
542 compatible = "snps,dw-apb-uart";
543 reg = <0xa000 0x100>;
544 interrupt-parent = <&sic>;
545 interrupts = <9>;
546 clocks = <&refclk>;
547 reg-shift = <2>;
548 pinctrl-0 = <&uart1_pmux>;
549 pinctrl-names = "default";
550 status = "disabled";
551 };
553 sm_gpio0: gpio@c000 {
554 compatible = "snps,dw-apb-gpio";
555 reg = <0xc000 0x400>;
556 #address-cells = <1>;
557 #size-cells = <0>;
559 porte: gpio-port@4 {
560 compatible = "snps,dw-apb-gpio-port";
561 gpio-controller;
562 #gpio-cells = <2>;
563 snps,nr-gpios = <32>;
564 reg = <0>;
565 };
566 };
568 sysctrl: pin-controller@d000 {
569 compatible = "simple-mfd", "syscon";
570 reg = <0xd000 0x100>;
572 sys_pinctrl: pin-controller {
573 compatible = "marvell,berlin2q-system-pinctrl";
575 uart0_pmux: uart0-pmux {
576 groups = "GSM12";
577 function = "uart0";
578 };
580 uart1_pmux: uart1-pmux {
581 groups = "GSM14";
582 function = "uart1";
583 };
585 twsi2_pmux: twsi2-pmux {
586 groups = "GSM13";
587 function = "twsi2";
588 };
590 twsi3_pmux: twsi3-pmux {
591 groups = "GSM14";
592 function = "twsi3";
593 };
594 };
596 adc: adc {
597 compatible = "marvell,berlin2-adc";
598 interrupts = <12>, <14>;
599 interrupt-names = "adc", "tsen";
600 };
601 };
603 sic: interrupt-controller@e000 {
604 compatible = "snps,dw-apb-ictl";
605 reg = <0xe000 0x30>;
606 interrupt-controller;
607 #interrupt-cells = <1>;
608 interrupt-parent = <&gic>;
609 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
610 };
611 };
612 };
613 };