| blob | b24610ea8c2a93619bfe75770b63d1b67b61d680 |
1 /*
2 * SAMSUNG EXYNOS5250 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
20 #include <dt-bindings/clock/exynos5250.h>
21 #include "exynos5.dtsi"
22 #include "exynos4-cpu-thermal.dtsi"
23 #include <dt-bindings/clock/exynos-audss-clk.h>
25 / {
26 compatible = "samsung,exynos5250", "samsung,exynos5";
28 aliases {
29 spi0 = &spi_0;
30 spi1 = &spi_1;
31 spi2 = &spi_2;
32 gsc0 = &gsc_0;
33 gsc1 = &gsc_1;
34 gsc2 = &gsc_2;
35 gsc3 = &gsc_3;
36 mshc0 = &mmc_0;
37 mshc1 = &mmc_1;
38 mshc2 = &mmc_2;
39 mshc3 = &mmc_3;
40 i2c0 = &i2c_0;
41 i2c1 = &i2c_1;
42 i2c2 = &i2c_2;
43 i2c3 = &i2c_3;
44 i2c4 = &i2c_4;
45 i2c5 = &i2c_5;
46 i2c6 = &i2c_6;
47 i2c7 = &i2c_7;
48 i2c8 = &i2c_8;
49 i2c9 = &i2c_9;
50 pinctrl0 = &pinctrl_0;
51 pinctrl1 = &pinctrl_1;
52 pinctrl2 = &pinctrl_2;
53 pinctrl3 = &pinctrl_3;
54 };
56 cpus {
57 #address-cells = <1>;
58 #size-cells = <0>;
60 cpu0: cpu@0 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a15";
63 reg = <0>;
64 clock-frequency = <1700000000>;
65 clocks = <&clock CLK_ARM_CLK>;
66 clock-names = "cpu";
67 clock-latency = <140000>;
69 operating-points = <
70 1700000 1300000
71 1600000 1250000
72 1500000 1225000
73 1400000 1200000
74 1300000 1150000
75 1200000 1125000
76 1100000 1100000
77 1000000 1075000
78 900000 1050000
79 800000 1025000
80 700000 1012500
81 600000 1000000
82 500000 975000
83 400000 950000
84 300000 937500
85 200000 925000
86 >;
87 cooling-min-level = <15>;
88 cooling-max-level = <9>;
89 #cooling-cells = <2>; /* min followed by max */
90 };
91 cpu@1 {
92 device_type = "cpu";
93 compatible = "arm,cortex-a15";
94 reg = <1>;
95 clock-frequency = <1700000000>;
96 };
97 };
99 sysram@02020000 {
100 compatible = "mmio-sram";
101 reg = <0x02020000 0x30000>;
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges = <0 0x02020000 0x30000>;
106 smp-sysram@0 {
107 compatible = "samsung,exynos4210-sysram";
108 reg = <0x0 0x1000>;
109 };
111 smp-sysram@2f000 {
112 compatible = "samsung,exynos4210-sysram-ns";
113 reg = <0x2f000 0x1000>;
114 };
115 };
117 pd_gsc: gsc-power-domain@10044000 {
118 compatible = "samsung,exynos4210-pd";
119 reg = <0x10044000 0x20>;
120 #power-domain-cells = <0>;
121 };
123 pd_mfc: mfc-power-domain@10044040 {
124 compatible = "samsung,exynos4210-pd";
125 reg = <0x10044040 0x20>;
126 #power-domain-cells = <0>;
127 };
129 pd_disp1: disp1-power-domain@100440A0 {
130 compatible = "samsung,exynos4210-pd";
131 reg = <0x100440A0 0x20>;
132 #power-domain-cells = <0>;
133 };
135 clock: clock-controller@10010000 {
136 compatible = "samsung,exynos5250-clock";
137 reg = <0x10010000 0x30000>;
138 #clock-cells = <1>;
139 };
141 clock_audss: audss-clock-controller@3810000 {
142 compatible = "samsung,exynos5250-audss-clock";
143 reg = <0x03810000 0x0C>;
144 #clock-cells = <1>;
145 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
146 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
147 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
148 };
150 timer {
151 compatible = "arm,armv7-timer";
152 interrupts = <1 13 0xf08>,
153 <1 14 0xf08>,
154 <1 11 0xf08>,
155 <1 10 0xf08>;
156 /* Unfortunately we need this since some versions of U-Boot
157 * on Exynos don't set the CNTFRQ register, so we need the
158 * value from DT.
159 */
160 clock-frequency = <24000000>;
161 };
163 mct@101C0000 {
164 compatible = "samsung,exynos4210-mct";
165 reg = <0x101C0000 0x800>;
166 interrupt-controller;
167 #interrupt-cells = <2>;
168 interrupt-parent = <&mct_map>;
169 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
170 <4 0>, <5 0>;
171 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
172 clock-names = "fin_pll", "mct";
174 mct_map: mct-map {
175 #interrupt-cells = <2>;
176 #address-cells = <0>;
177 #size-cells = <0>;
178 interrupt-map = <0x0 0 &combiner 23 3>,
179 <0x1 0 &combiner 23 4>,
180 <0x2 0 &combiner 25 2>,
181 <0x3 0 &combiner 25 3>,
182 <0x4 0 &gic 0 120 0>,
183 <0x5 0 &gic 0 121 0>;
184 };
185 };
187 pmu {
188 compatible = "arm,cortex-a15-pmu";
189 interrupt-parent = <&combiner>;
190 interrupts = <1 2>, <22 4>;
191 };
193 pinctrl_0: pinctrl@11400000 {
194 compatible = "samsung,exynos5250-pinctrl";
195 reg = <0x11400000 0x1000>;
196 interrupts = <0 46 0>;
198 wakup_eint: wakeup-interrupt-controller {
199 compatible = "samsung,exynos4210-wakeup-eint";
200 interrupt-parent = <&gic>;
201 interrupts = <0 32 0>;
202 };
203 };
205 pinctrl_1: pinctrl@13400000 {
206 compatible = "samsung,exynos5250-pinctrl";
207 reg = <0x13400000 0x1000>;
208 interrupts = <0 45 0>;
209 };
211 pinctrl_2: pinctrl@10d10000 {
212 compatible = "samsung,exynos5250-pinctrl";
213 reg = <0x10d10000 0x1000>;
214 interrupts = <0 50 0>;
215 };
217 pinctrl_3: pinctrl@03860000 {
218 compatible = "samsung,exynos5250-pinctrl";
219 reg = <0x03860000 0x1000>;
220 interrupts = <0 47 0>;
221 };
223 pmu_system_controller: system-controller@10040000 {
224 compatible = "samsung,exynos5250-pmu", "syscon";
225 reg = <0x10040000 0x5000>;
226 clock-names = "clkout16";
227 clocks = <&clock CLK_FIN_PLL>;
228 #clock-cells = <1>;
229 interrupt-controller;
230 #interrupt-cells = <3>;
231 interrupt-parent = <&gic>;
232 };
234 sysreg_system_controller: syscon@10050000 {
235 compatible = "samsung,exynos5-sysreg", "syscon";
236 reg = <0x10050000 0x5000>;
237 };
239 watchdog@101D0000 {
240 compatible = "samsung,exynos5250-wdt";
241 reg = <0x101D0000 0x100>;
242 interrupts = <0 42 0>;
243 clocks = <&clock CLK_WDT>;
244 clock-names = "watchdog";
245 samsung,syscon-phandle = <&pmu_system_controller>;
246 };
248 g2d@10850000 {
249 compatible = "samsung,exynos5250-g2d";
250 reg = <0x10850000 0x1000>;
251 interrupts = <0 91 0>;
252 clocks = <&clock CLK_G2D>;
253 clock-names = "fimg2d";
254 iommus = <&sysmmu_g2d>;
255 };
257 mfc: codec@11000000 {
258 compatible = "samsung,mfc-v6";
259 reg = <0x11000000 0x10000>;
260 interrupts = <0 96 0>;
261 power-domains = <&pd_mfc>;
262 clocks = <&clock CLK_MFC>;
263 clock-names = "mfc";
264 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
265 iommu-names = "left", "right";
266 };
268 tmu: tmu@10060000 {
269 compatible = "samsung,exynos5250-tmu";
270 reg = <0x10060000 0x100>;
271 interrupts = <0 65 0>;
272 clocks = <&clock CLK_TMU>;
273 clock-names = "tmu_apbif";
274 #include "exynos4412-tmu-sensor-conf.dtsi"
275 };
277 thermal-zones {
278 cpu_thermal: cpu-thermal {
279 polling-delay-passive = <0>;
280 polling-delay = <0>;
281 thermal-sensors = <&tmu 0>;
283 cooling-maps {
284 map0 {
285 /* Corresponds to 800MHz at freq_table */
286 cooling-device = <&cpu0 9 9>;
287 };
288 map1 {
289 /* Corresponds to 200MHz at freq_table */
290 cooling-device = <&cpu0 15 15>;
291 };
292 };
293 };
294 };
296 sata: sata@122F0000 {
297 compatible = "snps,dwc-ahci";
298 samsung,sata-freq = <66>;
299 reg = <0x122F0000 0x1ff>;
300 interrupts = <0 115 0>;
301 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
302 clock-names = "sata", "sclk_sata";
303 phys = <&sata_phy>;
304 phy-names = "sata-phy";
305 status = "disabled";
306 };
308 sata_phy: sata-phy@12170000 {
309 compatible = "samsung,exynos5250-sata-phy";
310 reg = <0x12170000 0x1ff>;
311 clocks = <&clock CLK_SATA_PHYCTRL>;
312 clock-names = "sata_phyctrl";
313 #phy-cells = <0>;
314 samsung,syscon-phandle = <&pmu_system_controller>;
315 status = "disabled";
316 };
318 i2c_0: i2c@12C60000 {
319 compatible = "samsung,s3c2440-i2c";
320 reg = <0x12C60000 0x100>;
321 interrupts = <0 56 0>;
322 #address-cells = <1>;
323 #size-cells = <0>;
324 clocks = <&clock CLK_I2C0>;
325 clock-names = "i2c";
326 pinctrl-names = "default";
327 pinctrl-0 = <&i2c0_bus>;
328 samsung,sysreg-phandle = <&sysreg_system_controller>;
329 status = "disabled";
330 };
332 i2c_1: i2c@12C70000 {
333 compatible = "samsung,s3c2440-i2c";
334 reg = <0x12C70000 0x100>;
335 interrupts = <0 57 0>;
336 #address-cells = <1>;
337 #size-cells = <0>;
338 clocks = <&clock CLK_I2C1>;
339 clock-names = "i2c";
340 pinctrl-names = "default";
341 pinctrl-0 = <&i2c1_bus>;
342 samsung,sysreg-phandle = <&sysreg_system_controller>;
343 status = "disabled";
344 };
346 i2c_2: i2c@12C80000 {
347 compatible = "samsung,s3c2440-i2c";
348 reg = <0x12C80000 0x100>;
349 interrupts = <0 58 0>;
350 #address-cells = <1>;
351 #size-cells = <0>;
352 clocks = <&clock CLK_I2C2>;
353 clock-names = "i2c";
354 pinctrl-names = "default";
355 pinctrl-0 = <&i2c2_bus>;
356 samsung,sysreg-phandle = <&sysreg_system_controller>;
357 status = "disabled";
358 };
360 i2c_3: i2c@12C90000 {
361 compatible = "samsung,s3c2440-i2c";
362 reg = <0x12C90000 0x100>;
363 interrupts = <0 59 0>;
364 #address-cells = <1>;
365 #size-cells = <0>;
366 clocks = <&clock CLK_I2C3>;
367 clock-names = "i2c";
368 pinctrl-names = "default";
369 pinctrl-0 = <&i2c3_bus>;
370 samsung,sysreg-phandle = <&sysreg_system_controller>;
371 status = "disabled";
372 };
374 i2c_4: i2c@12CA0000 {
375 compatible = "samsung,s3c2440-i2c";
376 reg = <0x12CA0000 0x100>;
377 interrupts = <0 60 0>;
378 #address-cells = <1>;
379 #size-cells = <0>;
380 clocks = <&clock CLK_I2C4>;
381 clock-names = "i2c";
382 pinctrl-names = "default";
383 pinctrl-0 = <&i2c4_bus>;
384 status = "disabled";
385 };
387 i2c_5: i2c@12CB0000 {
388 compatible = "samsung,s3c2440-i2c";
389 reg = <0x12CB0000 0x100>;
390 interrupts = <0 61 0>;
391 #address-cells = <1>;
392 #size-cells = <0>;
393 clocks = <&clock CLK_I2C5>;
394 clock-names = "i2c";
395 pinctrl-names = "default";
396 pinctrl-0 = <&i2c5_bus>;
397 status = "disabled";
398 };
400 i2c_6: i2c@12CC0000 {
401 compatible = "samsung,s3c2440-i2c";
402 reg = <0x12CC0000 0x100>;
403 interrupts = <0 62 0>;
404 #address-cells = <1>;
405 #size-cells = <0>;
406 clocks = <&clock CLK_I2C6>;
407 clock-names = "i2c";
408 pinctrl-names = "default";
409 pinctrl-0 = <&i2c6_bus>;
410 status = "disabled";
411 };
413 i2c_7: i2c@12CD0000 {
414 compatible = "samsung,s3c2440-i2c";
415 reg = <0x12CD0000 0x100>;
416 interrupts = <0 63 0>;
417 #address-cells = <1>;
418 #size-cells = <0>;
419 clocks = <&clock CLK_I2C7>;
420 clock-names = "i2c";
421 pinctrl-names = "default";
422 pinctrl-0 = <&i2c7_bus>;
423 status = "disabled";
424 };
426 i2c_8: i2c@12CE0000 {
427 compatible = "samsung,s3c2440-hdmiphy-i2c";
428 reg = <0x12CE0000 0x1000>;
429 interrupts = <0 64 0>;
430 #address-cells = <1>;
431 #size-cells = <0>;
432 clocks = <&clock CLK_I2C_HDMI>;
433 clock-names = "i2c";
434 status = "disabled";
435 };
437 i2c_9: i2c@121D0000 {
438 compatible = "samsung,exynos5-sata-phy-i2c";
439 reg = <0x121D0000 0x100>;
440 #address-cells = <1>;
441 #size-cells = <0>;
442 clocks = <&clock CLK_SATA_PHYI2C>;
443 clock-names = "i2c";
444 status = "disabled";
445 };
447 spi_0: spi@12d20000 {
448 compatible = "samsung,exynos4210-spi";
449 status = "disabled";
450 reg = <0x12d20000 0x100>;
451 interrupts = <0 66 0>;
452 dmas = <&pdma0 5
453 &pdma0 4>;
454 dma-names = "tx", "rx";
455 #address-cells = <1>;
456 #size-cells = <0>;
457 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
458 clock-names = "spi", "spi_busclk0";
459 pinctrl-names = "default";
460 pinctrl-0 = <&spi0_bus>;
461 };
463 spi_1: spi@12d30000 {
464 compatible = "samsung,exynos4210-spi";
465 status = "disabled";
466 reg = <0x12d30000 0x100>;
467 interrupts = <0 67 0>;
468 dmas = <&pdma1 5
469 &pdma1 4>;
470 dma-names = "tx", "rx";
471 #address-cells = <1>;
472 #size-cells = <0>;
473 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
474 clock-names = "spi", "spi_busclk0";
475 pinctrl-names = "default";
476 pinctrl-0 = <&spi1_bus>;
477 };
479 spi_2: spi@12d40000 {
480 compatible = "samsung,exynos4210-spi";
481 status = "disabled";
482 reg = <0x12d40000 0x100>;
483 interrupts = <0 68 0>;
484 dmas = <&pdma0 7
485 &pdma0 6>;
486 dma-names = "tx", "rx";
487 #address-cells = <1>;
488 #size-cells = <0>;
489 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
490 clock-names = "spi", "spi_busclk0";
491 pinctrl-names = "default";
492 pinctrl-0 = <&spi2_bus>;
493 };
495 mmc_0: mmc@12200000 {
496 compatible = "samsung,exynos5250-dw-mshc";
497 interrupts = <0 75 0>;
498 #address-cells = <1>;
499 #size-cells = <0>;
500 reg = <0x12200000 0x1000>;
501 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
502 clock-names = "biu", "ciu";
503 fifo-depth = <0x80>;
504 status = "disabled";
505 };
507 mmc_1: mmc@12210000 {
508 compatible = "samsung,exynos5250-dw-mshc";
509 interrupts = <0 76 0>;
510 #address-cells = <1>;
511 #size-cells = <0>;
512 reg = <0x12210000 0x1000>;
513 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
514 clock-names = "biu", "ciu";
515 fifo-depth = <0x80>;
516 status = "disabled";
517 };
519 mmc_2: mmc@12220000 {
520 compatible = "samsung,exynos5250-dw-mshc";
521 interrupts = <0 77 0>;
522 #address-cells = <1>;
523 #size-cells = <0>;
524 reg = <0x12220000 0x1000>;
525 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
526 clock-names = "biu", "ciu";
527 fifo-depth = <0x80>;
528 status = "disabled";
529 };
531 mmc_3: mmc@12230000 {
532 compatible = "samsung,exynos5250-dw-mshc";
533 reg = <0x12230000 0x1000>;
534 interrupts = <0 78 0>;
535 #address-cells = <1>;
536 #size-cells = <0>;
537 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
538 clock-names = "biu", "ciu";
539 fifo-depth = <0x80>;
540 status = "disabled";
541 };
543 i2s0: i2s@03830000 {
544 compatible = "samsung,s5pv210-i2s";
545 status = "disabled";
546 reg = <0x03830000 0x100>;
547 dmas = <&pdma0 10
548 &pdma0 9
549 &pdma0 8>;
550 dma-names = "tx", "rx", "tx-sec";
551 clocks = <&clock_audss EXYNOS_I2S_BUS>,
552 <&clock_audss EXYNOS_I2S_BUS>,
553 <&clock_audss EXYNOS_SCLK_I2S>;
554 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
555 samsung,idma-addr = <0x03000000>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&i2s0_bus>;
558 };
560 i2s1: i2s@12D60000 {
561 compatible = "samsung,s3c6410-i2s";
562 status = "disabled";
563 reg = <0x12D60000 0x100>;
564 dmas = <&pdma1 12
565 &pdma1 11>;
566 dma-names = "tx", "rx";
567 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
568 clock-names = "iis", "i2s_opclk0";
569 pinctrl-names = "default";
570 pinctrl-0 = <&i2s1_bus>;
571 };
573 i2s2: i2s@12D70000 {
574 compatible = "samsung,s3c6410-i2s";
575 status = "disabled";
576 reg = <0x12D70000 0x100>;
577 dmas = <&pdma0 12
578 &pdma0 11>;
579 dma-names = "tx", "rx";
580 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
581 clock-names = "iis", "i2s_opclk0";
582 pinctrl-names = "default";
583 pinctrl-0 = <&i2s2_bus>;
584 };
586 usb@12000000 {
587 compatible = "samsung,exynos5250-dwusb3";
588 clocks = <&clock CLK_USB3>;
589 clock-names = "usbdrd30";
590 #address-cells = <1>;
591 #size-cells = <1>;
592 ranges;
594 usbdrd_dwc3: dwc3 {
595 compatible = "synopsys,dwc3";
596 reg = <0x12000000 0x10000>;
597 interrupts = <0 72 0>;
598 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
599 phy-names = "usb2-phy", "usb3-phy";
600 };
601 };
603 usbdrd_phy: phy@12100000 {
604 compatible = "samsung,exynos5250-usbdrd-phy";
605 reg = <0x12100000 0x100>;
606 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
607 clock-names = "phy", "ref";
608 samsung,pmu-syscon = <&pmu_system_controller>;
609 #phy-cells = <1>;
610 };
612 ehci: usb@12110000 {
613 compatible = "samsung,exynos4210-ehci";
614 reg = <0x12110000 0x100>;
615 interrupts = <0 71 0>;
617 clocks = <&clock CLK_USB2>;
618 clock-names = "usbhost";
619 #address-cells = <1>;
620 #size-cells = <0>;
621 port@0 {
622 reg = <0>;
623 phys = <&usb2_phy_gen 1>;
624 };
625 };
627 ohci: usb@12120000 {
628 compatible = "samsung,exynos4210-ohci";
629 reg = <0x12120000 0x100>;
630 interrupts = <0 71 0>;
632 clocks = <&clock CLK_USB2>;
633 clock-names = "usbhost";
634 #address-cells = <1>;
635 #size-cells = <0>;
636 port@0 {
637 reg = <0>;
638 phys = <&usb2_phy_gen 1>;
639 };
640 };
642 usb2_phy_gen: phy@12130000 {
643 compatible = "samsung,exynos5250-usb2-phy";
644 reg = <0x12130000 0x100>;
645 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
646 clock-names = "phy", "ref";
647 #phy-cells = <1>;
648 samsung,sysreg-phandle = <&sysreg_system_controller>;
649 samsung,pmureg-phandle = <&pmu_system_controller>;
650 };
652 pwm: pwm@12dd0000 {
653 compatible = "samsung,exynos4210-pwm";
654 reg = <0x12dd0000 0x100>;
655 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
656 #pwm-cells = <3>;
657 clocks = <&clock CLK_PWM>;
658 clock-names = "timers";
659 };
661 amba {
662 #address-cells = <1>;
663 #size-cells = <1>;
664 compatible = "arm,amba-bus";
665 interrupt-parent = <&gic>;
666 ranges;
668 pdma0: pdma@121A0000 {
669 compatible = "arm,pl330", "arm,primecell";
670 reg = <0x121A0000 0x1000>;
671 interrupts = <0 34 0>;
672 clocks = <&clock CLK_PDMA0>;
673 clock-names = "apb_pclk";
674 #dma-cells = <1>;
675 #dma-channels = <8>;
676 #dma-requests = <32>;
677 };
679 pdma1: pdma@121B0000 {
680 compatible = "arm,pl330", "arm,primecell";
681 reg = <0x121B0000 0x1000>;
682 interrupts = <0 35 0>;
683 clocks = <&clock CLK_PDMA1>;
684 clock-names = "apb_pclk";
685 #dma-cells = <1>;
686 #dma-channels = <8>;
687 #dma-requests = <32>;
688 };
690 mdma0: mdma@10800000 {
691 compatible = "arm,pl330", "arm,primecell";
692 reg = <0x10800000 0x1000>;
693 interrupts = <0 33 0>;
694 clocks = <&clock CLK_MDMA0>;
695 clock-names = "apb_pclk";
696 #dma-cells = <1>;
697 #dma-channels = <8>;
698 #dma-requests = <1>;
699 };
701 mdma1: mdma@11C10000 {
702 compatible = "arm,pl330", "arm,primecell";
703 reg = <0x11C10000 0x1000>;
704 interrupts = <0 124 0>;
705 clocks = <&clock CLK_MDMA1>;
706 clock-names = "apb_pclk";
707 #dma-cells = <1>;
708 #dma-channels = <8>;
709 #dma-requests = <1>;
710 };
711 };
713 gsc_0: gsc@13e00000 {
714 compatible = "samsung,exynos5-gsc";
715 reg = <0x13e00000 0x1000>;
716 interrupts = <0 85 0>;
717 power-domains = <&pd_gsc>;
718 clocks = <&clock CLK_GSCL0>;
719 clock-names = "gscl";
720 iommu = <&sysmmu_gsc0>;
721 };
723 gsc_1: gsc@13e10000 {
724 compatible = "samsung,exynos5-gsc";
725 reg = <0x13e10000 0x1000>;
726 interrupts = <0 86 0>;
727 power-domains = <&pd_gsc>;
728 clocks = <&clock CLK_GSCL1>;
729 clock-names = "gscl";
730 iommu = <&sysmmu_gsc1>;
731 };
733 gsc_2: gsc@13e20000 {
734 compatible = "samsung,exynos5-gsc";
735 reg = <0x13e20000 0x1000>;
736 interrupts = <0 87 0>;
737 power-domains = <&pd_gsc>;
738 clocks = <&clock CLK_GSCL2>;
739 clock-names = "gscl";
740 iommu = <&sysmmu_gsc2>;
741 };
743 gsc_3: gsc@13e30000 {
744 compatible = "samsung,exynos5-gsc";
745 reg = <0x13e30000 0x1000>;
746 interrupts = <0 88 0>;
747 power-domains = <&pd_gsc>;
748 clocks = <&clock CLK_GSCL3>;
749 clock-names = "gscl";
750 iommu = <&sysmmu_gsc3>;
751 };
753 hdmi: hdmi {
754 compatible = "samsung,exynos4212-hdmi";
755 reg = <0x14530000 0x70000>;
756 power-domains = <&pd_disp1>;
757 interrupts = <0 95 0>;
758 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
759 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
760 <&clock CLK_MOUT_HDMI>;
761 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
762 "sclk_hdmiphy", "mout_hdmi";
763 samsung,syscon-phandle = <&pmu_system_controller>;
764 };
766 mixer {
767 compatible = "samsung,exynos5250-mixer";
768 reg = <0x14450000 0x10000>;
769 power-domains = <&pd_disp1>;
770 interrupts = <0 94 0>;
771 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
772 <&clock CLK_SCLK_HDMI>;
773 clock-names = "mixer", "hdmi", "sclk_hdmi";
774 iommus = <&sysmmu_tv>;
775 };
777 dp_phy: video-phy@10040720 {
778 compatible = "samsung,exynos5250-dp-video-phy";
779 samsung,pmu-syscon = <&pmu_system_controller>;
780 #phy-cells = <0>;
781 };
783 adc: adc@12D10000 {
784 compatible = "samsung,exynos-adc-v1";
785 reg = <0x12D10000 0x100>;
786 interrupts = <0 106 0>;
787 clocks = <&clock CLK_ADC>;
788 clock-names = "adc";
789 #io-channel-cells = <1>;
790 io-channel-ranges;
791 samsung,syscon-phandle = <&pmu_system_controller>;
792 status = "disabled";
793 };
795 sss@10830000 {
796 compatible = "samsung,exynos4210-secss";
797 reg = <0x10830000 0x10000>;
798 interrupts = <0 112 0>;
799 clocks = <&clock CLK_SSS>;
800 clock-names = "secss";
801 };
803 sysmmu_g2d: sysmmu@10A60000 {
804 compatible = "samsung,exynos-sysmmu";
805 reg = <0x10A60000 0x1000>;
806 interrupt-parent = <&combiner>;
807 interrupts = <24 5>;
808 clock-names = "sysmmu", "master";
809 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
810 #iommu-cells = <0>;
811 };
813 sysmmu_mfc_r: sysmmu@11200000 {
814 compatible = "samsung,exynos-sysmmu";
815 reg = <0x11200000 0x1000>;
816 interrupt-parent = <&combiner>;
817 interrupts = <6 2>;
818 power-domains = <&pd_mfc>;
819 clock-names = "sysmmu", "master";
820 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
821 #iommu-cells = <0>;
822 };
824 sysmmu_mfc_l: sysmmu@11210000 {
825 compatible = "samsung,exynos-sysmmu";
826 reg = <0x11210000 0x1000>;
827 interrupt-parent = <&combiner>;
828 interrupts = <8 5>;
829 power-domains = <&pd_mfc>;
830 clock-names = "sysmmu", "master";
831 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
832 #iommu-cells = <0>;
833 };
835 sysmmu_rotator: sysmmu@11D40000 {
836 compatible = "samsung,exynos-sysmmu";
837 reg = <0x11D40000 0x1000>;
838 interrupt-parent = <&combiner>;
839 interrupts = <4 0>;
840 clock-names = "sysmmu", "master";
841 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
842 #iommu-cells = <0>;
843 };
845 sysmmu_jpeg: sysmmu@11F20000 {
846 compatible = "samsung,exynos-sysmmu";
847 reg = <0x11F20000 0x1000>;
848 interrupt-parent = <&combiner>;
849 interrupts = <4 2>;
850 power-domains = <&pd_gsc>;
851 clock-names = "sysmmu", "master";
852 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
853 #iommu-cells = <0>;
854 };
856 sysmmu_fimc_isp: sysmmu@13260000 {
857 compatible = "samsung,exynos-sysmmu";
858 reg = <0x13260000 0x1000>;
859 interrupt-parent = <&combiner>;
860 interrupts = <10 6>;
861 clock-names = "sysmmu";
862 clocks = <&clock CLK_SMMU_FIMC_ISP>;
863 #iommu-cells = <0>;
864 };
866 sysmmu_fimc_drc: sysmmu@13270000 {
867 compatible = "samsung,exynos-sysmmu";
868 reg = <0x13270000 0x1000>;
869 interrupt-parent = <&combiner>;
870 interrupts = <11 6>;
871 clock-names = "sysmmu";
872 clocks = <&clock CLK_SMMU_FIMC_DRC>;
873 #iommu-cells = <0>;
874 };
876 sysmmu_fimc_fd: sysmmu@132A0000 {
877 compatible = "samsung,exynos-sysmmu";
878 reg = <0x132A0000 0x1000>;
879 interrupt-parent = <&combiner>;
880 interrupts = <5 0>;
881 clock-names = "sysmmu";
882 clocks = <&clock CLK_SMMU_FIMC_FD>;
883 #iommu-cells = <0>;
884 };
886 sysmmu_fimc_scc: sysmmu@13280000 {
887 compatible = "samsung,exynos-sysmmu";
888 reg = <0x13280000 0x1000>;
889 interrupt-parent = <&combiner>;
890 interrupts = <5 2>;
891 clock-names = "sysmmu";
892 clocks = <&clock CLK_SMMU_FIMC_SCC>;
893 #iommu-cells = <0>;
894 };
896 sysmmu_fimc_scp: sysmmu@13290000 {
897 compatible = "samsung,exynos-sysmmu";
898 reg = <0x13290000 0x1000>;
899 interrupt-parent = <&combiner>;
900 interrupts = <3 6>;
901 clock-names = "sysmmu";
902 clocks = <&clock CLK_SMMU_FIMC_SCP>;
903 #iommu-cells = <0>;
904 };
906 sysmmu_fimc_mcuctl: sysmmu@132B0000 {
907 compatible = "samsung,exynos-sysmmu";
908 reg = <0x132B0000 0x1000>;
909 interrupt-parent = <&combiner>;
910 interrupts = <5 4>;
911 clock-names = "sysmmu";
912 clocks = <&clock CLK_SMMU_FIMC_MCU>;
913 #iommu-cells = <0>;
914 };
916 sysmmu_fimc_odc: sysmmu@132C0000 {
917 compatible = "samsung,exynos-sysmmu";
918 reg = <0x132C0000 0x1000>;
919 interrupt-parent = <&combiner>;
920 interrupts = <11 0>;
921 clock-names = "sysmmu";
922 clocks = <&clock CLK_SMMU_FIMC_ODC>;
923 #iommu-cells = <0>;
924 };
926 sysmmu_fimc_dis0: sysmmu@132D0000 {
927 compatible = "samsung,exynos-sysmmu";
928 reg = <0x132D0000 0x1000>;
929 interrupt-parent = <&combiner>;
930 interrupts = <10 4>;
931 clock-names = "sysmmu";
932 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
933 #iommu-cells = <0>;
934 };
936 sysmmu_fimc_dis1: sysmmu@132E0000{
937 compatible = "samsung,exynos-sysmmu";
938 reg = <0x132E0000 0x1000>;
939 interrupt-parent = <&combiner>;
940 interrupts = <9 4>;
941 clock-names = "sysmmu";
942 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
943 #iommu-cells = <0>;
944 };
946 sysmmu_fimc_3dnr: sysmmu@132F0000 {
947 compatible = "samsung,exynos-sysmmu";
948 reg = <0x132F0000 0x1000>;
949 interrupt-parent = <&combiner>;
950 interrupts = <5 6>;
951 clock-names = "sysmmu";
952 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
953 #iommu-cells = <0>;
954 };
956 sysmmu_fimc_lite0: sysmmu@13C40000 {
957 compatible = "samsung,exynos-sysmmu";
958 reg = <0x13C40000 0x1000>;
959 interrupt-parent = <&combiner>;
960 interrupts = <3 4>;
961 power-domains = <&pd_gsc>;
962 clock-names = "sysmmu", "master";
963 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
964 #iommu-cells = <0>;
965 };
967 sysmmu_fimc_lite1: sysmmu@13C50000 {
968 compatible = "samsung,exynos-sysmmu";
969 reg = <0x13C50000 0x1000>;
970 interrupt-parent = <&combiner>;
971 interrupts = <24 1>;
972 power-domains = <&pd_gsc>;
973 clock-names = "sysmmu", "master";
974 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
975 #iommu-cells = <0>;
976 };
978 sysmmu_gsc0: sysmmu@13E80000 {
979 compatible = "samsung,exynos-sysmmu";
980 reg = <0x13E80000 0x1000>;
981 interrupt-parent = <&combiner>;
982 interrupts = <2 0>;
983 power-domains = <&pd_gsc>;
984 clock-names = "sysmmu", "master";
985 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
986 #iommu-cells = <0>;
987 };
989 sysmmu_gsc1: sysmmu@13E90000 {
990 compatible = "samsung,exynos-sysmmu";
991 reg = <0x13E90000 0x1000>;
992 interrupt-parent = <&combiner>;
993 interrupts = <2 2>;
994 power-domains = <&pd_gsc>;
995 clock-names = "sysmmu", "master";
996 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
997 #iommu-cells = <0>;
998 };
1000 sysmmu_gsc2: sysmmu@13EA0000 {
1001 compatible = "samsung,exynos-sysmmu";
1002 reg = <0x13EA0000 0x1000>;
1003 interrupt-parent = <&combiner>;
1004 interrupts = <2 4>;
1005 power-domains = <&pd_gsc>;
1006 clock-names = "sysmmu", "master";
1007 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
1008 #iommu-cells = <0>;
1009 };
1011 sysmmu_gsc3: sysmmu@13EB0000 {
1012 compatible = "samsung,exynos-sysmmu";
1013 reg = <0x13EB0000 0x1000>;
1014 interrupt-parent = <&combiner>;
1015 interrupts = <2 6>;
1016 power-domains = <&pd_gsc>;
1017 clock-names = "sysmmu", "master";
1018 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
1019 #iommu-cells = <0>;
1020 };
1022 sysmmu_fimd1: sysmmu@14640000 {
1023 compatible = "samsung,exynos-sysmmu";
1024 reg = <0x14640000 0x1000>;
1025 interrupt-parent = <&combiner>;
1026 interrupts = <3 2>;
1027 power-domains = <&pd_disp1>;
1028 clock-names = "sysmmu", "master";
1029 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1030 #iommu-cells = <0>;
1031 };
1033 sysmmu_tv: sysmmu@14650000 {
1034 compatible = "samsung,exynos-sysmmu";
1035 reg = <0x14650000 0x1000>;
1036 interrupt-parent = <&combiner>;
1037 interrupts = <7 4>;
1038 power-domains = <&pd_disp1>;
1039 clock-names = "sysmmu", "master";
1040 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1041 #iommu-cells = <0>;
1042 };
1043 };
1045 &dp {
1046 power-domains = <&pd_disp1>;
1047 clocks = <&clock CLK_DP>;
1048 clock-names = "dp";
1049 phys = <&dp_phy>;
1050 phy-names = "dp";
1051 };
1053 &fimd {
1054 power-domains = <&pd_disp1>;
1055 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1056 clock-names = "sclk_fimd", "fimd";
1057 iommus = <&sysmmu_fimd1>;
1058 };
1060 &rtc {
1061 clocks = <&clock CLK_RTC>;
1062 clock-names = "rtc";
1063 interrupt-parent = <&pmu_system_controller>;
1064 status = "disabled";
1065 };
1067 &serial_0 {
1068 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1069 clock-names = "uart", "clk_uart_baud0";
1070 };
1072 &serial_1 {
1073 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1074 clock-names = "uart", "clk_uart_baud0";
1075 };
1077 &serial_2 {
1078 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1079 clock-names = "uart", "clk_uart_baud0";
1080 };
1082 &serial_3 {
1083 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1084 clock-names = "uart", "clk_uart_baud0";
1085 };
1087 #include "exynos5250-pinctrl.dtsi"