2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include "skeleton.dtsi"
12 #include "imx6sl-pinfunc.h"
13 #include <dt-bindings/clock/imx6sl-clock.h>
41 compatible = "arm,cortex-a9";
44 next-level-cache = <&L2>;
51 fsl,soc-operating-points = <
52 /* ARM kHz SOC-PU uV */
57 clock-latency = <61036>; /* two CLK32 periods */
58 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
59 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
60 <&clks IMX6SL_CLK_PLL1_SYS>;
61 clock-names = "arm", "pll2_pfd2_396m", "step",
62 "pll1_sw", "pll1_sys";
63 arm-supply = <®_arm>;
64 pu-supply = <®_pu>;
65 soc-supply = <®_soc>;
69 intc: interrupt-controller@00a01000 {
70 compatible = "arm,cortex-a9-gic";
71 #interrupt-cells = <3>;
73 reg = <0x00a01000 0x1000>,
75 interrupt-parent = <&intc>;
83 compatible = "fixed-clock";
85 clock-frequency = <32768>;
89 compatible = "fixed-clock";
91 clock-frequency = <24000000>;
98 compatible = "simple-bus";
99 interrupt-parent = <&gpc>;
102 ocram: sram@00900000 {
103 compatible = "mmio-sram";
104 reg = <0x00900000 0x20000>;
105 clocks = <&clks IMX6SL_CLK_OCRAM>;
108 L2: l2-cache@00a02000 {
109 compatible = "arm,pl310-cache";
110 reg = <0x00a02000 0x1000>;
111 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
114 arm,tag-latency = <4 2 3>;
115 arm,data-latency = <4 2 3>;
119 compatible = "arm,cortex-a9-pmu";
120 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
123 aips1: aips-bus@02000000 {
124 compatible = "fsl,aips-bus", "simple-bus";
125 #address-cells = <1>;
127 reg = <0x02000000 0x100000>;
130 spba: spba-bus@02000000 {
131 compatible = "fsl,spba-bus", "simple-bus";
132 #address-cells = <1>;
134 reg = <0x02000000 0x40000>;
137 spdif: spdif@02004000 {
138 reg = <0x02004000 0x4000>;
139 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
142 ecspi1: ecspi@02008000 {
143 #address-cells = <1>;
145 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
146 reg = <0x02008000 0x4000>;
147 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&clks IMX6SL_CLK_ECSPI1>,
149 <&clks IMX6SL_CLK_ECSPI1>;
150 clock-names = "ipg", "per";
154 ecspi2: ecspi@0200c000 {
155 #address-cells = <1>;
157 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
158 reg = <0x0200c000 0x4000>;
159 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&clks IMX6SL_CLK_ECSPI2>,
161 <&clks IMX6SL_CLK_ECSPI2>;
162 clock-names = "ipg", "per";
166 ecspi3: ecspi@02010000 {
167 #address-cells = <1>;
169 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
170 reg = <0x02010000 0x4000>;
171 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&clks IMX6SL_CLK_ECSPI3>,
173 <&clks IMX6SL_CLK_ECSPI3>;
174 clock-names = "ipg", "per";
178 ecspi4: ecspi@02014000 {
179 #address-cells = <1>;
181 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
182 reg = <0x02014000 0x4000>;
183 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&clks IMX6SL_CLK_ECSPI4>,
185 <&clks IMX6SL_CLK_ECSPI4>;
186 clock-names = "ipg", "per";
190 uart5: serial@02018000 {
191 compatible = "fsl,imx6sl-uart",
192 "fsl,imx6q-uart", "fsl,imx21-uart";
193 reg = <0x02018000 0x4000>;
194 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&clks IMX6SL_CLK_UART>,
196 <&clks IMX6SL_CLK_UART_SERIAL>;
197 clock-names = "ipg", "per";
198 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
199 dma-names = "rx", "tx";
203 uart1: serial@02020000 {
204 compatible = "fsl,imx6sl-uart",
205 "fsl,imx6q-uart", "fsl,imx21-uart";
206 reg = <0x02020000 0x4000>;
207 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&clks IMX6SL_CLK_UART>,
209 <&clks IMX6SL_CLK_UART_SERIAL>;
210 clock-names = "ipg", "per";
211 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
212 dma-names = "rx", "tx";
216 uart2: serial@02024000 {
217 compatible = "fsl,imx6sl-uart",
218 "fsl,imx6q-uart", "fsl,imx21-uart";
219 reg = <0x02024000 0x4000>;
220 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&clks IMX6SL_CLK_UART>,
222 <&clks IMX6SL_CLK_UART_SERIAL>;
223 clock-names = "ipg", "per";
224 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
225 dma-names = "rx", "tx";
230 #sound-dai-cells = <0>;
231 compatible = "fsl,imx6sl-ssi",
233 reg = <0x02028000 0x4000>;
234 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
236 <&clks IMX6SL_CLK_SSI1>;
237 clock-names = "ipg", "baud";
238 dmas = <&sdma 37 1 0>,
240 dma-names = "rx", "tx";
241 fsl,fifo-depth = <15>;
246 #sound-dai-cells = <0>;
247 compatible = "fsl,imx6sl-ssi",
249 reg = <0x0202c000 0x4000>;
250 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
252 <&clks IMX6SL_CLK_SSI2>;
253 clock-names = "ipg", "baud";
254 dmas = <&sdma 41 1 0>,
256 dma-names = "rx", "tx";
257 fsl,fifo-depth = <15>;
262 #sound-dai-cells = <0>;
263 compatible = "fsl,imx6sl-ssi",
265 reg = <0x02030000 0x4000>;
266 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
268 <&clks IMX6SL_CLK_SSI3>;
269 clock-names = "ipg", "baud";
270 dmas = <&sdma 45 1 0>,
272 dma-names = "rx", "tx";
273 fsl,fifo-depth = <15>;
277 uart3: serial@02034000 {
278 compatible = "fsl,imx6sl-uart",
279 "fsl,imx6q-uart", "fsl,imx21-uart";
280 reg = <0x02034000 0x4000>;
281 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&clks IMX6SL_CLK_UART>,
283 <&clks IMX6SL_CLK_UART_SERIAL>;
284 clock-names = "ipg", "per";
285 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
286 dma-names = "rx", "tx";
290 uart4: serial@02038000 {
291 compatible = "fsl,imx6sl-uart",
292 "fsl,imx6q-uart", "fsl,imx21-uart";
293 reg = <0x02038000 0x4000>;
294 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&clks IMX6SL_CLK_UART>,
296 <&clks IMX6SL_CLK_UART_SERIAL>;
297 clock-names = "ipg", "per";
298 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
299 dma-names = "rx", "tx";
306 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
307 reg = <0x02080000 0x4000>;
308 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&clks IMX6SL_CLK_PWM1>,
310 <&clks IMX6SL_CLK_PWM1>;
311 clock-names = "ipg", "per";
316 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
317 reg = <0x02084000 0x4000>;
318 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&clks IMX6SL_CLK_PWM2>,
320 <&clks IMX6SL_CLK_PWM2>;
321 clock-names = "ipg", "per";
326 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
327 reg = <0x02088000 0x4000>;
328 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&clks IMX6SL_CLK_PWM3>,
330 <&clks IMX6SL_CLK_PWM3>;
331 clock-names = "ipg", "per";
336 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
337 reg = <0x0208c000 0x4000>;
338 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&clks IMX6SL_CLK_PWM4>,
340 <&clks IMX6SL_CLK_PWM4>;
341 clock-names = "ipg", "per";
345 compatible = "fsl,imx6sl-gpt";
346 reg = <0x02098000 0x4000>;
347 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&clks IMX6SL_CLK_GPT>,
349 <&clks IMX6SL_CLK_GPT_SERIAL>;
350 clock-names = "ipg", "per";
353 gpio1: gpio@0209c000 {
354 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
355 reg = <0x0209c000 0x4000>;
356 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
357 <0 67 IRQ_TYPE_LEVEL_HIGH>;
360 interrupt-controller;
361 #interrupt-cells = <2>;
364 gpio2: gpio@020a0000 {
365 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
366 reg = <0x020a0000 0x4000>;
367 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
368 <0 69 IRQ_TYPE_LEVEL_HIGH>;
371 interrupt-controller;
372 #interrupt-cells = <2>;
375 gpio3: gpio@020a4000 {
376 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
377 reg = <0x020a4000 0x4000>;
378 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
379 <0 71 IRQ_TYPE_LEVEL_HIGH>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
386 gpio4: gpio@020a8000 {
387 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
388 reg = <0x020a8000 0x4000>;
389 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
390 <0 73 IRQ_TYPE_LEVEL_HIGH>;
393 interrupt-controller;
394 #interrupt-cells = <2>;
397 gpio5: gpio@020ac000 {
398 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
399 reg = <0x020ac000 0x4000>;
400 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
401 <0 75 IRQ_TYPE_LEVEL_HIGH>;
404 interrupt-controller;
405 #interrupt-cells = <2>;
409 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
410 reg = <0x020b8000 0x4000>;
411 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&clks IMX6SL_CLK_DUMMY>;
416 wdog1: wdog@020bc000 {
417 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
418 reg = <0x020bc000 0x4000>;
419 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clks IMX6SL_CLK_DUMMY>;
423 wdog2: wdog@020c0000 {
424 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
425 reg = <0x020c0000 0x4000>;
426 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&clks IMX6SL_CLK_DUMMY>;
432 compatible = "fsl,imx6sl-ccm";
433 reg = <0x020c4000 0x4000>;
434 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
435 <0 88 IRQ_TYPE_LEVEL_HIGH>;
439 anatop: anatop@020c8000 {
440 compatible = "fsl,imx6sl-anatop",
442 "syscon", "simple-bus";
443 reg = <0x020c8000 0x1000>;
444 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
445 <0 54 IRQ_TYPE_LEVEL_HIGH>,
446 <0 127 IRQ_TYPE_LEVEL_HIGH>;
449 compatible = "fsl,anatop-regulator";
450 regulator-name = "vdd1p1";
451 regulator-min-microvolt = <800000>;
452 regulator-max-microvolt = <1375000>;
454 anatop-reg-offset = <0x110>;
455 anatop-vol-bit-shift = <8>;
456 anatop-vol-bit-width = <5>;
457 anatop-min-bit-val = <4>;
458 anatop-min-voltage = <800000>;
459 anatop-max-voltage = <1375000>;
463 compatible = "fsl,anatop-regulator";
464 regulator-name = "vdd3p0";
465 regulator-min-microvolt = <2800000>;
466 regulator-max-microvolt = <3150000>;
468 anatop-reg-offset = <0x120>;
469 anatop-vol-bit-shift = <8>;
470 anatop-vol-bit-width = <5>;
471 anatop-min-bit-val = <0>;
472 anatop-min-voltage = <2625000>;
473 anatop-max-voltage = <3400000>;
477 compatible = "fsl,anatop-regulator";
478 regulator-name = "vdd2p5";
479 regulator-min-microvolt = <2100000>;
480 regulator-max-microvolt = <2850000>;
482 anatop-reg-offset = <0x130>;
483 anatop-vol-bit-shift = <8>;
484 anatop-vol-bit-width = <5>;
485 anatop-min-bit-val = <0>;
486 anatop-min-voltage = <2100000>;
487 anatop-max-voltage = <2850000>;
490 reg_arm: regulator-vddcore@140 {
491 compatible = "fsl,anatop-regulator";
492 regulator-name = "vddarm";
493 regulator-min-microvolt = <725000>;
494 regulator-max-microvolt = <1450000>;
496 anatop-reg-offset = <0x140>;
497 anatop-vol-bit-shift = <0>;
498 anatop-vol-bit-width = <5>;
499 anatop-delay-reg-offset = <0x170>;
500 anatop-delay-bit-shift = <24>;
501 anatop-delay-bit-width = <2>;
502 anatop-min-bit-val = <1>;
503 anatop-min-voltage = <725000>;
504 anatop-max-voltage = <1450000>;
507 reg_pu: regulator-vddpu@140 {
508 compatible = "fsl,anatop-regulator";
509 regulator-name = "vddpu";
510 regulator-min-microvolt = <725000>;
511 regulator-max-microvolt = <1450000>;
513 anatop-reg-offset = <0x140>;
514 anatop-vol-bit-shift = <9>;
515 anatop-vol-bit-width = <5>;
516 anatop-delay-reg-offset = <0x170>;
517 anatop-delay-bit-shift = <26>;
518 anatop-delay-bit-width = <2>;
519 anatop-min-bit-val = <1>;
520 anatop-min-voltage = <725000>;
521 anatop-max-voltage = <1450000>;
524 reg_soc: regulator-vddsoc@140 {
525 compatible = "fsl,anatop-regulator";
526 regulator-name = "vddsoc";
527 regulator-min-microvolt = <725000>;
528 regulator-max-microvolt = <1450000>;
530 anatop-reg-offset = <0x140>;
531 anatop-vol-bit-shift = <18>;
532 anatop-vol-bit-width = <5>;
533 anatop-delay-reg-offset = <0x170>;
534 anatop-delay-bit-shift = <28>;
535 anatop-delay-bit-width = <2>;
536 anatop-min-bit-val = <1>;
537 anatop-min-voltage = <725000>;
538 anatop-max-voltage = <1450000>;
543 compatible = "fsl,imx6q-tempmon";
544 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
545 fsl,tempmon = <&anatop>;
546 fsl,tempmon-data = <&ocotp>;
547 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
550 usbphy1: usbphy@020c9000 {
551 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
552 reg = <0x020c9000 0x1000>;
553 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&clks IMX6SL_CLK_USBPHY1>;
555 fsl,anatop = <&anatop>;
558 usbphy2: usbphy@020ca000 {
559 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
560 reg = <0x020ca000 0x1000>;
561 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&clks IMX6SL_CLK_USBPHY2>;
563 fsl,anatop = <&anatop>;
566 snvs: snvs@020cc000 {
567 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
568 reg = <0x020cc000 0x4000>;
570 snvs_rtc: snvs-rtc-lp {
571 compatible = "fsl,sec-v4.0-mon-rtc-lp";
574 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
575 <0 20 IRQ_TYPE_LEVEL_HIGH>;
578 snvs_poweroff: snvs-poweroff {
579 compatible = "syscon-poweroff";
587 epit1: epit@020d0000 {
588 reg = <0x020d0000 0x4000>;
589 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
592 epit2: epit@020d4000 {
593 reg = <0x020d4000 0x4000>;
594 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
598 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
599 reg = <0x020d8000 0x4000>;
600 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
601 <0 96 IRQ_TYPE_LEVEL_HIGH>;
606 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
607 reg = <0x020dc000 0x4000>;
608 interrupt-controller;
609 #interrupt-cells = <3>;
610 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
611 interrupt-parent = <&intc>;
612 pu-supply = <®_pu>;
613 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
614 <&clks IMX6SL_CLK_GPU2D_PODF>;
615 #power-domain-cells = <1>;
618 gpr: iomuxc-gpr@020e0000 {
619 compatible = "fsl,imx6sl-iomuxc-gpr",
620 "fsl,imx6q-iomuxc-gpr", "syscon";
621 reg = <0x020e0000 0x38>;
624 iomuxc: iomuxc@020e0000 {
625 compatible = "fsl,imx6sl-iomuxc";
626 reg = <0x020e0000 0x4000>;
630 reg = <0x020e4000 0x4000>;
631 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
634 spdc: spdc@020e8000 {
635 reg = <0x020e8000 0x4000>;
636 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
639 sdma: sdma@020ec000 {
640 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
641 reg = <0x020ec000 0x4000>;
642 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&clks IMX6SL_CLK_SDMA>,
644 <&clks IMX6SL_CLK_SDMA>;
645 clock-names = "ipg", "ahb";
647 /* imx6sl reuses imx6q sdma firmware */
648 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
652 reg = <0x020f0000 0x4000>;
653 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
656 epdc: epdc@020f4000 {
657 reg = <0x020f4000 0x4000>;
658 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
661 lcdif: lcdif@020f8000 {
662 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
663 reg = <0x020f8000 0x4000>;
664 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
666 <&clks IMX6SL_CLK_LCDIF_AXI>,
667 <&clks IMX6SL_CLK_DUMMY>;
668 clock-names = "pix", "axi", "disp_axi";
673 reg = <0x020fc000 0x4000>;
674 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
678 aips2: aips-bus@02100000 {
679 compatible = "fsl,aips-bus", "simple-bus";
680 #address-cells = <1>;
682 reg = <0x02100000 0x100000>;
685 usbotg1: usb@02184000 {
686 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
687 reg = <0x02184000 0x200>;
688 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&clks IMX6SL_CLK_USBOH3>;
690 fsl,usbphy = <&usbphy1>;
691 fsl,usbmisc = <&usbmisc 0>;
695 usbotg2: usb@02184200 {
696 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
697 reg = <0x02184200 0x200>;
698 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
699 clocks = <&clks IMX6SL_CLK_USBOH3>;
700 fsl,usbphy = <&usbphy2>;
701 fsl,usbmisc = <&usbmisc 1>;
706 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
707 reg = <0x02184400 0x200>;
708 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&clks IMX6SL_CLK_USBOH3>;
710 fsl,usbmisc = <&usbmisc 2>;
715 usbmisc: usbmisc@02184800 {
717 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
718 reg = <0x02184800 0x200>;
719 clocks = <&clks IMX6SL_CLK_USBOH3>;
722 fec: ethernet@02188000 {
723 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
724 reg = <0x02188000 0x4000>;
725 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&clks IMX6SL_CLK_ENET>,
727 <&clks IMX6SL_CLK_ENET_REF>;
728 clock-names = "ipg", "ahb";
732 usdhc1: usdhc@02190000 {
733 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
734 reg = <0x02190000 0x4000>;
735 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&clks IMX6SL_CLK_USDHC1>,
737 <&clks IMX6SL_CLK_USDHC1>,
738 <&clks IMX6SL_CLK_USDHC1>;
739 clock-names = "ipg", "ahb", "per";
744 usdhc2: usdhc@02194000 {
745 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
746 reg = <0x02194000 0x4000>;
747 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&clks IMX6SL_CLK_USDHC2>,
749 <&clks IMX6SL_CLK_USDHC2>,
750 <&clks IMX6SL_CLK_USDHC2>;
751 clock-names = "ipg", "ahb", "per";
756 usdhc3: usdhc@02198000 {
757 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
758 reg = <0x02198000 0x4000>;
759 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
760 clocks = <&clks IMX6SL_CLK_USDHC3>,
761 <&clks IMX6SL_CLK_USDHC3>,
762 <&clks IMX6SL_CLK_USDHC3>;
763 clock-names = "ipg", "ahb", "per";
768 usdhc4: usdhc@0219c000 {
769 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
770 reg = <0x0219c000 0x4000>;
771 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&clks IMX6SL_CLK_USDHC4>,
773 <&clks IMX6SL_CLK_USDHC4>,
774 <&clks IMX6SL_CLK_USDHC4>;
775 clock-names = "ipg", "ahb", "per";
781 #address-cells = <1>;
783 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
784 reg = <0x021a0000 0x4000>;
785 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&clks IMX6SL_CLK_I2C1>;
791 #address-cells = <1>;
793 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
794 reg = <0x021a4000 0x4000>;
795 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&clks IMX6SL_CLK_I2C2>;
801 #address-cells = <1>;
803 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
804 reg = <0x021a8000 0x4000>;
805 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&clks IMX6SL_CLK_I2C3>;
810 mmdc: mmdc@021b0000 {
811 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
812 reg = <0x021b0000 0x4000>;
815 rngb: rngb@021b4000 {
816 reg = <0x021b4000 0x4000>;
817 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
820 weim: weim@021b8000 {
821 reg = <0x021b8000 0x4000>;
822 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
825 ocotp: ocotp@021bc000 {
826 compatible = "fsl,imx6sl-ocotp", "syscon";
827 reg = <0x021bc000 0x4000>;
830 audmux: audmux@021d8000 {
831 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
832 reg = <0x021d8000 0x4000>;