| blob | 09edbedfd908ec46db4b39e599f28ad00e8d21ab |
1 /*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
9 #include <dt-bindings/clock/imx6ul-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx6ul-pinfunc.h"
13 #include "skeleton.dtsi"
15 / {
16 aliases {
17 ethernet0 = &fec1;
18 ethernet1 = &fec2;
19 gpio0 = &gpio1;
20 gpio1 = &gpio2;
21 gpio2 = &gpio3;
22 gpio3 = &gpio4;
23 gpio4 = &gpio5;
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 mmc0 = &usdhc1;
29 mmc1 = &usdhc2;
30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 serial4 = &uart5;
35 serial5 = &uart6;
36 serial6 = &uart7;
37 serial7 = &uart8;
38 spi0 = &ecspi1;
39 spi1 = &ecspi2;
40 spi2 = &ecspi3;
41 spi3 = &ecspi4;
42 usbphy0 = &usbphy1;
43 usbphy1 = &usbphy2;
44 };
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
50 cpu0: cpu@0 {
51 compatible = "arm,cortex-a7";
52 device_type = "cpu";
53 reg = <0>;
54 clock-latency = <61036>; /* two CLK32 periods */
55 operating-points = <
56 /* kHz uV */
57 528000 1250000
58 396000 1150000
59 198000 1150000
60 >;
61 fsl,soc-operating-points = <
62 /* KHz uV */
63 528000 1250000
64 396000 1150000
65 198000 1150000
66 >;
67 clocks = <&clks IMX6UL_CLK_ARM>,
68 <&clks IMX6UL_CLK_PLL2_BUS>,
69 <&clks IMX6UL_CLK_PLL2_PFD2>,
70 <&clks IMX6UL_CA7_SECONDARY_SEL>,
71 <&clks IMX6UL_CLK_STEP>,
72 <&clks IMX6UL_CLK_PLL1_SW>,
73 <&clks IMX6UL_CLK_PLL1_SYS>,
74 <&clks IMX6UL_PLL1_BYPASS>,
75 <&clks IMX6UL_CLK_PLL1>,
76 <&clks IMX6UL_PLL1_BYPASS_SRC>,
77 <&clks IMX6UL_CLK_OSC>;
78 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
79 "secondary_sel", "step", "pll1_sw",
80 "pll1_sys", "pll1_bypass", "pll1",
81 "pll1_bypass_src", "osc";
82 arm-supply = <®_arm>;
83 soc-supply = <®_soc>;
84 };
85 };
87 intc: interrupt-controller@00a01000 {
88 compatible = "arm,cortex-a7-gic";
89 #interrupt-cells = <3>;
90 interrupt-controller;
91 reg = <0x00a01000 0x1000>,
92 <0x00a02000 0x1000>,
93 <0x00a04000 0x2000>,
94 <0x00a06000 0x2000>;
95 };
97 ckil: clock-cli {
98 compatible = "fixed-clock";
99 #clock-cells = <0>;
100 clock-frequency = <32768>;
101 clock-output-names = "ckil";
102 };
104 osc: clock-osc {
105 compatible = "fixed-clock";
106 #clock-cells = <0>;
107 clock-frequency = <24000000>;
108 clock-output-names = "osc";
109 };
111 ipp_di0: clock-di0 {
112 compatible = "fixed-clock";
113 #clock-cells = <0>;
114 clock-frequency = <0>;
115 clock-output-names = "ipp_di0";
116 };
118 ipp_di1: clock-di1 {
119 compatible = "fixed-clock";
120 #clock-cells = <0>;
121 clock-frequency = <0>;
122 clock-output-names = "ipp_di1";
123 };
125 soc {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "simple-bus";
129 interrupt-parent = <&gpc>;
130 ranges;
132 pmu {
133 compatible = "arm,cortex-a7-pmu";
134 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
135 status = "disabled";
136 };
138 aips1: aips-bus@02000000 {
139 compatible = "fsl,aips-bus", "simple-bus";
140 #address-cells = <1>;
141 #size-cells = <1>;
142 reg = <0x02000000 0x100000>;
143 ranges;
145 spba-bus@02000000 {
146 compatible = "fsl,spba-bus", "simple-bus";
147 #address-cells = <1>;
148 #size-cells = <1>;
149 reg = <0x02000000 0x40000>;
150 ranges;
152 ecspi1: ecspi@02008000 {
153 #address-cells = <1>;
154 #size-cells = <0>;
155 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
156 reg = <0x02008000 0x4000>;
157 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&clks IMX6UL_CLK_ECSPI1>,
159 <&clks IMX6UL_CLK_ECSPI1>;
160 clock-names = "ipg", "per";
161 status = "disabled";
162 };
164 ecspi2: ecspi@0200c000 {
165 #address-cells = <1>;
166 #size-cells = <0>;
167 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
168 reg = <0x0200c000 0x4000>;
169 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&clks IMX6UL_CLK_ECSPI2>,
171 <&clks IMX6UL_CLK_ECSPI2>;
172 clock-names = "ipg", "per";
173 status = "disabled";
174 };
176 ecspi3: ecspi@02010000 {
177 #address-cells = <1>;
178 #size-cells = <0>;
179 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
180 reg = <0x02010000 0x4000>;
181 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&clks IMX6UL_CLK_ECSPI3>,
183 <&clks IMX6UL_CLK_ECSPI3>;
184 clock-names = "ipg", "per";
185 status = "disabled";
186 };
188 ecspi4: ecspi@02014000 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
192 reg = <0x02014000 0x4000>;
193 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&clks IMX6UL_CLK_ECSPI4>,
195 <&clks IMX6UL_CLK_ECSPI4>;
196 clock-names = "ipg", "per";
197 status = "disabled";
198 };
200 uart7: serial@02018000 {
201 compatible = "fsl,imx6ul-uart",
202 "fsl,imx6q-uart";
203 reg = <0x02018000 0x4000>;
204 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
206 <&clks IMX6UL_CLK_UART7_SERIAL>;
207 clock-names = "ipg", "per";
208 status = "disabled";
209 };
211 uart1: serial@02020000 {
212 compatible = "fsl,imx6ul-uart",
213 "fsl,imx6q-uart";
214 reg = <0x02020000 0x4000>;
215 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
217 <&clks IMX6UL_CLK_UART1_SERIAL>;
218 clock-names = "ipg", "per";
219 status = "disabled";
220 };
222 uart8: serial@02024000 {
223 compatible = "fsl,imx6ul-uart",
224 "fsl,imx6q-uart";
225 reg = <0x02024000 0x4000>;
226 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
228 <&clks IMX6UL_CLK_UART8_SERIAL>;
229 clock-names = "ipg", "per";
230 status = "disabled";
231 };
232 };
234 gpt1: gpt@02098000 {
235 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
236 reg = <0x02098000 0x4000>;
237 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
239 <&clks IMX6UL_CLK_GPT1_SERIAL>;
240 clock-names = "ipg", "per";
241 };
243 gpio1: gpio@0209c000 {
244 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
245 reg = <0x0209c000 0x4000>;
246 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
248 gpio-controller;
249 #gpio-cells = <2>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
252 };
254 gpio2: gpio@020a0000 {
255 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
256 reg = <0x020a0000 0x4000>;
257 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
259 gpio-controller;
260 #gpio-cells = <2>;
261 interrupt-controller;
262 #interrupt-cells = <2>;
263 };
265 gpio3: gpio@020a4000 {
266 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
267 reg = <0x020a4000 0x4000>;
268 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
270 gpio-controller;
271 #gpio-cells = <2>;
272 interrupt-controller;
273 #interrupt-cells = <2>;
274 };
276 gpio4: gpio@020a8000 {
277 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
278 reg = <0x020a8000 0x4000>;
279 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
281 gpio-controller;
282 #gpio-cells = <2>;
283 interrupt-controller;
284 #interrupt-cells = <2>;
285 };
287 gpio5: gpio@020ac000 {
288 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
289 reg = <0x020ac000 0x4000>;
290 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
292 gpio-controller;
293 #gpio-cells = <2>;
294 interrupt-controller;
295 #interrupt-cells = <2>;
296 };
298 fec2: ethernet@020b4000 {
299 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
300 reg = <0x020b4000 0x4000>;
301 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&clks IMX6UL_CLK_ENET>,
304 <&clks IMX6UL_CLK_ENET_AHB>,
305 <&clks IMX6UL_CLK_ENET_PTP>,
306 <&clks IMX6UL_CLK_ENET2_REF_125M>,
307 <&clks IMX6UL_CLK_ENET2_REF_125M>;
308 clock-names = "ipg", "ahb", "ptp",
309 "enet_clk_ref", "enet_out";
310 fsl,num-tx-queues=<1>;
311 fsl,num-rx-queues=<1>;
312 status = "disabled";
313 };
315 wdog1: wdog@020bc000 {
316 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
317 reg = <0x020bc000 0x4000>;
318 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&clks IMX6UL_CLK_WDOG1>;
320 };
322 wdog2: wdog@020c0000 {
323 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
324 reg = <0x020c0000 0x4000>;
325 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&clks IMX6UL_CLK_WDOG2>;
327 status = "disabled";
328 };
330 clks: ccm@020c4000 {
331 compatible = "fsl,imx6ul-ccm";
332 reg = <0x020c4000 0x4000>;
333 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
335 #clock-cells = <1>;
336 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
337 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
338 };
340 anatop: anatop@020c8000 {
341 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
342 "syscon", "simple-bus";
343 reg = <0x020c8000 0x1000>;
344 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
348 reg_3p0: regulator-3p0@120 {
349 compatible = "fsl,anatop-regulator";
350 regulator-name = "vdd3p0";
351 regulator-min-microvolt = <2625000>;
352 regulator-max-microvolt = <3400000>;
353 anatop-reg-offset = <0x120>;
354 anatop-vol-bit-shift = <8>;
355 anatop-vol-bit-width = <5>;
356 anatop-min-bit-val = <0>;
357 anatop-min-voltage = <2625000>;
358 anatop-max-voltage = <3400000>;
359 anatop-enable-bit = <0>;
360 };
362 reg_arm: regulator-vddcore@140 {
363 compatible = "fsl,anatop-regulator";
364 regulator-name = "cpu";
365 regulator-min-microvolt = <725000>;
366 regulator-max-microvolt = <1450000>;
367 regulator-always-on;
368 anatop-reg-offset = <0x140>;
369 anatop-vol-bit-shift = <0>;
370 anatop-vol-bit-width = <5>;
371 anatop-delay-reg-offset = <0x170>;
372 anatop-delay-bit-shift = <24>;
373 anatop-delay-bit-width = <2>;
374 anatop-min-bit-val = <1>;
375 anatop-min-voltage = <725000>;
376 anatop-max-voltage = <1450000>;
377 };
379 reg_soc: regulator-vddsoc@140 {
380 compatible = "fsl,anatop-regulator";
381 regulator-name = "vddsoc";
382 regulator-min-microvolt = <725000>;
383 regulator-max-microvolt = <1450000>;
384 regulator-always-on;
385 anatop-reg-offset = <0x140>;
386 anatop-vol-bit-shift = <18>;
387 anatop-vol-bit-width = <5>;
388 anatop-delay-reg-offset = <0x170>;
389 anatop-delay-bit-shift = <28>;
390 anatop-delay-bit-width = <2>;
391 anatop-min-bit-val = <1>;
392 anatop-min-voltage = <725000>;
393 anatop-max-voltage = <1450000>;
394 };
395 };
397 usbphy1: usbphy@020c9000 {
398 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
399 reg = <0x020c9000 0x1000>;
400 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&clks IMX6UL_CLK_USBPHY1>;
402 phy-3p0-supply = <®_3p0>;
403 fsl,anatop = <&anatop>;
404 };
406 usbphy2: usbphy@020ca000 {
407 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
408 reg = <0x020ca000 0x1000>;
409 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&clks IMX6UL_CLK_USBPHY2>;
411 phy-3p0-supply = <®_3p0>;
412 fsl,anatop = <&anatop>;
413 };
415 snvs: snvs@020cc000 {
416 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
417 reg = <0x020cc000 0x4000>;
419 snvs_rtc: snvs-rtc-lp {
420 compatible = "fsl,sec-v4.0-mon-rtc-lp";
421 regmap = <&snvs>;
422 offset = <0x34>;
423 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
425 };
427 snvs_pwrkey: snvs-powerkey {
428 compatible = "fsl,sec-v4.0-pwrkey";
429 regmap = <&snvs>;
430 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
431 linux,keycode = <KEY_POWER>;
432 wakeup-source;
433 };
434 };
436 epit1: epit@020d0000 {
437 reg = <0x020d0000 0x4000>;
438 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
439 };
441 epit2: epit@020d4000 {
442 reg = <0x020d4000 0x4000>;
443 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
444 };
446 src: src@020d8000 {
447 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
448 reg = <0x020d8000 0x4000>;
449 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
451 #reset-cells = <1>;
452 };
454 gpc: gpc@020dc000 {
455 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
456 reg = <0x020dc000 0x4000>;
457 interrupt-controller;
458 #interrupt-cells = <3>;
459 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
460 interrupt-parent = <&intc>;
461 };
463 iomuxc: iomuxc@020e0000 {
464 compatible = "fsl,imx6ul-iomuxc";
465 reg = <0x020e0000 0x4000>;
466 };
468 gpr: iomuxc-gpr@020e4000 {
469 compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
470 reg = <0x020e4000 0x4000>;
471 };
473 gpt2: gpt@020e8000 {
474 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
475 reg = <0x020e8000 0x4000>;
476 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&clks IMX6UL_CLK_DUMMY>,
478 <&clks IMX6UL_CLK_DUMMY>;
479 clock-names = "ipg", "per";
480 };
482 pwm5: pwm@020f0000 {
483 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
484 reg = <0x020f0000 0x4000>;
485 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&clks IMX6UL_CLK_DUMMY>,
487 <&clks IMX6UL_CLK_DUMMY>;
488 clock-names = "ipg", "per";
489 #pwm-cells = <2>;
490 };
492 pwm6: pwm@020f4000 {
493 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
494 reg = <0x020f4000 0x4000>;
495 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&clks IMX6UL_CLK_DUMMY>,
497 <&clks IMX6UL_CLK_DUMMY>;
498 clock-names = "ipg", "per";
499 #pwm-cells = <2>;
500 };
502 pwm7: pwm@020f8000 {
503 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
504 reg = <0x020f8000 0x4000>;
505 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&clks IMX6UL_CLK_DUMMY>,
507 <&clks IMX6UL_CLK_DUMMY>;
508 clock-names = "ipg", "per";
509 #pwm-cells = <2>;
510 };
512 pwm8: pwm@020fc000 {
513 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
514 reg = <0x020fc000 0x4000>;
515 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&clks IMX6UL_CLK_DUMMY>,
517 <&clks IMX6UL_CLK_DUMMY>;
518 clock-names = "ipg", "per";
519 #pwm-cells = <2>;
520 };
521 };
523 aips2: aips-bus@02100000 {
524 compatible = "fsl,aips-bus", "simple-bus";
525 #address-cells = <1>;
526 #size-cells = <1>;
527 reg = <0x02100000 0x100000>;
528 ranges;
530 usbotg1: usb@02184000 {
531 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
532 reg = <0x02184000 0x200>;
533 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&clks IMX6UL_CLK_USBOH3>;
535 fsl,usbphy = <&usbphy1>;
536 fsl,usbmisc = <&usbmisc 0>;
537 fsl,anatop = <&anatop>;
538 status = "disabled";
539 };
541 usbotg2: usb@02184200 {
542 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
543 reg = <0x02184200 0x200>;
544 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&clks IMX6UL_CLK_USBOH3>;
546 fsl,usbphy = <&usbphy2>;
547 fsl,usbmisc = <&usbmisc 1>;
548 status = "disabled";
549 };
551 usbmisc: usbmisc@02184800 {
552 #index-cells = <1>;
553 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
554 reg = <0x02184800 0x200>;
555 };
557 fec1: ethernet@02188000 {
558 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
559 reg = <0x02188000 0x4000>;
560 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&clks IMX6UL_CLK_ENET>,
563 <&clks IMX6UL_CLK_ENET_AHB>,
564 <&clks IMX6UL_CLK_ENET_PTP>,
565 <&clks IMX6UL_CLK_ENET_REF>,
566 <&clks IMX6UL_CLK_ENET_REF>;
567 clock-names = "ipg", "ahb", "ptp",
568 "enet_clk_ref", "enet_out";
569 fsl,num-tx-queues=<1>;
570 fsl,num-rx-queues=<1>;
571 status = "disabled";
572 };
574 usdhc1: usdhc@02190000 {
575 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
576 reg = <0x02190000 0x4000>;
577 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&clks IMX6UL_CLK_USDHC1>,
579 <&clks IMX6UL_CLK_USDHC1>,
580 <&clks IMX6UL_CLK_USDHC1>;
581 clock-names = "ipg", "ahb", "per";
582 bus-width = <4>;
583 status = "disabled";
584 };
586 usdhc2: usdhc@02194000 {
587 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
588 reg = <0x02194000 0x4000>;
589 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&clks IMX6UL_CLK_USDHC2>,
591 <&clks IMX6UL_CLK_USDHC2>,
592 <&clks IMX6UL_CLK_USDHC2>;
593 clock-names = "ipg", "ahb", "per";
594 bus-width = <4>;
595 status = "disabled";
596 };
598 i2c1: i2c@021a0000 {
599 #address-cells = <1>;
600 #size-cells = <0>;
601 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
602 reg = <0x021a0000 0x4000>;
603 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&clks IMX6UL_CLK_I2C1>;
605 status = "disabled";
606 };
608 i2c2: i2c@021a4000 {
609 #address-cells = <1>;
610 #size-cells = <0>;
611 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
612 reg = <0x021a4000 0x4000>;
613 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&clks IMX6UL_CLK_I2C2>;
615 status = "disabled";
616 };
618 i2c3: i2c@021a8000 {
619 #address-cells = <1>;
620 #size-cells = <0>;
621 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
622 reg = <0x021a8000 0x4000>;
623 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&clks IMX6UL_CLK_I2C3>;
625 status = "disabled";
626 };
628 qspi: qspi@021e0000 {
629 #address-cells = <1>;
630 #size-cells = <0>;
631 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
632 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
633 reg-names = "QuadSPI", "QuadSPI-memory";
634 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&clks IMX6UL_CLK_QSPI>,
636 <&clks IMX6UL_CLK_QSPI>;
637 clock-names = "qspi_en", "qspi";
638 status = "disabled";
639 };
641 uart2: serial@021e8000 {
642 compatible = "fsl,imx6ul-uart",
643 "fsl,imx6q-uart";
644 reg = <0x021e8000 0x4000>;
645 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
647 <&clks IMX6UL_CLK_UART2_SERIAL>;
648 clock-names = "ipg", "per";
649 status = "disabled";
650 };
652 uart3: serial@021ec000 {
653 compatible = "fsl,imx6ul-uart",
654 "fsl,imx6q-uart";
655 reg = <0x021ec000 0x4000>;
656 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
658 <&clks IMX6UL_CLK_UART3_SERIAL>;
659 clock-names = "ipg", "per";
660 status = "disabled";
661 };
663 uart4: serial@021f0000 {
664 compatible = "fsl,imx6ul-uart",
665 "fsl,imx6q-uart";
666 reg = <0x021f0000 0x4000>;
667 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
669 <&clks IMX6UL_CLK_UART4_SERIAL>;
670 clock-names = "ipg", "per";
671 status = "disabled";
672 };
674 uart5: serial@021f4000 {
675 compatible = "fsl,imx6ul-uart",
676 "fsl,imx6q-uart";
677 reg = <0x021f4000 0x4000>;
678 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
680 <&clks IMX6UL_CLK_UART5_SERIAL>;
681 clock-names = "ipg", "per";
682 status = "disabled";
683 };
685 i2c4: i2c@021f8000 {
686 #address-cells = <1>;
687 #size-cells = <0>;
688 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
689 reg = <0x021f8000 0x4000>;
690 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&clks IMX6UL_CLK_I2C4>;
692 status = "disabled";
693 };
695 uart6: serial@021fc000 {
696 compatible = "fsl,imx6ul-uart",
697 "fsl,imx6q-uart";
698 reg = <0x021fc000 0x4000>;
699 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
701 <&clks IMX6UL_CLK_UART6_SERIAL>;
702 clock-names = "ipg", "per";
703 status = "disabled";
704 };
705 };
706 };
707 };