| blob | 97c8e9ace5ebee1ee83d1e193eb985ebc7cc6f40 |
1 /*
2 * Device Tree Source for the r8a7794 SoC
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2014 Ulrich Hecht
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
12 #include <dt-bindings/clock/r8a7794-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
16 / {
17 compatible = "renesas,r8a7794";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
26 cpu0: cpu@0 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a7";
29 reg = <0>;
30 clock-frequency = <1000000000>;
31 };
33 cpu1: cpu@1 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a7";
36 reg = <1>;
37 clock-frequency = <1000000000>;
38 };
39 };
41 gic: interrupt-controller@f1001000 {
42 compatible = "arm,gic-400";
43 #interrupt-cells = <3>;
44 #address-cells = <0>;
45 interrupt-controller;
46 reg = <0 0xf1001000 0 0x1000>,
47 <0 0xf1002000 0 0x1000>,
48 <0 0xf1004000 0 0x2000>,
49 <0 0xf1006000 0 0x2000>;
50 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
51 };
53 cmt0: timer@ffca0000 {
54 compatible = "renesas,cmt-48-gen2";
55 reg = <0 0xffca0000 0 0x1004>;
56 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
57 <0 143 IRQ_TYPE_LEVEL_HIGH>;
58 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
59 clock-names = "fck";
60 power-domains = <&cpg_clocks>;
62 renesas,channels-mask = <0x60>;
64 status = "disabled";
65 };
67 cmt1: timer@e6130000 {
68 compatible = "renesas,cmt-48-gen2";
69 reg = <0 0xe6130000 0 0x1004>;
70 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
71 <0 121 IRQ_TYPE_LEVEL_HIGH>,
72 <0 122 IRQ_TYPE_LEVEL_HIGH>,
73 <0 123 IRQ_TYPE_LEVEL_HIGH>,
74 <0 124 IRQ_TYPE_LEVEL_HIGH>,
75 <0 125 IRQ_TYPE_LEVEL_HIGH>,
76 <0 126 IRQ_TYPE_LEVEL_HIGH>,
77 <0 127 IRQ_TYPE_LEVEL_HIGH>;
78 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
79 clock-names = "fck";
80 power-domains = <&cpg_clocks>;
82 renesas,channels-mask = <0xff>;
84 status = "disabled";
85 };
87 timer {
88 compatible = "arm,armv7-timer";
89 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
90 <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
91 <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
92 <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
93 };
95 irqc0: interrupt-controller@e61c0000 {
96 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
97 #interrupt-cells = <2>;
98 interrupt-controller;
99 reg = <0 0xe61c0000 0 0x200>;
100 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
101 <0 1 IRQ_TYPE_LEVEL_HIGH>,
102 <0 2 IRQ_TYPE_LEVEL_HIGH>,
103 <0 3 IRQ_TYPE_LEVEL_HIGH>,
104 <0 12 IRQ_TYPE_LEVEL_HIGH>,
105 <0 13 IRQ_TYPE_LEVEL_HIGH>,
106 <0 14 IRQ_TYPE_LEVEL_HIGH>,
107 <0 15 IRQ_TYPE_LEVEL_HIGH>,
108 <0 16 IRQ_TYPE_LEVEL_HIGH>,
109 <0 17 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
111 power-domains = <&cpg_clocks>;
112 };
114 pfc: pin-controller@e6060000 {
115 compatible = "renesas,pfc-r8a7794";
116 reg = <0 0xe6060000 0 0x11c>;
117 #gpio-range-cells = <3>;
118 };
120 dmac0: dma-controller@e6700000 {
121 compatible = "renesas,rcar-dmac";
122 reg = <0 0xe6700000 0 0x20000>;
123 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
124 0 200 IRQ_TYPE_LEVEL_HIGH
125 0 201 IRQ_TYPE_LEVEL_HIGH
126 0 202 IRQ_TYPE_LEVEL_HIGH
127 0 203 IRQ_TYPE_LEVEL_HIGH
128 0 204 IRQ_TYPE_LEVEL_HIGH
129 0 205 IRQ_TYPE_LEVEL_HIGH
130 0 206 IRQ_TYPE_LEVEL_HIGH
131 0 207 IRQ_TYPE_LEVEL_HIGH
132 0 208 IRQ_TYPE_LEVEL_HIGH
133 0 209 IRQ_TYPE_LEVEL_HIGH
134 0 210 IRQ_TYPE_LEVEL_HIGH
135 0 211 IRQ_TYPE_LEVEL_HIGH
136 0 212 IRQ_TYPE_LEVEL_HIGH
137 0 213 IRQ_TYPE_LEVEL_HIGH
138 0 214 IRQ_TYPE_LEVEL_HIGH>;
139 interrupt-names = "error",
140 "ch0", "ch1", "ch2", "ch3",
141 "ch4", "ch5", "ch6", "ch7",
142 "ch8", "ch9", "ch10", "ch11",
143 "ch12", "ch13", "ch14";
144 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
145 clock-names = "fck";
146 power-domains = <&cpg_clocks>;
147 #dma-cells = <1>;
148 dma-channels = <15>;
149 };
151 dmac1: dma-controller@e6720000 {
152 compatible = "renesas,rcar-dmac";
153 reg = <0 0xe6720000 0 0x20000>;
154 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
155 0 216 IRQ_TYPE_LEVEL_HIGH
156 0 217 IRQ_TYPE_LEVEL_HIGH
157 0 218 IRQ_TYPE_LEVEL_HIGH
158 0 219 IRQ_TYPE_LEVEL_HIGH
159 0 308 IRQ_TYPE_LEVEL_HIGH
160 0 309 IRQ_TYPE_LEVEL_HIGH
161 0 310 IRQ_TYPE_LEVEL_HIGH
162 0 311 IRQ_TYPE_LEVEL_HIGH
163 0 312 IRQ_TYPE_LEVEL_HIGH
164 0 313 IRQ_TYPE_LEVEL_HIGH
165 0 314 IRQ_TYPE_LEVEL_HIGH
166 0 315 IRQ_TYPE_LEVEL_HIGH
167 0 316 IRQ_TYPE_LEVEL_HIGH
168 0 317 IRQ_TYPE_LEVEL_HIGH
169 0 318 IRQ_TYPE_LEVEL_HIGH>;
170 interrupt-names = "error",
171 "ch0", "ch1", "ch2", "ch3",
172 "ch4", "ch5", "ch6", "ch7",
173 "ch8", "ch9", "ch10", "ch11",
174 "ch12", "ch13", "ch14";
175 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
176 clock-names = "fck";
177 power-domains = <&cpg_clocks>;
178 #dma-cells = <1>;
179 dma-channels = <15>;
180 };
182 scifa0: serial@e6c40000 {
183 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
184 reg = <0 0xe6c40000 0 64>;
185 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
187 clock-names = "sci_ick";
188 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
189 dma-names = "tx", "rx";
190 power-domains = <&cpg_clocks>;
191 status = "disabled";
192 };
194 scifa1: serial@e6c50000 {
195 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
196 reg = <0 0xe6c50000 0 64>;
197 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
199 clock-names = "sci_ick";
200 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
201 dma-names = "tx", "rx";
202 power-domains = <&cpg_clocks>;
203 status = "disabled";
204 };
206 scifa2: serial@e6c60000 {
207 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
208 reg = <0 0xe6c60000 0 64>;
209 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
211 clock-names = "sci_ick";
212 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
213 dma-names = "tx", "rx";
214 power-domains = <&cpg_clocks>;
215 status = "disabled";
216 };
218 scifa3: serial@e6c70000 {
219 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
220 reg = <0 0xe6c70000 0 64>;
221 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
223 clock-names = "sci_ick";
224 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
225 dma-names = "tx", "rx";
226 power-domains = <&cpg_clocks>;
227 status = "disabled";
228 };
230 scifa4: serial@e6c78000 {
231 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
232 reg = <0 0xe6c78000 0 64>;
233 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
235 clock-names = "sci_ick";
236 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
237 dma-names = "tx", "rx";
238 power-domains = <&cpg_clocks>;
239 status = "disabled";
240 };
242 scifa5: serial@e6c80000 {
243 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
244 reg = <0 0xe6c80000 0 64>;
245 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
247 clock-names = "sci_ick";
248 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
249 dma-names = "tx", "rx";
250 power-domains = <&cpg_clocks>;
251 status = "disabled";
252 };
254 scifb0: serial@e6c20000 {
255 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
256 reg = <0 0xe6c20000 0 64>;
257 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
259 clock-names = "sci_ick";
260 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
261 dma-names = "tx", "rx";
262 power-domains = <&cpg_clocks>;
263 status = "disabled";
264 };
266 scifb1: serial@e6c30000 {
267 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
268 reg = <0 0xe6c30000 0 64>;
269 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
271 clock-names = "sci_ick";
272 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
273 dma-names = "tx", "rx";
274 power-domains = <&cpg_clocks>;
275 status = "disabled";
276 };
278 scifb2: serial@e6ce0000 {
279 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
280 reg = <0 0xe6ce0000 0 64>;
281 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
283 clock-names = "sci_ick";
284 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
285 dma-names = "tx", "rx";
286 power-domains = <&cpg_clocks>;
287 status = "disabled";
288 };
290 scif0: serial@e6e60000 {
291 compatible = "renesas,scif-r8a7794", "renesas,scif";
292 reg = <0 0xe6e60000 0 64>;
293 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>;
295 clock-names = "sci_ick";
296 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
297 dma-names = "tx", "rx";
298 power-domains = <&cpg_clocks>;
299 status = "disabled";
300 };
302 scif1: serial@e6e68000 {
303 compatible = "renesas,scif-r8a7794", "renesas,scif";
304 reg = <0 0xe6e68000 0 64>;
305 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>;
307 clock-names = "sci_ick";
308 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
309 dma-names = "tx", "rx";
310 power-domains = <&cpg_clocks>;
311 status = "disabled";
312 };
314 scif2: serial@e6e58000 {
315 compatible = "renesas,scif-r8a7794", "renesas,scif";
316 reg = <0 0xe6e58000 0 64>;
317 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>;
319 clock-names = "sci_ick";
320 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
321 dma-names = "tx", "rx";
322 power-domains = <&cpg_clocks>;
323 status = "disabled";
324 };
326 scif3: serial@e6ea8000 {
327 compatible = "renesas,scif-r8a7794", "renesas,scif";
328 reg = <0 0xe6ea8000 0 64>;
329 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>;
331 clock-names = "sci_ick";
332 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
333 dma-names = "tx", "rx";
334 power-domains = <&cpg_clocks>;
335 status = "disabled";
336 };
338 scif4: serial@e6ee0000 {
339 compatible = "renesas,scif-r8a7794", "renesas,scif";
340 reg = <0 0xe6ee0000 0 64>;
341 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>;
343 clock-names = "sci_ick";
344 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
345 dma-names = "tx", "rx";
346 power-domains = <&cpg_clocks>;
347 status = "disabled";
348 };
350 scif5: serial@e6ee8000 {
351 compatible = "renesas,scif-r8a7794", "renesas,scif";
352 reg = <0 0xe6ee8000 0 64>;
353 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>;
355 clock-names = "sci_ick";
356 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
357 dma-names = "tx", "rx";
358 power-domains = <&cpg_clocks>;
359 status = "disabled";
360 };
362 hscif0: serial@e62c0000 {
363 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
364 reg = <0 0xe62c0000 0 96>;
365 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>;
367 clock-names = "sci_ick";
368 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
369 dma-names = "tx", "rx";
370 power-domains = <&cpg_clocks>;
371 status = "disabled";
372 };
374 hscif1: serial@e62c8000 {
375 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
376 reg = <0 0xe62c8000 0 96>;
377 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>;
379 clock-names = "sci_ick";
380 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
381 dma-names = "tx", "rx";
382 power-domains = <&cpg_clocks>;
383 status = "disabled";
384 };
386 hscif2: serial@e62d0000 {
387 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
388 reg = <0 0xe62d0000 0 96>;
389 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>;
391 clock-names = "sci_ick";
392 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
393 dma-names = "tx", "rx";
394 power-domains = <&cpg_clocks>;
395 status = "disabled";
396 };
398 ether: ethernet@ee700000 {
399 compatible = "renesas,ether-r8a7794";
400 reg = <0 0xee700000 0 0x400>;
401 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
403 power-domains = <&cpg_clocks>;
404 phy-mode = "rmii";
405 #address-cells = <1>;
406 #size-cells = <0>;
407 status = "disabled";
408 };
410 mmcif0: mmc@ee200000 {
411 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
412 reg = <0 0xee200000 0 0x80>;
413 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
415 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
416 dma-names = "tx", "rx";
417 power-domains = <&cpg_clocks>;
418 reg-io-width = <4>;
419 status = "disabled";
420 };
422 sdhi0: sd@ee100000 {
423 compatible = "renesas,sdhi-r8a7794";
424 reg = <0 0xee100000 0 0x200>;
425 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
427 power-domains = <&cpg_clocks>;
428 status = "disabled";
429 };
431 sdhi1: sd@ee140000 {
432 compatible = "renesas,sdhi-r8a7794";
433 reg = <0 0xee140000 0 0x100>;
434 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
436 power-domains = <&cpg_clocks>;
437 status = "disabled";
438 };
440 sdhi2: sd@ee160000 {
441 compatible = "renesas,sdhi-r8a7794";
442 reg = <0 0xee160000 0 0x100>;
443 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
445 power-domains = <&cpg_clocks>;
446 status = "disabled";
447 };
449 clocks {
450 #address-cells = <2>;
451 #size-cells = <2>;
452 ranges;
454 /* External root clock */
455 extal_clk: extal_clk {
456 compatible = "fixed-clock";
457 #clock-cells = <0>;
458 /* This value must be overriden by the board. */
459 clock-frequency = <0>;
460 clock-output-names = "extal";
461 };
463 /* Special CPG clocks */
464 cpg_clocks: cpg_clocks@e6150000 {
465 compatible = "renesas,r8a7794-cpg-clocks",
466 "renesas,rcar-gen2-cpg-clocks";
467 reg = <0 0xe6150000 0 0x1000>;
468 clocks = <&extal_clk>;
469 #clock-cells = <1>;
470 clock-output-names = "main", "pll0", "pll1", "pll3",
471 "lb", "qspi", "sdh", "sd0", "z";
472 #power-domain-cells = <0>;
473 };
474 /* Variable factor clocks */
475 sd2_clk: sd2_clk@e6150078 {
476 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
477 reg = <0 0xe6150078 0 4>;
478 clocks = <&pll1_div2_clk>;
479 #clock-cells = <0>;
480 clock-output-names = "sd2";
481 };
482 sd3_clk: sd3_clk@e615026c {
483 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
484 reg = <0 0xe615026c 0 4>;
485 clocks = <&pll1_div2_clk>;
486 #clock-cells = <0>;
487 clock-output-names = "sd3";
488 };
489 mmc0_clk: mmc0_clk@e6150240 {
490 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
491 reg = <0 0xe6150240 0 4>;
492 clocks = <&pll1_div2_clk>;
493 #clock-cells = <0>;
494 clock-output-names = "mmc0";
495 };
497 /* Fixed factor clocks */
498 pll1_div2_clk: pll1_div2_clk {
499 compatible = "fixed-factor-clock";
500 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
501 #clock-cells = <0>;
502 clock-div = <2>;
503 clock-mult = <1>;
504 clock-output-names = "pll1_div2";
505 };
506 zg_clk: zg_clk {
507 compatible = "fixed-factor-clock";
508 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
509 #clock-cells = <0>;
510 clock-div = <6>;
511 clock-mult = <1>;
512 clock-output-names = "zg";
513 };
514 zx_clk: zx_clk {
515 compatible = "fixed-factor-clock";
516 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
517 #clock-cells = <0>;
518 clock-div = <3>;
519 clock-mult = <1>;
520 clock-output-names = "zx";
521 };
522 zs_clk: zs_clk {
523 compatible = "fixed-factor-clock";
524 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
525 #clock-cells = <0>;
526 clock-div = <6>;
527 clock-mult = <1>;
528 clock-output-names = "zs";
529 };
530 hp_clk: hp_clk {
531 compatible = "fixed-factor-clock";
532 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
533 #clock-cells = <0>;
534 clock-div = <12>;
535 clock-mult = <1>;
536 clock-output-names = "hp";
537 };
538 i_clk: i_clk {
539 compatible = "fixed-factor-clock";
540 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
541 #clock-cells = <0>;
542 clock-div = <2>;
543 clock-mult = <1>;
544 clock-output-names = "i";
545 };
546 b_clk: b_clk {
547 compatible = "fixed-factor-clock";
548 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
549 #clock-cells = <0>;
550 clock-div = <12>;
551 clock-mult = <1>;
552 clock-output-names = "b";
553 };
554 p_clk: p_clk {
555 compatible = "fixed-factor-clock";
556 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
557 #clock-cells = <0>;
558 clock-div = <24>;
559 clock-mult = <1>;
560 clock-output-names = "p";
561 };
562 cl_clk: cl_clk {
563 compatible = "fixed-factor-clock";
564 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
565 #clock-cells = <0>;
566 clock-div = <48>;
567 clock-mult = <1>;
568 clock-output-names = "cl";
569 };
570 m2_clk: m2_clk {
571 compatible = "fixed-factor-clock";
572 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
573 #clock-cells = <0>;
574 clock-div = <8>;
575 clock-mult = <1>;
576 clock-output-names = "m2";
577 };
578 imp_clk: imp_clk {
579 compatible = "fixed-factor-clock";
580 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
581 #clock-cells = <0>;
582 clock-div = <4>;
583 clock-mult = <1>;
584 clock-output-names = "imp";
585 };
586 rclk_clk: rclk_clk {
587 compatible = "fixed-factor-clock";
588 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
589 #clock-cells = <0>;
590 clock-div = <(48 * 1024)>;
591 clock-mult = <1>;
592 clock-output-names = "rclk";
593 };
594 oscclk_clk: oscclk_clk {
595 compatible = "fixed-factor-clock";
596 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
597 #clock-cells = <0>;
598 clock-div = <(12 * 1024)>;
599 clock-mult = <1>;
600 clock-output-names = "oscclk";
601 };
602 zb3_clk: zb3_clk {
603 compatible = "fixed-factor-clock";
604 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
605 #clock-cells = <0>;
606 clock-div = <4>;
607 clock-mult = <1>;
608 clock-output-names = "zb3";
609 };
610 zb3d2_clk: zb3d2_clk {
611 compatible = "fixed-factor-clock";
612 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
613 #clock-cells = <0>;
614 clock-div = <8>;
615 clock-mult = <1>;
616 clock-output-names = "zb3d2";
617 };
618 ddr_clk: ddr_clk {
619 compatible = "fixed-factor-clock";
620 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
621 #clock-cells = <0>;
622 clock-div = <8>;
623 clock-mult = <1>;
624 clock-output-names = "ddr";
625 };
626 mp_clk: mp_clk {
627 compatible = "fixed-factor-clock";
628 clocks = <&pll1_div2_clk>;
629 #clock-cells = <0>;
630 clock-div = <15>;
631 clock-mult = <1>;
632 clock-output-names = "mp";
633 };
634 cp_clk: cp_clk {
635 compatible = "fixed-factor-clock";
636 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
637 #clock-cells = <0>;
638 clock-div = <48>;
639 clock-mult = <1>;
640 clock-output-names = "cp";
641 };
643 acp_clk: acp_clk {
644 compatible = "fixed-factor-clock";
645 clocks = <&extal_clk>;
646 #clock-cells = <0>;
647 clock-div = <2>;
648 clock-mult = <1>;
649 clock-output-names = "acp";
650 };
652 /* Gate clocks */
653 mstp0_clks: mstp0_clks@e6150130 {
654 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
655 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
656 clocks = <&mp_clk>;
657 #clock-cells = <1>;
658 clock-indices = <R8A7794_CLK_MSIOF0>;
659 clock-output-names = "msiof0";
660 };
661 mstp1_clks: mstp1_clks@e6150134 {
662 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
663 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
664 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
665 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
666 <&zs_clk>, <&zs_clk>;
667 #clock-cells = <1>;
668 clock-indices = <
669 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
670 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
671 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
672 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
673 >;
674 clock-output-names =
675 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
676 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
677 };
678 mstp2_clks: mstp2_clks@e6150138 {
679 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
680 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
681 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
682 <&mp_clk>, <&mp_clk>, <&mp_clk>,
683 <&zs_clk>, <&zs_clk>;
684 #clock-cells = <1>;
685 clock-indices = <
686 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
687 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
688 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
689 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
690 >;
691 clock-output-names =
692 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
693 "scifb1", "msiof1", "scifb2",
694 "sys-dmac1", "sys-dmac0";
695 };
696 mstp3_clks: mstp3_clks@e615013c {
697 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
698 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
699 clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
700 <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
701 #clock-cells = <1>;
702 clock-indices = <
703 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
704 R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
705 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
706 >;
707 clock-output-names =
708 "sdhi2", "sdhi1", "sdhi0",
709 "mmcif0", "cmt1", "usbdmac0", "usbdmac1";
710 };
711 mstp4_clks: mstp4_clks@e6150140 {
712 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
713 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
714 clocks = <&cp_clk>;
715 #clock-cells = <1>;
716 clock-indices = <R8A7794_CLK_IRQC>;
717 clock-output-names = "irqc";
718 };
719 mstp7_clks: mstp7_clks@e615014c {
720 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
721 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
722 clocks = <&mp_clk>, <&mp_clk>,
723 <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
724 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
725 #clock-cells = <1>;
726 clock-indices = <
727 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
728 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
729 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
730 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
731 R8A7794_CLK_SCIF0
732 >;
733 clock-output-names =
734 "ehci", "hsusb",
735 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
736 "scif3", "scif2", "scif1", "scif0";
737 };
738 mstp8_clks: mstp8_clks@e6150990 {
739 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
740 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
741 clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
742 #clock-cells = <1>;
743 clock-indices = <
744 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
745 >;
746 clock-output-names =
747 "vin1", "vin0", "ether";
748 };
749 mstp9_clks: mstp9_clks@e6150994 {
750 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
751 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
752 clocks = <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
753 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
754 #clock-cells = <1>;
755 clock-indices = <
756 R8A7794_CLK_QSPI_MOD R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
757 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 R8A7794_CLK_I2C1
758 R8A7794_CLK_I2C0
759 >;
760 clock-output-names =
761 "qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
762 };
763 mstp11_clks: mstp11_clks@e615099c {
764 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
765 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
766 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
767 #clock-cells = <1>;
768 clock-indices = <
769 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
770 >;
771 clock-output-names = "scifa3", "scifa4", "scifa5";
772 };
773 };
775 ipmmu_sy0: mmu@e6280000 {
776 compatible = "renesas,ipmmu-vmsa";
777 reg = <0 0xe6280000 0 0x1000>;
778 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
779 <0 224 IRQ_TYPE_LEVEL_HIGH>;
780 #iommu-cells = <1>;
781 status = "disabled";
782 };
784 ipmmu_sy1: mmu@e6290000 {
785 compatible = "renesas,ipmmu-vmsa";
786 reg = <0 0xe6290000 0 0x1000>;
787 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
788 #iommu-cells = <1>;
789 status = "disabled";
790 };
792 ipmmu_ds: mmu@e6740000 {
793 compatible = "renesas,ipmmu-vmsa";
794 reg = <0 0xe6740000 0 0x1000>;
795 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
796 <0 199 IRQ_TYPE_LEVEL_HIGH>;
797 #iommu-cells = <1>;
798 };
800 ipmmu_mp: mmu@ec680000 {
801 compatible = "renesas,ipmmu-vmsa";
802 reg = <0 0xec680000 0 0x1000>;
803 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
804 #iommu-cells = <1>;
805 status = "disabled";
806 };
808 ipmmu_mx: mmu@fe951000 {
809 compatible = "renesas,ipmmu-vmsa";
810 reg = <0 0xfe951000 0 0x1000>;
811 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
812 <0 221 IRQ_TYPE_LEVEL_HIGH>;
813 #iommu-cells = <1>;
814 };
816 ipmmu_gp: mmu@e62a0000 {
817 compatible = "renesas,ipmmu-vmsa";
818 reg = <0 0xe62a0000 0 0x1000>;
819 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
820 <0 261 IRQ_TYPE_LEVEL_HIGH>;
821 #iommu-cells = <1>;
822 status = "disabled";
823 };
824 };