arch/arm/boot/dts/rk3188.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/pinctrl/rockchip.h>
  46 #include <dt-bindings/clock/rk3188-cru.h>
  47 #include "rk3xxx.dtsi"
  48
  49 / {
  50         compatible = "rockchip,rk3188";
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55                 enable-method = "rockchip,rk3066-smp";
  56
  57                 cpu0: cpu@0 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a9";
  60                         next-level-cache = <&L2>;
  61                         reg = <0x0>;
  62                         operating-points = <
  63                                 /* kHz    uV */
  64                                 1608000 1350000
  65                                 1416000 1250000
  66                                 1200000 1150000
  67                                 1008000 1075000
  68                                  816000  975000
  69                                  600000  950000
  70                                  504000  925000
  71                                  312000  875000
  72                         >;
  73                         clock-latency = <40000>;
  74                         clocks = <&cru ARMCLK>;
  75                 };
  76                 cpu@1 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a9";
  79                         next-level-cache = <&L2>;
  80                         reg = <0x1>;
  81                 };
  82                 cpu@2 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a9";
  85                         next-level-cache = <&L2>;
  86                         reg = <0x2>;
  87                 };
  88                 cpu@3 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a9";
  91                         next-level-cache = <&L2>;
  92                         reg = <0x3>;
  93                 };
  94         };
  95
  96         sram: sram@10080000 {
  97                 compatible = "mmio-sram";
  98                 reg = <0x10080000 0x8000>;
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 ranges = <0 0x10080000 0x8000>;
 102
 103                 smp-sram@0 {
 104                         compatible = "rockchip,rk3066-smp-sram";
 105                         reg = <0x0 0x50>;
 106                 };
 107         };
 108
 109         i2s0: i2s@1011a000 {
 110                 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
 111                 reg = <0x1011a000 0x2000>;
 112                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 113                 #address-cells = <1>;
 114                 #size-cells = <0>;
 115                 pinctrl-names = "default";
 116                 pinctrl-0 = <&i2s0_bus>;
 117                 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
 118                 dma-names = "tx", "rx";
 119                 clock-names = "i2s_hclk", "i2s_clk";
 120                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 121                 status = "disabled";
 122         };
 123
 124         cru: clock-controller@20000000 {
 125                 compatible = "rockchip,rk3188-cru";
 126                 reg = <0x20000000 0x1000>;
 127                 rockchip,grf = <&grf>;
 128
 129                 #clock-cells = <1>;
 130                 #reset-cells = <1>;
 131         };
 132
 133         usbphy: phy {
 134                 compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
 135                 rockchip,grf = <&grf>;
 136                 #address-cells = <1>;
 137                 #size-cells = <0>;
 138                 status = "disabled";
 139
 140                 usbphy0: usb-phy0 {
 141                         #phy-cells = <0>;
 142                         reg = <0x10c>;
 143                         clocks = <&cru SCLK_OTGPHY0>;
 144                         clock-names = "phyclk";
 145                 };
 146
 147                 usbphy1: usb-phy1 {
 148                         #phy-cells = <0>;
 149                         reg = <0x11c>;
 150                         clocks = <&cru SCLK_OTGPHY1>;
 151                         clock-names = "phyclk";
 152                 };
 153         };
 154
 155         pinctrl: pinctrl {
 156                 compatible = "rockchip,rk3188-pinctrl";
 157                 rockchip,grf = <&grf>;
 158                 rockchip,pmu = <&pmu>;
 159
 160                 #address-cells = <1>;
 161                 #size-cells = <1>;
 162                 ranges;
 163
 164                 gpio0: gpio0@2000a000 {
 165                         compatible = "rockchip,rk3188-gpio-bank0";
 166                         reg = <0x2000a000 0x100>;
 167                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 168                         clocks = <&cru PCLK_GPIO0>;
 169
 170                         gpio-controller;
 171                         #gpio-cells = <2>;
 172
 173                         interrupt-controller;
 174                         #interrupt-cells = <2>;
 175                 };
 176
 177                 gpio1: gpio1@2003c000 {
 178                         compatible = "rockchip,gpio-bank";
 179                         reg = <0x2003c000 0x100>;
 180                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 181                         clocks = <&cru PCLK_GPIO1>;
 182
 183                         gpio-controller;
 184                         #gpio-cells = <2>;
 185
 186                         interrupt-controller;
 187                         #interrupt-cells = <2>;
 188                 };
 189
 190                 gpio2: gpio2@2003e000 {
 191                         compatible = "rockchip,gpio-bank";
 192                         reg = <0x2003e000 0x100>;
 193                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 194                         clocks = <&cru PCLK_GPIO2>;
 195
 196                         gpio-controller;
 197                         #gpio-cells = <2>;
 198
 199                         interrupt-controller;
 200                         #interrupt-cells = <2>;
 201                 };
 202
 203                 gpio3: gpio3@20080000 {
 204                         compatible = "rockchip,gpio-bank";
 205                         reg = <0x20080000 0x100>;
 206                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 207                         clocks = <&cru PCLK_GPIO3>;
 208
 209                         gpio-controller;
 210                         #gpio-cells = <2>;
 211
 212                         interrupt-controller;
 213                         #interrupt-cells = <2>;
 214                 };
 215
 216                 pcfg_pull_up: pcfg_pull_up {
 217                         bias-pull-up;
 218                 };
 219
 220                 pcfg_pull_down: pcfg_pull_down {
 221                         bias-pull-down;
 222                 };
 223
 224                 pcfg_pull_none: pcfg_pull_none {
 225                         bias-disable;
 226                 };
 227
 228                 emmc {
 229                         emmc_clk: emmc-clk {
 230                                 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
 231                         };
 232
 233                         emmc_cmd: emmc-cmd {
 234                                 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
 235                         };
 236
 237                         emmc_rst: emmc-rst {
 238                                 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
 239                         };
 240
 241                         /*
 242                          * The data pins are shared between nandc and emmc and
 243                          * not accessible through pinctrl. Also they should've
 244                          * been already set correctly by firmware, as
 245                          * flash/emmc is the boot-device.
 246                          */
 247                 };
 248
 249                 emac {
 250                         emac_xfer: emac-xfer {
 251                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
 252                                                 <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
 253                                                 <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
 254                                                 <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
 255                                                 <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
 256                                                 <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
 257                                                 <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
 258                                                 <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
 259                         };
 260
 261                         emac_mdio: emac-mdio {
 262                                 rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
 263                                                 <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
 264                         };
 265                 };
 266
 267                 i2c0 {
 268                         i2c0_xfer: i2c0-xfer {
 269                                 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
 270                                                 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
 271                         };
 272                 };
 273
 274                 i2c1 {
 275                         i2c1_xfer: i2c1-xfer {
 276                                 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
 277                                                 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
 278                         };
 279                 };
 280
 281                 i2c2 {
 282                         i2c2_xfer: i2c2-xfer {
 283                                 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
 284                                                 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
 285                         };
 286                 };
 287
 288                 i2c3 {
 289                         i2c3_xfer: i2c3-xfer {
 290                                 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
 291                                                 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
 292                         };
 293                 };
 294
 295                 i2c4 {
 296                         i2c4_xfer: i2c4-xfer {
 297                                 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
 298                                                 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
 299                         };
 300                 };
 301
 302                 pwm0 {
 303                         pwm0_out: pwm0-out {
 304                                 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
 305                         };
 306                 };
 307
 308                 pwm1 {
 309                         pwm1_out: pwm1-out {
 310                                 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
 311                         };
 312                 };
 313
 314                 pwm2 {
 315                         pwm2_out: pwm2-out {
 316                                 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
 317                         };
 318                 };
 319
 320                 pwm3 {
 321                         pwm3_out: pwm3-out {
 322                                 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
 323                         };
 324                 };
 325
 326                 spi0 {
 327                         spi0_clk: spi0-clk {
 328                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
 329                         };
 330                         spi0_cs0: spi0-cs0 {
 331                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
 332                         };
 333                         spi0_tx: spi0-tx {
 334                                 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
 335                         };
 336                         spi0_rx: spi0-rx {
 337                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
 338                         };
 339                         spi0_cs1: spi0-cs1 {
 340                                 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
 341                         };
 342                 };
 343
 344                 spi1 {
 345                         spi1_clk: spi1-clk {
 346                                 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
 347                         };
 348                         spi1_cs0: spi1-cs0 {
 349                                 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
 350                         };
 351                         spi1_rx: spi1-rx {
 352                                 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
 353                         };
 354                         spi1_tx: spi1-tx {
 355                                 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
 356                         };
 357                         spi1_cs1: spi1-cs1 {
 358                                 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
 359                         };
 360                 };
 361
 362                 uart0 {
 363                         uart0_xfer: uart0-xfer {
 364                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
 365                                                 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
 366                         };
 367
 368                         uart0_cts: uart0-cts {
 369                                 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
 370                         };
 371
 372                         uart0_rts: uart0-rts {
 373                                 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
 374                         };
 375                 };
 376
 377                 uart1 {
 378                         uart1_xfer: uart1-xfer {
 379                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
 380                                                 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
 381                         };
 382
 383                         uart1_cts: uart1-cts {
 384                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
 385                         };
 386
 387                         uart1_rts: uart1-rts {
 388                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
 389                         };
 390                 };
 391
 392                 uart2 {
 393                         uart2_xfer: uart2-xfer {
 394                                 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
 395                                                 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
 396                         };
 397                         /* no rts / cts for uart2 */
 398                 };
 399
 400                 uart3 {
 401                         uart3_xfer: uart3-xfer {
 402                                 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
 403                                                 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
 404                         };
 405
 406                         uart3_cts: uart3-cts {
 407                                 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
 408                         };
 409
 410                         uart3_rts: uart3-rts {
 411                                 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
 412                         };
 413                 };
 414
 415                 sd0 {
 416                         sd0_clk: sd0-clk {
 417                                 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
 418                         };
 419
 420                         sd0_cmd: sd0-cmd {
 421                                 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
 422                         };
 423
 424                         sd0_cd: sd0-cd {
 425                                 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
 426                         };
 427
 428                         sd0_wp: sd0-wp {
 429                                 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
 430                         };
 431
 432                         sd0_pwr: sd0-pwr {
 433                                 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 434                         };
 435
 436                         sd0_bus1: sd0-bus-width1 {
 437                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
 438                         };
 439
 440                         sd0_bus4: sd0-bus-width4 {
 441                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 442                                                 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
 443                                                 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
 444                                                 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
 445                         };
 446                 };
 447
 448                 sd1 {
 449                         sd1_clk: sd1-clk {
 450                                 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
 451                         };
 452
 453                         sd1_cmd: sd1-cmd {
 454                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
 455                         };
 456
 457                         sd1_cd: sd1-cd {
 458                                 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
 459                         };
 460
 461                         sd1_wp: sd1-wp {
 462                                 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
 463                         };
 464
 465                         sd1_bus1: sd1-bus-width1 {
 466                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
 467                         };
 468
 469                         sd1_bus4: sd1-bus-width4 {
 470                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
 471                                                 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
 472                                                 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
 473                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
 474                         };
 475                 };
 476
 477                 i2s0 {
 478                         i2s0_bus: i2s0-bus {
 479                                 rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
 480                                                 <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
 481                                                 <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
 482                                                 <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
 483                                                 <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
 484                                                 <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
 485                         };
 486                 };
 487         };
 488 };
 489
 490 &emac {
 491         compatible = "rockchip,rk3188-emac";
 492 };
 493
 494 &global_timer {
 495         interrupts = <GIC_PPI 11 0xf04>;
 496 };
 497
 498 &local_timer {
 499         interrupts = <GIC_PPI 13 0xf04>;
 500 };
 501
 502 &i2c0 {
 503         compatible = "rockchip,rk3188-i2c";
 504         pinctrl-names = "default";
 505         pinctrl-0 = <&i2c0_xfer>;
 506 };
 507
 508 &i2c1 {
 509         compatible = "rockchip,rk3188-i2c";
 510         pinctrl-names = "default";
 511         pinctrl-0 = <&i2c1_xfer>;
 512 };
 513
 514 &i2c2 {
 515         compatible = "rockchip,rk3188-i2c";
 516         pinctrl-names = "default";
 517         pinctrl-0 = <&i2c2_xfer>;
 518 };
 519
 520 &i2c3 {
 521         compatible = "rockchip,rk3188-i2c";
 522         pinctrl-names = "default";
 523         pinctrl-0 = <&i2c3_xfer>;
 524 };
 525
 526 &i2c4 {
 527         compatible = "rockchip,rk3188-i2c";
 528         pinctrl-names = "default";
 529         pinctrl-0 = <&i2c4_xfer>;
 530 };
 531
 532 &pwm0 {
 533         pinctrl-names = "default";
 534         pinctrl-0 = <&pwm0_out>;
 535 };
 536
 537 &pwm1 {
 538         pinctrl-names = "default";
 539         pinctrl-0 = <&pwm1_out>;
 540 };
 541
 542 &pwm2 {
 543         pinctrl-names = "default";
 544         pinctrl-0 = <&pwm2_out>;
 545 };
 546
 547 &pwm3 {
 548         pinctrl-names = "default";
 549         pinctrl-0 = <&pwm3_out>;
 550 };
 551
 552 &spi0 {
 553         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 554         pinctrl-names = "default";
 555         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 556 };
 557
 558 &spi1 {
 559         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 560         pinctrl-names = "default";
 561         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 562 };
 563
 564 &uart0 {
 565         pinctrl-names = "default";
 566         pinctrl-0 = <&uart0_xfer>;
 567 };
 568
 569 &uart1 {
 570         pinctrl-names = "default";
 571         pinctrl-0 = <&uart1_xfer>;
 572 };
 573
 574 &uart2 {
 575         pinctrl-names = "default";
 576         pinctrl-0 = <&uart2_xfer>;
 577 };
 578
 579 &uart3 {
 580         pinctrl-names = "default";
 581         pinctrl-0 = <&uart3_xfer>;
 582 };
 583
 584 &wdt {
 585         compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
 586 };