| blob | 906e938fb6bfc70d9ec7948171ad425f34ae11f3 |
1 /*
2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
5 * whole.
6 *
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Or, alternatively,
18 *
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
26 * conditions:
27 *
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
30 *
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
39 */
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include "skeleton.dtsi"
49 / {
50 compatible = "rockchip,rk3288";
52 interrupt-parent = <&gic>;
54 aliases {
55 i2c0 = &i2c0;
56 i2c1 = &i2c1;
57 i2c2 = &i2c2;
58 i2c3 = &i2c3;
59 i2c4 = &i2c4;
60 i2c5 = &i2c5;
61 mshc0 = &emmc;
62 mshc1 = &sdmmc;
63 mshc2 = &sdio0;
64 mshc3 = &sdio1;
65 serial0 = &uart0;
66 serial1 = &uart1;
67 serial2 = &uart2;
68 serial3 = &uart3;
69 serial4 = &uart4;
70 spi0 = &spi0;
71 spi1 = &spi1;
72 spi2 = &spi2;
73 };
75 arm-pmu {
76 compatible = "arm,cortex-a12-pmu";
77 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
81 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
82 };
84 cpus {
85 #address-cells = <1>;
86 #size-cells = <0>;
87 enable-method = "rockchip,rk3066-smp";
88 rockchip,pmu = <&pmu>;
90 cpu0: cpu@500 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a12";
93 reg = <0x500>;
94 resets = <&cru SRST_CORE0>;
95 operating-points = <
96 /* KHz uV */
97 1608000 1350000
98 1512000 1300000
99 1416000 1200000
100 1200000 1100000
101 1008000 1050000
102 816000 1000000
103 696000 950000
104 600000 900000
105 408000 900000
106 312000 900000
107 216000 900000
108 126000 900000
109 >;
110 #cooling-cells = <2>; /* min followed by max */
111 clock-latency = <40000>;
112 clocks = <&cru ARMCLK>;
113 };
114 cpu1: cpu@501 {
115 device_type = "cpu";
116 compatible = "arm,cortex-a12";
117 reg = <0x501>;
118 resets = <&cru SRST_CORE1>;
119 };
120 cpu2: cpu@502 {
121 device_type = "cpu";
122 compatible = "arm,cortex-a12";
123 reg = <0x502>;
124 resets = <&cru SRST_CORE2>;
125 };
126 cpu3: cpu@503 {
127 device_type = "cpu";
128 compatible = "arm,cortex-a12";
129 reg = <0x503>;
130 resets = <&cru SRST_CORE3>;
131 };
132 };
134 amba {
135 compatible = "arm,amba-bus";
136 #address-cells = <1>;
137 #size-cells = <1>;
138 ranges;
140 dmac_peri: dma-controller@ff250000 {
141 compatible = "arm,pl330", "arm,primecell";
142 reg = <0xff250000 0x4000>;
143 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
145 #dma-cells = <1>;
146 clocks = <&cru ACLK_DMAC2>;
147 clock-names = "apb_pclk";
148 };
150 dmac_bus_ns: dma-controller@ff600000 {
151 compatible = "arm,pl330", "arm,primecell";
152 reg = <0xff600000 0x4000>;
153 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
155 #dma-cells = <1>;
156 clocks = <&cru ACLK_DMAC1>;
157 clock-names = "apb_pclk";
158 status = "disabled";
159 };
161 dmac_bus_s: dma-controller@ffb20000 {
162 compatible = "arm,pl330", "arm,primecell";
163 reg = <0xffb20000 0x4000>;
164 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
166 #dma-cells = <1>;
167 clocks = <&cru ACLK_DMAC1>;
168 clock-names = "apb_pclk";
169 };
170 };
172 reserved-memory {
173 #address-cells = <1>;
174 #size-cells = <1>;
175 ranges;
177 /*
178 * The rk3288 cannot use the memory area above 0xfe000000
179 * for dma operations for some reason. While there is
180 * probably a better solution available somewhere, we
181 * haven't found it yet and while devices with 2GB of ram
182 * are not affected, this issue prevents 4GB from booting.
183 * So to make these devices at least bootable, block
184 * this area for the time being until the real solution
185 * is found.
186 */
187 dma-unusable@fe000000 {
188 reg = <0xfe000000 0x1000000>;
189 };
190 };
192 xin24m: oscillator {
193 compatible = "fixed-clock";
194 clock-frequency = <24000000>;
195 clock-output-names = "xin24m";
196 #clock-cells = <0>;
197 };
199 timer {
200 compatible = "arm,armv7-timer";
201 arm,cpu-registers-not-fw-configured;
202 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
203 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
204 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
206 clock-frequency = <24000000>;
207 };
209 timer: timer@ff810000 {
210 compatible = "rockchip,rk3288-timer";
211 reg = <0xff810000 0x20>;
212 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&xin24m>, <&cru PCLK_TIMER>;
214 clock-names = "timer", "pclk";
215 };
217 display-subsystem {
218 compatible = "rockchip,display-subsystem";
219 ports = <&vopl_out>, <&vopb_out>;
220 };
222 sdmmc: dwmmc@ff0c0000 {
223 compatible = "rockchip,rk3288-dw-mshc";
224 clock-freq-min-max = <400000 150000000>;
225 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
226 clock-names = "biu", "ciu";
227 fifo-depth = <0x100>;
228 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
229 reg = <0xff0c0000 0x4000>;
230 status = "disabled";
231 };
233 sdio0: dwmmc@ff0d0000 {
234 compatible = "rockchip,rk3288-dw-mshc";
235 clock-freq-min-max = <400000 150000000>;
236 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
237 clock-names = "biu", "ciu";
238 fifo-depth = <0x100>;
239 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
240 reg = <0xff0d0000 0x4000>;
241 status = "disabled";
242 };
244 sdio1: dwmmc@ff0e0000 {
245 compatible = "rockchip,rk3288-dw-mshc";
246 clock-freq-min-max = <400000 150000000>;
247 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
248 clock-names = "biu", "ciu";
249 fifo-depth = <0x100>;
250 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
251 reg = <0xff0e0000 0x4000>;
252 status = "disabled";
253 };
255 emmc: dwmmc@ff0f0000 {
256 compatible = "rockchip,rk3288-dw-mshc";
257 clock-freq-min-max = <400000 150000000>;
258 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
259 clock-names = "biu", "ciu";
260 fifo-depth = <0x100>;
261 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
262 reg = <0xff0f0000 0x4000>;
263 status = "disabled";
264 };
266 saradc: saradc@ff100000 {
267 compatible = "rockchip,saradc";
268 reg = <0xff100000 0x100>;
269 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
270 #io-channel-cells = <1>;
271 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
272 clock-names = "saradc", "apb_pclk";
273 status = "disabled";
274 };
276 spi0: spi@ff110000 {
277 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
278 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
279 clock-names = "spiclk", "apb_pclk";
280 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
281 dma-names = "tx", "rx";
282 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
285 reg = <0xff110000 0x1000>;
286 #address-cells = <1>;
287 #size-cells = <0>;
288 status = "disabled";
289 };
291 spi1: spi@ff120000 {
292 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
293 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
294 clock-names = "spiclk", "apb_pclk";
295 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
296 dma-names = "tx", "rx";
297 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
300 reg = <0xff120000 0x1000>;
301 #address-cells = <1>;
302 #size-cells = <0>;
303 status = "disabled";
304 };
306 spi2: spi@ff130000 {
307 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
308 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
309 clock-names = "spiclk", "apb_pclk";
310 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
311 dma-names = "tx", "rx";
312 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
315 reg = <0xff130000 0x1000>;
316 #address-cells = <1>;
317 #size-cells = <0>;
318 status = "disabled";
319 };
321 i2c1: i2c@ff140000 {
322 compatible = "rockchip,rk3288-i2c";
323 reg = <0xff140000 0x1000>;
324 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
325 #address-cells = <1>;
326 #size-cells = <0>;
327 clock-names = "i2c";
328 clocks = <&cru PCLK_I2C1>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&i2c1_xfer>;
331 status = "disabled";
332 };
334 i2c3: i2c@ff150000 {
335 compatible = "rockchip,rk3288-i2c";
336 reg = <0xff150000 0x1000>;
337 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
338 #address-cells = <1>;
339 #size-cells = <0>;
340 clock-names = "i2c";
341 clocks = <&cru PCLK_I2C3>;
342 pinctrl-names = "default";
343 pinctrl-0 = <&i2c3_xfer>;
344 status = "disabled";
345 };
347 i2c4: i2c@ff160000 {
348 compatible = "rockchip,rk3288-i2c";
349 reg = <0xff160000 0x1000>;
350 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
351 #address-cells = <1>;
352 #size-cells = <0>;
353 clock-names = "i2c";
354 clocks = <&cru PCLK_I2C4>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&i2c4_xfer>;
357 status = "disabled";
358 };
360 i2c5: i2c@ff170000 {
361 compatible = "rockchip,rk3288-i2c";
362 reg = <0xff170000 0x1000>;
363 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
364 #address-cells = <1>;
365 #size-cells = <0>;
366 clock-names = "i2c";
367 clocks = <&cru PCLK_I2C5>;
368 pinctrl-names = "default";
369 pinctrl-0 = <&i2c5_xfer>;
370 status = "disabled";
371 };
373 uart0: serial@ff180000 {
374 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
375 reg = <0xff180000 0x100>;
376 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
377 reg-shift = <2>;
378 reg-io-width = <4>;
379 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
380 clock-names = "baudclk", "apb_pclk";
381 pinctrl-names = "default";
382 pinctrl-0 = <&uart0_xfer>;
383 status = "disabled";
384 };
386 uart1: serial@ff190000 {
387 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
388 reg = <0xff190000 0x100>;
389 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
390 reg-shift = <2>;
391 reg-io-width = <4>;
392 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
393 clock-names = "baudclk", "apb_pclk";
394 pinctrl-names = "default";
395 pinctrl-0 = <&uart1_xfer>;
396 status = "disabled";
397 };
399 uart2: serial@ff690000 {
400 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
401 reg = <0xff690000 0x100>;
402 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
403 reg-shift = <2>;
404 reg-io-width = <4>;
405 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
406 clock-names = "baudclk", "apb_pclk";
407 pinctrl-names = "default";
408 pinctrl-0 = <&uart2_xfer>;
409 status = "disabled";
410 };
412 uart3: serial@ff1b0000 {
413 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
414 reg = <0xff1b0000 0x100>;
415 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
416 reg-shift = <2>;
417 reg-io-width = <4>;
418 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
419 clock-names = "baudclk", "apb_pclk";
420 pinctrl-names = "default";
421 pinctrl-0 = <&uart3_xfer>;
422 status = "disabled";
423 };
425 uart4: serial@ff1c0000 {
426 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
427 reg = <0xff1c0000 0x100>;
428 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
429 reg-shift = <2>;
430 reg-io-width = <4>;
431 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
432 clock-names = "baudclk", "apb_pclk";
433 pinctrl-names = "default";
434 pinctrl-0 = <&uart4_xfer>;
435 status = "disabled";
436 };
438 thermal-zones {
439 #include "rk3288-thermal.dtsi"
440 };
442 tsadc: tsadc@ff280000 {
443 compatible = "rockchip,rk3288-tsadc";
444 reg = <0xff280000 0x100>;
445 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
447 clock-names = "tsadc", "apb_pclk";
448 resets = <&cru SRST_TSADC>;
449 reset-names = "tsadc-apb";
450 pinctrl-names = "default";
451 pinctrl-0 = <&otp_out>;
452 #thermal-sensor-cells = <1>;
453 rockchip,hw-tshut-temp = <95000>;
454 status = "disabled";
455 };
457 gmac: ethernet@ff290000 {
458 compatible = "rockchip,rk3288-gmac";
459 reg = <0xff290000 0x10000>;
460 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
461 interrupt-names = "macirq";
462 rockchip,grf = <&grf>;
463 clocks = <&cru SCLK_MAC>,
464 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
465 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
466 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
467 clock-names = "stmmaceth",
468 "mac_clk_rx", "mac_clk_tx",
469 "clk_mac_ref", "clk_mac_refout",
470 "aclk_mac", "pclk_mac";
471 resets = <&cru SRST_MAC>;
472 reset-names = "stmmaceth";
473 status = "disabled";
474 };
476 usb_host0_ehci: usb@ff500000 {
477 compatible = "generic-ehci";
478 reg = <0xff500000 0x100>;
479 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&cru HCLK_USBHOST0>;
481 clock-names = "usbhost";
482 phys = <&usbphy1>;
483 phy-names = "usb";
484 status = "disabled";
485 };
487 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
489 usb_host1: usb@ff540000 {
490 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
491 "snps,dwc2";
492 reg = <0xff540000 0x40000>;
493 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&cru HCLK_USBHOST1>;
495 clock-names = "otg";
496 dr_mode = "host";
497 phys = <&usbphy2>;
498 phy-names = "usb2-phy";
499 status = "disabled";
500 };
502 usb_otg: usb@ff580000 {
503 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
504 "snps,dwc2";
505 reg = <0xff580000 0x40000>;
506 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&cru HCLK_OTG0>;
508 clock-names = "otg";
509 dr_mode = "otg";
510 g-np-tx-fifo-size = <16>;
511 g-rx-fifo-size = <275>;
512 g-tx-fifo-size = <256 128 128 64 64 32>;
513 g-use-dma;
514 phys = <&usbphy0>;
515 phy-names = "usb2-phy";
516 status = "disabled";
517 };
519 usb_hsic: usb@ff5c0000 {
520 compatible = "generic-ehci";
521 reg = <0xff5c0000 0x100>;
522 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&cru HCLK_HSIC>;
524 clock-names = "usbhost";
525 status = "disabled";
526 };
528 i2c0: i2c@ff650000 {
529 compatible = "rockchip,rk3288-i2c";
530 reg = <0xff650000 0x1000>;
531 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
532 #address-cells = <1>;
533 #size-cells = <0>;
534 clock-names = "i2c";
535 clocks = <&cru PCLK_I2C0>;
536 pinctrl-names = "default";
537 pinctrl-0 = <&i2c0_xfer>;
538 status = "disabled";
539 };
541 i2c2: i2c@ff660000 {
542 compatible = "rockchip,rk3288-i2c";
543 reg = <0xff660000 0x1000>;
544 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
545 #address-cells = <1>;
546 #size-cells = <0>;
547 clock-names = "i2c";
548 clocks = <&cru PCLK_I2C2>;
549 pinctrl-names = "default";
550 pinctrl-0 = <&i2c2_xfer>;
551 status = "disabled";
552 };
554 pwm0: pwm@ff680000 {
555 compatible = "rockchip,rk3288-pwm";
556 reg = <0xff680000 0x10>;
557 #pwm-cells = <3>;
558 pinctrl-names = "default";
559 pinctrl-0 = <&pwm0_pin>;
560 clocks = <&cru PCLK_PWM>;
561 clock-names = "pwm";
562 status = "disabled";
563 };
565 pwm1: pwm@ff680010 {
566 compatible = "rockchip,rk3288-pwm";
567 reg = <0xff680010 0x10>;
568 #pwm-cells = <3>;
569 pinctrl-names = "default";
570 pinctrl-0 = <&pwm1_pin>;
571 clocks = <&cru PCLK_PWM>;
572 clock-names = "pwm";
573 status = "disabled";
574 };
576 pwm2: pwm@ff680020 {
577 compatible = "rockchip,rk3288-pwm";
578 reg = <0xff680020 0x10>;
579 #pwm-cells = <3>;
580 pinctrl-names = "default";
581 pinctrl-0 = <&pwm2_pin>;
582 clocks = <&cru PCLK_PWM>;
583 clock-names = "pwm";
584 status = "disabled";
585 };
587 pwm3: pwm@ff680030 {
588 compatible = "rockchip,rk3288-pwm";
589 reg = <0xff680030 0x10>;
590 #pwm-cells = <2>;
591 pinctrl-names = "default";
592 pinctrl-0 = <&pwm3_pin>;
593 clocks = <&cru PCLK_PWM>;
594 clock-names = "pwm";
595 status = "disabled";
596 };
598 bus_intmem@ff700000 {
599 compatible = "mmio-sram";
600 reg = <0xff700000 0x18000>;
601 #address-cells = <1>;
602 #size-cells = <1>;
603 ranges = <0 0xff700000 0x18000>;
604 smp-sram@0 {
605 compatible = "rockchip,rk3066-smp-sram";
606 reg = <0x00 0x10>;
607 };
608 };
610 sram@ff720000 {
611 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
612 reg = <0xff720000 0x1000>;
613 };
615 pmu: power-management@ff730000 {
616 compatible = "rockchip,rk3288-pmu", "syscon";
617 reg = <0xff730000 0x100>;
618 };
620 sgrf: syscon@ff740000 {
621 compatible = "rockchip,rk3288-sgrf", "syscon";
622 reg = <0xff740000 0x1000>;
623 };
625 cru: clock-controller@ff760000 {
626 compatible = "rockchip,rk3288-cru";
627 reg = <0xff760000 0x1000>;
628 rockchip,grf = <&grf>;
629 #clock-cells = <1>;
630 #reset-cells = <1>;
631 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
632 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
633 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
634 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
635 <&cru PCLK_PERI>;
636 assigned-clock-rates = <594000000>, <400000000>,
637 <500000000>, <300000000>,
638 <150000000>, <75000000>,
639 <300000000>, <150000000>,
640 <75000000>;
641 };
643 grf: syscon@ff770000 {
644 compatible = "rockchip,rk3288-grf", "syscon";
645 reg = <0xff770000 0x1000>;
646 };
648 wdt: watchdog@ff800000 {
649 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
650 reg = <0xff800000 0x100>;
651 clocks = <&cru PCLK_WDT>;
652 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
653 status = "disabled";
654 };
656 i2s: i2s@ff890000 {
657 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
658 reg = <0xff890000 0x10000>;
659 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
660 #address-cells = <1>;
661 #size-cells = <0>;
662 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
663 dma-names = "tx", "rx";
664 clock-names = "i2s_hclk", "i2s_clk";
665 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
666 pinctrl-names = "default";
667 pinctrl-0 = <&i2s0_bus>;
668 status = "disabled";
669 };
671 vopb: vop@ff930000 {
672 compatible = "rockchip,rk3288-vop";
673 reg = <0xff930000 0x19c>;
674 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
676 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
677 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
678 reset-names = "axi", "ahb", "dclk";
679 iommus = <&vopb_mmu>;
680 status = "disabled";
682 vopb_out: port {
683 #address-cells = <1>;
684 #size-cells = <0>;
686 vopb_out_hdmi: endpoint@0 {
687 reg = <0>;
688 remote-endpoint = <&hdmi_in_vopb>;
689 };
690 };
691 };
693 vopb_mmu: iommu@ff930300 {
694 compatible = "rockchip,iommu";
695 reg = <0xff930300 0x100>;
696 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
697 interrupt-names = "vopb_mmu";
698 #iommu-cells = <0>;
699 status = "disabled";
700 };
702 vopl: vop@ff940000 {
703 compatible = "rockchip,rk3288-vop";
704 reg = <0xff940000 0x19c>;
705 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
707 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
708 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
709 reset-names = "axi", "ahb", "dclk";
710 iommus = <&vopl_mmu>;
711 status = "disabled";
713 vopl_out: port {
714 #address-cells = <1>;
715 #size-cells = <0>;
717 vopl_out_hdmi: endpoint@0 {
718 reg = <0>;
719 remote-endpoint = <&hdmi_in_vopl>;
720 };
721 };
722 };
724 vopl_mmu: iommu@ff940300 {
725 compatible = "rockchip,iommu";
726 reg = <0xff940300 0x100>;
727 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
728 interrupt-names = "vopl_mmu";
729 #iommu-cells = <0>;
730 status = "disabled";
731 };
733 hdmi: hdmi@ff980000 {
734 compatible = "rockchip,rk3288-dw-hdmi";
735 reg = <0xff980000 0x20000>;
736 reg-io-width = <4>;
737 rockchip,grf = <&grf>;
738 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
740 clock-names = "iahb", "isfr";
741 status = "disabled";
743 ports {
744 hdmi_in: port {
745 #address-cells = <1>;
746 #size-cells = <0>;
747 hdmi_in_vopb: endpoint@0 {
748 reg = <0>;
749 remote-endpoint = <&vopb_out_hdmi>;
750 };
751 hdmi_in_vopl: endpoint@1 {
752 reg = <1>;
753 remote-endpoint = <&vopl_out_hdmi>;
754 };
755 };
756 };
757 };
759 gic: interrupt-controller@ffc01000 {
760 compatible = "arm,gic-400";
761 interrupt-controller;
762 #interrupt-cells = <3>;
763 #address-cells = <0>;
765 reg = <0xffc01000 0x1000>,
766 <0xffc02000 0x1000>,
767 <0xffc04000 0x2000>,
768 <0xffc06000 0x2000>;
769 interrupts = <GIC_PPI 9 0xf04>;
770 };
772 usbphy: phy {
773 compatible = "rockchip,rk3288-usb-phy";
774 rockchip,grf = <&grf>;
775 #address-cells = <1>;
776 #size-cells = <0>;
777 status = "disabled";
779 usbphy0: usb-phy0 {
780 #phy-cells = <0>;
781 reg = <0x320>;
782 clocks = <&cru SCLK_OTGPHY0>;
783 clock-names = "phyclk";
784 };
786 usbphy1: usb-phy1 {
787 #phy-cells = <0>;
788 reg = <0x334>;
789 clocks = <&cru SCLK_OTGPHY1>;
790 clock-names = "phyclk";
791 };
793 usbphy2: usb-phy2 {
794 #phy-cells = <0>;
795 reg = <0x348>;
796 clocks = <&cru SCLK_OTGPHY2>;
797 clock-names = "phyclk";
798 };
799 };
801 pinctrl: pinctrl {
802 compatible = "rockchip,rk3288-pinctrl";
803 rockchip,grf = <&grf>;
804 rockchip,pmu = <&pmu>;
805 #address-cells = <1>;
806 #size-cells = <1>;
807 ranges;
809 gpio0: gpio0@ff750000 {
810 compatible = "rockchip,gpio-bank";
811 reg = <0xff750000 0x100>;
812 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&cru PCLK_GPIO0>;
815 gpio-controller;
816 #gpio-cells = <2>;
818 interrupt-controller;
819 #interrupt-cells = <2>;
820 };
822 gpio1: gpio1@ff780000 {
823 compatible = "rockchip,gpio-bank";
824 reg = <0xff780000 0x100>;
825 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
826 clocks = <&cru PCLK_GPIO1>;
828 gpio-controller;
829 #gpio-cells = <2>;
831 interrupt-controller;
832 #interrupt-cells = <2>;
833 };
835 gpio2: gpio2@ff790000 {
836 compatible = "rockchip,gpio-bank";
837 reg = <0xff790000 0x100>;
838 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&cru PCLK_GPIO2>;
841 gpio-controller;
842 #gpio-cells = <2>;
844 interrupt-controller;
845 #interrupt-cells = <2>;
846 };
848 gpio3: gpio3@ff7a0000 {
849 compatible = "rockchip,gpio-bank";
850 reg = <0xff7a0000 0x100>;
851 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&cru PCLK_GPIO3>;
854 gpio-controller;
855 #gpio-cells = <2>;
857 interrupt-controller;
858 #interrupt-cells = <2>;
859 };
861 gpio4: gpio4@ff7b0000 {
862 compatible = "rockchip,gpio-bank";
863 reg = <0xff7b0000 0x100>;
864 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&cru PCLK_GPIO4>;
867 gpio-controller;
868 #gpio-cells = <2>;
870 interrupt-controller;
871 #interrupt-cells = <2>;
872 };
874 gpio5: gpio5@ff7c0000 {
875 compatible = "rockchip,gpio-bank";
876 reg = <0xff7c0000 0x100>;
877 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
878 clocks = <&cru PCLK_GPIO5>;
880 gpio-controller;
881 #gpio-cells = <2>;
883 interrupt-controller;
884 #interrupt-cells = <2>;
885 };
887 gpio6: gpio6@ff7d0000 {
888 compatible = "rockchip,gpio-bank";
889 reg = <0xff7d0000 0x100>;
890 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
891 clocks = <&cru PCLK_GPIO6>;
893 gpio-controller;
894 #gpio-cells = <2>;
896 interrupt-controller;
897 #interrupt-cells = <2>;
898 };
900 gpio7: gpio7@ff7e0000 {
901 compatible = "rockchip,gpio-bank";
902 reg = <0xff7e0000 0x100>;
903 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
904 clocks = <&cru PCLK_GPIO7>;
906 gpio-controller;
907 #gpio-cells = <2>;
909 interrupt-controller;
910 #interrupt-cells = <2>;
911 };
913 gpio8: gpio8@ff7f0000 {
914 compatible = "rockchip,gpio-bank";
915 reg = <0xff7f0000 0x100>;
916 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
917 clocks = <&cru PCLK_GPIO8>;
919 gpio-controller;
920 #gpio-cells = <2>;
922 interrupt-controller;
923 #interrupt-cells = <2>;
924 };
926 pcfg_pull_up: pcfg-pull-up {
927 bias-pull-up;
928 };
930 pcfg_pull_down: pcfg-pull-down {
931 bias-pull-down;
932 };
934 pcfg_pull_none: pcfg-pull-none {
935 bias-disable;
936 };
938 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
939 bias-disable;
940 drive-strength = <12>;
941 };
943 sleep {
944 global_pwroff: global-pwroff {
945 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
946 };
948 ddrio_pwroff: ddrio-pwroff {
949 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
950 };
952 ddr0_retention: ddr0-retention {
953 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
954 };
956 ddr1_retention: ddr1-retention {
957 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
958 };
959 };
961 i2c0 {
962 i2c0_xfer: i2c0-xfer {
963 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
964 <0 16 RK_FUNC_1 &pcfg_pull_none>;
965 };
966 };
968 i2c1 {
969 i2c1_xfer: i2c1-xfer {
970 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
971 <8 5 RK_FUNC_1 &pcfg_pull_none>;
972 };
973 };
975 i2c2 {
976 i2c2_xfer: i2c2-xfer {
977 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
978 <6 10 RK_FUNC_1 &pcfg_pull_none>;
979 };
980 };
982 i2c3 {
983 i2c3_xfer: i2c3-xfer {
984 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
985 <2 17 RK_FUNC_1 &pcfg_pull_none>;
986 };
987 };
989 i2c4 {
990 i2c4_xfer: i2c4-xfer {
991 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
992 <7 18 RK_FUNC_1 &pcfg_pull_none>;
993 };
994 };
996 i2c5 {
997 i2c5_xfer: i2c5-xfer {
998 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
999 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1000 };
1001 };
1003 i2s0 {
1004 i2s0_bus: i2s0-bus {
1005 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1006 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1007 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1008 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1009 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1010 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1011 };
1012 };
1014 sdmmc {
1015 sdmmc_clk: sdmmc-clk {
1016 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1017 };
1019 sdmmc_cmd: sdmmc-cmd {
1020 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1021 };
1023 sdmmc_cd: sdmcc-cd {
1024 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1025 };
1027 sdmmc_bus1: sdmmc-bus1 {
1028 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1029 };
1031 sdmmc_bus4: sdmmc-bus4 {
1032 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1033 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1034 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1035 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1036 };
1037 };
1039 sdio0 {
1040 sdio0_bus1: sdio0-bus1 {
1041 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1042 };
1044 sdio0_bus4: sdio0-bus4 {
1045 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1046 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1047 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1048 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1049 };
1051 sdio0_cmd: sdio0-cmd {
1052 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1053 };
1055 sdio0_clk: sdio0-clk {
1056 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1057 };
1059 sdio0_cd: sdio0-cd {
1060 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1061 };
1063 sdio0_wp: sdio0-wp {
1064 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1065 };
1067 sdio0_pwr: sdio0-pwr {
1068 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1069 };
1071 sdio0_bkpwr: sdio0-bkpwr {
1072 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1073 };
1075 sdio0_int: sdio0-int {
1076 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1077 };
1078 };
1080 sdio1 {
1081 sdio1_bus1: sdio1-bus1 {
1082 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1083 };
1085 sdio1_bus4: sdio1-bus4 {
1086 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1087 <3 25 4 &pcfg_pull_up>,
1088 <3 26 4 &pcfg_pull_up>,
1089 <3 27 4 &pcfg_pull_up>;
1090 };
1092 sdio1_cd: sdio1-cd {
1093 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1094 };
1096 sdio1_wp: sdio1-wp {
1097 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1098 };
1100 sdio1_bkpwr: sdio1-bkpwr {
1101 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1102 };
1104 sdio1_int: sdio1-int {
1105 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1106 };
1108 sdio1_cmd: sdio1-cmd {
1109 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1110 };
1112 sdio1_clk: sdio1-clk {
1113 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1114 };
1116 sdio1_pwr: sdio1-pwr {
1117 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1118 };
1119 };
1121 emmc {
1122 emmc_clk: emmc-clk {
1123 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1124 };
1126 emmc_cmd: emmc-cmd {
1127 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1128 };
1130 emmc_pwr: emmc-pwr {
1131 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1132 };
1134 emmc_bus1: emmc-bus1 {
1135 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1136 };
1138 emmc_bus4: emmc-bus4 {
1139 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1140 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1141 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1142 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1143 };
1145 emmc_bus8: emmc-bus8 {
1146 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1147 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1148 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1149 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1150 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1151 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1152 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1153 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1154 };
1155 };
1157 spi0 {
1158 spi0_clk: spi0-clk {
1159 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1160 };
1161 spi0_cs0: spi0-cs0 {
1162 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1163 };
1164 spi0_tx: spi0-tx {
1165 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1166 };
1167 spi0_rx: spi0-rx {
1168 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1169 };
1170 spi0_cs1: spi0-cs1 {
1171 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1172 };
1173 };
1174 spi1 {
1175 spi1_clk: spi1-clk {
1176 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1177 };
1178 spi1_cs0: spi1-cs0 {
1179 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1180 };
1181 spi1_rx: spi1-rx {
1182 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1183 };
1184 spi1_tx: spi1-tx {
1185 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1186 };
1187 };
1189 spi2 {
1190 spi2_cs1: spi2-cs1 {
1191 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1192 };
1193 spi2_clk: spi2-clk {
1194 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1195 };
1196 spi2_cs0: spi2-cs0 {
1197 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1198 };
1199 spi2_rx: spi2-rx {
1200 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1201 };
1202 spi2_tx: spi2-tx {
1203 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1204 };
1205 };
1207 uart0 {
1208 uart0_xfer: uart0-xfer {
1209 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1210 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1211 };
1213 uart0_cts: uart0-cts {
1214 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1215 };
1217 uart0_rts: uart0-rts {
1218 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1219 };
1220 };
1222 uart1 {
1223 uart1_xfer: uart1-xfer {
1224 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1225 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1226 };
1228 uart1_cts: uart1-cts {
1229 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1230 };
1232 uart1_rts: uart1-rts {
1233 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1234 };
1235 };
1237 uart2 {
1238 uart2_xfer: uart2-xfer {
1239 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1240 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1241 };
1242 /* no rts / cts for uart2 */
1243 };
1245 uart3 {
1246 uart3_xfer: uart3-xfer {
1247 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1248 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1249 };
1251 uart3_cts: uart3-cts {
1252 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1253 };
1255 uart3_rts: uart3-rts {
1256 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1257 };
1258 };
1260 uart4 {
1261 uart4_xfer: uart4-xfer {
1262 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1263 <5 13 3 &pcfg_pull_none>;
1264 };
1266 uart4_cts: uart4-cts {
1267 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1268 };
1270 uart4_rts: uart4-rts {
1271 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1272 };
1273 };
1275 tsadc {
1276 otp_out: otp-out {
1277 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1278 };
1279 };
1281 pwm0 {
1282 pwm0_pin: pwm0-pin {
1283 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1284 };
1285 };
1287 pwm1 {
1288 pwm1_pin: pwm1-pin {
1289 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1290 };
1291 };
1293 pwm2 {
1294 pwm2_pin: pwm2-pin {
1295 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1296 };
1297 };
1299 pwm3 {
1300 pwm3_pin: pwm3-pin {
1301 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1302 };
1303 };
1305 gmac {
1306 rgmii_pins: rgmii-pins {
1307 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1308 <3 31 3 &pcfg_pull_none>,
1309 <3 26 3 &pcfg_pull_none>,
1310 <3 27 3 &pcfg_pull_none>,
1311 <3 28 3 &pcfg_pull_none_12ma>,
1312 <3 29 3 &pcfg_pull_none_12ma>,
1313 <3 24 3 &pcfg_pull_none_12ma>,
1314 <3 25 3 &pcfg_pull_none_12ma>,
1315 <4 0 3 &pcfg_pull_none>,
1316 <4 5 3 &pcfg_pull_none>,
1317 <4 6 3 &pcfg_pull_none>,
1318 <4 9 3 &pcfg_pull_none_12ma>,
1319 <4 4 3 &pcfg_pull_none_12ma>,
1320 <4 1 3 &pcfg_pull_none>,
1321 <4 3 3 &pcfg_pull_none>;
1322 };
1324 rmii_pins: rmii-pins {
1325 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1326 <3 31 3 &pcfg_pull_none>,
1327 <3 28 3 &pcfg_pull_none>,
1328 <3 29 3 &pcfg_pull_none>,
1329 <4 0 3 &pcfg_pull_none>,
1330 <4 5 3 &pcfg_pull_none>,
1331 <4 4 3 &pcfg_pull_none>,
1332 <4 1 3 &pcfg_pull_none>,
1333 <4 2 3 &pcfg_pull_none>,
1334 <4 3 3 &pcfg_pull_none>;
1335 };
1336 };
1337 };
1338 };