| blob | 78b993abbaa3976ac8582dedd12583e62a912826 |
1 /*
2 * Copyright 2012-2015 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
45 #include "skeleton.dtsi"
47 #include <dt-bindings/dma/sun4i-a10.h>
48 #include <dt-bindings/pinctrl/sun4i-a10.h>
50 / {
51 interrupt-parent = <&intc>;
53 cpus {
54 #address-cells = <1>;
55 #size-cells = <0>;
57 cpu0: cpu@0 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a8";
60 reg = <0x0>;
61 clocks = <&cpu>;
62 };
63 };
65 clocks {
66 #address-cells = <1>;
67 #size-cells = <1>;
68 ranges;
70 /*
71 * This is a dummy clock, to be used as placeholder on
72 * other mux clocks when a specific parent clock is not
73 * yet implemented. It should be dropped when the driver
74 * is complete.
75 */
76 dummy: dummy {
77 #clock-cells = <0>;
78 compatible = "fixed-clock";
79 clock-frequency = <0>;
80 };
82 osc24M: clk@01c20050 {
83 #clock-cells = <0>;
84 compatible = "allwinner,sun4i-a10-osc-clk";
85 reg = <0x01c20050 0x4>;
86 clock-frequency = <24000000>;
87 clock-output-names = "osc24M";
88 };
90 osc32k: clk@0 {
91 #clock-cells = <0>;
92 compatible = "fixed-clock";
93 clock-frequency = <32768>;
94 clock-output-names = "osc32k";
95 };
97 pll1: clk@01c20000 {
98 #clock-cells = <0>;
99 compatible = "allwinner,sun4i-a10-pll1-clk";
100 reg = <0x01c20000 0x4>;
101 clocks = <&osc24M>;
102 clock-output-names = "pll1";
103 };
105 pll4: clk@01c20018 {
106 #clock-cells = <0>;
107 compatible = "allwinner,sun4i-a10-pll1-clk";
108 reg = <0x01c20018 0x4>;
109 clocks = <&osc24M>;
110 clock-output-names = "pll4";
111 };
113 pll5: clk@01c20020 {
114 #clock-cells = <1>;
115 compatible = "allwinner,sun4i-a10-pll5-clk";
116 reg = <0x01c20020 0x4>;
117 clocks = <&osc24M>;
118 clock-output-names = "pll5_ddr", "pll5_other";
119 };
121 pll6: clk@01c20028 {
122 #clock-cells = <1>;
123 compatible = "allwinner,sun4i-a10-pll6-clk";
124 reg = <0x01c20028 0x4>;
125 clocks = <&osc24M>;
126 clock-output-names = "pll6_sata", "pll6_other", "pll6";
127 };
129 /* dummy is 200M */
130 cpu: cpu@01c20054 {
131 #clock-cells = <0>;
132 compatible = "allwinner,sun4i-a10-cpu-clk";
133 reg = <0x01c20054 0x4>;
134 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
135 clock-output-names = "cpu";
136 };
138 axi: axi@01c20054 {
139 #clock-cells = <0>;
140 compatible = "allwinner,sun4i-a10-axi-clk";
141 reg = <0x01c20054 0x4>;
142 clocks = <&cpu>;
143 clock-output-names = "axi";
144 };
146 ahb: ahb@01c20054 {
147 #clock-cells = <0>;
148 compatible = "allwinner,sun5i-a13-ahb-clk";
149 reg = <0x01c20054 0x4>;
150 clocks = <&axi>, <&cpu>, <&pll6 1>;
151 clock-output-names = "ahb";
152 /*
153 * Use PLL6 as parent, instead of CPU/AXI
154 * which has rate changes due to cpufreq
155 */
156 assigned-clocks = <&ahb>;
157 assigned-clock-parents = <&pll6 1>;
158 };
160 apb0: apb0@01c20054 {
161 #clock-cells = <0>;
162 compatible = "allwinner,sun4i-a10-apb0-clk";
163 reg = <0x01c20054 0x4>;
164 clocks = <&ahb>;
165 clock-output-names = "apb0";
166 };
168 apb1: clk@01c20058 {
169 #clock-cells = <0>;
170 compatible = "allwinner,sun4i-a10-apb1-clk";
171 reg = <0x01c20058 0x4>;
172 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
173 clock-output-names = "apb1";
174 };
176 axi_gates: clk@01c2005c {
177 #clock-cells = <1>;
178 compatible = "allwinner,sun4i-a10-axi-gates-clk";
179 reg = <0x01c2005c 0x4>;
180 clocks = <&axi>;
181 clock-indices = <0>;
182 clock-output-names = "axi_dram";
183 };
185 nand_clk: clk@01c20080 {
186 #clock-cells = <0>;
187 compatible = "allwinner,sun4i-a10-mod0-clk";
188 reg = <0x01c20080 0x4>;
189 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
190 clock-output-names = "nand";
191 };
193 ms_clk: clk@01c20084 {
194 #clock-cells = <0>;
195 compatible = "allwinner,sun4i-a10-mod0-clk";
196 reg = <0x01c20084 0x4>;
197 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
198 clock-output-names = "ms";
199 };
201 mmc0_clk: clk@01c20088 {
202 #clock-cells = <1>;
203 compatible = "allwinner,sun4i-a10-mmc-clk";
204 reg = <0x01c20088 0x4>;
205 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
206 clock-output-names = "mmc0",
207 "mmc0_output",
208 "mmc0_sample";
209 };
211 mmc1_clk: clk@01c2008c {
212 #clock-cells = <1>;
213 compatible = "allwinner,sun4i-a10-mmc-clk";
214 reg = <0x01c2008c 0x4>;
215 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
216 clock-output-names = "mmc1",
217 "mmc1_output",
218 "mmc1_sample";
219 };
221 mmc2_clk: clk@01c20090 {
222 #clock-cells = <1>;
223 compatible = "allwinner,sun4i-a10-mmc-clk";
224 reg = <0x01c20090 0x4>;
225 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
226 clock-output-names = "mmc2",
227 "mmc2_output",
228 "mmc2_sample";
229 };
231 ts_clk: clk@01c20098 {
232 #clock-cells = <0>;
233 compatible = "allwinner,sun4i-a10-mod0-clk";
234 reg = <0x01c20098 0x4>;
235 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
236 clock-output-names = "ts";
237 };
239 ss_clk: clk@01c2009c {
240 #clock-cells = <0>;
241 compatible = "allwinner,sun4i-a10-mod0-clk";
242 reg = <0x01c2009c 0x4>;
243 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
244 clock-output-names = "ss";
245 };
247 spi0_clk: clk@01c200a0 {
248 #clock-cells = <0>;
249 compatible = "allwinner,sun4i-a10-mod0-clk";
250 reg = <0x01c200a0 0x4>;
251 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
252 clock-output-names = "spi0";
253 };
255 spi1_clk: clk@01c200a4 {
256 #clock-cells = <0>;
257 compatible = "allwinner,sun4i-a10-mod0-clk";
258 reg = <0x01c200a4 0x4>;
259 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
260 clock-output-names = "spi1";
261 };
263 spi2_clk: clk@01c200a8 {
264 #clock-cells = <0>;
265 compatible = "allwinner,sun4i-a10-mod0-clk";
266 reg = <0x01c200a8 0x4>;
267 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
268 clock-output-names = "spi2";
269 };
271 ir0_clk: clk@01c200b0 {
272 #clock-cells = <0>;
273 compatible = "allwinner,sun4i-a10-mod0-clk";
274 reg = <0x01c200b0 0x4>;
275 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
276 clock-output-names = "ir0";
277 };
279 usb_clk: clk@01c200cc {
280 #clock-cells = <1>;
281 #reset-cells = <1>;
282 compatible = "allwinner,sun5i-a13-usb-clk";
283 reg = <0x01c200cc 0x4>;
284 clocks = <&pll6 1>;
285 clock-output-names = "usb_ohci0", "usb_phy";
286 };
288 mbus_clk: clk@01c2015c {
289 #clock-cells = <0>;
290 compatible = "allwinner,sun5i-a13-mbus-clk";
291 reg = <0x01c2015c 0x4>;
292 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
293 clock-output-names = "mbus";
294 };
295 };
297 soc@01c00000 {
298 compatible = "simple-bus";
299 #address-cells = <1>;
300 #size-cells = <1>;
301 ranges;
303 sram-controller@01c00000 {
304 compatible = "allwinner,sun4i-a10-sram-controller";
305 reg = <0x01c00000 0x30>;
306 #address-cells = <1>;
307 #size-cells = <1>;
308 ranges;
310 sram_a: sram@00000000 {
311 compatible = "mmio-sram";
312 reg = <0x00000000 0xc000>;
313 #address-cells = <1>;
314 #size-cells = <1>;
315 ranges = <0 0x00000000 0xc000>;
316 };
318 sram_d: sram@00010000 {
319 compatible = "mmio-sram";
320 reg = <0x00010000 0x1000>;
321 #address-cells = <1>;
322 #size-cells = <1>;
323 ranges = <0 0x00010000 0x1000>;
325 otg_sram: sram-section@0000 {
326 compatible = "allwinner,sun4i-a10-sram-d";
327 reg = <0x0000 0x1000>;
328 status = "disabled";
329 };
330 };
331 };
333 dma: dma-controller@01c02000 {
334 compatible = "allwinner,sun4i-a10-dma";
335 reg = <0x01c02000 0x1000>;
336 interrupts = <27>;
337 clocks = <&ahb_gates 6>;
338 #dma-cells = <2>;
339 };
341 spi0: spi@01c05000 {
342 compatible = "allwinner,sun4i-a10-spi";
343 reg = <0x01c05000 0x1000>;
344 interrupts = <10>;
345 clocks = <&ahb_gates 20>, <&spi0_clk>;
346 clock-names = "ahb", "mod";
347 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
348 <&dma SUN4I_DMA_DEDICATED 26>;
349 dma-names = "rx", "tx";
350 status = "disabled";
351 #address-cells = <1>;
352 #size-cells = <0>;
353 };
355 spi1: spi@01c06000 {
356 compatible = "allwinner,sun4i-a10-spi";
357 reg = <0x01c06000 0x1000>;
358 interrupts = <11>;
359 clocks = <&ahb_gates 21>, <&spi1_clk>;
360 clock-names = "ahb", "mod";
361 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
362 <&dma SUN4I_DMA_DEDICATED 8>;
363 dma-names = "rx", "tx";
364 status = "disabled";
365 #address-cells = <1>;
366 #size-cells = <0>;
367 };
369 mmc0: mmc@01c0f000 {
370 compatible = "allwinner,sun5i-a13-mmc";
371 reg = <0x01c0f000 0x1000>;
372 clocks = <&ahb_gates 8>,
373 <&mmc0_clk 0>,
374 <&mmc0_clk 1>,
375 <&mmc0_clk 2>;
376 clock-names = "ahb",
377 "mmc",
378 "output",
379 "sample";
380 interrupts = <32>;
381 status = "disabled";
382 #address-cells = <1>;
383 #size-cells = <0>;
384 };
386 mmc1: mmc@01c10000 {
387 compatible = "allwinner,sun5i-a13-mmc";
388 reg = <0x01c10000 0x1000>;
389 clocks = <&ahb_gates 9>,
390 <&mmc1_clk 0>,
391 <&mmc1_clk 1>,
392 <&mmc1_clk 2>;
393 clock-names = "ahb",
394 "mmc",
395 "output",
396 "sample";
397 interrupts = <33>;
398 status = "disabled";
399 #address-cells = <1>;
400 #size-cells = <0>;
401 };
403 mmc2: mmc@01c11000 {
404 compatible = "allwinner,sun5i-a13-mmc";
405 reg = <0x01c11000 0x1000>;
406 clocks = <&ahb_gates 10>,
407 <&mmc2_clk 0>,
408 <&mmc2_clk 1>,
409 <&mmc2_clk 2>;
410 clock-names = "ahb",
411 "mmc",
412 "output",
413 "sample";
414 interrupts = <34>;
415 status = "disabled";
416 #address-cells = <1>;
417 #size-cells = <0>;
418 };
420 usb_otg: usb@01c13000 {
421 compatible = "allwinner,sun4i-a10-musb";
422 reg = <0x01c13000 0x0400>;
423 clocks = <&ahb_gates 0>;
424 interrupts = <38>;
425 interrupt-names = "mc";
426 phys = <&usbphy 0>;
427 phy-names = "usb";
428 extcon = <&usbphy 0>;
429 allwinner,sram = <&otg_sram 1>;
430 status = "disabled";
431 };
433 usbphy: phy@01c13400 {
434 #phy-cells = <1>;
435 compatible = "allwinner,sun5i-a13-usb-phy";
436 reg = <0x01c13400 0x10 0x01c14800 0x4>;
437 reg-names = "phy_ctrl", "pmu1";
438 clocks = <&usb_clk 8>;
439 clock-names = "usb_phy";
440 resets = <&usb_clk 0>, <&usb_clk 1>;
441 reset-names = "usb0_reset", "usb1_reset";
442 status = "disabled";
443 };
445 ehci0: usb@01c14000 {
446 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
447 reg = <0x01c14000 0x100>;
448 interrupts = <39>;
449 clocks = <&ahb_gates 1>;
450 phys = <&usbphy 1>;
451 phy-names = "usb";
452 status = "disabled";
453 };
455 ohci0: usb@01c14400 {
456 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
457 reg = <0x01c14400 0x100>;
458 interrupts = <40>;
459 clocks = <&usb_clk 6>, <&ahb_gates 2>;
460 phys = <&usbphy 1>;
461 phy-names = "usb";
462 status = "disabled";
463 };
465 spi2: spi@01c17000 {
466 compatible = "allwinner,sun4i-a10-spi";
467 reg = <0x01c17000 0x1000>;
468 interrupts = <12>;
469 clocks = <&ahb_gates 22>, <&spi2_clk>;
470 clock-names = "ahb", "mod";
471 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
472 <&dma SUN4I_DMA_DEDICATED 28>;
473 dma-names = "rx", "tx";
474 status = "disabled";
475 #address-cells = <1>;
476 #size-cells = <0>;
477 };
479 intc: interrupt-controller@01c20400 {
480 compatible = "allwinner,sun4i-a10-ic";
481 reg = <0x01c20400 0x400>;
482 interrupt-controller;
483 #interrupt-cells = <1>;
484 };
486 pio: pinctrl@01c20800 {
487 reg = <0x01c20800 0x400>;
488 interrupts = <28>;
489 clocks = <&apb0_gates 5>;
490 gpio-controller;
491 interrupt-controller;
492 #interrupt-cells = <3>;
493 #gpio-cells = <3>;
495 i2c0_pins_a: i2c0@0 {
496 allwinner,pins = "PB0", "PB1";
497 allwinner,function = "i2c0";
498 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
499 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
500 };
502 i2c1_pins_a: i2c1@0 {
503 allwinner,pins = "PB15", "PB16";
504 allwinner,function = "i2c1";
505 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
506 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
507 };
509 i2c2_pins_a: i2c2@0 {
510 allwinner,pins = "PB17", "PB18";
511 allwinner,function = "i2c2";
512 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
513 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
514 };
516 mmc0_pins_a: mmc0@0 {
517 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
518 "PF4", "PF5";
519 allwinner,function = "mmc0";
520 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
521 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
522 };
524 mmc2_pins_a: mmc2@0 {
525 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
526 "PC10", "PC11", "PC12", "PC13",
527 "PC14", "PC15";
528 allwinner,function = "mmc2";
529 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
530 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
531 };
532 };
534 timer@01c20c00 {
535 compatible = "allwinner,sun4i-a10-timer";
536 reg = <0x01c20c00 0x90>;
537 interrupts = <22>;
538 clocks = <&osc24M>;
539 };
541 wdt: watchdog@01c20c90 {
542 compatible = "allwinner,sun4i-a10-wdt";
543 reg = <0x01c20c90 0x10>;
544 };
546 lradc: lradc@01c22800 {
547 compatible = "allwinner,sun4i-a10-lradc-keys";
548 reg = <0x01c22800 0x100>;
549 interrupts = <31>;
550 status = "disabled";
551 };
553 sid: eeprom@01c23800 {
554 compatible = "allwinner,sun4i-a10-sid";
555 reg = <0x01c23800 0x10>;
556 };
558 rtp: rtp@01c25000 {
559 compatible = "allwinner,sun5i-a13-ts";
560 reg = <0x01c25000 0x100>;
561 interrupts = <29>;
562 #thermal-sensor-cells = <0>;
563 };
565 uart1: serial@01c28400 {
566 compatible = "snps,dw-apb-uart";
567 reg = <0x01c28400 0x400>;
568 interrupts = <2>;
569 reg-shift = <2>;
570 reg-io-width = <4>;
571 clocks = <&apb1_gates 17>;
572 status = "disabled";
573 };
575 uart3: serial@01c28c00 {
576 compatible = "snps,dw-apb-uart";
577 reg = <0x01c28c00 0x400>;
578 interrupts = <4>;
579 reg-shift = <2>;
580 reg-io-width = <4>;
581 clocks = <&apb1_gates 19>;
582 status = "disabled";
583 };
585 i2c0: i2c@01c2ac00 {
586 compatible = "allwinner,sun4i-a10-i2c";
587 reg = <0x01c2ac00 0x400>;
588 interrupts = <7>;
589 clocks = <&apb1_gates 0>;
590 status = "disabled";
591 #address-cells = <1>;
592 #size-cells = <0>;
593 };
595 i2c1: i2c@01c2b000 {
596 compatible = "allwinner,sun4i-a10-i2c";
597 reg = <0x01c2b000 0x400>;
598 interrupts = <8>;
599 clocks = <&apb1_gates 1>;
600 status = "disabled";
601 #address-cells = <1>;
602 #size-cells = <0>;
603 };
605 i2c2: i2c@01c2b400 {
606 compatible = "allwinner,sun4i-a10-i2c";
607 reg = <0x01c2b400 0x400>;
608 interrupts = <9>;
609 clocks = <&apb1_gates 2>;
610 status = "disabled";
611 #address-cells = <1>;
612 #size-cells = <0>;
613 };
615 timer@01c60000 {
616 compatible = "allwinner,sun5i-a13-hstimer";
617 reg = <0x01c60000 0x1000>;
618 interrupts = <82>, <83>;
619 clocks = <&ahb_gates 28>;
620 };
621 };
622 };