arch/arm/boot/dts/tegra20.dtsi

   1 #include <dt-bindings/clock/tegra20-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5
   6 #include "skeleton.dtsi"
   7
   8 / {
   9         compatible = "nvidia,tegra20";
  10         interrupt-parent = <&lic>;
  11
  12         host1x@50000000 {
  13                 compatible = "nvidia,tegra20-host1x", "simple-bus";
  14                 reg = <0x50000000 0x00024000>;
  15                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  16                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  17                 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
  18                 resets = <&tegra_car 28>;
  19                 reset-names = "host1x";
  20
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23
  24                 ranges = <0x54000000 0x54000000 0x04000000>;
  25
  26                 mpe@54040000 {
  27                         compatible = "nvidia,tegra20-mpe";
  28                         reg = <0x54040000 0x00040000>;
  29                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
  30                         clocks = <&tegra_car TEGRA20_CLK_MPE>;
  31                         resets = <&tegra_car 60>;
  32                         reset-names = "mpe";
  33                 };
  34
  35                 vi@54080000 {
  36                         compatible = "nvidia,tegra20-vi";
  37                         reg = <0x54080000 0x00040000>;
  38                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  39                         clocks = <&tegra_car TEGRA20_CLK_VI>;
  40                         resets = <&tegra_car 20>;
  41                         reset-names = "vi";
  42                 };
  43
  44                 epp@540c0000 {
  45                         compatible = "nvidia,tegra20-epp";
  46                         reg = <0x540c0000 0x00040000>;
  47                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  48                         clocks = <&tegra_car TEGRA20_CLK_EPP>;
  49                         resets = <&tegra_car 19>;
  50                         reset-names = "epp";
  51                 };
  52
  53                 isp@54100000 {
  54                         compatible = "nvidia,tegra20-isp";
  55                         reg = <0x54100000 0x00040000>;
  56                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  57                         clocks = <&tegra_car TEGRA20_CLK_ISP>;
  58                         resets = <&tegra_car 23>;
  59                         reset-names = "isp";
  60                 };
  61
  62                 gr2d@54140000 {
  63                         compatible = "nvidia,tegra20-gr2d";
  64                         reg = <0x54140000 0x00040000>;
  65                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  66                         clocks = <&tegra_car TEGRA20_CLK_GR2D>;
  67                         resets = <&tegra_car 21>;
  68                         reset-names = "2d";
  69                 };
  70
  71                 gr3d@54180000 {
  72                         compatible = "nvidia,tegra20-gr3d";
  73                         reg = <0x54180000 0x00040000>;
  74                         clocks = <&tegra_car TEGRA20_CLK_GR3D>;
  75                         resets = <&tegra_car 24>;
  76                         reset-names = "3d";
  77                 };
  78
  79                 dc@54200000 {
  80                         compatible = "nvidia,tegra20-dc";
  81                         reg = <0x54200000 0x00040000>;
  82                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  83                         clocks = <&tegra_car TEGRA20_CLK_DISP1>,
  84                                  <&tegra_car TEGRA20_CLK_PLL_P>;
  85                         clock-names = "dc", "parent";
  86                         resets = <&tegra_car 27>;
  87                         reset-names = "dc";
  88
  89                         nvidia,head = <0>;
  90
  91                         rgb {
  92                                 status = "disabled";
  93                         };
  94                 };
  95
  96                 dc@54240000 {
  97                         compatible = "nvidia,tegra20-dc";
  98                         reg = <0x54240000 0x00040000>;
  99                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 100                         clocks = <&tegra_car TEGRA20_CLK_DISP2>,
 101                                  <&tegra_car TEGRA20_CLK_PLL_P>;
 102                         clock-names = "dc", "parent";
 103                         resets = <&tegra_car 26>;
 104                         reset-names = "dc";
 105
 106                         nvidia,head = <1>;
 107
 108                         rgb {
 109                                 status = "disabled";
 110                         };
 111                 };
 112
 113                 hdmi@54280000 {
 114                         compatible = "nvidia,tegra20-hdmi";
 115                         reg = <0x54280000 0x00040000>;
 116                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 117                         clocks = <&tegra_car TEGRA20_CLK_HDMI>,
 118                                  <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 119                         clock-names = "hdmi", "parent";
 120                         resets = <&tegra_car 51>;
 121                         reset-names = "hdmi";
 122                         status = "disabled";
 123                 };
 124
 125                 tvo@542c0000 {
 126                         compatible = "nvidia,tegra20-tvo";
 127                         reg = <0x542c0000 0x00040000>;
 128                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 129                         clocks = <&tegra_car TEGRA20_CLK_TVO>;
 130                         status = "disabled";
 131                 };
 132
 133                 dsi@54300000 {
 134                         compatible = "nvidia,tegra20-dsi";
 135                         reg = <0x54300000 0x00040000>;
 136                         clocks = <&tegra_car TEGRA20_CLK_DSI>;
 137                         resets = <&tegra_car 48>;
 138                         reset-names = "dsi";
 139                         status = "disabled";
 140                 };
 141         };
 142
 143         timer@50040600 {
 144                 compatible = "arm,cortex-a9-twd-timer";
 145                 interrupt-parent = <&intc>;
 146                 reg = <0x50040600 0x20>;
 147                 interrupts = <GIC_PPI 13
 148                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 149                 clocks = <&tegra_car TEGRA20_CLK_TWD>;
 150         };
 151
 152         intc: interrupt-controller@50041000 {
 153                 compatible = "arm,cortex-a9-gic";
 154                 reg = <0x50041000 0x1000
 155                        0x50040100 0x0100>;
 156                 interrupt-controller;
 157                 #interrupt-cells = <3>;
 158                 interrupt-parent = <&intc>;
 159         };
 160
 161         cache-controller@50043000 {
 162                 compatible = "arm,pl310-cache";
 163                 reg = <0x50043000 0x1000>;
 164                 arm,data-latency = <5 5 2>;
 165                 arm,tag-latency = <4 4 2>;
 166                 cache-unified;
 167                 cache-level = <2>;
 168         };
 169
 170         lic: interrupt-controller@60004000 {
 171                 compatible = "nvidia,tegra20-ictlr";
 172                 reg = <0x60004000 0x100>,
 173                       <0x60004100 0x50>,
 174                       <0x60004200 0x50>,
 175                       <0x60004300 0x50>;
 176                 interrupt-controller;
 177                 #interrupt-cells = <3>;
 178                 interrupt-parent = <&intc>;
 179         };
 180
 181         timer@60005000 {
 182                 compatible = "nvidia,tegra20-timer";
 183                 reg = <0x60005000 0x60>;
 184                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 185                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 186                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 187                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 188                 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
 189         };
 190
 191         tegra_car: clock@60006000 {
 192                 compatible = "nvidia,tegra20-car";
 193                 reg = <0x60006000 0x1000>;
 194                 #clock-cells = <1>;
 195                 #reset-cells = <1>;
 196         };
 197
 198         flow-controller@60007000 {
 199                 compatible = "nvidia,tegra20-flowctrl";
 200                 reg = <0x60007000 0x1000>;
 201         };
 202
 203         apbdma: dma@6000a000 {
 204                 compatible = "nvidia,tegra20-apbdma";
 205                 reg = <0x6000a000 0x1200>;
 206                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 207                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 208                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 209                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 210                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 211                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 212                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 213                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 214                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 215                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 216                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 217                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 218                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 221                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 222                 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
 223                 resets = <&tegra_car 34>;
 224                 reset-names = "dma";
 225                 #dma-cells = <1>;
 226         };
 227
 228         ahb@6000c000 {
 229                 compatible = "nvidia,tegra20-ahb";
 230                 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
 231         };
 232
 233         gpio: gpio@6000d000 {
 234                 compatible = "nvidia,tegra20-gpio";
 235                 reg = <0x6000d000 0x1000>;
 236                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 237                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 238                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 239                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 240                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 241                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 242                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 243                 #gpio-cells = <2>;
 244                 gpio-controller;
 245                 #interrupt-cells = <2>;
 246                 interrupt-controller;
 247                 gpio-ranges = <&pinmux 0 0 224>;
 248         };
 249
 250         apbmisc@70000800 {
 251                 compatible = "nvidia,tegra20-apbmisc";
 252                 reg = <0x70000800 0x64   /* Chip revision */
 253                        0x70000008 0x04>; /* Strapping options */
 254         };
 255
 256         pinmux: pinmux@70000014 {
 257                 compatible = "nvidia,tegra20-pinmux";
 258                 reg = <0x70000014 0x10   /* Tri-state registers */
 259                        0x70000080 0x20   /* Mux registers */
 260                        0x700000a0 0x14   /* Pull-up/down registers */
 261                        0x70000868 0xa8>; /* Pad control registers */
 262         };
 263
 264         das@70000c00 {
 265                 compatible = "nvidia,tegra20-das";
 266                 reg = <0x70000c00 0x80>;
 267         };
 268
 269         tegra_ac97: ac97@70002000 {
 270                 compatible = "nvidia,tegra20-ac97";
 271                 reg = <0x70002000 0x200>;
 272                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 273                 clocks = <&tegra_car TEGRA20_CLK_AC97>;
 274                 resets = <&tegra_car 3>;
 275                 reset-names = "ac97";
 276                 dmas = <&apbdma 12>, <&apbdma 12>;
 277                 dma-names = "rx", "tx";
 278                 status = "disabled";
 279         };
 280
 281         tegra_i2s1: i2s@70002800 {
 282                 compatible = "nvidia,tegra20-i2s";
 283                 reg = <0x70002800 0x200>;
 284                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 285                 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
 286                 resets = <&tegra_car 11>;
 287                 reset-names = "i2s";
 288                 dmas = <&apbdma 2>, <&apbdma 2>;
 289                 dma-names = "rx", "tx";
 290                 status = "disabled";
 291         };
 292
 293         tegra_i2s2: i2s@70002a00 {
 294                 compatible = "nvidia,tegra20-i2s";
 295                 reg = <0x70002a00 0x200>;
 296                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 297                 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
 298                 resets = <&tegra_car 18>;
 299                 reset-names = "i2s";
 300                 dmas = <&apbdma 1>, <&apbdma 1>;
 301                 dma-names = "rx", "tx";
 302                 status = "disabled";
 303         };
 304
 305         /*
 306          * There are two serial driver i.e. 8250 based simple serial
 307          * driver and APB DMA based serial driver for higher baudrate
 308          * and performace. To enable the 8250 based driver, the compatible
 309          * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
 310          * driver, the comptible is "nvidia,tegra20-hsuart".
 311          */
 312         uarta: serial@70006000 {
 313                 compatible = "nvidia,tegra20-uart";
 314                 reg = <0x70006000 0x40>;
 315                 reg-shift = <2>;
 316                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 317                 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
 318                 resets = <&tegra_car 6>;
 319                 reset-names = "serial";
 320                 dmas = <&apbdma 8>, <&apbdma 8>;
 321                 dma-names = "rx", "tx";
 322                 status = "disabled";
 323         };
 324
 325         uartb: serial@70006040 {
 326                 compatible = "nvidia,tegra20-uart";
 327                 reg = <0x70006040 0x40>;
 328                 reg-shift = <2>;
 329                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 330                 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
 331                 resets = <&tegra_car 7>;
 332                 reset-names = "serial";
 333                 dmas = <&apbdma 9>, <&apbdma 9>;
 334                 dma-names = "rx", "tx";
 335                 status = "disabled";
 336         };
 337
 338         uartc: serial@70006200 {
 339                 compatible = "nvidia,tegra20-uart";
 340                 reg = <0x70006200 0x100>;
 341                 reg-shift = <2>;
 342                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 343                 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
 344                 resets = <&tegra_car 55>;
 345                 reset-names = "serial";
 346                 dmas = <&apbdma 10>, <&apbdma 10>;
 347                 dma-names = "rx", "tx";
 348                 status = "disabled";
 349         };
 350
 351         uartd: serial@70006300 {
 352                 compatible = "nvidia,tegra20-uart";
 353                 reg = <0x70006300 0x100>;
 354                 reg-shift = <2>;
 355                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 356                 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
 357                 resets = <&tegra_car 65>;
 358                 reset-names = "serial";
 359                 dmas = <&apbdma 19>, <&apbdma 19>;
 360                 dma-names = "rx", "tx";
 361                 status = "disabled";
 362         };
 363
 364         uarte: serial@70006400 {
 365                 compatible = "nvidia,tegra20-uart";
 366                 reg = <0x70006400 0x100>;
 367                 reg-shift = <2>;
 368                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 369                 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
 370                 resets = <&tegra_car 66>;
 371                 reset-names = "serial";
 372                 dmas = <&apbdma 20>, <&apbdma 20>;
 373                 dma-names = "rx", "tx";
 374                 status = "disabled";
 375         };
 376
 377         pwm: pwm@7000a000 {
 378                 compatible = "nvidia,tegra20-pwm";
 379                 reg = <0x7000a000 0x100>;
 380                 #pwm-cells = <2>;
 381                 clocks = <&tegra_car TEGRA20_CLK_PWM>;
 382                 resets = <&tegra_car 17>;
 383                 reset-names = "pwm";
 384                 status = "disabled";
 385         };
 386
 387         rtc@7000e000 {
 388                 compatible = "nvidia,tegra20-rtc";
 389                 reg = <0x7000e000 0x100>;
 390                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 391                 clocks = <&tegra_car TEGRA20_CLK_RTC>;
 392         };
 393
 394         i2c@7000c000 {
 395                 compatible = "nvidia,tegra20-i2c";
 396                 reg = <0x7000c000 0x100>;
 397                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 398                 #address-cells = <1>;
 399                 #size-cells = <0>;
 400                 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
 401                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 402                 clock-names = "div-clk", "fast-clk";
 403                 resets = <&tegra_car 12>;
 404                 reset-names = "i2c";
 405                 dmas = <&apbdma 21>, <&apbdma 21>;
 406                 dma-names = "rx", "tx";
 407                 status = "disabled";
 408         };
 409
 410         spi@7000c380 {
 411                 compatible = "nvidia,tegra20-sflash";
 412                 reg = <0x7000c380 0x80>;
 413                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 414                 #address-cells = <1>;
 415                 #size-cells = <0>;
 416                 clocks = <&tegra_car TEGRA20_CLK_SPI>;
 417                 resets = <&tegra_car 43>;
 418                 reset-names = "spi";
 419                 dmas = <&apbdma 11>, <&apbdma 11>;
 420                 dma-names = "rx", "tx";
 421                 status = "disabled";
 422         };
 423
 424         i2c@7000c400 {
 425                 compatible = "nvidia,tegra20-i2c";
 426                 reg = <0x7000c400 0x100>;
 427                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 428                 #address-cells = <1>;
 429                 #size-cells = <0>;
 430                 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
 431                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 432                 clock-names = "div-clk", "fast-clk";
 433                 resets = <&tegra_car 54>;
 434                 reset-names = "i2c";
 435                 dmas = <&apbdma 22>, <&apbdma 22>;
 436                 dma-names = "rx", "tx";
 437                 status = "disabled";
 438         };
 439
 440         i2c@7000c500 {
 441                 compatible = "nvidia,tegra20-i2c";
 442                 reg = <0x7000c500 0x100>;
 443                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 444                 #address-cells = <1>;
 445                 #size-cells = <0>;
 446                 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
 447                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 448                 clock-names = "div-clk", "fast-clk";
 449                 resets = <&tegra_car 67>;
 450                 reset-names = "i2c";
 451                 dmas = <&apbdma 23>, <&apbdma 23>;
 452                 dma-names = "rx", "tx";
 453                 status = "disabled";
 454         };
 455
 456         i2c@7000d000 {
 457                 compatible = "nvidia,tegra20-i2c-dvc";
 458                 reg = <0x7000d000 0x200>;
 459                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 460                 #address-cells = <1>;
 461                 #size-cells = <0>;
 462                 clocks = <&tegra_car TEGRA20_CLK_DVC>,
 463                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 464                 clock-names = "div-clk", "fast-clk";
 465                 resets = <&tegra_car 47>;
 466                 reset-names = "i2c";
 467                 dmas = <&apbdma 24>, <&apbdma 24>;
 468                 dma-names = "rx", "tx";
 469                 status = "disabled";
 470         };
 471
 472         spi@7000d400 {
 473                 compatible = "nvidia,tegra20-slink";
 474                 reg = <0x7000d400 0x200>;
 475                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 476                 #address-cells = <1>;
 477                 #size-cells = <0>;
 478                 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
 479                 resets = <&tegra_car 41>;
 480                 reset-names = "spi";
 481                 dmas = <&apbdma 15>, <&apbdma 15>;
 482                 dma-names = "rx", "tx";
 483                 status = "disabled";
 484         };
 485
 486         spi@7000d600 {
 487                 compatible = "nvidia,tegra20-slink";
 488                 reg = <0x7000d600 0x200>;
 489                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 490                 #address-cells = <1>;
 491                 #size-cells = <0>;
 492                 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
 493                 resets = <&tegra_car 44>;
 494                 reset-names = "spi";
 495                 dmas = <&apbdma 16>, <&apbdma 16>;
 496                 dma-names = "rx", "tx";
 497                 status = "disabled";
 498         };
 499
 500         spi@7000d800 {
 501                 compatible = "nvidia,tegra20-slink";
 502                 reg = <0x7000d800 0x200>;
 503                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 504                 #address-cells = <1>;
 505                 #size-cells = <0>;
 506                 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
 507                 resets = <&tegra_car 46>;
 508                 reset-names = "spi";
 509                 dmas = <&apbdma 17>, <&apbdma 17>;
 510                 dma-names = "rx", "tx";
 511                 status = "disabled";
 512         };
 513
 514         spi@7000da00 {
 515                 compatible = "nvidia,tegra20-slink";
 516                 reg = <0x7000da00 0x200>;
 517                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 518                 #address-cells = <1>;
 519                 #size-cells = <0>;
 520                 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
 521                 resets = <&tegra_car 68>;
 522                 reset-names = "spi";
 523                 dmas = <&apbdma 18>, <&apbdma 18>;
 524                 dma-names = "rx", "tx";
 525                 status = "disabled";
 526         };
 527
 528         kbc@7000e200 {
 529                 compatible = "nvidia,tegra20-kbc";
 530                 reg = <0x7000e200 0x100>;
 531                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 532                 clocks = <&tegra_car TEGRA20_CLK_KBC>;
 533                 resets = <&tegra_car 36>;
 534                 reset-names = "kbc";
 535                 status = "disabled";
 536         };
 537
 538         pmc@7000e400 {
 539                 compatible = "nvidia,tegra20-pmc";
 540                 reg = <0x7000e400 0x400>;
 541                 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
 542                 clock-names = "pclk", "clk32k_in";
 543         };
 544
 545         memory-controller@7000f000 {
 546                 compatible = "nvidia,tegra20-mc";
 547                 reg = <0x7000f000 0x024
 548                        0x7000f03c 0x3c4>;
 549                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 550         };
 551
 552         iommu@7000f024 {
 553                 compatible = "nvidia,tegra20-gart";
 554                 reg = <0x7000f024 0x00000018    /* controller registers */
 555                        0x58000000 0x02000000>;  /* GART aperture */
 556         };
 557
 558         memory-controller@7000f400 {
 559                 compatible = "nvidia,tegra20-emc";
 560                 reg = <0x7000f400 0x200>;
 561                 #address-cells = <1>;
 562                 #size-cells = <0>;
 563         };
 564
 565         fuse@7000f800 {
 566                 compatible = "nvidia,tegra20-efuse";
 567                 reg = <0x7000f800 0x400>;
 568                 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
 569                 clock-names = "fuse";
 570                 resets = <&tegra_car 39>;
 571                 reset-names = "fuse";
 572         };
 573
 574         pcie-controller@80003000 {
 575                 compatible = "nvidia,tegra20-pcie";
 576                 device_type = "pci";
 577                 reg = <0x80003000 0x00000800   /* PADS registers */
 578                        0x80003800 0x00000200   /* AFI registers */
 579                        0x90000000 0x10000000>; /* configuration space */
 580                 reg-names = "pads", "afi", "cs";
 581                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
 582                               GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
 583                 interrupt-names = "intr", "msi";
 584
 585                 #interrupt-cells = <1>;
 586                 interrupt-map-mask = <0 0 0 0>;
 587                 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 588
 589                 bus-range = <0x00 0xff>;
 590                 #address-cells = <3>;
 591                 #size-cells = <2>;
 592
 593                 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000   /* port 0 registers */
 594                           0x82000000 0 0x80001000 0x80001000 0 0x00001000   /* port 1 registers */
 595                           0x81000000 0 0          0x82000000 0 0x00010000   /* downstream I/O */
 596                           0x82000000 0 0xa0000000 0xa0000000 0 0x08000000   /* non-prefetchable memory */
 597                           0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
 598
 599                 clocks = <&tegra_car TEGRA20_CLK_PEX>,
 600                          <&tegra_car TEGRA20_CLK_AFI>,
 601                          <&tegra_car TEGRA20_CLK_PLL_E>;
 602                 clock-names = "pex", "afi", "pll_e";
 603                 resets = <&tegra_car 70>,
 604                          <&tegra_car 72>,
 605                          <&tegra_car 74>;
 606                 reset-names = "pex", "afi", "pcie_x";
 607                 status = "disabled";
 608
 609                 pci@1,0 {
 610                         device_type = "pci";
 611                         assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
 612                         reg = <0x000800 0 0 0 0>;
 613                         status = "disabled";
 614
 615                         #address-cells = <3>;
 616                         #size-cells = <2>;
 617                         ranges;
 618
 619                         nvidia,num-lanes = <2>;
 620                 };
 621
 622                 pci@2,0 {
 623                         device_type = "pci";
 624                         assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
 625                         reg = <0x001000 0 0 0 0>;
 626                         status = "disabled";
 627
 628                         #address-cells = <3>;
 629                         #size-cells = <2>;
 630                         ranges;
 631
 632                         nvidia,num-lanes = <2>;
 633                 };
 634         };
 635
 636         usb@c5000000 {
 637                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 638                 reg = <0xc5000000 0x4000>;
 639                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 640                 phy_type = "utmi";
 641                 nvidia,has-legacy-mode;
 642                 clocks = <&tegra_car TEGRA20_CLK_USBD>;
 643                 resets = <&tegra_car 22>;
 644                 reset-names = "usb";
 645                 nvidia,needs-double-reset;
 646                 nvidia,phy = <&phy1>;
 647                 status = "disabled";
 648         };
 649
 650         phy1: usb-phy@c5000000 {
 651                 compatible = "nvidia,tegra20-usb-phy";
 652                 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
 653                 phy_type = "utmi";
 654                 clocks = <&tegra_car TEGRA20_CLK_USBD>,
 655                          <&tegra_car TEGRA20_CLK_PLL_U>,
 656                          <&tegra_car TEGRA20_CLK_CLK_M>,
 657                          <&tegra_car TEGRA20_CLK_USBD>;
 658                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 659                 resets = <&tegra_car 22>, <&tegra_car 22>;
 660                 reset-names = "usb", "utmi-pads";
 661                 nvidia,has-legacy-mode;
 662                 nvidia,hssync-start-delay = <9>;
 663                 nvidia,idle-wait-delay = <17>;
 664                 nvidia,elastic-limit = <16>;
 665                 nvidia,term-range-adj = <6>;
 666                 nvidia,xcvr-setup = <9>;
 667                 nvidia,xcvr-lsfslew = <1>;
 668                 nvidia,xcvr-lsrslew = <1>;
 669                 nvidia,has-utmi-pad-registers;
 670                 status = "disabled";
 671         };
 672
 673         usb@c5004000 {
 674                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 675                 reg = <0xc5004000 0x4000>;
 676                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 677                 phy_type = "ulpi";
 678                 clocks = <&tegra_car TEGRA20_CLK_USB2>;
 679                 resets = <&tegra_car 58>;
 680                 reset-names = "usb";
 681                 nvidia,phy = <&phy2>;
 682                 status = "disabled";
 683         };
 684
 685         phy2: usb-phy@c5004000 {
 686                 compatible = "nvidia,tegra20-usb-phy";
 687                 reg = <0xc5004000 0x4000>;
 688                 phy_type = "ulpi";
 689                 clocks = <&tegra_car TEGRA20_CLK_USB2>,
 690                          <&tegra_car TEGRA20_CLK_PLL_U>,
 691                          <&tegra_car TEGRA20_CLK_CDEV2>;
 692                 clock-names = "reg", "pll_u", "ulpi-link";
 693                 resets = <&tegra_car 58>, <&tegra_car 22>;
 694                 reset-names = "usb", "utmi-pads";
 695                 status = "disabled";
 696         };
 697
 698         usb@c5008000 {
 699                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 700                 reg = <0xc5008000 0x4000>;
 701                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 702                 phy_type = "utmi";
 703                 clocks = <&tegra_car TEGRA20_CLK_USB3>;
 704                 resets = <&tegra_car 59>;
 705                 reset-names = "usb";
 706                 nvidia,phy = <&phy3>;
 707                 status = "disabled";
 708         };
 709
 710         phy3: usb-phy@c5008000 {
 711                 compatible = "nvidia,tegra20-usb-phy";
 712                 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
 713                 phy_type = "utmi";
 714                 clocks = <&tegra_car TEGRA20_CLK_USB3>,
 715                          <&tegra_car TEGRA20_CLK_PLL_U>,
 716                          <&tegra_car TEGRA20_CLK_CLK_M>,
 717                          <&tegra_car TEGRA20_CLK_USBD>;
 718                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 719                 resets = <&tegra_car 59>, <&tegra_car 22>;
 720                 reset-names = "usb", "utmi-pads";
 721                 nvidia,hssync-start-delay = <9>;
 722                 nvidia,idle-wait-delay = <17>;
 723                 nvidia,elastic-limit = <16>;
 724                 nvidia,term-range-adj = <6>;
 725                 nvidia,xcvr-setup = <9>;
 726                 nvidia,xcvr-lsfslew = <2>;
 727                 nvidia,xcvr-lsrslew = <2>;
 728                 status = "disabled";
 729         };
 730
 731         sdhci@c8000000 {
 732                 compatible = "nvidia,tegra20-sdhci";
 733                 reg = <0xc8000000 0x200>;
 734                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 735                 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
 736                 resets = <&tegra_car 14>;
 737                 reset-names = "sdhci";
 738                 status = "disabled";
 739         };
 740
 741         sdhci@c8000200 {
 742                 compatible = "nvidia,tegra20-sdhci";
 743                 reg = <0xc8000200 0x200>;
 744                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 745                 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
 746                 resets = <&tegra_car 9>;
 747                 reset-names = "sdhci";
 748                 status = "disabled";
 749         };
 750
 751         sdhci@c8000400 {
 752                 compatible = "nvidia,tegra20-sdhci";
 753                 reg = <0xc8000400 0x200>;
 754                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 755                 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
 756                 resets = <&tegra_car 69>;
 757                 reset-names = "sdhci";
 758                 status = "disabled";
 759         };
 760
 761         sdhci@c8000600 {
 762                 compatible = "nvidia,tegra20-sdhci";
 763                 reg = <0xc8000600 0x200>;
 764                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 765                 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
 766                 resets = <&tegra_car 15>;
 767                 reset-names = "sdhci";
 768                 status = "disabled";
 769         };
 770
 771         cpus {
 772                 #address-cells = <1>;
 773                 #size-cells = <0>;
 774
 775                 cpu@0 {
 776                         device_type = "cpu";
 777                         compatible = "arm,cortex-a9";
 778                         reg = <0>;
 779                 };
 780
 781                 cpu@1 {
 782                         device_type = "cpu";
 783                         compatible = "arm,cortex-a9";
 784                         reg = <1>;
 785                 };
 786         };
 787
 788         pmu {
 789                 compatible = "arm,cortex-a9-pmu";
 790                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 791                              <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 792         };
 793 };