arch/arm/mach-ixp4xx/include/mach/qmgr.h

   1 /*
   2  * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of version 2 of the GNU General Public License
   6  * as published by the Free Software Foundation.
   7  */
   8
   9 #ifndef IXP4XX_QMGR_H
  10 #define IXP4XX_QMGR_H
  11
  12 #include <linux/io.h>
  13 #include <linux/kernel.h>
  14
  15 #define DEBUG_QMGR      0
  16
  17 #define HALF_QUEUES     32
  18 #define QUEUES          64
  19 #define MAX_QUEUE_LENGTH 4      /* in dwords */
  20
  21 #define QUEUE_STAT1_EMPTY               1 /* queue status bits */
  22 #define QUEUE_STAT1_NEARLY_EMPTY        2
  23 #define QUEUE_STAT1_NEARLY_FULL         4
  24 #define QUEUE_STAT1_FULL                8
  25 #define QUEUE_STAT2_UNDERFLOW           1
  26 #define QUEUE_STAT2_OVERFLOW            2
  27
  28 #define QUEUE_WATERMARK_0_ENTRIES       0
  29 #define QUEUE_WATERMARK_1_ENTRY         1
  30 #define QUEUE_WATERMARK_2_ENTRIES       2
  31 #define QUEUE_WATERMARK_4_ENTRIES       3
  32 #define QUEUE_WATERMARK_8_ENTRIES       4
  33 #define QUEUE_WATERMARK_16_ENTRIES      5
  34 #define QUEUE_WATERMARK_32_ENTRIES      6
  35 #define QUEUE_WATERMARK_64_ENTRIES      7
  36
  37 /* queue interrupt request conditions */
  38 #define QUEUE_IRQ_SRC_EMPTY             0
  39 #define QUEUE_IRQ_SRC_NEARLY_EMPTY      1
  40 #define QUEUE_IRQ_SRC_NEARLY_FULL       2
  41 #define QUEUE_IRQ_SRC_FULL              3
  42 #define QUEUE_IRQ_SRC_NOT_EMPTY         4
  43 #define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY  5
  44 #define QUEUE_IRQ_SRC_NOT_NEARLY_FULL   6
  45 #define QUEUE_IRQ_SRC_NOT_FULL          7
  46
  47 struct qmgr_regs {
  48         u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
  49         u32 stat1[4];           /* 0x400 - 0x40F */
  50         u32 stat2[2];           /* 0x410 - 0x417 */
  51         u32 statne_h;           /* 0x418 - queue nearly empty */
  52         u32 statf_h;            /* 0x41C - queue full */
  53         u32 irqsrc[4];          /* 0x420 - 0x42F IRC source */
  54         u32 irqen[2];           /* 0x430 - 0x437 IRQ enabled */
  55         u32 irqstat[2];         /* 0x438 - 0x43F - IRQ access only */
  56         u32 reserved[1776];
  57         u32 sram[2048];         /* 0x2000 - 0x3FFF - config and buffer */
  58 };
  59
  60 void qmgr_set_irq(unsigned int queue, int src,
  61                   void (*handler)(void *pdev), void *pdev);
  62 void qmgr_enable_irq(unsigned int queue);
  63 void qmgr_disable_irq(unsigned int queue);
  64
  65 /* request_ and release_queue() must be called from non-IRQ context */
  66
  67 #if DEBUG_QMGR
  68 extern char qmgr_queue_descs[QUEUES][32];
  69
  70 int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
  71                        unsigned int nearly_empty_watermark,
  72                        unsigned int nearly_full_watermark,
  73                        const char *desc_format, const char* name);
  74 #else
  75 int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
  76                          unsigned int nearly_empty_watermark,
  77                          unsigned int nearly_full_watermark);
  78 #define qmgr_request_queue(queue, len, nearly_empty_watermark,          \
  79                            nearly_full_watermark, desc_format, name)    \
  80         __qmgr_request_queue(queue, len, nearly_empty_watermark,        \
  81                              nearly_full_watermark)
  82 #endif
  83
  84 void qmgr_release_queue(unsigned int queue);
  85
  86
  87 static inline void qmgr_put_entry(unsigned int queue, u32 val)
  88 {
  89         struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
  90 #if DEBUG_QMGR
  91         BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
  92
  93         printk(KERN_DEBUG "Queue %s(%i) put %X\n",
  94                qmgr_queue_descs[queue], queue, val);
  95 #endif
  96         __raw_writel(val, &qmgr_regs->acc[queue][0]);
  97 }
  98
  99 static inline u32 qmgr_get_entry(unsigned int queue)
 100 {
 101         u32 val;
 102         const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
 103         val = __raw_readl(&qmgr_regs->acc[queue][0]);
 104 #if DEBUG_QMGR
 105         BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
 106
 107         printk(KERN_DEBUG "Queue %s(%i) get %X\n",
 108                qmgr_queue_descs[queue], queue, val);
 109 #endif
 110         return val;
 111 }
 112
 113 static inline int __qmgr_get_stat1(unsigned int queue)
 114 {
 115         const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
 116         return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
 117                 >> ((queue & 7) << 2)) & 0xF;
 118 }
 119
 120 static inline int __qmgr_get_stat2(unsigned int queue)
 121 {
 122         const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
 123         BUG_ON(queue >= HALF_QUEUES);
 124         return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
 125                 >> ((queue & 0xF) << 1)) & 0x3;
 126 }
 127
 128 /**
 129  * qmgr_stat_empty() - checks if a hardware queue is empty
 130  * @queue:      queue number
 131  *
 132  * Returns non-zero value if the queue is empty.
 133  */
 134 static inline int qmgr_stat_empty(unsigned int queue)
 135 {
 136         BUG_ON(queue >= HALF_QUEUES);
 137         return __qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY;
 138 }
 139
 140 /**
 141  * qmgr_stat_below_low_watermark() - checks if a queue is below low watermark
 142  * @queue:      queue number
 143  *
 144  * Returns non-zero value if the queue is below low watermark.
 145  */
 146 static inline int qmgr_stat_below_low_watermark(unsigned int queue)
 147 {
 148         const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
 149         if (queue >= HALF_QUEUES)
 150                 return (__raw_readl(&qmgr_regs->statne_h) >>
 151                         (queue - HALF_QUEUES)) & 0x01;
 152         return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY;
 153 }
 154
 155 /**
 156  * qmgr_stat_above_high_watermark() - checks if a queue is above high watermark
 157  * @queue:      queue number
 158  *
 159  * Returns non-zero value if the queue is above high watermark
 160  */
 161 static inline int qmgr_stat_above_high_watermark(unsigned int queue)
 162 {
 163         BUG_ON(queue >= HALF_QUEUES);
 164         return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL;
 165 }
 166
 167 /**
 168  * qmgr_stat_full() - checks if a hardware queue is full
 169  * @queue:      queue number
 170  *
 171  * Returns non-zero value if the queue is full.
 172  */
 173 static inline int qmgr_stat_full(unsigned int queue)
 174 {
 175         const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
 176         if (queue >= HALF_QUEUES)
 177                 return (__raw_readl(&qmgr_regs->statf_h) >>
 178                         (queue - HALF_QUEUES)) & 0x01;
 179         return __qmgr_get_stat1(queue) & QUEUE_STAT1_FULL;
 180 }
 181
 182 /**
 183  * qmgr_stat_underflow() - checks if a hardware queue experienced underflow
 184  * @queue:      queue number
 185  *
 186  * Returns non-zero value if the queue experienced underflow.
 187  */
 188 static inline int qmgr_stat_underflow(unsigned int queue)
 189 {
 190         return __qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW;
 191 }
 192
 193 /**
 194  * qmgr_stat_overflow() - checks if a hardware queue experienced overflow
 195  * @queue:      queue number
 196  *
 197  * Returns non-zero value if the queue experienced overflow.
 198  */
 199 static inline int qmgr_stat_overflow(unsigned int queue)
 200 {
 201         return __qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW;
 202 }
 203
 204 #endif