| blob | cf5855174c93cbb57d3b0ccb9f2a5e417a59c7eb |
1 /*
2 * OMAP2/3 System Control Module register access
3 *
4 * Copyright (C) 2007, 2012 Texas Instruments, Inc.
5 * Copyright (C) 2007 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #undef DEBUG
15 #include <linux/kernel.h>
16 #include <linux/io.h>
17 #include <linux/of_address.h>
18 #include <linux/regmap.h>
19 #include <linux/mfd/syscon.h>
33 /* Used by omap3_ctrl_save_padconf() */
34 #define START_PADCONF_SAVE 0x2
35 #define PADCONF_SAVE_DONE 0x1
41 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
43 u32 boot_config_ptr;
44 u32 public_restore_ptr;
45 u32 secure_ram_restore_ptr;
46 u32 sdrc_module_semaphore;
47 u32 prcm_block_offset;
48 u32 sdrc_block_offset;
49 };
54 u32 prcm_block_size;
55 };
58 u16 sysconfig;
59 u16 cs_cfg;
60 u16 sharing;
61 u16 err_type;
62 u32 dll_a_ctrl;
63 u32 dll_b_ctrl;
64 u32 power;
65 u32 cs_0;
66 u32 mcfg_0;
67 u16 mr_0;
68 u16 emr_1_0;
69 u16 emr_2_0;
70 u16 emr_3_0;
71 u32 actim_ctrla_0;
72 u32 actim_ctrlb_0;
73 u32 rfr_ctrl_0;
74 u32 cs_1;
75 u32 mcfg_1;
76 u16 mr_1;
77 u16 emr_1_1;
78 u16 emr_2_1;
79 u16 emr_3_1;
80 u32 actim_ctrla_1;
81 u32 actim_ctrlb_1;
82 u32 rfr_ctrl_1;
83 u16 dcdl_1_ctrl;
84 u16 dcdl_2_ctrl;
85 u32 flags;
86 u32 block_size;
87 };
91 /*
92 * This is used to store ARM registers in SDRAM before attempting
93 * an MPU OFF. The save and restore happens from the SRAM sleep code.
94 * The address is stored in scratchpad, so that it can be used
95 * during the restore path.
96 */
100 u32 sysconfig;
101 u32 devconf0;
102 u32 mem_dftrw0;
103 u32 mem_dftrw1;
104 u32 msuspendmux_0;
105 u32 msuspendmux_1;
106 u32 msuspendmux_2;
107 u32 msuspendmux_3;
108 u32 msuspendmux_4;
109 u32 msuspendmux_5;
110 u32 sec_ctrl;
111 u32 devconf1;
112 u32 csirxfe;
113 u32 iva2_bootaddr;
114 u32 iva2_bootmod;
115 u32 wkup_ctrl;
116 u32 debobs_0;
117 u32 debobs_1;
118 u32 debobs_2;
119 u32 debobs_3;
120 u32 debobs_4;
121 u32 debobs_5;
122 u32 debobs_6;
123 u32 debobs_7;
124 u32 debobs_8;
125 u32 prog_io0;
126 u32 prog_io1;
127 u32 dss_dpll_spreading;
128 u32 core_dpll_spreading;
129 u32 per_dpll_spreading;
130 u32 usbhost_dpll_spreading;
131 u32 pbias_lite;
132 u32 temp_sensor;
133 u32 sramldo4;
134 u32 sramldo5;
135 u32 csi;
136 u32 padconf_sys_nirq;
137 };
143 {
145 }
148 {
149 u32 val;
155 }
158 {
159 u32 val;
165 }
168 {
169 u32 val;
174 else
179 }
182 {
183 u32 tmp;
192 }
195 {
196 u32 tmp;
205 }
208 {
212 else
214 val);
215 }
217 #ifdef CONFIG_ARCH_OMAP3
219 /**
220 * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
221 * @bootmode: 8-bit value to pass to some boot code
222 *
223 * Set the bootmode in the scratchpad RAM. This is used after the
224 * system restarts. Not sure what actually uses this - it may be the
225 * bootloader, rather than the boot ROM - contrary to the preserved
226 * comment below. No return value.
227 */
229 {
230 u32 l;
234 /*
235 * Reserve the first word in scratchpad for communicating
236 * with the boot ROM. A pointer to a data structure
237 * describing the boot process can be stored there,
238 * cf. OMAP34xx TRM, Initialization / Software Booting
239 * Configuration.
240 *
241 * XXX This should use some omap_ctrl_writel()-type function
242 */
244 }
246 #endif
248 /**
249 * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
250 * @bootaddr: physical address of the boot loader
251 *
252 * Set boot address for the boot loader of a supported processor
253 * when a power ON sequence occurs.
254 */
256 {
266 }
269 }
271 /**
272 * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
273 * @bootmode: 8-bit value to pass to some boot code
274 *
275 * Sets boot mode for the boot loader of a supported processor
276 * when a power ON sequence occurs.
277 */
279 {
287 }
290 }
292 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
293 /*
294 * Clears the scratchpad contents in case of cold boot-
295 * called during bootup
296 */
298 {
307 }
308 }
310 /* Populate the scratchpad structure with restore structure */
312 {
314 u32 arm_context_addr;
319 /*
320 * Populate the Scratchpad contents
321 *
322 * The "get_*restore_pointer" functions are used to provide a
323 * physical restore address where the ROM code jumps while waking
324 * up from MPU OFF/OSWR state.
325 * The restore pointer is stored into the scratchpad.
326 */
336 else
342 else
349 /* Populate the PRCM block contents */
355 /* Populate the SDRC block contents */
366 /*
367 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
368 * be programed to issue automatic self refresh on timeout
369 * of AUTO_CNT = 1 prior to any transition to OFF mode.
370 */
375 SDRC_POWER_CLKCTRL_MASK)) |
377 SDRC_SELF_REFRESH_ON_AUTOCOUNT;
378 else
412 /* Copy all the contents to the scratchpad location */
416 /* Scratchpad contents being 32 bits, a divide by 4 done here */
423 /*
424 * Copies the address of the location in SDRAM where ARM
425 * registers get saved during a MPU OFF transition.
426 */
430 }
433 {
488 }
491 {
495 OMAP343X_CONTROL_MEM_DFTRW0);
497 OMAP343X_CONTROL_MEM_DFTRW1);
499 OMAP2_CONTROL_MSUSPENDMUX_0);
501 OMAP2_CONTROL_MSUSPENDMUX_1);
503 OMAP2_CONTROL_MSUSPENDMUX_2);
505 OMAP2_CONTROL_MSUSPENDMUX_3);
507 OMAP2_CONTROL_MSUSPENDMUX_4);
509 OMAP2_CONTROL_MSUSPENDMUX_5);
514 OMAP343X_CONTROL_IVA2_BOOTADDR);
516 OMAP343X_CONTROL_IVA2_BOOTMOD);
530 OMAP343X_CONTROL_DSS_DPLL_SPREADING);
532 OMAP343X_CONTROL_CORE_DPLL_SPREADING);
534 OMAP343X_CONTROL_PER_DPLL_SPREADING);
536 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
538 OMAP343X_CONTROL_PBIAS_LITE);
540 OMAP343X_CONTROL_TEMP_SENSOR);
545 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
546 }
549 {
553 }
555 /**
556 * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM
557 *
558 * Tell the SCM to start saving the padconf registers, then wait for
559 * the process to complete. Returns 0 unconditionally, although it
560 * should also eventually be able to return -ETIMEDOUT, if the save
561 * does not complete.
562 *
563 * XXX This function is missing a timeout. What should it be?
564 */
566 {
567 u32 cpo;
569 /* Save the padconf registers */
574 /* wait for the save to complete */
580 }
582 /**
583 * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle
584 *
585 * Sets the bootmode for IVA2 to idle. This is needed by the PM code to
586 * force disable IVA2 so that it does not prevent any low-power states.
587 */
589 {
591 OMAP343X_CONTROL_IVA2_BOOTMOD);
592 }
594 /**
595 * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle
596 *
597 * Sets up the pads controlling the stacked modem in such way that the
598 * device can enter idle.
599 */
601 {
604 /*
605 * In a stand alone OMAP3430 where there is not a stacked
606 * modem for the D2D Idle Ack and D2D MStandby must be pulled
607 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
608 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up.
609 */
618 }
620 /**
621 * omap3_ctrl_init - does static initializations for control module
622 *
623 * Initializes system control module. This sets up the sysconfig autoidle,
624 * and sets up modem and iva2 so that they can be idled properly.
625 */
627 {
633 }
638 s16 offset;
639 };
643 };
648 };
660 { }
661 };
663 /**
664 * omap2_control_base_init - initialize iomappings for the control driver
665 *
666 * Detects and initializes the iomappings for the control driver, based
667 * on the DT data. Returns 0 in success, negative error value
668 * otherwise.
669 */
671 {
684 }
687 }
689 /**
690 * omap_control_init - low level init for the control driver
691 *
692 * Initializes the low level clock infrastructure for control driver.
693 * Returns 0 in success, negative error value in failure.
694 */
696 {
706 /*
707 * Check if we have scm_conf node, if yes, use this to
708 * access clock registers.
709 */
726 }
731 /* No scm_conf found, direct access */
733 omap2_ctrl_base);
736 }
737 }
740 }
742 /**
743 * omap3_control_legacy_iomap_init - legacy iomap init for clock providers
744 *
745 * Legacy iomap init for clock provider. Needed only by legacy boot mode,
746 * where the base addresses are not parsed from DT, but still required
747 * by the clock driver to be setup properly.
748 */
750 {
752 }