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blk: rq_data_dir() should not return a boolean
[cris-mirror.git] / arch / arm / mach-omap2 / omap_hwmod_7xx_data.c
blob562247bced496bc085f75cb65f5061f8ec2be6c1
1 /*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20 #include <linux/io.h>
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/platform_data/hsmmc-omap.h>
23 #include <linux/power/smartreflex.h>
24 #include <linux/i2c-omap.h>
25
26 #include <linux/omap-dma.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <linux/platform_data/asoc-ti-mcbsp.h>
29 #include <plat/dmtimer.h>
30
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
33 #include "cm1_7xx.h"
34 #include "cm2_7xx.h"
35 #include "prm7xx.h"
36 #include "i2c.h"
37 #include "wd_timer.h"
38 #include "soc.h"
39
40 /* Base offset for all DRA7XX interrupts external to MPUSS */
41 #define DRA7XX_IRQ_GIC_START 32
42
43 /* Base offset for all DRA7XX dma requests */
44 #define DRA7XX_DMA_REQ_START 1
45
46
47 /*
48 * IP blocks
49 */
50
51 /*
52 * 'dmm' class
53 * instance(s): dmm
54 */
55 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
56 .name = "dmm",
57 };
58
59 /* dmm */
60 static struct omap_hwmod dra7xx_dmm_hwmod = {
61 .name = "dmm",
62 .class = &dra7xx_dmm_hwmod_class,
63 .clkdm_name = "emif_clkdm",
64 .prcm = {
65 .omap4 = {
66 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
67 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
68 },
69 },
70 };
71
72 /*
73 * 'l3' class
74 * instance(s): l3_instr, l3_main_1, l3_main_2
75 */
76 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
77 .name = "l3",
78 };
79
80 /* l3_instr */
81 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
82 .name = "l3_instr",
83 .class = &dra7xx_l3_hwmod_class,
84 .clkdm_name = "l3instr_clkdm",
85 .prcm = {
86 .omap4 = {
87 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
88 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
89 .modulemode = MODULEMODE_HWCTRL,
90 },
91 },
92 };
93
94 /* l3_main_1 */
95 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
96 .name = "l3_main_1",
97 .class = &dra7xx_l3_hwmod_class,
98 .clkdm_name = "l3main1_clkdm",
99 .prcm = {
100 .omap4 = {
101 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
102 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
103 },
104 },
105 };
106
107 /* l3_main_2 */
108 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
109 .name = "l3_main_2",
110 .class = &dra7xx_l3_hwmod_class,
111 .clkdm_name = "l3instr_clkdm",
112 .prcm = {
113 .omap4 = {
114 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
116 .modulemode = MODULEMODE_HWCTRL,
117 },
118 },
119 };
120
121 /*
122 * 'l4' class
123 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
124 */
125 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
126 .name = "l4",
127 };
128
129 /* l4_cfg */
130 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
131 .name = "l4_cfg",
132 .class = &dra7xx_l4_hwmod_class,
133 .clkdm_name = "l4cfg_clkdm",
134 .prcm = {
135 .omap4 = {
136 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
137 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
138 },
139 },
140 };
141
142 /* l4_per1 */
143 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
144 .name = "l4_per1",
145 .class = &dra7xx_l4_hwmod_class,
146 .clkdm_name = "l4per_clkdm",
147 .prcm = {
148 .omap4 = {
149 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
150 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
151 },
152 },
153 };
154
155 /* l4_per2 */
156 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
157 .name = "l4_per2",
158 .class = &dra7xx_l4_hwmod_class,
159 .clkdm_name = "l4per2_clkdm",
160 .prcm = {
161 .omap4 = {
162 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
163 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
164 },
165 },
166 };
167
168 /* l4_per3 */
169 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
170 .name = "l4_per3",
171 .class = &dra7xx_l4_hwmod_class,
172 .clkdm_name = "l4per3_clkdm",
173 .prcm = {
174 .omap4 = {
175 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
176 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
177 },
178 },
179 };
180
181 /* l4_wkup */
182 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
183 .name = "l4_wkup",
184 .class = &dra7xx_l4_hwmod_class,
185 .clkdm_name = "wkupaon_clkdm",
186 .prcm = {
187 .omap4 = {
188 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
189 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
190 },
191 },
192 };
193
194 /*
195 * 'atl' class
196 *
197 */
198
199 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
200 .name = "atl",
201 };
202
203 /* atl */
204 static struct omap_hwmod dra7xx_atl_hwmod = {
205 .name = "atl",
206 .class = &dra7xx_atl_hwmod_class,
207 .clkdm_name = "atl_clkdm",
208 .main_clk = "atl_gfclk_mux",
209 .prcm = {
210 .omap4 = {
211 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
212 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
213 .modulemode = MODULEMODE_SWCTRL,
214 },
215 },
216 };
217
218 /*
219 * 'bb2d' class
220 *
221 */
222
223 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
224 .name = "bb2d",
225 };
226
227 /* bb2d */
228 static struct omap_hwmod dra7xx_bb2d_hwmod = {
229 .name = "bb2d",
230 .class = &dra7xx_bb2d_hwmod_class,
231 .clkdm_name = "dss_clkdm",
232 .main_clk = "dpll_core_h24x2_ck",
233 .prcm = {
234 .omap4 = {
235 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
236 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
237 .modulemode = MODULEMODE_SWCTRL,
238 },
239 },
240 };
241
242 /*
243 * 'counter' class
244 *
245 */
246
247 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
248 .rev_offs = 0x0000,
249 .sysc_offs = 0x0010,
250 .sysc_flags = SYSC_HAS_SIDLEMODE,
251 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
252 SIDLE_SMART_WKUP),
253 .sysc_fields = &omap_hwmod_sysc_type1,
254 };
255
256 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
257 .name = "counter",
258 .sysc = &dra7xx_counter_sysc,
259 };
260
261 /* counter_32k */
262 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
263 .name = "counter_32k",
264 .class = &dra7xx_counter_hwmod_class,
265 .clkdm_name = "wkupaon_clkdm",
266 .flags = HWMOD_SWSUP_SIDLE,
267 .main_clk = "wkupaon_iclk_mux",
268 .prcm = {
269 .omap4 = {
270 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
271 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
272 },
273 },
274 };
275
276 /*
277 * 'ctrl_module' class
278 *
279 */
280
281 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
282 .name = "ctrl_module",
283 };
284
285 /* ctrl_module_wkup */
286 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
287 .name = "ctrl_module_wkup",
288 .class = &dra7xx_ctrl_module_hwmod_class,
289 .clkdm_name = "wkupaon_clkdm",
290 .prcm = {
291 .omap4 = {
292 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
293 },
294 },
295 };
296
297 /*
298 * 'gmac' class
299 * cpsw/gmac sub system
300 */
301 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
302 .rev_offs = 0x0,
303 .sysc_offs = 0x8,
304 .syss_offs = 0x4,
305 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
306 SYSS_HAS_RESET_STATUS),
307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
308 MSTANDBY_NO),
309 .sysc_fields = &omap_hwmod_sysc_type3,
310 };
311
312 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
313 .name = "gmac",
314 .sysc = &dra7xx_gmac_sysc,
315 };
316
317 static struct omap_hwmod dra7xx_gmac_hwmod = {
318 .name = "gmac",
319 .class = &dra7xx_gmac_hwmod_class,
320 .clkdm_name = "gmac_clkdm",
321 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
322 .main_clk = "dpll_gmac_ck",
323 .mpu_rt_idx = 1,
324 .prcm = {
325 .omap4 = {
326 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
327 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
328 .modulemode = MODULEMODE_SWCTRL,
329 },
330 },
331 };
332
333 /*
334 * 'mdio' class
335 */
336 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
337 .name = "davinci_mdio",
338 };
339
340 static struct omap_hwmod dra7xx_mdio_hwmod = {
341 .name = "davinci_mdio",
342 .class = &dra7xx_mdio_hwmod_class,
343 .clkdm_name = "gmac_clkdm",
344 .main_clk = "dpll_gmac_ck",
345 };
346
347 /*
348 * 'dcan' class
349 *
350 */
351
352 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
353 .name = "dcan",
354 };
355
356 /* dcan1 */
357 static struct omap_hwmod dra7xx_dcan1_hwmod = {
358 .name = "dcan1",
359 .class = &dra7xx_dcan_hwmod_class,
360 .clkdm_name = "wkupaon_clkdm",
361 .main_clk = "dcan1_sys_clk_mux",
362 .prcm = {
363 .omap4 = {
364 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
365 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
366 .modulemode = MODULEMODE_SWCTRL,
367 },
368 },
369 };
370
371 /* dcan2 */
372 static struct omap_hwmod dra7xx_dcan2_hwmod = {
373 .name = "dcan2",
374 .class = &dra7xx_dcan_hwmod_class,
375 .clkdm_name = "l4per2_clkdm",
376 .main_clk = "sys_clkin1",
377 .prcm = {
378 .omap4 = {
379 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
380 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
381 .modulemode = MODULEMODE_SWCTRL,
382 },
383 },
384 };
385
386 /*
387 * 'dma' class
388 *
389 */
390
391 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
392 .rev_offs = 0x0000,
393 .sysc_offs = 0x002c,
394 .syss_offs = 0x0028,
395 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
396 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
397 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
398 SYSS_HAS_RESET_STATUS),
399 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
400 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
401 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
402 .sysc_fields = &omap_hwmod_sysc_type1,
403 };
404
405 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
406 .name = "dma",
407 .sysc = &dra7xx_dma_sysc,
408 };
409
410 /* dma dev_attr */
411 static struct omap_dma_dev_attr dma_dev_attr = {
412 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
413 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
414 .lch_count = 32,
415 };
416
417 /* dma_system */
418 static struct omap_hwmod dra7xx_dma_system_hwmod = {
419 .name = "dma_system",
420 .class = &dra7xx_dma_hwmod_class,
421 .clkdm_name = "dma_clkdm",
422 .main_clk = "l3_iclk_div",
423 .prcm = {
424 .omap4 = {
425 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
426 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
427 },
428 },
429 .dev_attr = &dma_dev_attr,
430 };
431
432 /*
433 * 'dss' class
434 *
435 */
436
437 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
438 .rev_offs = 0x0000,
439 .syss_offs = 0x0014,
440 .sysc_flags = SYSS_HAS_RESET_STATUS,
441 };
442
443 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
444 .name = "dss",
445 .sysc = &dra7xx_dss_sysc,
446 .reset = omap_dss_reset,
447 };
448
449 /* dss */
450 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
451 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
452 { .dma_req = -1 }
453 };
454
455 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
456 { .role = "dss_clk", .clk = "dss_dss_clk" },
457 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
458 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
459 { .role = "video2_clk", .clk = "dss_video2_clk" },
460 { .role = "video1_clk", .clk = "dss_video1_clk" },
461 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
462 { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
463 };
464
465 static struct omap_hwmod dra7xx_dss_hwmod = {
466 .name = "dss_core",
467 .class = &dra7xx_dss_hwmod_class,
468 .clkdm_name = "dss_clkdm",
469 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
470 .sdma_reqs = dra7xx_dss_sdma_reqs,
471 .main_clk = "dss_dss_clk",
472 .prcm = {
473 .omap4 = {
474 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
475 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
476 .modulemode = MODULEMODE_SWCTRL,
477 },
478 },
479 .opt_clks = dss_opt_clks,
480 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
481 };
482
483 /*
484 * 'dispc' class
485 * display controller
486 */
487
488 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
489 .rev_offs = 0x0000,
490 .sysc_offs = 0x0010,
491 .syss_offs = 0x0014,
492 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
493 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
494 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
495 SYSS_HAS_RESET_STATUS),
496 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
497 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
498 .sysc_fields = &omap_hwmod_sysc_type1,
499 };
500
501 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
502 .name = "dispc",
503 .sysc = &dra7xx_dispc_sysc,
504 };
505
506 /* dss_dispc */
507 /* dss_dispc dev_attr */
508 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
509 .has_framedonetv_irq = 1,
510 .manager_count = 4,
511 };
512
513 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
514 .name = "dss_dispc",
515 .class = &dra7xx_dispc_hwmod_class,
516 .clkdm_name = "dss_clkdm",
517 .main_clk = "dss_dss_clk",
518 .prcm = {
519 .omap4 = {
520 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
521 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
522 },
523 },
524 .dev_attr = &dss_dispc_dev_attr,
525 .parent_hwmod = &dra7xx_dss_hwmod,
526 };
527
528 /*
529 * 'hdmi' class
530 * hdmi controller
531 */
532
533 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
534 .rev_offs = 0x0000,
535 .sysc_offs = 0x0010,
536 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
537 SYSC_HAS_SOFTRESET),
538 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
539 SIDLE_SMART_WKUP),
540 .sysc_fields = &omap_hwmod_sysc_type2,
541 };
542
543 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
544 .name = "hdmi",
545 .sysc = &dra7xx_hdmi_sysc,
546 };
547
548 /* dss_hdmi */
549
550 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
551 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
552 };
553
554 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
555 .name = "dss_hdmi",
556 .class = &dra7xx_hdmi_hwmod_class,
557 .clkdm_name = "dss_clkdm",
558 .main_clk = "dss_48mhz_clk",
559 .prcm = {
560 .omap4 = {
561 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
562 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
563 },
564 },
565 .opt_clks = dss_hdmi_opt_clks,
566 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
567 .parent_hwmod = &dra7xx_dss_hwmod,
568 };
569
570 /*
571 * 'elm' class
572 *
573 */
574
575 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
576 .rev_offs = 0x0000,
577 .sysc_offs = 0x0010,
578 .syss_offs = 0x0014,
579 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
580 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
581 SYSS_HAS_RESET_STATUS),
582 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
583 SIDLE_SMART_WKUP),
584 .sysc_fields = &omap_hwmod_sysc_type1,
585 };
586
587 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
588 .name = "elm",
589 .sysc = &dra7xx_elm_sysc,
590 };
591
592 /* elm */
593
594 static struct omap_hwmod dra7xx_elm_hwmod = {
595 .name = "elm",
596 .class = &dra7xx_elm_hwmod_class,
597 .clkdm_name = "l4per_clkdm",
598 .main_clk = "l3_iclk_div",
599 .prcm = {
600 .omap4 = {
601 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
602 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
603 },
604 },
605 };
606
607 /*
608 * 'gpio' class
609 *
610 */
611
612 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
613 .rev_offs = 0x0000,
614 .sysc_offs = 0x0010,
615 .syss_offs = 0x0114,
616 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
617 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
618 SYSS_HAS_RESET_STATUS),
619 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
620 SIDLE_SMART_WKUP),
621 .sysc_fields = &omap_hwmod_sysc_type1,
622 };
623
624 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
625 .name = "gpio",
626 .sysc = &dra7xx_gpio_sysc,
627 .rev = 2,
628 };
629
630 /* gpio dev_attr */
631 static struct omap_gpio_dev_attr gpio_dev_attr = {
632 .bank_width = 32,
633 .dbck_flag = true,
634 };
635
636 /* gpio1 */
637 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
638 { .role = "dbclk", .clk = "gpio1_dbclk" },
639 };
640
641 static struct omap_hwmod dra7xx_gpio1_hwmod = {
642 .name = "gpio1",
643 .class = &dra7xx_gpio_hwmod_class,
644 .clkdm_name = "wkupaon_clkdm",
645 .main_clk = "wkupaon_iclk_mux",
646 .prcm = {
647 .omap4 = {
648 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
649 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
650 .modulemode = MODULEMODE_HWCTRL,
651 },
652 },
653 .opt_clks = gpio1_opt_clks,
654 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
655 .dev_attr = &gpio_dev_attr,
656 };
657
658 /* gpio2 */
659 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
660 { .role = "dbclk", .clk = "gpio2_dbclk" },
661 };
662
663 static struct omap_hwmod dra7xx_gpio2_hwmod = {
664 .name = "gpio2",
665 .class = &dra7xx_gpio_hwmod_class,
666 .clkdm_name = "l4per_clkdm",
667 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
668 .main_clk = "l3_iclk_div",
669 .prcm = {
670 .omap4 = {
671 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
672 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
673 .modulemode = MODULEMODE_HWCTRL,
674 },
675 },
676 .opt_clks = gpio2_opt_clks,
677 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
678 .dev_attr = &gpio_dev_attr,
679 };
680
681 /* gpio3 */
682 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
683 { .role = "dbclk", .clk = "gpio3_dbclk" },
684 };
685
686 static struct omap_hwmod dra7xx_gpio3_hwmod = {
687 .name = "gpio3",
688 .class = &dra7xx_gpio_hwmod_class,
689 .clkdm_name = "l4per_clkdm",
690 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
691 .main_clk = "l3_iclk_div",
692 .prcm = {
693 .omap4 = {
694 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
695 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
696 .modulemode = MODULEMODE_HWCTRL,
697 },
698 },
699 .opt_clks = gpio3_opt_clks,
700 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
701 .dev_attr = &gpio_dev_attr,
702 };
703
704 /* gpio4 */
705 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
706 { .role = "dbclk", .clk = "gpio4_dbclk" },
707 };
708
709 static struct omap_hwmod dra7xx_gpio4_hwmod = {
710 .name = "gpio4",
711 .class = &dra7xx_gpio_hwmod_class,
712 .clkdm_name = "l4per_clkdm",
713 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
714 .main_clk = "l3_iclk_div",
715 .prcm = {
716 .omap4 = {
717 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
718 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
719 .modulemode = MODULEMODE_HWCTRL,
720 },
721 },
722 .opt_clks = gpio4_opt_clks,
723 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
724 .dev_attr = &gpio_dev_attr,
725 };
726
727 /* gpio5 */
728 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
729 { .role = "dbclk", .clk = "gpio5_dbclk" },
730 };
731
732 static struct omap_hwmod dra7xx_gpio5_hwmod = {
733 .name = "gpio5",
734 .class = &dra7xx_gpio_hwmod_class,
735 .clkdm_name = "l4per_clkdm",
736 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
737 .main_clk = "l3_iclk_div",
738 .prcm = {
739 .omap4 = {
740 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
741 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
742 .modulemode = MODULEMODE_HWCTRL,
743 },
744 },
745 .opt_clks = gpio5_opt_clks,
746 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
747 .dev_attr = &gpio_dev_attr,
748 };
749
750 /* gpio6 */
751 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
752 { .role = "dbclk", .clk = "gpio6_dbclk" },
753 };
754
755 static struct omap_hwmod dra7xx_gpio6_hwmod = {
756 .name = "gpio6",
757 .class = &dra7xx_gpio_hwmod_class,
758 .clkdm_name = "l4per_clkdm",
759 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
760 .main_clk = "l3_iclk_div",
761 .prcm = {
762 .omap4 = {
763 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
764 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
765 .modulemode = MODULEMODE_HWCTRL,
766 },
767 },
768 .opt_clks = gpio6_opt_clks,
769 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
770 .dev_attr = &gpio_dev_attr,
771 };
772
773 /* gpio7 */
774 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
775 { .role = "dbclk", .clk = "gpio7_dbclk" },
776 };
777
778 static struct omap_hwmod dra7xx_gpio7_hwmod = {
779 .name = "gpio7",
780 .class = &dra7xx_gpio_hwmod_class,
781 .clkdm_name = "l4per_clkdm",
782 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
783 .main_clk = "l3_iclk_div",
784 .prcm = {
785 .omap4 = {
786 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
787 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
788 .modulemode = MODULEMODE_HWCTRL,
789 },
790 },
791 .opt_clks = gpio7_opt_clks,
792 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
793 .dev_attr = &gpio_dev_attr,
794 };
795
796 /* gpio8 */
797 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
798 { .role = "dbclk", .clk = "gpio8_dbclk" },
799 };
800
801 static struct omap_hwmod dra7xx_gpio8_hwmod = {
802 .name = "gpio8",
803 .class = &dra7xx_gpio_hwmod_class,
804 .clkdm_name = "l4per_clkdm",
805 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
806 .main_clk = "l3_iclk_div",
807 .prcm = {
808 .omap4 = {
809 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
810 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
811 .modulemode = MODULEMODE_HWCTRL,
812 },
813 },
814 .opt_clks = gpio8_opt_clks,
815 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
816 .dev_attr = &gpio_dev_attr,
817 };
818
819 /*
820 * 'gpmc' class
821 *
822 */
823
824 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
825 .rev_offs = 0x0000,
826 .sysc_offs = 0x0010,
827 .syss_offs = 0x0014,
828 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
829 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
830 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
831 .sysc_fields = &omap_hwmod_sysc_type1,
832 };
833
834 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
835 .name = "gpmc",
836 .sysc = &dra7xx_gpmc_sysc,
837 };
838
839 /* gpmc */
840
841 static struct omap_hwmod dra7xx_gpmc_hwmod = {
842 .name = "gpmc",
843 .class = &dra7xx_gpmc_hwmod_class,
844 .clkdm_name = "l3main1_clkdm",
845 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
846 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
847 .main_clk = "l3_iclk_div",
848 .prcm = {
849 .omap4 = {
850 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
851 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
852 .modulemode = MODULEMODE_HWCTRL,
853 },
854 },
855 };
856
857 /*
858 * 'hdq1w' class
859 *
860 */
861
862 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
863 .rev_offs = 0x0000,
864 .sysc_offs = 0x0014,
865 .syss_offs = 0x0018,
866 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
867 SYSS_HAS_RESET_STATUS),
868 .sysc_fields = &omap_hwmod_sysc_type1,
869 };
870
871 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
872 .name = "hdq1w",
873 .sysc = &dra7xx_hdq1w_sysc,
874 };
875
876 /* hdq1w */
877
878 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
879 .name = "hdq1w",
880 .class = &dra7xx_hdq1w_hwmod_class,
881 .clkdm_name = "l4per_clkdm",
882 .flags = HWMOD_INIT_NO_RESET,
883 .main_clk = "func_12m_fclk",
884 .prcm = {
885 .omap4 = {
886 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
887 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
888 .modulemode = MODULEMODE_SWCTRL,
889 },
890 },
891 };
892
893 /*
894 * 'i2c' class
895 *
896 */
897
898 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
899 .sysc_offs = 0x0010,
900 .syss_offs = 0x0090,
901 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
902 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
903 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
904 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
905 SIDLE_SMART_WKUP),
906 .clockact = CLOCKACT_TEST_ICLK,
907 .sysc_fields = &omap_hwmod_sysc_type1,
908 };
909
910 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
911 .name = "i2c",
912 .sysc = &dra7xx_i2c_sysc,
913 .reset = &omap_i2c_reset,
914 .rev = OMAP_I2C_IP_VERSION_2,
915 };
916
917 /* i2c dev_attr */
918 static struct omap_i2c_dev_attr i2c_dev_attr = {
919 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
920 };
921
922 /* i2c1 */
923 static struct omap_hwmod dra7xx_i2c1_hwmod = {
924 .name = "i2c1",
925 .class = &dra7xx_i2c_hwmod_class,
926 .clkdm_name = "l4per_clkdm",
927 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
928 .main_clk = "func_96m_fclk",
929 .prcm = {
930 .omap4 = {
931 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
932 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
933 .modulemode = MODULEMODE_SWCTRL,
934 },
935 },
936 .dev_attr = &i2c_dev_attr,
937 };
938
939 /* i2c2 */
940 static struct omap_hwmod dra7xx_i2c2_hwmod = {
941 .name = "i2c2",
942 .class = &dra7xx_i2c_hwmod_class,
943 .clkdm_name = "l4per_clkdm",
944 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
945 .main_clk = "func_96m_fclk",
946 .prcm = {
947 .omap4 = {
948 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
949 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
950 .modulemode = MODULEMODE_SWCTRL,
951 },
952 },
953 .dev_attr = &i2c_dev_attr,
954 };
955
956 /* i2c3 */
957 static struct omap_hwmod dra7xx_i2c3_hwmod = {
958 .name = "i2c3",
959 .class = &dra7xx_i2c_hwmod_class,
960 .clkdm_name = "l4per_clkdm",
961 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
962 .main_clk = "func_96m_fclk",
963 .prcm = {
964 .omap4 = {
965 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
966 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
967 .modulemode = MODULEMODE_SWCTRL,
968 },
969 },
970 .dev_attr = &i2c_dev_attr,
971 };
972
973 /* i2c4 */
974 static struct omap_hwmod dra7xx_i2c4_hwmod = {
975 .name = "i2c4",
976 .class = &dra7xx_i2c_hwmod_class,
977 .clkdm_name = "l4per_clkdm",
978 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
979 .main_clk = "func_96m_fclk",
980 .prcm = {
981 .omap4 = {
982 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
983 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
984 .modulemode = MODULEMODE_SWCTRL,
985 },
986 },
987 .dev_attr = &i2c_dev_attr,
988 };
989
990 /* i2c5 */
991 static struct omap_hwmod dra7xx_i2c5_hwmod = {
992 .name = "i2c5",
993 .class = &dra7xx_i2c_hwmod_class,
994 .clkdm_name = "ipu_clkdm",
995 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
996 .main_clk = "func_96m_fclk",
997 .prcm = {
998 .omap4 = {
999 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1000 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1001 .modulemode = MODULEMODE_SWCTRL,
1002 },
1003 },
1004 .dev_attr = &i2c_dev_attr,
1005 };
1006
1007 /*
1008 * 'mailbox' class
1009 *
1010 */
1011
1012 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1013 .rev_offs = 0x0000,
1014 .sysc_offs = 0x0010,
1015 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1016 SYSC_HAS_SOFTRESET),
1017 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1018 .sysc_fields = &omap_hwmod_sysc_type2,
1019 };
1020
1021 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1022 .name = "mailbox",
1023 .sysc = &dra7xx_mailbox_sysc,
1024 };
1025
1026 /* mailbox1 */
1027 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1028 .name = "mailbox1",
1029 .class = &dra7xx_mailbox_hwmod_class,
1030 .clkdm_name = "l4cfg_clkdm",
1031 .prcm = {
1032 .omap4 = {
1033 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1034 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1035 },
1036 },
1037 };
1038
1039 /* mailbox2 */
1040 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1041 .name = "mailbox2",
1042 .class = &dra7xx_mailbox_hwmod_class,
1043 .clkdm_name = "l4cfg_clkdm",
1044 .prcm = {
1045 .omap4 = {
1046 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1047 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1048 },
1049 },
1050 };
1051
1052 /* mailbox3 */
1053 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1054 .name = "mailbox3",
1055 .class = &dra7xx_mailbox_hwmod_class,
1056 .clkdm_name = "l4cfg_clkdm",
1057 .prcm = {
1058 .omap4 = {
1059 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1060 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1061 },
1062 },
1063 };
1064
1065 /* mailbox4 */
1066 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1067 .name = "mailbox4",
1068 .class = &dra7xx_mailbox_hwmod_class,
1069 .clkdm_name = "l4cfg_clkdm",
1070 .prcm = {
1071 .omap4 = {
1072 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1073 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1074 },
1075 },
1076 };
1077
1078 /* mailbox5 */
1079 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1080 .name = "mailbox5",
1081 .class = &dra7xx_mailbox_hwmod_class,
1082 .clkdm_name = "l4cfg_clkdm",
1083 .prcm = {
1084 .omap4 = {
1085 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1086 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1087 },
1088 },
1089 };
1090
1091 /* mailbox6 */
1092 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1093 .name = "mailbox6",
1094 .class = &dra7xx_mailbox_hwmod_class,
1095 .clkdm_name = "l4cfg_clkdm",
1096 .prcm = {
1097 .omap4 = {
1098 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1099 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1100 },
1101 },
1102 };
1103
1104 /* mailbox7 */
1105 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1106 .name = "mailbox7",
1107 .class = &dra7xx_mailbox_hwmod_class,
1108 .clkdm_name = "l4cfg_clkdm",
1109 .prcm = {
1110 .omap4 = {
1111 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1112 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1113 },
1114 },
1115 };
1116
1117 /* mailbox8 */
1118 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1119 .name = "mailbox8",
1120 .class = &dra7xx_mailbox_hwmod_class,
1121 .clkdm_name = "l4cfg_clkdm",
1122 .prcm = {
1123 .omap4 = {
1124 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1125 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1126 },
1127 },
1128 };
1129
1130 /* mailbox9 */
1131 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1132 .name = "mailbox9",
1133 .class = &dra7xx_mailbox_hwmod_class,
1134 .clkdm_name = "l4cfg_clkdm",
1135 .prcm = {
1136 .omap4 = {
1137 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1138 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1139 },
1140 },
1141 };
1142
1143 /* mailbox10 */
1144 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1145 .name = "mailbox10",
1146 .class = &dra7xx_mailbox_hwmod_class,
1147 .clkdm_name = "l4cfg_clkdm",
1148 .prcm = {
1149 .omap4 = {
1150 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1151 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1152 },
1153 },
1154 };
1155
1156 /* mailbox11 */
1157 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1158 .name = "mailbox11",
1159 .class = &dra7xx_mailbox_hwmod_class,
1160 .clkdm_name = "l4cfg_clkdm",
1161 .prcm = {
1162 .omap4 = {
1163 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1164 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1165 },
1166 },
1167 };
1168
1169 /* mailbox12 */
1170 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1171 .name = "mailbox12",
1172 .class = &dra7xx_mailbox_hwmod_class,
1173 .clkdm_name = "l4cfg_clkdm",
1174 .prcm = {
1175 .omap4 = {
1176 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1177 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1178 },
1179 },
1180 };
1181
1182 /* mailbox13 */
1183 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1184 .name = "mailbox13",
1185 .class = &dra7xx_mailbox_hwmod_class,
1186 .clkdm_name = "l4cfg_clkdm",
1187 .prcm = {
1188 .omap4 = {
1189 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1190 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1191 },
1192 },
1193 };
1194
1195 /*
1196 * 'mcspi' class
1197 *
1198 */
1199
1200 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1201 .rev_offs = 0x0000,
1202 .sysc_offs = 0x0010,
1203 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1204 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1205 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1206 SIDLE_SMART_WKUP),
1207 .sysc_fields = &omap_hwmod_sysc_type2,
1208 };
1209
1210 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1211 .name = "mcspi",
1212 .sysc = &dra7xx_mcspi_sysc,
1213 .rev = OMAP4_MCSPI_REV,
1214 };
1215
1216 /* mcspi1 */
1217 /* mcspi1 dev_attr */
1218 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1219 .num_chipselect = 4,
1220 };
1221
1222 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1223 .name = "mcspi1",
1224 .class = &dra7xx_mcspi_hwmod_class,
1225 .clkdm_name = "l4per_clkdm",
1226 .main_clk = "func_48m_fclk",
1227 .prcm = {
1228 .omap4 = {
1229 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1230 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1231 .modulemode = MODULEMODE_SWCTRL,
1232 },
1233 },
1234 .dev_attr = &mcspi1_dev_attr,
1235 };
1236
1237 /* mcspi2 */
1238 /* mcspi2 dev_attr */
1239 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1240 .num_chipselect = 2,
1241 };
1242
1243 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1244 .name = "mcspi2",
1245 .class = &dra7xx_mcspi_hwmod_class,
1246 .clkdm_name = "l4per_clkdm",
1247 .main_clk = "func_48m_fclk",
1248 .prcm = {
1249 .omap4 = {
1250 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1251 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1252 .modulemode = MODULEMODE_SWCTRL,
1253 },
1254 },
1255 .dev_attr = &mcspi2_dev_attr,
1256 };
1257
1258 /* mcspi3 */
1259 /* mcspi3 dev_attr */
1260 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1261 .num_chipselect = 2,
1262 };
1263
1264 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1265 .name = "mcspi3",
1266 .class = &dra7xx_mcspi_hwmod_class,
1267 .clkdm_name = "l4per_clkdm",
1268 .main_clk = "func_48m_fclk",
1269 .prcm = {
1270 .omap4 = {
1271 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1272 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1273 .modulemode = MODULEMODE_SWCTRL,
1274 },
1275 },
1276 .dev_attr = &mcspi3_dev_attr,
1277 };
1278
1279 /* mcspi4 */
1280 /* mcspi4 dev_attr */
1281 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1282 .num_chipselect = 1,
1283 };
1284
1285 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1286 .name = "mcspi4",
1287 .class = &dra7xx_mcspi_hwmod_class,
1288 .clkdm_name = "l4per_clkdm",
1289 .main_clk = "func_48m_fclk",
1290 .prcm = {
1291 .omap4 = {
1292 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1293 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1294 .modulemode = MODULEMODE_SWCTRL,
1295 },
1296 },
1297 .dev_attr = &mcspi4_dev_attr,
1298 };
1299
1300 /*
1301 * 'mmc' class
1302 *
1303 */
1304
1305 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1306 .rev_offs = 0x0000,
1307 .sysc_offs = 0x0010,
1308 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1309 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1310 SYSC_HAS_SOFTRESET),
1311 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1312 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1313 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1314 .sysc_fields = &omap_hwmod_sysc_type2,
1315 };
1316
1317 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1318 .name = "mmc",
1319 .sysc = &dra7xx_mmc_sysc,
1320 };
1321
1322 /* mmc1 */
1323 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1324 { .role = "clk32k", .clk = "mmc1_clk32k" },
1325 };
1326
1327 /* mmc1 dev_attr */
1328 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1329 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1330 };
1331
1332 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1333 .name = "mmc1",
1334 .class = &dra7xx_mmc_hwmod_class,
1335 .clkdm_name = "l3init_clkdm",
1336 .main_clk = "mmc1_fclk_div",
1337 .prcm = {
1338 .omap4 = {
1339 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1340 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1341 .modulemode = MODULEMODE_SWCTRL,
1342 },
1343 },
1344 .opt_clks = mmc1_opt_clks,
1345 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1346 .dev_attr = &mmc1_dev_attr,
1347 };
1348
1349 /* mmc2 */
1350 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1351 { .role = "clk32k", .clk = "mmc2_clk32k" },
1352 };
1353
1354 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1355 .name = "mmc2",
1356 .class = &dra7xx_mmc_hwmod_class,
1357 .clkdm_name = "l3init_clkdm",
1358 .main_clk = "mmc2_fclk_div",
1359 .prcm = {
1360 .omap4 = {
1361 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1362 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1363 .modulemode = MODULEMODE_SWCTRL,
1364 },
1365 },
1366 .opt_clks = mmc2_opt_clks,
1367 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1368 };
1369
1370 /* mmc3 */
1371 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1372 { .role = "clk32k", .clk = "mmc3_clk32k" },
1373 };
1374
1375 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1376 .name = "mmc3",
1377 .class = &dra7xx_mmc_hwmod_class,
1378 .clkdm_name = "l4per_clkdm",
1379 .main_clk = "mmc3_gfclk_div",
1380 .prcm = {
1381 .omap4 = {
1382 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1383 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1384 .modulemode = MODULEMODE_SWCTRL,
1385 },
1386 },
1387 .opt_clks = mmc3_opt_clks,
1388 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1389 };
1390
1391 /* mmc4 */
1392 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1393 { .role = "clk32k", .clk = "mmc4_clk32k" },
1394 };
1395
1396 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1397 .name = "mmc4",
1398 .class = &dra7xx_mmc_hwmod_class,
1399 .clkdm_name = "l4per_clkdm",
1400 .main_clk = "mmc4_gfclk_div",
1401 .prcm = {
1402 .omap4 = {
1403 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1404 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1405 .modulemode = MODULEMODE_SWCTRL,
1406 },
1407 },
1408 .opt_clks = mmc4_opt_clks,
1409 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1410 };
1411
1412 /*
1413 * 'mpu' class
1414 *
1415 */
1416
1417 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1418 .name = "mpu",
1419 };
1420
1421 /* mpu */
1422 static struct omap_hwmod dra7xx_mpu_hwmod = {
1423 .name = "mpu",
1424 .class = &dra7xx_mpu_hwmod_class,
1425 .clkdm_name = "mpu_clkdm",
1426 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1427 .main_clk = "dpll_mpu_m2_ck",
1428 .prcm = {
1429 .omap4 = {
1430 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1431 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1432 },
1433 },
1434 };
1435
1436 /*
1437 * 'ocp2scp' class
1438 *
1439 */
1440
1441 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1442 .rev_offs = 0x0000,
1443 .sysc_offs = 0x0010,
1444 .syss_offs = 0x0014,
1445 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1446 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1447 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1448 SIDLE_SMART_WKUP),
1449 .sysc_fields = &omap_hwmod_sysc_type1,
1450 };
1451
1452 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1453 .name = "ocp2scp",
1454 .sysc = &dra7xx_ocp2scp_sysc,
1455 };
1456
1457 /* ocp2scp1 */
1458 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1459 .name = "ocp2scp1",
1460 .class = &dra7xx_ocp2scp_hwmod_class,
1461 .clkdm_name = "l3init_clkdm",
1462 .main_clk = "l4_root_clk_div",
1463 .prcm = {
1464 .omap4 = {
1465 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1466 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1467 .modulemode = MODULEMODE_HWCTRL,
1468 },
1469 },
1470 };
1471
1472 /* ocp2scp3 */
1473 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1474 .name = "ocp2scp3",
1475 .class = &dra7xx_ocp2scp_hwmod_class,
1476 .clkdm_name = "l3init_clkdm",
1477 .main_clk = "l4_root_clk_div",
1478 .prcm = {
1479 .omap4 = {
1480 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1481 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1482 .modulemode = MODULEMODE_HWCTRL,
1483 },
1484 },
1485 };
1486
1487 /*
1488 * 'PCIE' class
1489 *
1490 */
1491
1492 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1493 .name = "pcie",
1494 };
1495
1496 /* pcie1 */
1497 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1498 .name = "pcie1",
1499 .class = &dra7xx_pciess_hwmod_class,
1500 .clkdm_name = "pcie_clkdm",
1501 .main_clk = "l4_root_clk_div",
1502 .prcm = {
1503 .omap4 = {
1504 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1505 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1506 .modulemode = MODULEMODE_SWCTRL,
1507 },
1508 },
1509 };
1510
1511 /* pcie2 */
1512 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1513 .name = "pcie2",
1514 .class = &dra7xx_pciess_hwmod_class,
1515 .clkdm_name = "pcie_clkdm",
1516 .main_clk = "l4_root_clk_div",
1517 .prcm = {
1518 .omap4 = {
1519 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1520 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1521 .modulemode = MODULEMODE_SWCTRL,
1522 },
1523 },
1524 };
1525
1526 /*
1527 * 'qspi' class
1528 *
1529 */
1530
1531 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1532 .sysc_offs = 0x0010,
1533 .sysc_flags = SYSC_HAS_SIDLEMODE,
1534 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1535 SIDLE_SMART_WKUP),
1536 .sysc_fields = &omap_hwmod_sysc_type2,
1537 };
1538
1539 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1540 .name = "qspi",
1541 .sysc = &dra7xx_qspi_sysc,
1542 };
1543
1544 /* qspi */
1545 static struct omap_hwmod dra7xx_qspi_hwmod = {
1546 .name = "qspi",
1547 .class = &dra7xx_qspi_hwmod_class,
1548 .clkdm_name = "l4per2_clkdm",
1549 .main_clk = "qspi_gfclk_div",
1550 .prcm = {
1551 .omap4 = {
1552 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1553 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1554 .modulemode = MODULEMODE_SWCTRL,
1555 },
1556 },
1557 };
1558
1559 /*
1560 * 'rtcss' class
1561 *
1562 */
1563 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1564 .sysc_offs = 0x0078,
1565 .sysc_flags = SYSC_HAS_SIDLEMODE,
1566 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1567 SIDLE_SMART_WKUP),
1568 .sysc_fields = &omap_hwmod_sysc_type3,
1569 };
1570
1571 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1572 .name = "rtcss",
1573 .sysc = &dra7xx_rtcss_sysc,
1574 };
1575
1576 /* rtcss */
1577 static struct omap_hwmod dra7xx_rtcss_hwmod = {
1578 .name = "rtcss",
1579 .class = &dra7xx_rtcss_hwmod_class,
1580 .clkdm_name = "rtc_clkdm",
1581 .main_clk = "sys_32k_ck",
1582 .prcm = {
1583 .omap4 = {
1584 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1585 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1586 .modulemode = MODULEMODE_SWCTRL,
1587 },
1588 },
1589 };
1590
1591 /*
1592 * 'sata' class
1593 *
1594 */
1595
1596 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1597 .sysc_offs = 0x0000,
1598 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1599 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1600 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1601 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1602 .sysc_fields = &omap_hwmod_sysc_type2,
1603 };
1604
1605 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1606 .name = "sata",
1607 .sysc = &dra7xx_sata_sysc,
1608 };
1609
1610 /* sata */
1611
1612 static struct omap_hwmod dra7xx_sata_hwmod = {
1613 .name = "sata",
1614 .class = &dra7xx_sata_hwmod_class,
1615 .clkdm_name = "l3init_clkdm",
1616 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1617 .main_clk = "func_48m_fclk",
1618 .mpu_rt_idx = 1,
1619 .prcm = {
1620 .omap4 = {
1621 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1622 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1623 .modulemode = MODULEMODE_SWCTRL,
1624 },
1625 },
1626 };
1627
1628 /*
1629 * 'smartreflex' class
1630 *
1631 */
1632
1633 /* The IP is not compliant to type1 / type2 scheme */
1634 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1635 .sidle_shift = 24,
1636 .enwkup_shift = 26,
1637 };
1638
1639 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1640 .sysc_offs = 0x0038,
1641 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1642 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1643 SIDLE_SMART_WKUP),
1644 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1645 };
1646
1647 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1648 .name = "smartreflex",
1649 .sysc = &dra7xx_smartreflex_sysc,
1650 .rev = 2,
1651 };
1652
1653 /* smartreflex_core */
1654 /* smartreflex_core dev_attr */
1655 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1656 .sensor_voltdm_name = "core",
1657 };
1658
1659 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1660 .name = "smartreflex_core",
1661 .class = &dra7xx_smartreflex_hwmod_class,
1662 .clkdm_name = "coreaon_clkdm",
1663 .main_clk = "wkupaon_iclk_mux",
1664 .prcm = {
1665 .omap4 = {
1666 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1667 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1668 .modulemode = MODULEMODE_SWCTRL,
1669 },
1670 },
1671 .dev_attr = &smartreflex_core_dev_attr,
1672 };
1673
1674 /* smartreflex_mpu */
1675 /* smartreflex_mpu dev_attr */
1676 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1677 .sensor_voltdm_name = "mpu",
1678 };
1679
1680 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1681 .name = "smartreflex_mpu",
1682 .class = &dra7xx_smartreflex_hwmod_class,
1683 .clkdm_name = "coreaon_clkdm",
1684 .main_clk = "wkupaon_iclk_mux",
1685 .prcm = {
1686 .omap4 = {
1687 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1688 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1689 .modulemode = MODULEMODE_SWCTRL,
1690 },
1691 },
1692 .dev_attr = &smartreflex_mpu_dev_attr,
1693 };
1694
1695 /*
1696 * 'spinlock' class
1697 *
1698 */
1699
1700 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1701 .rev_offs = 0x0000,
1702 .sysc_offs = 0x0010,
1703 .syss_offs = 0x0014,
1704 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1705 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1706 SYSS_HAS_RESET_STATUS),
1707 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1708 .sysc_fields = &omap_hwmod_sysc_type1,
1709 };
1710
1711 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1712 .name = "spinlock",
1713 .sysc = &dra7xx_spinlock_sysc,
1714 };
1715
1716 /* spinlock */
1717 static struct omap_hwmod dra7xx_spinlock_hwmod = {
1718 .name = "spinlock",
1719 .class = &dra7xx_spinlock_hwmod_class,
1720 .clkdm_name = "l4cfg_clkdm",
1721 .main_clk = "l3_iclk_div",
1722 .prcm = {
1723 .omap4 = {
1724 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1725 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1726 },
1727 },
1728 };
1729
1730 /*
1731 * 'timer' class
1732 *
1733 * This class contains several variants: ['timer_1ms', 'timer_secure',
1734 * 'timer']
1735 */
1736
1737 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1738 .rev_offs = 0x0000,
1739 .sysc_offs = 0x0010,
1740 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1741 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1742 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1743 SIDLE_SMART_WKUP),
1744 .sysc_fields = &omap_hwmod_sysc_type2,
1745 };
1746
1747 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1748 .name = "timer",
1749 .sysc = &dra7xx_timer_1ms_sysc,
1750 };
1751
1752 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1753 .rev_offs = 0x0000,
1754 .sysc_offs = 0x0010,
1755 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1756 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1757 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1758 SIDLE_SMART_WKUP),
1759 .sysc_fields = &omap_hwmod_sysc_type2,
1760 };
1761
1762 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1763 .name = "timer",
1764 .sysc = &dra7xx_timer_sysc,
1765 };
1766
1767 /* timer1 */
1768 static struct omap_hwmod dra7xx_timer1_hwmod = {
1769 .name = "timer1",
1770 .class = &dra7xx_timer_1ms_hwmod_class,
1771 .clkdm_name = "wkupaon_clkdm",
1772 .main_clk = "timer1_gfclk_mux",
1773 .prcm = {
1774 .omap4 = {
1775 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1776 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1777 .modulemode = MODULEMODE_SWCTRL,
1778 },
1779 },
1780 };
1781
1782 /* timer2 */
1783 static struct omap_hwmod dra7xx_timer2_hwmod = {
1784 .name = "timer2",
1785 .class = &dra7xx_timer_1ms_hwmod_class,
1786 .clkdm_name = "l4per_clkdm",
1787 .main_clk = "timer2_gfclk_mux",
1788 .prcm = {
1789 .omap4 = {
1790 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1791 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1792 .modulemode = MODULEMODE_SWCTRL,
1793 },
1794 },
1795 };
1796
1797 /* timer3 */
1798 static struct omap_hwmod dra7xx_timer3_hwmod = {
1799 .name = "timer3",
1800 .class = &dra7xx_timer_hwmod_class,
1801 .clkdm_name = "l4per_clkdm",
1802 .main_clk = "timer3_gfclk_mux",
1803 .prcm = {
1804 .omap4 = {
1805 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1806 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1807 .modulemode = MODULEMODE_SWCTRL,
1808 },
1809 },
1810 };
1811
1812 /* timer4 */
1813 static struct omap_hwmod dra7xx_timer4_hwmod = {
1814 .name = "timer4",
1815 .class = &dra7xx_timer_hwmod_class,
1816 .clkdm_name = "l4per_clkdm",
1817 .main_clk = "timer4_gfclk_mux",
1818 .prcm = {
1819 .omap4 = {
1820 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1821 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1822 .modulemode = MODULEMODE_SWCTRL,
1823 },
1824 },
1825 };
1826
1827 /* timer5 */
1828 static struct omap_hwmod dra7xx_timer5_hwmod = {
1829 .name = "timer5",
1830 .class = &dra7xx_timer_hwmod_class,
1831 .clkdm_name = "ipu_clkdm",
1832 .main_clk = "timer5_gfclk_mux",
1833 .prcm = {
1834 .omap4 = {
1835 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1836 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1837 .modulemode = MODULEMODE_SWCTRL,
1838 },
1839 },
1840 };
1841
1842 /* timer6 */
1843 static struct omap_hwmod dra7xx_timer6_hwmod = {
1844 .name = "timer6",
1845 .class = &dra7xx_timer_hwmod_class,
1846 .clkdm_name = "ipu_clkdm",
1847 .main_clk = "timer6_gfclk_mux",
1848 .prcm = {
1849 .omap4 = {
1850 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1851 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1852 .modulemode = MODULEMODE_SWCTRL,
1853 },
1854 },
1855 };
1856
1857 /* timer7 */
1858 static struct omap_hwmod dra7xx_timer7_hwmod = {
1859 .name = "timer7",
1860 .class = &dra7xx_timer_hwmod_class,
1861 .clkdm_name = "ipu_clkdm",
1862 .main_clk = "timer7_gfclk_mux",
1863 .prcm = {
1864 .omap4 = {
1865 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1866 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1867 .modulemode = MODULEMODE_SWCTRL,
1868 },
1869 },
1870 };
1871
1872 /* timer8 */
1873 static struct omap_hwmod dra7xx_timer8_hwmod = {
1874 .name = "timer8",
1875 .class = &dra7xx_timer_hwmod_class,
1876 .clkdm_name = "ipu_clkdm",
1877 .main_clk = "timer8_gfclk_mux",
1878 .prcm = {
1879 .omap4 = {
1880 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1881 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1882 .modulemode = MODULEMODE_SWCTRL,
1883 },
1884 },
1885 };
1886
1887 /* timer9 */
1888 static struct omap_hwmod dra7xx_timer9_hwmod = {
1889 .name = "timer9",
1890 .class = &dra7xx_timer_hwmod_class,
1891 .clkdm_name = "l4per_clkdm",
1892 .main_clk = "timer9_gfclk_mux",
1893 .prcm = {
1894 .omap4 = {
1895 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1896 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1897 .modulemode = MODULEMODE_SWCTRL,
1898 },
1899 },
1900 };
1901
1902 /* timer10 */
1903 static struct omap_hwmod dra7xx_timer10_hwmod = {
1904 .name = "timer10",
1905 .class = &dra7xx_timer_1ms_hwmod_class,
1906 .clkdm_name = "l4per_clkdm",
1907 .main_clk = "timer10_gfclk_mux",
1908 .prcm = {
1909 .omap4 = {
1910 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1911 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1912 .modulemode = MODULEMODE_SWCTRL,
1913 },
1914 },
1915 };
1916
1917 /* timer11 */
1918 static struct omap_hwmod dra7xx_timer11_hwmod = {
1919 .name = "timer11",
1920 .class = &dra7xx_timer_hwmod_class,
1921 .clkdm_name = "l4per_clkdm",
1922 .main_clk = "timer11_gfclk_mux",
1923 .prcm = {
1924 .omap4 = {
1925 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1926 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1927 .modulemode = MODULEMODE_SWCTRL,
1928 },
1929 },
1930 };
1931
1932 /* timer13 */
1933 static struct omap_hwmod dra7xx_timer13_hwmod = {
1934 .name = "timer13",
1935 .class = &dra7xx_timer_hwmod_class,
1936 .clkdm_name = "l4per3_clkdm",
1937 .main_clk = "timer13_gfclk_mux",
1938 .prcm = {
1939 .omap4 = {
1940 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
1941 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
1942 .modulemode = MODULEMODE_SWCTRL,
1943 },
1944 },
1945 };
1946
1947 /* timer14 */
1948 static struct omap_hwmod dra7xx_timer14_hwmod = {
1949 .name = "timer14",
1950 .class = &dra7xx_timer_hwmod_class,
1951 .clkdm_name = "l4per3_clkdm",
1952 .main_clk = "timer14_gfclk_mux",
1953 .prcm = {
1954 .omap4 = {
1955 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
1956 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
1957 .modulemode = MODULEMODE_SWCTRL,
1958 },
1959 },
1960 };
1961
1962 /* timer15 */
1963 static struct omap_hwmod dra7xx_timer15_hwmod = {
1964 .name = "timer15",
1965 .class = &dra7xx_timer_hwmod_class,
1966 .clkdm_name = "l4per3_clkdm",
1967 .main_clk = "timer15_gfclk_mux",
1968 .prcm = {
1969 .omap4 = {
1970 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
1971 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
1972 .modulemode = MODULEMODE_SWCTRL,
1973 },
1974 },
1975 };
1976
1977 /* timer16 */
1978 static struct omap_hwmod dra7xx_timer16_hwmod = {
1979 .name = "timer16",
1980 .class = &dra7xx_timer_hwmod_class,
1981 .clkdm_name = "l4per3_clkdm",
1982 .main_clk = "timer16_gfclk_mux",
1983 .prcm = {
1984 .omap4 = {
1985 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
1986 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
1987 .modulemode = MODULEMODE_SWCTRL,
1988 },
1989 },
1990 };
1991
1992 /*
1993 * 'uart' class
1994 *
1995 */
1996
1997 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1998 .rev_offs = 0x0050,
1999 .sysc_offs = 0x0054,
2000 .syss_offs = 0x0058,
2001 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2002 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2003 SYSS_HAS_RESET_STATUS),
2004 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2005 SIDLE_SMART_WKUP),
2006 .sysc_fields = &omap_hwmod_sysc_type1,
2007 };
2008
2009 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2010 .name = "uart",
2011 .sysc = &dra7xx_uart_sysc,
2012 };
2013
2014 /* uart1 */
2015 static struct omap_hwmod dra7xx_uart1_hwmod = {
2016 .name = "uart1",
2017 .class = &dra7xx_uart_hwmod_class,
2018 .clkdm_name = "l4per_clkdm",
2019 .main_clk = "uart1_gfclk_mux",
2020 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2021 .prcm = {
2022 .omap4 = {
2023 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2024 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2025 .modulemode = MODULEMODE_SWCTRL,
2026 },
2027 },
2028 };
2029
2030 /* uart2 */
2031 static struct omap_hwmod dra7xx_uart2_hwmod = {
2032 .name = "uart2",
2033 .class = &dra7xx_uart_hwmod_class,
2034 .clkdm_name = "l4per_clkdm",
2035 .main_clk = "uart2_gfclk_mux",
2036 .flags = HWMOD_SWSUP_SIDLE_ACT,
2037 .prcm = {
2038 .omap4 = {
2039 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2040 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2041 .modulemode = MODULEMODE_SWCTRL,
2042 },
2043 },
2044 };
2045
2046 /* uart3 */
2047 static struct omap_hwmod dra7xx_uart3_hwmod = {
2048 .name = "uart3",
2049 .class = &dra7xx_uart_hwmod_class,
2050 .clkdm_name = "l4per_clkdm",
2051 .main_clk = "uart3_gfclk_mux",
2052 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2053 .prcm = {
2054 .omap4 = {
2055 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2056 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2057 .modulemode = MODULEMODE_SWCTRL,
2058 },
2059 },
2060 };
2061
2062 /* uart4 */
2063 static struct omap_hwmod dra7xx_uart4_hwmod = {
2064 .name = "uart4",
2065 .class = &dra7xx_uart_hwmod_class,
2066 .clkdm_name = "l4per_clkdm",
2067 .main_clk = "uart4_gfclk_mux",
2068 .flags = HWMOD_SWSUP_SIDLE_ACT,
2069 .prcm = {
2070 .omap4 = {
2071 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2072 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2073 .modulemode = MODULEMODE_SWCTRL,
2074 },
2075 },
2076 };
2077
2078 /* uart5 */
2079 static struct omap_hwmod dra7xx_uart5_hwmod = {
2080 .name = "uart5",
2081 .class = &dra7xx_uart_hwmod_class,
2082 .clkdm_name = "l4per_clkdm",
2083 .main_clk = "uart5_gfclk_mux",
2084 .flags = HWMOD_SWSUP_SIDLE_ACT,
2085 .prcm = {
2086 .omap4 = {
2087 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2088 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2089 .modulemode = MODULEMODE_SWCTRL,
2090 },
2091 },
2092 };
2093
2094 /* uart6 */
2095 static struct omap_hwmod dra7xx_uart6_hwmod = {
2096 .name = "uart6",
2097 .class = &dra7xx_uart_hwmod_class,
2098 .clkdm_name = "ipu_clkdm",
2099 .main_clk = "uart6_gfclk_mux",
2100 .flags = HWMOD_SWSUP_SIDLE_ACT,
2101 .prcm = {
2102 .omap4 = {
2103 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2104 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2105 .modulemode = MODULEMODE_SWCTRL,
2106 },
2107 },
2108 };
2109
2110 /* uart7 */
2111 static struct omap_hwmod dra7xx_uart7_hwmod = {
2112 .name = "uart7",
2113 .class = &dra7xx_uart_hwmod_class,
2114 .clkdm_name = "l4per2_clkdm",
2115 .main_clk = "uart7_gfclk_mux",
2116 .flags = HWMOD_SWSUP_SIDLE_ACT,
2117 .prcm = {
2118 .omap4 = {
2119 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2120 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2121 .modulemode = MODULEMODE_SWCTRL,
2122 },
2123 },
2124 };
2125
2126 /* uart8 */
2127 static struct omap_hwmod dra7xx_uart8_hwmod = {
2128 .name = "uart8",
2129 .class = &dra7xx_uart_hwmod_class,
2130 .clkdm_name = "l4per2_clkdm",
2131 .main_clk = "uart8_gfclk_mux",
2132 .flags = HWMOD_SWSUP_SIDLE_ACT,
2133 .prcm = {
2134 .omap4 = {
2135 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2136 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2137 .modulemode = MODULEMODE_SWCTRL,
2138 },
2139 },
2140 };
2141
2142 /* uart9 */
2143 static struct omap_hwmod dra7xx_uart9_hwmod = {
2144 .name = "uart9",
2145 .class = &dra7xx_uart_hwmod_class,
2146 .clkdm_name = "l4per2_clkdm",
2147 .main_clk = "uart9_gfclk_mux",
2148 .flags = HWMOD_SWSUP_SIDLE_ACT,
2149 .prcm = {
2150 .omap4 = {
2151 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2152 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2153 .modulemode = MODULEMODE_SWCTRL,
2154 },
2155 },
2156 };
2157
2158 /* uart10 */
2159 static struct omap_hwmod dra7xx_uart10_hwmod = {
2160 .name = "uart10",
2161 .class = &dra7xx_uart_hwmod_class,
2162 .clkdm_name = "wkupaon_clkdm",
2163 .main_clk = "uart10_gfclk_mux",
2164 .flags = HWMOD_SWSUP_SIDLE_ACT,
2165 .prcm = {
2166 .omap4 = {
2167 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2168 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2169 .modulemode = MODULEMODE_SWCTRL,
2170 },
2171 },
2172 };
2173
2174 /*
2175 * 'usb_otg_ss' class
2176 *
2177 */
2178
2179 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2180 .rev_offs = 0x0000,
2181 .sysc_offs = 0x0010,
2182 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2183 SYSC_HAS_SIDLEMODE),
2184 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2185 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2186 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2187 .sysc_fields = &omap_hwmod_sysc_type2,
2188 };
2189
2190 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2191 .name = "usb_otg_ss",
2192 .sysc = &dra7xx_usb_otg_ss_sysc,
2193 };
2194
2195 /* usb_otg_ss1 */
2196 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2197 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2198 };
2199
2200 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2201 .name = "usb_otg_ss1",
2202 .class = &dra7xx_usb_otg_ss_hwmod_class,
2203 .clkdm_name = "l3init_clkdm",
2204 .main_clk = "dpll_core_h13x2_ck",
2205 .prcm = {
2206 .omap4 = {
2207 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2208 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2209 .modulemode = MODULEMODE_HWCTRL,
2210 },
2211 },
2212 .opt_clks = usb_otg_ss1_opt_clks,
2213 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2214 };
2215
2216 /* usb_otg_ss2 */
2217 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2218 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2219 };
2220
2221 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2222 .name = "usb_otg_ss2",
2223 .class = &dra7xx_usb_otg_ss_hwmod_class,
2224 .clkdm_name = "l3init_clkdm",
2225 .main_clk = "dpll_core_h13x2_ck",
2226 .prcm = {
2227 .omap4 = {
2228 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2229 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2230 .modulemode = MODULEMODE_HWCTRL,
2231 },
2232 },
2233 .opt_clks = usb_otg_ss2_opt_clks,
2234 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2235 };
2236
2237 /* usb_otg_ss3 */
2238 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2239 .name = "usb_otg_ss3",
2240 .class = &dra7xx_usb_otg_ss_hwmod_class,
2241 .clkdm_name = "l3init_clkdm",
2242 .main_clk = "dpll_core_h13x2_ck",
2243 .prcm = {
2244 .omap4 = {
2245 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2246 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2247 .modulemode = MODULEMODE_HWCTRL,
2248 },
2249 },
2250 };
2251
2252 /* usb_otg_ss4 */
2253 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2254 .name = "usb_otg_ss4",
2255 .class = &dra7xx_usb_otg_ss_hwmod_class,
2256 .clkdm_name = "l3init_clkdm",
2257 .main_clk = "dpll_core_h13x2_ck",
2258 .prcm = {
2259 .omap4 = {
2260 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2261 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2262 .modulemode = MODULEMODE_HWCTRL,
2263 },
2264 },
2265 };
2266
2267 /*
2268 * 'vcp' class
2269 *
2270 */
2271
2272 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2273 .name = "vcp",
2274 };
2275
2276 /* vcp1 */
2277 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2278 .name = "vcp1",
2279 .class = &dra7xx_vcp_hwmod_class,
2280 .clkdm_name = "l3main1_clkdm",
2281 .main_clk = "l3_iclk_div",
2282 .prcm = {
2283 .omap4 = {
2284 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2285 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2286 },
2287 },
2288 };
2289
2290 /* vcp2 */
2291 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2292 .name = "vcp2",
2293 .class = &dra7xx_vcp_hwmod_class,
2294 .clkdm_name = "l3main1_clkdm",
2295 .main_clk = "l3_iclk_div",
2296 .prcm = {
2297 .omap4 = {
2298 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2299 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2300 },
2301 },
2302 };
2303
2304 /*
2305 * 'wd_timer' class
2306 *
2307 */
2308
2309 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2310 .rev_offs = 0x0000,
2311 .sysc_offs = 0x0010,
2312 .syss_offs = 0x0014,
2313 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2314 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2315 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2316 SIDLE_SMART_WKUP),
2317 .sysc_fields = &omap_hwmod_sysc_type1,
2318 };
2319
2320 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2321 .name = "wd_timer",
2322 .sysc = &dra7xx_wd_timer_sysc,
2323 .pre_shutdown = &omap2_wd_timer_disable,
2324 .reset = &omap2_wd_timer_reset,
2325 };
2326
2327 /* wd_timer2 */
2328 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2329 .name = "wd_timer2",
2330 .class = &dra7xx_wd_timer_hwmod_class,
2331 .clkdm_name = "wkupaon_clkdm",
2332 .main_clk = "sys_32k_ck",
2333 .prcm = {
2334 .omap4 = {
2335 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2336 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2337 .modulemode = MODULEMODE_SWCTRL,
2338 },
2339 },
2340 };
2341
2342
2343 /*
2344 * Interfaces
2345 */
2346
2347 /* l3_main_1 -> dmm */
2348 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2349 .master = &dra7xx_l3_main_1_hwmod,
2350 .slave = &dra7xx_dmm_hwmod,
2351 .clk = "l3_iclk_div",
2352 .user = OCP_USER_SDMA,
2353 };
2354
2355 /* l3_main_2 -> l3_instr */
2356 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2357 .master = &dra7xx_l3_main_2_hwmod,
2358 .slave = &dra7xx_l3_instr_hwmod,
2359 .clk = "l3_iclk_div",
2360 .user = OCP_USER_MPU | OCP_USER_SDMA,
2361 };
2362
2363 /* l4_cfg -> l3_main_1 */
2364 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2365 .master = &dra7xx_l4_cfg_hwmod,
2366 .slave = &dra7xx_l3_main_1_hwmod,
2367 .clk = "l3_iclk_div",
2368 .user = OCP_USER_MPU | OCP_USER_SDMA,
2369 };
2370
2371 /* mpu -> l3_main_1 */
2372 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2373 .master = &dra7xx_mpu_hwmod,
2374 .slave = &dra7xx_l3_main_1_hwmod,
2375 .clk = "l3_iclk_div",
2376 .user = OCP_USER_MPU,
2377 };
2378
2379 /* l3_main_1 -> l3_main_2 */
2380 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2381 .master = &dra7xx_l3_main_1_hwmod,
2382 .slave = &dra7xx_l3_main_2_hwmod,
2383 .clk = "l3_iclk_div",
2384 .user = OCP_USER_MPU,
2385 };
2386
2387 /* l4_cfg -> l3_main_2 */
2388 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2389 .master = &dra7xx_l4_cfg_hwmod,
2390 .slave = &dra7xx_l3_main_2_hwmod,
2391 .clk = "l3_iclk_div",
2392 .user = OCP_USER_MPU | OCP_USER_SDMA,
2393 };
2394
2395 /* l3_main_1 -> l4_cfg */
2396 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2397 .master = &dra7xx_l3_main_1_hwmod,
2398 .slave = &dra7xx_l4_cfg_hwmod,
2399 .clk = "l3_iclk_div",
2400 .user = OCP_USER_MPU | OCP_USER_SDMA,
2401 };
2402
2403 /* l3_main_1 -> l4_per1 */
2404 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2405 .master = &dra7xx_l3_main_1_hwmod,
2406 .slave = &dra7xx_l4_per1_hwmod,
2407 .clk = "l3_iclk_div",
2408 .user = OCP_USER_MPU | OCP_USER_SDMA,
2409 };
2410
2411 /* l3_main_1 -> l4_per2 */
2412 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2413 .master = &dra7xx_l3_main_1_hwmod,
2414 .slave = &dra7xx_l4_per2_hwmod,
2415 .clk = "l3_iclk_div",
2416 .user = OCP_USER_MPU | OCP_USER_SDMA,
2417 };
2418
2419 /* l3_main_1 -> l4_per3 */
2420 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2421 .master = &dra7xx_l3_main_1_hwmod,
2422 .slave = &dra7xx_l4_per3_hwmod,
2423 .clk = "l3_iclk_div",
2424 .user = OCP_USER_MPU | OCP_USER_SDMA,
2425 };
2426
2427 /* l3_main_1 -> l4_wkup */
2428 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2429 .master = &dra7xx_l3_main_1_hwmod,
2430 .slave = &dra7xx_l4_wkup_hwmod,
2431 .clk = "wkupaon_iclk_mux",
2432 .user = OCP_USER_MPU | OCP_USER_SDMA,
2433 };
2434
2435 /* l4_per2 -> atl */
2436 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2437 .master = &dra7xx_l4_per2_hwmod,
2438 .slave = &dra7xx_atl_hwmod,
2439 .clk = "l3_iclk_div",
2440 .user = OCP_USER_MPU | OCP_USER_SDMA,
2441 };
2442
2443 /* l3_main_1 -> bb2d */
2444 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2445 .master = &dra7xx_l3_main_1_hwmod,
2446 .slave = &dra7xx_bb2d_hwmod,
2447 .clk = "l3_iclk_div",
2448 .user = OCP_USER_MPU | OCP_USER_SDMA,
2449 };
2450
2451 /* l4_wkup -> counter_32k */
2452 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2453 .master = &dra7xx_l4_wkup_hwmod,
2454 .slave = &dra7xx_counter_32k_hwmod,
2455 .clk = "wkupaon_iclk_mux",
2456 .user = OCP_USER_MPU | OCP_USER_SDMA,
2457 };
2458
2459 /* l4_wkup -> ctrl_module_wkup */
2460 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2461 .master = &dra7xx_l4_wkup_hwmod,
2462 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2463 .clk = "wkupaon_iclk_mux",
2464 .user = OCP_USER_MPU | OCP_USER_SDMA,
2465 };
2466
2467 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2468 .master = &dra7xx_l4_per2_hwmod,
2469 .slave = &dra7xx_gmac_hwmod,
2470 .clk = "dpll_gmac_ck",
2471 .user = OCP_USER_MPU,
2472 };
2473
2474 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2475 .master = &dra7xx_gmac_hwmod,
2476 .slave = &dra7xx_mdio_hwmod,
2477 .user = OCP_USER_MPU,
2478 };
2479
2480 /* l4_wkup -> dcan1 */
2481 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2482 .master = &dra7xx_l4_wkup_hwmod,
2483 .slave = &dra7xx_dcan1_hwmod,
2484 .clk = "wkupaon_iclk_mux",
2485 .user = OCP_USER_MPU | OCP_USER_SDMA,
2486 };
2487
2488 /* l4_per2 -> dcan2 */
2489 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2490 .master = &dra7xx_l4_per2_hwmod,
2491 .slave = &dra7xx_dcan2_hwmod,
2492 .clk = "l3_iclk_div",
2493 .user = OCP_USER_MPU | OCP_USER_SDMA,
2494 };
2495
2496 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2497 {
2498 .pa_start = 0x4a056000,
2499 .pa_end = 0x4a056fff,
2500 .flags = ADDR_TYPE_RT
2501 },
2502 { }
2503 };
2504
2505 /* l4_cfg -> dma_system */
2506 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2507 .master = &dra7xx_l4_cfg_hwmod,
2508 .slave = &dra7xx_dma_system_hwmod,
2509 .clk = "l3_iclk_div",
2510 .addr = dra7xx_dma_system_addrs,
2511 .user = OCP_USER_MPU | OCP_USER_SDMA,
2512 };
2513
2514 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2515 {
2516 .name = "family",
2517 .pa_start = 0x58000000,
2518 .pa_end = 0x5800007f,
2519 .flags = ADDR_TYPE_RT
2520 },
2521 };
2522
2523 /* l3_main_1 -> dss */
2524 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2525 .master = &dra7xx_l3_main_1_hwmod,
2526 .slave = &dra7xx_dss_hwmod,
2527 .clk = "l3_iclk_div",
2528 .addr = dra7xx_dss_addrs,
2529 .user = OCP_USER_MPU | OCP_USER_SDMA,
2530 };
2531
2532 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2533 {
2534 .name = "dispc",
2535 .pa_start = 0x58001000,
2536 .pa_end = 0x58001fff,
2537 .flags = ADDR_TYPE_RT
2538 },
2539 };
2540
2541 /* l3_main_1 -> dispc */
2542 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2543 .master = &dra7xx_l3_main_1_hwmod,
2544 .slave = &dra7xx_dss_dispc_hwmod,
2545 .clk = "l3_iclk_div",
2546 .addr = dra7xx_dss_dispc_addrs,
2547 .user = OCP_USER_MPU | OCP_USER_SDMA,
2548 };
2549
2550 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2551 {
2552 .name = "hdmi_wp",
2553 .pa_start = 0x58040000,
2554 .pa_end = 0x580400ff,
2555 .flags = ADDR_TYPE_RT
2556 },
2557 { }
2558 };
2559
2560 /* l3_main_1 -> dispc */
2561 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2562 .master = &dra7xx_l3_main_1_hwmod,
2563 .slave = &dra7xx_dss_hdmi_hwmod,
2564 .clk = "l3_iclk_div",
2565 .addr = dra7xx_dss_hdmi_addrs,
2566 .user = OCP_USER_MPU | OCP_USER_SDMA,
2567 };
2568
2569 static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2570 {
2571 .pa_start = 0x48078000,
2572 .pa_end = 0x48078fff,
2573 .flags = ADDR_TYPE_RT
2574 },
2575 { }
2576 };
2577
2578 /* l4_per1 -> elm */
2579 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2580 .master = &dra7xx_l4_per1_hwmod,
2581 .slave = &dra7xx_elm_hwmod,
2582 .clk = "l3_iclk_div",
2583 .addr = dra7xx_elm_addrs,
2584 .user = OCP_USER_MPU | OCP_USER_SDMA,
2585 };
2586
2587 /* l4_wkup -> gpio1 */
2588 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2589 .master = &dra7xx_l4_wkup_hwmod,
2590 .slave = &dra7xx_gpio1_hwmod,
2591 .clk = "wkupaon_iclk_mux",
2592 .user = OCP_USER_MPU | OCP_USER_SDMA,
2593 };
2594
2595 /* l4_per1 -> gpio2 */
2596 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2597 .master = &dra7xx_l4_per1_hwmod,
2598 .slave = &dra7xx_gpio2_hwmod,
2599 .clk = "l3_iclk_div",
2600 .user = OCP_USER_MPU | OCP_USER_SDMA,
2601 };
2602
2603 /* l4_per1 -> gpio3 */
2604 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2605 .master = &dra7xx_l4_per1_hwmod,
2606 .slave = &dra7xx_gpio3_hwmod,
2607 .clk = "l3_iclk_div",
2608 .user = OCP_USER_MPU | OCP_USER_SDMA,
2609 };
2610
2611 /* l4_per1 -> gpio4 */
2612 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2613 .master = &dra7xx_l4_per1_hwmod,
2614 .slave = &dra7xx_gpio4_hwmod,
2615 .clk = "l3_iclk_div",
2616 .user = OCP_USER_MPU | OCP_USER_SDMA,
2617 };
2618
2619 /* l4_per1 -> gpio5 */
2620 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2621 .master = &dra7xx_l4_per1_hwmod,
2622 .slave = &dra7xx_gpio5_hwmod,
2623 .clk = "l3_iclk_div",
2624 .user = OCP_USER_MPU | OCP_USER_SDMA,
2625 };
2626
2627 /* l4_per1 -> gpio6 */
2628 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2629 .master = &dra7xx_l4_per1_hwmod,
2630 .slave = &dra7xx_gpio6_hwmod,
2631 .clk = "l3_iclk_div",
2632 .user = OCP_USER_MPU | OCP_USER_SDMA,
2633 };
2634
2635 /* l4_per1 -> gpio7 */
2636 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2637 .master = &dra7xx_l4_per1_hwmod,
2638 .slave = &dra7xx_gpio7_hwmod,
2639 .clk = "l3_iclk_div",
2640 .user = OCP_USER_MPU | OCP_USER_SDMA,
2641 };
2642
2643 /* l4_per1 -> gpio8 */
2644 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2645 .master = &dra7xx_l4_per1_hwmod,
2646 .slave = &dra7xx_gpio8_hwmod,
2647 .clk = "l3_iclk_div",
2648 .user = OCP_USER_MPU | OCP_USER_SDMA,
2649 };
2650
2651 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2652 {
2653 .pa_start = 0x50000000,
2654 .pa_end = 0x500003ff,
2655 .flags = ADDR_TYPE_RT
2656 },
2657 { }
2658 };
2659
2660 /* l3_main_1 -> gpmc */
2661 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2662 .master = &dra7xx_l3_main_1_hwmod,
2663 .slave = &dra7xx_gpmc_hwmod,
2664 .clk = "l3_iclk_div",
2665 .addr = dra7xx_gpmc_addrs,
2666 .user = OCP_USER_MPU | OCP_USER_SDMA,
2667 };
2668
2669 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2670 {
2671 .pa_start = 0x480b2000,
2672 .pa_end = 0x480b201f,
2673 .flags = ADDR_TYPE_RT
2674 },
2675 { }
2676 };
2677
2678 /* l4_per1 -> hdq1w */
2679 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2680 .master = &dra7xx_l4_per1_hwmod,
2681 .slave = &dra7xx_hdq1w_hwmod,
2682 .clk = "l3_iclk_div",
2683 .addr = dra7xx_hdq1w_addrs,
2684 .user = OCP_USER_MPU | OCP_USER_SDMA,
2685 };
2686
2687 /* l4_per1 -> i2c1 */
2688 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2689 .master = &dra7xx_l4_per1_hwmod,
2690 .slave = &dra7xx_i2c1_hwmod,
2691 .clk = "l3_iclk_div",
2692 .user = OCP_USER_MPU | OCP_USER_SDMA,
2693 };
2694
2695 /* l4_per1 -> i2c2 */
2696 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2697 .master = &dra7xx_l4_per1_hwmod,
2698 .slave = &dra7xx_i2c2_hwmod,
2699 .clk = "l3_iclk_div",
2700 .user = OCP_USER_MPU | OCP_USER_SDMA,
2701 };
2702
2703 /* l4_per1 -> i2c3 */
2704 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2705 .master = &dra7xx_l4_per1_hwmod,
2706 .slave = &dra7xx_i2c3_hwmod,
2707 .clk = "l3_iclk_div",
2708 .user = OCP_USER_MPU | OCP_USER_SDMA,
2709 };
2710
2711 /* l4_per1 -> i2c4 */
2712 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2713 .master = &dra7xx_l4_per1_hwmod,
2714 .slave = &dra7xx_i2c4_hwmod,
2715 .clk = "l3_iclk_div",
2716 .user = OCP_USER_MPU | OCP_USER_SDMA,
2717 };
2718
2719 /* l4_per1 -> i2c5 */
2720 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2721 .master = &dra7xx_l4_per1_hwmod,
2722 .slave = &dra7xx_i2c5_hwmod,
2723 .clk = "l3_iclk_div",
2724 .user = OCP_USER_MPU | OCP_USER_SDMA,
2725 };
2726
2727 /* l4_cfg -> mailbox1 */
2728 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2729 .master = &dra7xx_l4_cfg_hwmod,
2730 .slave = &dra7xx_mailbox1_hwmod,
2731 .clk = "l3_iclk_div",
2732 .user = OCP_USER_MPU | OCP_USER_SDMA,
2733 };
2734
2735 /* l4_per3 -> mailbox2 */
2736 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2737 .master = &dra7xx_l4_per3_hwmod,
2738 .slave = &dra7xx_mailbox2_hwmod,
2739 .clk = "l3_iclk_div",
2740 .user = OCP_USER_MPU | OCP_USER_SDMA,
2741 };
2742
2743 /* l4_per3 -> mailbox3 */
2744 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2745 .master = &dra7xx_l4_per3_hwmod,
2746 .slave = &dra7xx_mailbox3_hwmod,
2747 .clk = "l3_iclk_div",
2748 .user = OCP_USER_MPU | OCP_USER_SDMA,
2749 };
2750
2751 /* l4_per3 -> mailbox4 */
2752 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2753 .master = &dra7xx_l4_per3_hwmod,
2754 .slave = &dra7xx_mailbox4_hwmod,
2755 .clk = "l3_iclk_div",
2756 .user = OCP_USER_MPU | OCP_USER_SDMA,
2757 };
2758
2759 /* l4_per3 -> mailbox5 */
2760 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2761 .master = &dra7xx_l4_per3_hwmod,
2762 .slave = &dra7xx_mailbox5_hwmod,
2763 .clk = "l3_iclk_div",
2764 .user = OCP_USER_MPU | OCP_USER_SDMA,
2765 };
2766
2767 /* l4_per3 -> mailbox6 */
2768 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2769 .master = &dra7xx_l4_per3_hwmod,
2770 .slave = &dra7xx_mailbox6_hwmod,
2771 .clk = "l3_iclk_div",
2772 .user = OCP_USER_MPU | OCP_USER_SDMA,
2773 };
2774
2775 /* l4_per3 -> mailbox7 */
2776 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2777 .master = &dra7xx_l4_per3_hwmod,
2778 .slave = &dra7xx_mailbox7_hwmod,
2779 .clk = "l3_iclk_div",
2780 .user = OCP_USER_MPU | OCP_USER_SDMA,
2781 };
2782
2783 /* l4_per3 -> mailbox8 */
2784 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
2785 .master = &dra7xx_l4_per3_hwmod,
2786 .slave = &dra7xx_mailbox8_hwmod,
2787 .clk = "l3_iclk_div",
2788 .user = OCP_USER_MPU | OCP_USER_SDMA,
2789 };
2790
2791 /* l4_per3 -> mailbox9 */
2792 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
2793 .master = &dra7xx_l4_per3_hwmod,
2794 .slave = &dra7xx_mailbox9_hwmod,
2795 .clk = "l3_iclk_div",
2796 .user = OCP_USER_MPU | OCP_USER_SDMA,
2797 };
2798
2799 /* l4_per3 -> mailbox10 */
2800 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
2801 .master = &dra7xx_l4_per3_hwmod,
2802 .slave = &dra7xx_mailbox10_hwmod,
2803 .clk = "l3_iclk_div",
2804 .user = OCP_USER_MPU | OCP_USER_SDMA,
2805 };
2806
2807 /* l4_per3 -> mailbox11 */
2808 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
2809 .master = &dra7xx_l4_per3_hwmod,
2810 .slave = &dra7xx_mailbox11_hwmod,
2811 .clk = "l3_iclk_div",
2812 .user = OCP_USER_MPU | OCP_USER_SDMA,
2813 };
2814
2815 /* l4_per3 -> mailbox12 */
2816 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
2817 .master = &dra7xx_l4_per3_hwmod,
2818 .slave = &dra7xx_mailbox12_hwmod,
2819 .clk = "l3_iclk_div",
2820 .user = OCP_USER_MPU | OCP_USER_SDMA,
2821 };
2822
2823 /* l4_per3 -> mailbox13 */
2824 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
2825 .master = &dra7xx_l4_per3_hwmod,
2826 .slave = &dra7xx_mailbox13_hwmod,
2827 .clk = "l3_iclk_div",
2828 .user = OCP_USER_MPU | OCP_USER_SDMA,
2829 };
2830
2831 /* l4_per1 -> mcspi1 */
2832 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2833 .master = &dra7xx_l4_per1_hwmod,
2834 .slave = &dra7xx_mcspi1_hwmod,
2835 .clk = "l3_iclk_div",
2836 .user = OCP_USER_MPU | OCP_USER_SDMA,
2837 };
2838
2839 /* l4_per1 -> mcspi2 */
2840 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2841 .master = &dra7xx_l4_per1_hwmod,
2842 .slave = &dra7xx_mcspi2_hwmod,
2843 .clk = "l3_iclk_div",
2844 .user = OCP_USER_MPU | OCP_USER_SDMA,
2845 };
2846
2847 /* l4_per1 -> mcspi3 */
2848 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2849 .master = &dra7xx_l4_per1_hwmod,
2850 .slave = &dra7xx_mcspi3_hwmod,
2851 .clk = "l3_iclk_div",
2852 .user = OCP_USER_MPU | OCP_USER_SDMA,
2853 };
2854
2855 /* l4_per1 -> mcspi4 */
2856 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2857 .master = &dra7xx_l4_per1_hwmod,
2858 .slave = &dra7xx_mcspi4_hwmod,
2859 .clk = "l3_iclk_div",
2860 .user = OCP_USER_MPU | OCP_USER_SDMA,
2861 };
2862
2863 /* l4_per1 -> mmc1 */
2864 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2865 .master = &dra7xx_l4_per1_hwmod,
2866 .slave = &dra7xx_mmc1_hwmod,
2867 .clk = "l3_iclk_div",
2868 .user = OCP_USER_MPU | OCP_USER_SDMA,
2869 };
2870
2871 /* l4_per1 -> mmc2 */
2872 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2873 .master = &dra7xx_l4_per1_hwmod,
2874 .slave = &dra7xx_mmc2_hwmod,
2875 .clk = "l3_iclk_div",
2876 .user = OCP_USER_MPU | OCP_USER_SDMA,
2877 };
2878
2879 /* l4_per1 -> mmc3 */
2880 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2881 .master = &dra7xx_l4_per1_hwmod,
2882 .slave = &dra7xx_mmc3_hwmod,
2883 .clk = "l3_iclk_div",
2884 .user = OCP_USER_MPU | OCP_USER_SDMA,
2885 };
2886
2887 /* l4_per1 -> mmc4 */
2888 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2889 .master = &dra7xx_l4_per1_hwmod,
2890 .slave = &dra7xx_mmc4_hwmod,
2891 .clk = "l3_iclk_div",
2892 .user = OCP_USER_MPU | OCP_USER_SDMA,
2893 };
2894
2895 /* l4_cfg -> mpu */
2896 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2897 .master = &dra7xx_l4_cfg_hwmod,
2898 .slave = &dra7xx_mpu_hwmod,
2899 .clk = "l3_iclk_div",
2900 .user = OCP_USER_MPU | OCP_USER_SDMA,
2901 };
2902
2903 /* l4_cfg -> ocp2scp1 */
2904 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2905 .master = &dra7xx_l4_cfg_hwmod,
2906 .slave = &dra7xx_ocp2scp1_hwmod,
2907 .clk = "l4_root_clk_div",
2908 .user = OCP_USER_MPU | OCP_USER_SDMA,
2909 };
2910
2911 /* l4_cfg -> ocp2scp3 */
2912 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2913 .master = &dra7xx_l4_cfg_hwmod,
2914 .slave = &dra7xx_ocp2scp3_hwmod,
2915 .clk = "l4_root_clk_div",
2916 .user = OCP_USER_MPU | OCP_USER_SDMA,
2917 };
2918
2919 /* l3_main_1 -> pciess1 */
2920 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
2921 .master = &dra7xx_l3_main_1_hwmod,
2922 .slave = &dra7xx_pciess1_hwmod,
2923 .clk = "l3_iclk_div",
2924 .user = OCP_USER_MPU | OCP_USER_SDMA,
2925 };
2926
2927 /* l4_cfg -> pciess1 */
2928 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
2929 .master = &dra7xx_l4_cfg_hwmod,
2930 .slave = &dra7xx_pciess1_hwmod,
2931 .clk = "l4_root_clk_div",
2932 .user = OCP_USER_MPU | OCP_USER_SDMA,
2933 };
2934
2935 /* l3_main_1 -> pciess2 */
2936 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
2937 .master = &dra7xx_l3_main_1_hwmod,
2938 .slave = &dra7xx_pciess2_hwmod,
2939 .clk = "l3_iclk_div",
2940 .user = OCP_USER_MPU | OCP_USER_SDMA,
2941 };
2942
2943 /* l4_cfg -> pciess2 */
2944 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
2945 .master = &dra7xx_l4_cfg_hwmod,
2946 .slave = &dra7xx_pciess2_hwmod,
2947 .clk = "l4_root_clk_div",
2948 .user = OCP_USER_MPU | OCP_USER_SDMA,
2949 };
2950
2951 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2952 {
2953 .pa_start = 0x4b300000,
2954 .pa_end = 0x4b30007f,
2955 .flags = ADDR_TYPE_RT
2956 },
2957 { }
2958 };
2959
2960 /* l3_main_1 -> qspi */
2961 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2962 .master = &dra7xx_l3_main_1_hwmod,
2963 .slave = &dra7xx_qspi_hwmod,
2964 .clk = "l3_iclk_div",
2965 .addr = dra7xx_qspi_addrs,
2966 .user = OCP_USER_MPU | OCP_USER_SDMA,
2967 };
2968
2969 /* l4_per3 -> rtcss */
2970 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
2971 .master = &dra7xx_l4_per3_hwmod,
2972 .slave = &dra7xx_rtcss_hwmod,
2973 .clk = "l4_root_clk_div",
2974 .user = OCP_USER_MPU | OCP_USER_SDMA,
2975 };
2976
2977 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2978 {
2979 .name = "sysc",
2980 .pa_start = 0x4a141100,
2981 .pa_end = 0x4a141107,
2982 .flags = ADDR_TYPE_RT
2983 },
2984 { }
2985 };
2986
2987 /* l4_cfg -> sata */
2988 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2989 .master = &dra7xx_l4_cfg_hwmod,
2990 .slave = &dra7xx_sata_hwmod,
2991 .clk = "l3_iclk_div",
2992 .addr = dra7xx_sata_addrs,
2993 .user = OCP_USER_MPU | OCP_USER_SDMA,
2994 };
2995
2996 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
2997 {
2998 .pa_start = 0x4a0dd000,
2999 .pa_end = 0x4a0dd07f,
3000 .flags = ADDR_TYPE_RT
3001 },
3002 { }
3003 };
3004
3005 /* l4_cfg -> smartreflex_core */
3006 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3007 .master = &dra7xx_l4_cfg_hwmod,
3008 .slave = &dra7xx_smartreflex_core_hwmod,
3009 .clk = "l4_root_clk_div",
3010 .addr = dra7xx_smartreflex_core_addrs,
3011 .user = OCP_USER_MPU | OCP_USER_SDMA,
3012 };
3013
3014 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
3015 {
3016 .pa_start = 0x4a0d9000,
3017 .pa_end = 0x4a0d907f,
3018 .flags = ADDR_TYPE_RT
3019 },
3020 { }
3021 };
3022
3023 /* l4_cfg -> smartreflex_mpu */
3024 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3025 .master = &dra7xx_l4_cfg_hwmod,
3026 .slave = &dra7xx_smartreflex_mpu_hwmod,
3027 .clk = "l4_root_clk_div",
3028 .addr = dra7xx_smartreflex_mpu_addrs,
3029 .user = OCP_USER_MPU | OCP_USER_SDMA,
3030 };
3031
3032 static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
3033 {
3034 .pa_start = 0x4a0f6000,
3035 .pa_end = 0x4a0f6fff,
3036 .flags = ADDR_TYPE_RT
3037 },
3038 { }
3039 };
3040
3041 /* l4_cfg -> spinlock */
3042 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3043 .master = &dra7xx_l4_cfg_hwmod,
3044 .slave = &dra7xx_spinlock_hwmod,
3045 .clk = "l3_iclk_div",
3046 .addr = dra7xx_spinlock_addrs,
3047 .user = OCP_USER_MPU | OCP_USER_SDMA,
3048 };
3049
3050 /* l4_wkup -> timer1 */
3051 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3052 .master = &dra7xx_l4_wkup_hwmod,
3053 .slave = &dra7xx_timer1_hwmod,
3054 .clk = "wkupaon_iclk_mux",
3055 .user = OCP_USER_MPU | OCP_USER_SDMA,
3056 };
3057
3058 /* l4_per1 -> timer2 */
3059 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3060 .master = &dra7xx_l4_per1_hwmod,
3061 .slave = &dra7xx_timer2_hwmod,
3062 .clk = "l3_iclk_div",
3063 .user = OCP_USER_MPU | OCP_USER_SDMA,
3064 };
3065
3066 /* l4_per1 -> timer3 */
3067 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3068 .master = &dra7xx_l4_per1_hwmod,
3069 .slave = &dra7xx_timer3_hwmod,
3070 .clk = "l3_iclk_div",
3071 .user = OCP_USER_MPU | OCP_USER_SDMA,
3072 };
3073
3074 /* l4_per1 -> timer4 */
3075 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3076 .master = &dra7xx_l4_per1_hwmod,
3077 .slave = &dra7xx_timer4_hwmod,
3078 .clk = "l3_iclk_div",
3079 .user = OCP_USER_MPU | OCP_USER_SDMA,
3080 };
3081
3082 /* l4_per3 -> timer5 */
3083 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3084 .master = &dra7xx_l4_per3_hwmod,
3085 .slave = &dra7xx_timer5_hwmod,
3086 .clk = "l3_iclk_div",
3087 .user = OCP_USER_MPU | OCP_USER_SDMA,
3088 };
3089
3090 /* l4_per3 -> timer6 */
3091 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3092 .master = &dra7xx_l4_per3_hwmod,
3093 .slave = &dra7xx_timer6_hwmod,
3094 .clk = "l3_iclk_div",
3095 .user = OCP_USER_MPU | OCP_USER_SDMA,
3096 };
3097
3098 /* l4_per3 -> timer7 */
3099 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3100 .master = &dra7xx_l4_per3_hwmod,
3101 .slave = &dra7xx_timer7_hwmod,
3102 .clk = "l3_iclk_div",
3103 .user = OCP_USER_MPU | OCP_USER_SDMA,
3104 };
3105
3106 /* l4_per3 -> timer8 */
3107 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3108 .master = &dra7xx_l4_per3_hwmod,
3109 .slave = &dra7xx_timer8_hwmod,
3110 .clk = "l3_iclk_div",
3111 .user = OCP_USER_MPU | OCP_USER_SDMA,
3112 };
3113
3114 /* l4_per1 -> timer9 */
3115 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3116 .master = &dra7xx_l4_per1_hwmod,
3117 .slave = &dra7xx_timer9_hwmod,
3118 .clk = "l3_iclk_div",
3119 .user = OCP_USER_MPU | OCP_USER_SDMA,
3120 };
3121
3122 /* l4_per1 -> timer10 */
3123 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3124 .master = &dra7xx_l4_per1_hwmod,
3125 .slave = &dra7xx_timer10_hwmod,
3126 .clk = "l3_iclk_div",
3127 .user = OCP_USER_MPU | OCP_USER_SDMA,
3128 };
3129
3130 /* l4_per1 -> timer11 */
3131 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3132 .master = &dra7xx_l4_per1_hwmod,
3133 .slave = &dra7xx_timer11_hwmod,
3134 .clk = "l3_iclk_div",
3135 .user = OCP_USER_MPU | OCP_USER_SDMA,
3136 };
3137
3138 /* l4_per3 -> timer13 */
3139 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3140 .master = &dra7xx_l4_per3_hwmod,
3141 .slave = &dra7xx_timer13_hwmod,
3142 .clk = "l3_iclk_div",
3143 .user = OCP_USER_MPU | OCP_USER_SDMA,
3144 };
3145
3146 /* l4_per3 -> timer14 */
3147 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3148 .master = &dra7xx_l4_per3_hwmod,
3149 .slave = &dra7xx_timer14_hwmod,
3150 .clk = "l3_iclk_div",
3151 .user = OCP_USER_MPU | OCP_USER_SDMA,
3152 };
3153
3154 /* l4_per3 -> timer15 */
3155 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3156 .master = &dra7xx_l4_per3_hwmod,
3157 .slave = &dra7xx_timer15_hwmod,
3158 .clk = "l3_iclk_div",
3159 .user = OCP_USER_MPU | OCP_USER_SDMA,
3160 };
3161
3162 /* l4_per3 -> timer16 */
3163 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3164 .master = &dra7xx_l4_per3_hwmod,
3165 .slave = &dra7xx_timer16_hwmod,
3166 .clk = "l3_iclk_div",
3167 .user = OCP_USER_MPU | OCP_USER_SDMA,
3168 };
3169
3170 /* l4_per1 -> uart1 */
3171 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3172 .master = &dra7xx_l4_per1_hwmod,
3173 .slave = &dra7xx_uart1_hwmod,
3174 .clk = "l3_iclk_div",
3175 .user = OCP_USER_MPU | OCP_USER_SDMA,
3176 };
3177
3178 /* l4_per1 -> uart2 */
3179 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3180 .master = &dra7xx_l4_per1_hwmod,
3181 .slave = &dra7xx_uart2_hwmod,
3182 .clk = "l3_iclk_div",
3183 .user = OCP_USER_MPU | OCP_USER_SDMA,
3184 };
3185
3186 /* l4_per1 -> uart3 */
3187 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3188 .master = &dra7xx_l4_per1_hwmod,
3189 .slave = &dra7xx_uart3_hwmod,
3190 .clk = "l3_iclk_div",
3191 .user = OCP_USER_MPU | OCP_USER_SDMA,
3192 };
3193
3194 /* l4_per1 -> uart4 */
3195 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3196 .master = &dra7xx_l4_per1_hwmod,
3197 .slave = &dra7xx_uart4_hwmod,
3198 .clk = "l3_iclk_div",
3199 .user = OCP_USER_MPU | OCP_USER_SDMA,
3200 };
3201
3202 /* l4_per1 -> uart5 */
3203 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3204 .master = &dra7xx_l4_per1_hwmod,
3205 .slave = &dra7xx_uart5_hwmod,
3206 .clk = "l3_iclk_div",
3207 .user = OCP_USER_MPU | OCP_USER_SDMA,
3208 };
3209
3210 /* l4_per1 -> uart6 */
3211 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3212 .master = &dra7xx_l4_per1_hwmod,
3213 .slave = &dra7xx_uart6_hwmod,
3214 .clk = "l3_iclk_div",
3215 .user = OCP_USER_MPU | OCP_USER_SDMA,
3216 };
3217
3218 /* l4_per2 -> uart7 */
3219 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3220 .master = &dra7xx_l4_per2_hwmod,
3221 .slave = &dra7xx_uart7_hwmod,
3222 .clk = "l3_iclk_div",
3223 .user = OCP_USER_MPU | OCP_USER_SDMA,
3224 };
3225
3226 /* l4_per2 -> uart8 */
3227 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3228 .master = &dra7xx_l4_per2_hwmod,
3229 .slave = &dra7xx_uart8_hwmod,
3230 .clk = "l3_iclk_div",
3231 .user = OCP_USER_MPU | OCP_USER_SDMA,
3232 };
3233
3234 /* l4_per2 -> uart9 */
3235 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3236 .master = &dra7xx_l4_per2_hwmod,
3237 .slave = &dra7xx_uart9_hwmod,
3238 .clk = "l3_iclk_div",
3239 .user = OCP_USER_MPU | OCP_USER_SDMA,
3240 };
3241
3242 /* l4_wkup -> uart10 */
3243 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3244 .master = &dra7xx_l4_wkup_hwmod,
3245 .slave = &dra7xx_uart10_hwmod,
3246 .clk = "wkupaon_iclk_mux",
3247 .user = OCP_USER_MPU | OCP_USER_SDMA,
3248 };
3249
3250 /* l4_per3 -> usb_otg_ss1 */
3251 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3252 .master = &dra7xx_l4_per3_hwmod,
3253 .slave = &dra7xx_usb_otg_ss1_hwmod,
3254 .clk = "dpll_core_h13x2_ck",
3255 .user = OCP_USER_MPU | OCP_USER_SDMA,
3256 };
3257
3258 /* l4_per3 -> usb_otg_ss2 */
3259 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3260 .master = &dra7xx_l4_per3_hwmod,
3261 .slave = &dra7xx_usb_otg_ss2_hwmod,
3262 .clk = "dpll_core_h13x2_ck",
3263 .user = OCP_USER_MPU | OCP_USER_SDMA,
3264 };
3265
3266 /* l4_per3 -> usb_otg_ss3 */
3267 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3268 .master = &dra7xx_l4_per3_hwmod,
3269 .slave = &dra7xx_usb_otg_ss3_hwmod,
3270 .clk = "dpll_core_h13x2_ck",
3271 .user = OCP_USER_MPU | OCP_USER_SDMA,
3272 };
3273
3274 /* l4_per3 -> usb_otg_ss4 */
3275 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3276 .master = &dra7xx_l4_per3_hwmod,
3277 .slave = &dra7xx_usb_otg_ss4_hwmod,
3278 .clk = "dpll_core_h13x2_ck",
3279 .user = OCP_USER_MPU | OCP_USER_SDMA,
3280 };
3281
3282 /* l3_main_1 -> vcp1 */
3283 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3284 .master = &dra7xx_l3_main_1_hwmod,
3285 .slave = &dra7xx_vcp1_hwmod,
3286 .clk = "l3_iclk_div",
3287 .user = OCP_USER_MPU | OCP_USER_SDMA,
3288 };
3289
3290 /* l4_per2 -> vcp1 */
3291 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3292 .master = &dra7xx_l4_per2_hwmod,
3293 .slave = &dra7xx_vcp1_hwmod,
3294 .clk = "l3_iclk_div",
3295 .user = OCP_USER_MPU | OCP_USER_SDMA,
3296 };
3297
3298 /* l3_main_1 -> vcp2 */
3299 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3300 .master = &dra7xx_l3_main_1_hwmod,
3301 .slave = &dra7xx_vcp2_hwmod,
3302 .clk = "l3_iclk_div",
3303 .user = OCP_USER_MPU | OCP_USER_SDMA,
3304 };
3305
3306 /* l4_per2 -> vcp2 */
3307 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3308 .master = &dra7xx_l4_per2_hwmod,
3309 .slave = &dra7xx_vcp2_hwmod,
3310 .clk = "l3_iclk_div",
3311 .user = OCP_USER_MPU | OCP_USER_SDMA,
3312 };
3313
3314 /* l4_wkup -> wd_timer2 */
3315 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3316 .master = &dra7xx_l4_wkup_hwmod,
3317 .slave = &dra7xx_wd_timer2_hwmod,
3318 .clk = "wkupaon_iclk_mux",
3319 .user = OCP_USER_MPU | OCP_USER_SDMA,
3320 };
3321
3322 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3323 &dra7xx_l3_main_1__dmm,
3324 &dra7xx_l3_main_2__l3_instr,
3325 &dra7xx_l4_cfg__l3_main_1,
3326 &dra7xx_mpu__l3_main_1,
3327 &dra7xx_l3_main_1__l3_main_2,
3328 &dra7xx_l4_cfg__l3_main_2,
3329 &dra7xx_l3_main_1__l4_cfg,
3330 &dra7xx_l3_main_1__l4_per1,
3331 &dra7xx_l3_main_1__l4_per2,
3332 &dra7xx_l3_main_1__l4_per3,
3333 &dra7xx_l3_main_1__l4_wkup,
3334 &dra7xx_l4_per2__atl,
3335 &dra7xx_l3_main_1__bb2d,
3336 &dra7xx_l4_wkup__counter_32k,
3337 &dra7xx_l4_wkup__ctrl_module_wkup,
3338 &dra7xx_l4_wkup__dcan1,
3339 &dra7xx_l4_per2__dcan2,
3340 &dra7xx_l4_per2__cpgmac0,
3341 &dra7xx_gmac__mdio,
3342 &dra7xx_l4_cfg__dma_system,
3343 &dra7xx_l3_main_1__dss,
3344 &dra7xx_l3_main_1__dispc,
3345 &dra7xx_l3_main_1__hdmi,
3346 &dra7xx_l4_per1__elm,
3347 &dra7xx_l4_wkup__gpio1,
3348 &dra7xx_l4_per1__gpio2,
3349 &dra7xx_l4_per1__gpio3,
3350 &dra7xx_l4_per1__gpio4,
3351 &dra7xx_l4_per1__gpio5,
3352 &dra7xx_l4_per1__gpio6,
3353 &dra7xx_l4_per1__gpio7,
3354 &dra7xx_l4_per1__gpio8,
3355 &dra7xx_l3_main_1__gpmc,
3356 &dra7xx_l4_per1__hdq1w,
3357 &dra7xx_l4_per1__i2c1,
3358 &dra7xx_l4_per1__i2c2,
3359 &dra7xx_l4_per1__i2c3,
3360 &dra7xx_l4_per1__i2c4,
3361 &dra7xx_l4_per1__i2c5,
3362 &dra7xx_l4_cfg__mailbox1,
3363 &dra7xx_l4_per3__mailbox2,
3364 &dra7xx_l4_per3__mailbox3,
3365 &dra7xx_l4_per3__mailbox4,
3366 &dra7xx_l4_per3__mailbox5,
3367 &dra7xx_l4_per3__mailbox6,
3368 &dra7xx_l4_per3__mailbox7,
3369 &dra7xx_l4_per3__mailbox8,
3370 &dra7xx_l4_per3__mailbox9,
3371 &dra7xx_l4_per3__mailbox10,
3372 &dra7xx_l4_per3__mailbox11,
3373 &dra7xx_l4_per3__mailbox12,
3374 &dra7xx_l4_per3__mailbox13,
3375 &dra7xx_l4_per1__mcspi1,
3376 &dra7xx_l4_per1__mcspi2,
3377 &dra7xx_l4_per1__mcspi3,
3378 &dra7xx_l4_per1__mcspi4,
3379 &dra7xx_l4_per1__mmc1,
3380 &dra7xx_l4_per1__mmc2,
3381 &dra7xx_l4_per1__mmc3,
3382 &dra7xx_l4_per1__mmc4,
3383 &dra7xx_l4_cfg__mpu,
3384 &dra7xx_l4_cfg__ocp2scp1,
3385 &dra7xx_l4_cfg__ocp2scp3,
3386 &dra7xx_l3_main_1__pciess1,
3387 &dra7xx_l4_cfg__pciess1,
3388 &dra7xx_l3_main_1__pciess2,
3389 &dra7xx_l4_cfg__pciess2,
3390 &dra7xx_l3_main_1__qspi,
3391 &dra7xx_l4_per3__rtcss,
3392 &dra7xx_l4_cfg__sata,
3393 &dra7xx_l4_cfg__smartreflex_core,
3394 &dra7xx_l4_cfg__smartreflex_mpu,
3395 &dra7xx_l4_cfg__spinlock,
3396 &dra7xx_l4_wkup__timer1,
3397 &dra7xx_l4_per1__timer2,
3398 &dra7xx_l4_per1__timer3,
3399 &dra7xx_l4_per1__timer4,
3400 &dra7xx_l4_per3__timer5,
3401 &dra7xx_l4_per3__timer6,
3402 &dra7xx_l4_per3__timer7,
3403 &dra7xx_l4_per3__timer8,
3404 &dra7xx_l4_per1__timer9,
3405 &dra7xx_l4_per1__timer10,
3406 &dra7xx_l4_per1__timer11,
3407 &dra7xx_l4_per3__timer13,
3408 &dra7xx_l4_per3__timer14,
3409 &dra7xx_l4_per3__timer15,
3410 &dra7xx_l4_per3__timer16,
3411 &dra7xx_l4_per1__uart1,
3412 &dra7xx_l4_per1__uart2,
3413 &dra7xx_l4_per1__uart3,
3414 &dra7xx_l4_per1__uart4,
3415 &dra7xx_l4_per1__uart5,
3416 &dra7xx_l4_per1__uart6,
3417 &dra7xx_l4_per2__uart7,
3418 &dra7xx_l4_per2__uart8,
3419 &dra7xx_l4_per2__uart9,
3420 &dra7xx_l4_wkup__uart10,
3421 &dra7xx_l4_per3__usb_otg_ss1,
3422 &dra7xx_l4_per3__usb_otg_ss2,
3423 &dra7xx_l4_per3__usb_otg_ss3,
3424 &dra7xx_l3_main_1__vcp1,
3425 &dra7xx_l4_per2__vcp1,
3426 &dra7xx_l3_main_1__vcp2,
3427 &dra7xx_l4_per2__vcp2,
3428 &dra7xx_l4_wkup__wd_timer2,
3429 NULL,
3430 };
3431
3432 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3433 &dra7xx_l4_per3__usb_otg_ss4,
3434 NULL,
3435 };
3436
3437 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3438 NULL,
3439 };
3440
3441 int __init dra7xx_hwmod_init(void)
3442 {
3443 int ret;
3444
3445 omap_hwmod_init();
3446 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3447
3448 if (!ret && soc_is_dra74x())
3449 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3450 else if (!ret && soc_is_dra72x())
3451 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3452
3453 return ret;
3454 }
CRIS linux kernel tree