arch/microblaze/kernel/intc.c

   1 /*
   2  * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
   3  * Copyright (C) 2012-2013 Xilinx, Inc.
   4  * Copyright (C) 2007-2009 PetaLogix
   5  * Copyright (C) 2006 Atmark Techno, Inc.
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License. See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11
  12 #include <linux/irqdomain.h>
  13 #include <linux/irq.h>
  14 #include <linux/irqchip.h>
  15 #include <linux/of_address.h>
  16 #include <linux/io.h>
  17 #include <linux/bug.h>
  18
  19 static void __iomem *intc_baseaddr;
  20
  21 /* No one else should require these constants, so define them locally here. */
  22 #define ISR 0x00                        /* Interrupt Status Register */
  23 #define IPR 0x04                        /* Interrupt Pending Register */
  24 #define IER 0x08                        /* Interrupt Enable Register */
  25 #define IAR 0x0c                        /* Interrupt Acknowledge Register */
  26 #define SIE 0x10                        /* Set Interrupt Enable bits */
  27 #define CIE 0x14                        /* Clear Interrupt Enable bits */
  28 #define IVR 0x18                        /* Interrupt Vector Register */
  29 #define MER 0x1c                        /* Master Enable Register */
  30
  31 #define MER_ME (1<<0)
  32 #define MER_HIE (1<<1)
  33
  34 static unsigned int (*read_fn)(void __iomem *);
  35 static void (*write_fn)(u32, void __iomem *);
  36
  37 static void intc_write32(u32 val, void __iomem *addr)
  38 {
  39         iowrite32(val, addr);
  40 }
  41
  42 static unsigned int intc_read32(void __iomem *addr)
  43 {
  44         return ioread32(addr);
  45 }
  46
  47 static void intc_write32_be(u32 val, void __iomem *addr)
  48 {
  49         iowrite32be(val, addr);
  50 }
  51
  52 static unsigned int intc_read32_be(void __iomem *addr)
  53 {
  54         return ioread32be(addr);
  55 }
  56
  57 static void intc_enable_or_unmask(struct irq_data *d)
  58 {
  59         unsigned long mask = 1 << d->hwirq;
  60
  61         pr_debug("enable_or_unmask: %ld\n", d->hwirq);
  62
  63         /* ack level irqs because they can't be acked during
  64          * ack function since the handle_level_irq function
  65          * acks the irq before calling the interrupt handler
  66          */
  67         if (irqd_is_level_type(d))
  68                 write_fn(mask, intc_baseaddr + IAR);
  69
  70         write_fn(mask, intc_baseaddr + SIE);
  71 }
  72
  73 static void intc_disable_or_mask(struct irq_data *d)
  74 {
  75         pr_debug("disable: %ld\n", d->hwirq);
  76         write_fn(1 << d->hwirq, intc_baseaddr + CIE);
  77 }
  78
  79 static void intc_ack(struct irq_data *d)
  80 {
  81         pr_debug("ack: %ld\n", d->hwirq);
  82         write_fn(1 << d->hwirq, intc_baseaddr + IAR);
  83 }
  84
  85 static void intc_mask_ack(struct irq_data *d)
  86 {
  87         unsigned long mask = 1 << d->hwirq;
  88
  89         pr_debug("disable_and_ack: %ld\n", d->hwirq);
  90         write_fn(mask, intc_baseaddr + CIE);
  91         write_fn(mask, intc_baseaddr + IAR);
  92 }
  93
  94 static struct irq_chip intc_dev = {
  95         .name = "Xilinx INTC",
  96         .irq_unmask = intc_enable_or_unmask,
  97         .irq_mask = intc_disable_or_mask,
  98         .irq_ack = intc_ack,
  99         .irq_mask_ack = intc_mask_ack,
 100 };
 101
 102 static struct irq_domain *root_domain;
 103
 104 unsigned int get_irq(void)
 105 {
 106         unsigned int hwirq, irq = -1;
 107
 108         hwirq = read_fn(intc_baseaddr + IVR);
 109         if (hwirq != -1U)
 110                 irq = irq_find_mapping(root_domain, hwirq);
 111
 112         pr_debug("get_irq: hwirq=%d, irq=%d\n", hwirq, irq);
 113
 114         return irq;
 115 }
 116
 117 static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 118 {
 119         u32 intr_mask = (u32)d->host_data;
 120
 121         if (intr_mask & (1 << hw)) {
 122                 irq_set_chip_and_handler_name(irq, &intc_dev,
 123                                                 handle_edge_irq, "edge");
 124                 irq_clear_status_flags(irq, IRQ_LEVEL);
 125         } else {
 126                 irq_set_chip_and_handler_name(irq, &intc_dev,
 127                                                 handle_level_irq, "level");
 128                 irq_set_status_flags(irq, IRQ_LEVEL);
 129         }
 130         return 0;
 131 }
 132
 133 static const struct irq_domain_ops xintc_irq_domain_ops = {
 134         .xlate = irq_domain_xlate_onetwocell,
 135         .map = xintc_map,
 136 };
 137
 138 static int __init xilinx_intc_of_init(struct device_node *intc,
 139                                              struct device_node *parent)
 140 {
 141         u32 nr_irq, intr_mask;
 142         int ret;
 143
 144         intc_baseaddr = of_iomap(intc, 0);
 145         BUG_ON(!intc_baseaddr);
 146
 147         ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &nr_irq);
 148         if (ret < 0) {
 149                 pr_err("%s: unable to read xlnx,num-intr-inputs\n", __func__);
 150                 return ret;
 151         }
 152
 153         ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &intr_mask);
 154         if (ret < 0) {
 155                 pr_err("%s: unable to read xlnx,kind-of-intr\n", __func__);
 156                 return ret;
 157         }
 158
 159         if (intr_mask >> nr_irq)
 160                 pr_warn("%s: mismatch in kind-of-intr param\n", __func__);
 161
 162         pr_info("%s: num_irq=%d, edge=0x%x\n",
 163                 intc->full_name, nr_irq, intr_mask);
 164
 165         write_fn = intc_write32;
 166         read_fn = intc_read32;
 167
 168         /*
 169          * Disable all external interrupts until they are
 170          * explicity requested.
 171          */
 172         write_fn(0, intc_baseaddr + IER);
 173
 174         /* Acknowledge any pending interrupts just in case. */
 175         write_fn(0xffffffff, intc_baseaddr + IAR);
 176
 177         /* Turn on the Master Enable. */
 178         write_fn(MER_HIE | MER_ME, intc_baseaddr + MER);
 179         if (!(read_fn(intc_baseaddr + MER) & (MER_HIE | MER_ME))) {
 180                 write_fn = intc_write32_be;
 181                 read_fn = intc_read32_be;
 182                 write_fn(MER_HIE | MER_ME, intc_baseaddr + MER);
 183         }
 184
 185         /* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm
 186          * lazy and Michal can clean it up to something nicer when he tests
 187          * and commits this patch.  ~~gcl */
 188         root_domain = irq_domain_add_linear(intc, nr_irq, &xintc_irq_domain_ops,
 189                                                         (void *)intr_mask);
 190
 191         irq_set_default_host(root_domain);
 192
 193         return 0;
 194 }
 195
 196 IRQCHIP_DECLARE(xilinx_intc, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);