arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h

   1 #ifndef BCM63XX_DEV_ENET_H_
   2 #define BCM63XX_DEV_ENET_H_
   3
   4 #include <linux/if_ether.h>
   5 #include <linux/init.h>
   6
   7 #include <bcm63xx_regs.h>
   8
   9 /*
  10  * on board ethernet platform data
  11  */
  12 struct bcm63xx_enet_platform_data {
  13         char mac_addr[ETH_ALEN];
  14
  15         int has_phy;
  16
  17         /* if has_phy, then set use_internal_phy */
  18         int use_internal_phy;
  19
  20         /* or fill phy info to use an external one */
  21         int phy_id;
  22         int has_phy_interrupt;
  23         int phy_interrupt;
  24
  25         /* if has_phy, use autonegociated pause parameters or force
  26          * them */
  27         int pause_auto;
  28         int pause_rx;
  29         int pause_tx;
  30
  31         /* if !has_phy, set desired forced speed/duplex */
  32         int force_speed_100;
  33         int force_duplex_full;
  34
  35         /* if !has_phy, set callback to perform mii device
  36          * init/remove */
  37         int (*mii_config)(struct net_device *dev, int probe,
  38                           int (*mii_read)(struct net_device *dev,
  39                                           int phy_id, int reg),
  40                           void (*mii_write)(struct net_device *dev,
  41                                             int phy_id, int reg, int val));
  42
  43         /* DMA channel enable mask */
  44         u32 dma_chan_en_mask;
  45
  46         /* DMA channel interrupt mask */
  47         u32 dma_chan_int_mask;
  48
  49         /* DMA engine has internal SRAM */
  50         bool dma_has_sram;
  51
  52         /* DMA channel register width */
  53         unsigned int dma_chan_width;
  54
  55         /* DMA descriptor shift */
  56         unsigned int dma_desc_shift;
  57 };
  58
  59 /*
  60  * on board ethernet switch platform data
  61  */
  62 #define ENETSW_MAX_PORT 8
  63 #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
  64 #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
  65
  66 #define ENETSW_RGMII_PORT0      4
  67
  68 struct bcm63xx_enetsw_port {
  69         int             used;
  70         int             phy_id;
  71
  72         int             bypass_link;
  73         int             force_speed;
  74         int             force_duplex_full;
  75
  76         const char      *name;
  77 };
  78
  79 struct bcm63xx_enetsw_platform_data {
  80         char mac_addr[ETH_ALEN];
  81         int num_ports;
  82         struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
  83
  84         /* DMA channel enable mask */
  85         u32 dma_chan_en_mask;
  86
  87         /* DMA channel interrupt mask */
  88         u32 dma_chan_int_mask;
  89
  90         /* DMA channel register width */
  91         unsigned int dma_chan_width;
  92
  93         /* DMA engine has internal SRAM */
  94         bool dma_has_sram;
  95 };
  96
  97 int __init bcm63xx_enet_register(int unit,
  98                                  const struct bcm63xx_enet_platform_data *pd);
  99
 100 int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
 101
 102 enum bcm63xx_regs_enetdmac {
 103         ENETDMAC_CHANCFG,
 104         ENETDMAC_IR,
 105         ENETDMAC_IRMASK,
 106         ENETDMAC_MAXBURST,
 107         ENETDMAC_BUFALLOC,
 108         ENETDMAC_RSTART,
 109         ENETDMAC_FC,
 110         ENETDMAC_LEN,
 111 };
 112
 113 static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
 114 {
 115         extern const unsigned long *bcm63xx_regs_enetdmac;
 116
 117         return bcm63xx_regs_enetdmac[reg];
 118 }
 119
 120
 121 #endif /* ! BCM63XX_DEV_ENET_H_ */