arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h

   1 /*
   2  * Defines for the address space, registers and register configuration
   3  * (bit masks, access macros etc) for the PMC-Sierra line of MSP products.
   4  * This file contains addess maps for all the devices in the line of
   5  * products but only has register definitions and configuration masks for
   6  * registers which aren't definitely associated with any device.  Things
   7  * like clock settings, reset access, the ELB etc.  Individual device
   8  * drivers will reference the appropriate XXX_BASE value defined here
   9  * and have individual registers offset from that.
  10  *
  11  * Copyright (C) 2005-2007 PMC-Sierra, Inc.  All rights reserved.
  12  * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
  13  *
  14  * ########################################################################
  15  *
  16  *  This program is free software; you can distribute it and/or modify it
  17  *  under the terms of the GNU General Public License (Version 2) as
  18  *  published by the Free Software Foundation.
  19  *
  20  *  This program is distributed in the hope it will be useful, but WITHOUT
  21  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23  *  for more details.
  24  *
  25  *  You should have received a copy of the GNU General Public License along
  26  *  with this program; if not, write to the Free Software Foundation, Inc.,
  27  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  28  *
  29  * ########################################################################
  30  */
  31
  32 #include <asm/addrspace.h>
  33 #include <linux/types.h>
  34
  35 #ifndef _ASM_MSP_REGS_H
  36 #define _ASM_MSP_REGS_H
  37
  38 /*
  39  ########################################################################
  40  #  Address space and device base definitions                           #
  41  ########################################################################
  42  */
  43
  44 /*
  45  ***************************************************************************
  46  * System Logic and Peripherals (ELB, UART0, etc) device address space     *
  47  ***************************************************************************
  48  */
  49 #define MSP_SLP_BASE            0x1c000000
  50                                         /* System Logic and Peripherals */
  51 #define MSP_RST_BASE            (MSP_SLP_BASE + 0x10)
  52                                         /* System reset register base   */
  53 #define MSP_RST_SIZE            0x0C    /* System reset register space  */
  54
  55 #define MSP_WTIMER_BASE         (MSP_SLP_BASE + 0x04C)
  56                                         /* watchdog timer base          */
  57 #define MSP_ITIMER_BASE         (MSP_SLP_BASE + 0x054)
  58                                         /* internal timer base          */
  59 #define MSP_UART0_BASE          (MSP_SLP_BASE + 0x100)
  60                                         /* UART0 controller base        */
  61 #define MSP_BCPY_CTRL_BASE      (MSP_SLP_BASE + 0x120)
  62                                         /* Block Copy controller base   */
  63 #define MSP_BCPY_DESC_BASE      (MSP_SLP_BASE + 0x160)
  64                                         /* Block Copy descriptor base   */
  65
  66 /*
  67  ***************************************************************************
  68  * PCI address space                                                       *
  69  ***************************************************************************
  70  */
  71 #define MSP_PCI_BASE            0x19000000
  72
  73 /*
  74  ***************************************************************************
  75  * MSbus device address space                                              *
  76  ***************************************************************************
  77  */
  78 #define MSP_MSB_BASE            0x18000000
  79                                         /* MSbus address start          */
  80 #define MSP_PER_BASE            (MSP_MSB_BASE + 0x400000)
  81                                         /* Peripheral device registers  */
  82 #define MSP_MAC0_BASE           (MSP_MSB_BASE + 0x600000)
  83                                         /* MAC A device registers       */
  84 #define MSP_MAC1_BASE           (MSP_MSB_BASE + 0x700000)
  85                                         /* MAC B device registers       */
  86 #define MSP_MAC_SIZE            0xE0    /* MAC register space           */
  87
  88 #define MSP_SEC_BASE            (MSP_MSB_BASE + 0x800000)
  89                                         /* Security Engine registers    */
  90 #define MSP_MAC2_BASE           (MSP_MSB_BASE + 0x900000)
  91                                         /* MAC C device registers       */
  92 #define MSP_ADSL2_BASE          (MSP_MSB_BASE + 0xA80000)
  93                                         /* ADSL2 device registers       */
  94 #define MSP_USB0_BASE           (MSP_MSB_BASE + 0xB00000)
  95                                         /* USB0 device registers        */
  96 #define MSP_USB1_BASE           (MSP_MSB_BASE + 0x300000)
  97                                         /* USB1 device registers        */
  98 #define MSP_CPUIF_BASE          (MSP_MSB_BASE + 0xC00000)
  99                                         /* CPU interface registers      */
 100
 101 /* Devices within the MSbus peripheral block */
 102 #define MSP_UART1_BASE          (MSP_PER_BASE + 0x030)
 103                                         /* UART1 controller base        */
 104 #define MSP_SPI_BASE            (MSP_PER_BASE + 0x058)
 105                                         /* SPI/MPI control registers    */
 106 #define MSP_TWI_BASE            (MSP_PER_BASE + 0x090)
 107                                         /* Two-wire control registers   */
 108 #define MSP_PTIMER_BASE         (MSP_PER_BASE + 0x0F0)
 109                                         /* Programmable timer control   */
 110
 111 /*
 112  ***************************************************************************
 113  * Physical Memory configuration address space                             *
 114  ***************************************************************************
 115  */
 116 #define MSP_MEM_CFG_BASE        0x17f00000
 117
 118 #define MSP_MEM_INDIRECT_CTL_10 0x10
 119
 120 /*
 121  * Notes:
 122  *  1) The SPI registers are split into two blocks, one offset from the
 123  *     MSP_SPI_BASE by 0x00 and the other offset from the MSP_SPI_BASE by
 124  *     0x68.  The SPI driver definitions for the register must be aware
 125  *     of this.
 126  *  2) The block copy engine register are divided into two regions, one
 127  *     for the control/configuration of the engine proper and one for the
 128  *     values of the descriptors used in the copy process.  These have
 129  *     different base defines (CTRL_BASE vs DESC_BASE)
 130  *  3) These constants are for physical addresses which means that they
 131  *     work correctly with "ioremap" and friends.  This means that device
 132  *     drivers will need to remap these addresses using ioremap and perhaps
 133  *     the readw/writew macros.  Or they could use the regptr() macro
 134  *     defined below, but the readw/writew calls are the correct thing.
 135  *  4) The UARTs have an additional status register offset from the base
 136  *     address.  This register isn't used in the standard 8250 driver but
 137  *     may be used in other software.  Consult the hardware datasheet for
 138  *     offset details.
 139  *  5) For some unknown reason the security engine (MSP_SEC_BASE) registers
 140  *     start at an offset of 0x84 from the base address but the block of
 141  *     registers before this is reserved for the security engine.  The
 142  *     driver will have to be aware of this but it makes the register
 143  *     definitions line up better with the documentation.
 144  */
 145
 146 /*
 147  ########################################################################
 148  #  System register definitions.  Not associated with a specific device #
 149  ########################################################################
 150  */
 151
 152 /*
 153  * This macro maps the physical register number into uncached space
 154  * and (for C code) casts it into a u32 pointer so it can be dereferenced
 155  * Normally these would be accessed with ioremap and readX/writeX, but
 156  * these are convenient for a lot of internal kernel code.
 157  */
 158 #ifdef __ASSEMBLER__
 159         #define regptr(addr) (KSEG1ADDR(addr))
 160 #else
 161         #define regptr(addr) ((volatile u32 *const)(KSEG1ADDR(addr)))
 162 #endif
 163
 164 /*
 165  ***************************************************************************
 166  * System Logic and Peripherals (RESET, ELB, etc) registers                *
 167  ***************************************************************************
 168  */
 169
 170 /* System Control register definitions */
 171 #define DEV_ID_REG      regptr(MSP_SLP_BASE + 0x00)
 172                                         /* Device-ID                 RO */
 173 #define FWR_ID_REG      regptr(MSP_SLP_BASE + 0x04)
 174                                         /* Firmware-ID Register      RW */
 175 #define SYS_ID_REG0     regptr(MSP_SLP_BASE + 0x08)
 176                                         /* System-ID Register-0      RW */
 177 #define SYS_ID_REG1     regptr(MSP_SLP_BASE + 0x0C)
 178                                         /* System-ID Register-1      RW */
 179
 180 /* System Reset register definitions */
 181 #define RST_STS_REG     regptr(MSP_SLP_BASE + 0x10)
 182                                         /* System Reset Status       RO */
 183 #define RST_SET_REG     regptr(MSP_SLP_BASE + 0x14)
 184                                         /* System Set Reset          WO */
 185 #define RST_CLR_REG     regptr(MSP_SLP_BASE + 0x18)
 186                                         /* System Clear Reset        WO */
 187
 188 /* System Clock Registers */
 189 #define PCI_SLP_REG     regptr(MSP_SLP_BASE + 0x1C)
 190                                         /* PCI clock generator       RW */
 191 #define URT_SLP_REG     regptr(MSP_SLP_BASE + 0x20)
 192                                         /* UART clock generator      RW */
 193 /* reserved                   (MSP_SLP_BASE + 0x24)                     */
 194 /* reserved                   (MSP_SLP_BASE + 0x28)                     */
 195 #define PLL1_SLP_REG    regptr(MSP_SLP_BASE + 0x2C)
 196                                         /* PLL1 clock generator      RW */
 197 #define PLL0_SLP_REG    regptr(MSP_SLP_BASE + 0x30)
 198                                         /* PLL0 clock generator      RW */
 199 #define MIPS_SLP_REG    regptr(MSP_SLP_BASE + 0x34)
 200                                         /* MIPS clock generator      RW */
 201 #define VE_SLP_REG      regptr(MSP_SLP_BASE + 0x38)
 202                                         /* Voice Eng clock generator RW */
 203 /* reserved                   (MSP_SLP_BASE + 0x3C)                     */
 204 #define MSB_SLP_REG     regptr(MSP_SLP_BASE + 0x40)
 205                                         /* MS-Bus clock generator    RW */
 206 #define SMAC_SLP_REG    regptr(MSP_SLP_BASE + 0x44)
 207                                         /* Sec & MAC clock generator RW */
 208 #define PERF_SLP_REG    regptr(MSP_SLP_BASE + 0x48)
 209                                         /* Per & TDM clock generator RW */
 210
 211 /* Interrupt Controller Registers */
 212 #define SLP_INT_STS_REG regptr(MSP_SLP_BASE + 0x70)
 213                                         /* Interrupt status register RW */
 214 #define SLP_INT_MSK_REG regptr(MSP_SLP_BASE + 0x74)
 215                                         /* Interrupt enable/mask     RW */
 216 #define SE_MBOX_REG     regptr(MSP_SLP_BASE + 0x78)
 217                                         /* Security Engine mailbox   RW */
 218 #define VE_MBOX_REG     regptr(MSP_SLP_BASE + 0x7C)
 219                                         /* Voice Engine mailbox      RW */
 220
 221 /* ELB Controller Registers */
 222 #define CS0_CNFG_REG    regptr(MSP_SLP_BASE + 0x80)
 223                                         /* ELB CS0 Configuration Reg    */
 224 #define CS0_ADDR_REG    regptr(MSP_SLP_BASE + 0x84)
 225                                         /* ELB CS0 Base Address Reg     */
 226 #define CS0_MASK_REG    regptr(MSP_SLP_BASE + 0x88)
 227                                         /* ELB CS0 Mask Register        */
 228 #define CS0_ACCESS_REG  regptr(MSP_SLP_BASE + 0x8C)
 229                                         /* ELB CS0 access register      */
 230
 231 #define CS1_CNFG_REG    regptr(MSP_SLP_BASE + 0x90)
 232                                         /* ELB CS1 Configuration Reg    */
 233 #define CS1_ADDR_REG    regptr(MSP_SLP_BASE + 0x94)
 234                                         /* ELB CS1 Base Address Reg     */
 235 #define CS1_MASK_REG    regptr(MSP_SLP_BASE + 0x98)
 236                                         /* ELB CS1 Mask Register        */
 237 #define CS1_ACCESS_REG  regptr(MSP_SLP_BASE + 0x9C)
 238                                         /* ELB CS1 access register      */
 239
 240 #define CS2_CNFG_REG    regptr(MSP_SLP_BASE + 0xA0)
 241                                         /* ELB CS2 Configuration Reg    */
 242 #define CS2_ADDR_REG    regptr(MSP_SLP_BASE + 0xA4)
 243                                         /* ELB CS2 Base Address Reg     */
 244 #define CS2_MASK_REG    regptr(MSP_SLP_BASE + 0xA8)
 245                                         /* ELB CS2 Mask Register        */
 246 #define CS2_ACCESS_REG  regptr(MSP_SLP_BASE + 0xAC)
 247                                         /* ELB CS2 access register      */
 248
 249 #define CS3_CNFG_REG    regptr(MSP_SLP_BASE + 0xB0)
 250                                         /* ELB CS3 Configuration Reg    */
 251 #define CS3_ADDR_REG    regptr(MSP_SLP_BASE + 0xB4)
 252                                         /* ELB CS3 Base Address Reg     */
 253 #define CS3_MASK_REG    regptr(MSP_SLP_BASE + 0xB8)
 254                                         /* ELB CS3 Mask Register        */
 255 #define CS3_ACCESS_REG  regptr(MSP_SLP_BASE + 0xBC)
 256                                         /* ELB CS3 access register      */
 257
 258 #define CS4_CNFG_REG    regptr(MSP_SLP_BASE + 0xC0)
 259                                         /* ELB CS4 Configuration Reg    */
 260 #define CS4_ADDR_REG    regptr(MSP_SLP_BASE + 0xC4)
 261                                         /* ELB CS4 Base Address Reg     */
 262 #define CS4_MASK_REG    regptr(MSP_SLP_BASE + 0xC8)
 263                                         /* ELB CS4 Mask Register        */
 264 #define CS4_ACCESS_REG  regptr(MSP_SLP_BASE + 0xCC)
 265                                         /* ELB CS4 access register      */
 266
 267 #define CS5_CNFG_REG    regptr(MSP_SLP_BASE + 0xD0)
 268                                         /* ELB CS5 Configuration Reg    */
 269 #define CS5_ADDR_REG    regptr(MSP_SLP_BASE + 0xD4)
 270                                         /* ELB CS5 Base Address Reg     */
 271 #define CS5_MASK_REG    regptr(MSP_SLP_BASE + 0xD8)
 272                                         /* ELB CS5 Mask Register        */
 273 #define CS5_ACCESS_REG  regptr(MSP_SLP_BASE + 0xDC)
 274                                         /* ELB CS5 access register      */
 275
 276 /* reserved                            0xE0 - 0xE8                      */
 277 #define ELB_1PC_EN_REG  regptr(MSP_SLP_BASE + 0xEC)
 278                                         /* ELB single PC card detect    */
 279
 280 /* reserved                            0xF0 - 0xF8                      */
 281 #define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC)
 282                                         /* SDRAM read/ELB timing Reg    */
 283
 284 /* Extended UART status registers */
 285 #define UART0_STATUS_REG        regptr(MSP_UART0_BASE + 0x0c0)
 286                                         /* UART Status Register 0       */
 287 #define UART1_STATUS_REG        regptr(MSP_UART1_BASE + 0x170)
 288                                         /* UART Status Register 1       */
 289
 290 /* Performance monitoring registers */
 291 #define PERF_MON_CTRL_REG       regptr(MSP_SLP_BASE + 0x140)
 292                                         /* Performance monitor control  */
 293 #define PERF_MON_CLR_REG        regptr(MSP_SLP_BASE + 0x144)
 294                                         /* Performance monitor clear    */
 295 #define PERF_MON_CNTH_REG       regptr(MSP_SLP_BASE + 0x148)
 296                                         /* Perf monitor counter high    */
 297 #define PERF_MON_CNTL_REG       regptr(MSP_SLP_BASE + 0x14C)
 298                                         /* Perf monitor counter low     */
 299
 300 /* System control registers */
 301 #define SYS_CTRL_REG            regptr(MSP_SLP_BASE + 0x150)
 302                                         /* System control register      */
 303 #define SYS_ERR1_REG            regptr(MSP_SLP_BASE + 0x154)
 304                                         /* System Error status 1        */
 305 #define SYS_ERR2_REG            regptr(MSP_SLP_BASE + 0x158)
 306                                         /* System Error status 2        */
 307 #define SYS_INT_CFG_REG         regptr(MSP_SLP_BASE + 0x15C)
 308                                         /* System Interrupt config      */
 309
 310 /* Voice Engine Memory configuration */
 311 #define VE_MEM_REG              regptr(MSP_SLP_BASE + 0x17C)
 312                                         /* Voice engine memory config   */
 313
 314 /* CPU/SLP Error Status registers */
 315 #define CPU_ERR1_REG            regptr(MSP_SLP_BASE + 0x180)
 316                                         /* CPU/SLP Error status 1       */
 317 #define CPU_ERR2_REG            regptr(MSP_SLP_BASE + 0x184)
 318                                         /* CPU/SLP Error status 1       */
 319
 320 /* Extended GPIO registers       */
 321 #define EXTENDED_GPIO1_REG      regptr(MSP_SLP_BASE + 0x188)
 322 #define EXTENDED_GPIO2_REG      regptr(MSP_SLP_BASE + 0x18c)
 323 #define EXTENDED_GPIO_REG       EXTENDED_GPIO1_REG
 324                                         /* Backward-compatibility       */
 325
 326 /* System Error registers */
 327 #define SLP_ERR_STS_REG         regptr(MSP_SLP_BASE + 0x190)
 328                                         /* Int status for SLP errors    */
 329 #define SLP_ERR_MSK_REG         regptr(MSP_SLP_BASE + 0x194)
 330                                         /* Int mask for SLP errors      */
 331 #define SLP_ELB_ERST_REG        regptr(MSP_SLP_BASE + 0x198)
 332                                         /* External ELB reset           */
 333 #define SLP_BOOT_STS_REG        regptr(MSP_SLP_BASE + 0x19C)
 334                                         /* Boot Status                  */
 335
 336 /* Extended ELB addressing */
 337 #define CS0_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1A0)
 338                                         /* CS0 Extended address         */
 339 #define CS1_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1A4)
 340                                         /* CS1 Extended address         */
 341 #define CS2_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1A8)
 342                                         /* CS2 Extended address         */
 343 #define CS3_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1AC)
 344                                         /* CS3 Extended address         */
 345 /* reserved                                           0x1B0             */
 346 #define CS5_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1B4)
 347                                         /* CS5 Extended address         */
 348
 349 /* PLL Adjustment registers */
 350 #define PLL_LOCK_REG            regptr(MSP_SLP_BASE + 0x200)
 351                                         /* PLL0 lock status             */
 352 #define PLL_ARST_REG            regptr(MSP_SLP_BASE + 0x204)
 353                                         /* PLL Analog reset status      */
 354 #define PLL0_ADJ_REG            regptr(MSP_SLP_BASE + 0x208)
 355                                         /* PLL0 Adjustment value        */
 356 #define PLL1_ADJ_REG            regptr(MSP_SLP_BASE + 0x20C)
 357                                         /* PLL1 Adjustment value        */
 358
 359 /*
 360  ***************************************************************************
 361  * Peripheral Register definitions                                         *
 362  ***************************************************************************
 363  */
 364
 365 /* Peripheral status */
 366 #define PER_CTRL_REG            regptr(MSP_PER_BASE + 0x50)
 367                                         /* Peripheral control register  */
 368 #define PER_STS_REG             regptr(MSP_PER_BASE + 0x54)
 369                                         /* Peripheral status register   */
 370
 371 /* SPI/MPI Registers */
 372 #define SMPI_TX_SZ_REG          regptr(MSP_PER_BASE + 0x58)
 373                                         /* SPI/MPI Tx Size register     */
 374 #define SMPI_RX_SZ_REG          regptr(MSP_PER_BASE + 0x5C)
 375                                         /* SPI/MPI Rx Size register     */
 376 #define SMPI_CTL_REG            regptr(MSP_PER_BASE + 0x60)
 377                                         /* SPI/MPI Control register     */
 378 #define SMPI_MS_REG             regptr(MSP_PER_BASE + 0x64)
 379                                         /* SPI/MPI Chip Select reg      */
 380 #define SMPI_CORE_DATA_REG      regptr(MSP_PER_BASE + 0xC0)
 381                                         /* SPI/MPI Core Data reg        */
 382 #define SMPI_CORE_CTRL_REG      regptr(MSP_PER_BASE + 0xC4)
 383                                         /* SPI/MPI Core Control reg     */
 384 #define SMPI_CORE_STAT_REG      regptr(MSP_PER_BASE + 0xC8)
 385                                         /* SPI/MPI Core Status reg      */
 386 #define SMPI_CORE_SSEL_REG      regptr(MSP_PER_BASE + 0xCC)
 387                                         /* SPI/MPI Core Ssel reg        */
 388 #define SMPI_FIFO_REG           regptr(MSP_PER_BASE + 0xD0)
 389                                         /* SPI/MPI Data FIFO reg        */
 390
 391 /* Peripheral Block Error Registers           */
 392 #define PER_ERR_STS_REG         regptr(MSP_PER_BASE + 0x70)
 393                                         /* Error Bit Status Register    */
 394 #define PER_ERR_MSK_REG         regptr(MSP_PER_BASE + 0x74)
 395                                         /* Error Bit Mask Register      */
 396 #define PER_HDR1_REG            regptr(MSP_PER_BASE + 0x78)
 397                                         /* Error Header 1 Register      */
 398 #define PER_HDR2_REG            regptr(MSP_PER_BASE + 0x7C)
 399                                         /* Error Header 2 Register      */
 400
 401 /* Peripheral Block Interrupt Registers       */
 402 #define PER_INT_STS_REG         regptr(MSP_PER_BASE + 0x80)
 403                                         /* Interrupt status register    */
 404 #define PER_INT_MSK_REG         regptr(MSP_PER_BASE + 0x84)
 405                                         /* Interrupt Mask Register      */
 406 #define GPIO_INT_STS_REG        regptr(MSP_PER_BASE + 0x88)
 407                                         /* GPIO interrupt status reg    */
 408 #define GPIO_INT_MSK_REG        regptr(MSP_PER_BASE + 0x8C)
 409                                         /* GPIO interrupt MASK Reg      */
 410
 411 /* POLO GPIO registers                        */
 412 #define POLO_GPIO_DAT1_REG      regptr(MSP_PER_BASE + 0x0E0)
 413                                         /* Polo GPIO[8:0]  data reg     */
 414 #define POLO_GPIO_CFG1_REG      regptr(MSP_PER_BASE + 0x0E4)
 415                                         /* Polo GPIO[7:0]  config reg   */
 416 #define POLO_GPIO_CFG2_REG      regptr(MSP_PER_BASE + 0x0E8)
 417                                         /* Polo GPIO[15:8] config reg   */
 418 #define POLO_GPIO_OD1_REG       regptr(MSP_PER_BASE + 0x0EC)
 419                                         /* Polo GPIO[31:0] output drive */
 420 #define POLO_GPIO_CFG3_REG      regptr(MSP_PER_BASE + 0x170)
 421                                         /* Polo GPIO[23:16] config reg  */
 422 #define POLO_GPIO_DAT2_REG      regptr(MSP_PER_BASE + 0x174)
 423                                         /* Polo GPIO[15:9]  data reg    */
 424 #define POLO_GPIO_DAT3_REG      regptr(MSP_PER_BASE + 0x178)
 425                                         /* Polo GPIO[23:16]  data reg   */
 426 #define POLO_GPIO_DAT4_REG      regptr(MSP_PER_BASE + 0x17C)
 427                                         /* Polo GPIO[31:24]  data reg   */
 428 #define POLO_GPIO_DAT5_REG      regptr(MSP_PER_BASE + 0x180)
 429                                         /* Polo GPIO[39:32]  data reg   */
 430 #define POLO_GPIO_DAT6_REG      regptr(MSP_PER_BASE + 0x184)
 431                                         /* Polo GPIO[47:40]  data reg   */
 432 #define POLO_GPIO_DAT7_REG      regptr(MSP_PER_BASE + 0x188)
 433                                         /* Polo GPIO[54:48]  data reg   */
 434 #define POLO_GPIO_CFG4_REG      regptr(MSP_PER_BASE + 0x18C)
 435                                         /* Polo GPIO[31:24] config reg  */
 436 #define POLO_GPIO_CFG5_REG      regptr(MSP_PER_BASE + 0x190)
 437                                         /* Polo GPIO[39:32] config reg  */
 438 #define POLO_GPIO_CFG6_REG      regptr(MSP_PER_BASE + 0x194)
 439                                         /* Polo GPIO[47:40] config reg  */
 440 #define POLO_GPIO_CFG7_REG      regptr(MSP_PER_BASE + 0x198)
 441                                         /* Polo GPIO[54:48] config reg  */
 442 #define POLO_GPIO_OD2_REG       regptr(MSP_PER_BASE + 0x19C)
 443                                         /* Polo GPIO[54:32] output drive */
 444
 445 /* Generic GPIO registers                     */
 446 #define GPIO_DATA1_REG          regptr(MSP_PER_BASE + 0x170)
 447                                         /* GPIO[1:0] data register      */
 448 #define GPIO_DATA2_REG          regptr(MSP_PER_BASE + 0x174)
 449                                         /* GPIO[5:2] data register      */
 450 #define GPIO_DATA3_REG          regptr(MSP_PER_BASE + 0x178)
 451                                         /* GPIO[9:6] data register      */
 452 #define GPIO_DATA4_REG          regptr(MSP_PER_BASE + 0x17C)
 453                                         /* GPIO[15:10] data register    */
 454 #define GPIO_CFG1_REG           regptr(MSP_PER_BASE + 0x180)
 455                                         /* GPIO[1:0] config register    */
 456 #define GPIO_CFG2_REG           regptr(MSP_PER_BASE + 0x184)
 457                                         /* GPIO[5:2] config register    */
 458 #define GPIO_CFG3_REG           regptr(MSP_PER_BASE + 0x188)
 459                                         /* GPIO[9:6] config register    */
 460 #define GPIO_CFG4_REG           regptr(MSP_PER_BASE + 0x18C)
 461                                         /* GPIO[15:10] config register  */
 462 #define GPIO_OD_REG             regptr(MSP_PER_BASE + 0x190)
 463                                         /* GPIO[15:0] output drive      */
 464
 465 /*
 466  ***************************************************************************
 467  * CPU Interface register definitions                                      *
 468  ***************************************************************************
 469  */
 470 #define PCI_FLUSH_REG           regptr(MSP_CPUIF_BASE + 0x00)
 471                                         /* PCI-SDRAM queue flush trigger */
 472 #define OCP_ERR1_REG            regptr(MSP_CPUIF_BASE + 0x04)
 473                                         /* OCP Error Attribute 1        */
 474 #define OCP_ERR2_REG            regptr(MSP_CPUIF_BASE + 0x08)
 475                                         /* OCP Error Attribute 2        */
 476 #define OCP_STS_REG             regptr(MSP_CPUIF_BASE + 0x0C)
 477                                         /* OCP Error Status             */
 478 #define CPUIF_PM_REG            regptr(MSP_CPUIF_BASE + 0x10)
 479                                         /* CPU policy configuration     */
 480 #define CPUIF_CFG_REG           regptr(MSP_CPUIF_BASE + 0x10)
 481                                         /* Misc configuration options   */
 482
 483 /* Central Interrupt Controller Registers */
 484 #define MSP_CIC_BASE            (MSP_CPUIF_BASE + 0x8000)
 485                                         /* Central Interrupt registers  */
 486 #define CIC_EXT_CFG_REG         regptr(MSP_CIC_BASE + 0x00)
 487                                         /* External interrupt config    */
 488 #define CIC_STS_REG             regptr(MSP_CIC_BASE + 0x04)
 489                                         /* CIC Interrupt Status         */
 490 #define CIC_VPE0_MSK_REG        regptr(MSP_CIC_BASE + 0x08)
 491                                         /* VPE0 Interrupt Mask          */
 492 #define CIC_VPE1_MSK_REG        regptr(MSP_CIC_BASE + 0x0C)
 493                                         /* VPE1 Interrupt Mask          */
 494 #define CIC_TC0_MSK_REG         regptr(MSP_CIC_BASE + 0x10)
 495                                         /* Thread Context 0 Int Mask    */
 496 #define CIC_TC1_MSK_REG         regptr(MSP_CIC_BASE + 0x14)
 497                                         /* Thread Context 1 Int Mask    */
 498 #define CIC_TC2_MSK_REG         regptr(MSP_CIC_BASE + 0x18)
 499                                         /* Thread Context 2 Int Mask    */
 500 #define CIC_TC3_MSK_REG         regptr(MSP_CIC_BASE + 0x18)
 501                                         /* Thread Context 3 Int Mask    */
 502 #define CIC_TC4_MSK_REG         regptr(MSP_CIC_BASE + 0x18)
 503                                         /* Thread Context 4 Int Mask    */
 504 #define CIC_PCIMSI_STS_REG      regptr(MSP_CIC_BASE + 0x18)
 505 #define CIC_PCIMSI_MSK_REG      regptr(MSP_CIC_BASE + 0x18)
 506 #define CIC_PCIFLSH_REG         regptr(MSP_CIC_BASE + 0x18)
 507 #define CIC_VPE0_SWINT_REG      regptr(MSP_CIC_BASE + 0x08)
 508
 509
 510 /*
 511  ***************************************************************************
 512  * Memory controller registers                                             *
 513  ***************************************************************************
 514  */
 515 #define MEM_CFG1_REG            regptr(MSP_MEM_CFG_BASE + 0x00)
 516 #define MEM_SS_ADDR             regptr(MSP_MEM_CFG_BASE + 0x00)
 517 #define MEM_SS_DATA             regptr(MSP_MEM_CFG_BASE + 0x04)
 518 #define MEM_SS_WRITE            regptr(MSP_MEM_CFG_BASE + 0x08)
 519
 520 /*
 521  ***************************************************************************
 522  * PCI controller registers                                                *
 523  ***************************************************************************
 524  */
 525 #define PCI_BASE_REG            regptr(MSP_PCI_BASE + 0x00)
 526 #define PCI_CONFIG_SPACE_REG    regptr(MSP_PCI_BASE + 0x800)
 527 #define PCI_JTAG_DEVID_REG      regptr(MSP_SLP_BASE + 0x13c)
 528
 529 /*
 530  ########################################################################
 531  #  Register content & macro definitions                                #
 532  ########################################################################
 533  */
 534
 535 /*
 536  ***************************************************************************
 537  * DEV_ID defines                                                          *
 538  ***************************************************************************
 539  */
 540 #define DEV_ID_PCI_DIS          (1 << 26)       /* Set if PCI disabled */
 541 #define DEV_ID_PCI_HOST         (1 << 20)       /* Set if PCI host */
 542 #define DEV_ID_SINGLE_PC        (1 << 19)       /* Set if single PC Card */
 543 #define DEV_ID_FAMILY           (0xff << 8)     /* family ID code */
 544 #define POLO_ZEUS_SUB_FAMILY    (0x7  << 16)    /* sub family for Polo/Zeus */
 545
 546 #define MSPFPGA_ID              (0x00  << 8)    /* you are on your own here */
 547 #define MSP5000_ID              (0x50  << 8)
 548 #define MSP4F00_ID              (0x4f  << 8)    /* FPGA version of MSP4200 */
 549 #define MSP4E00_ID              (0x4f  << 8)    /* FPGA version of MSP7120 */
 550 #define MSP4200_ID              (0x42  << 8)
 551 #define MSP4000_ID              (0x40  << 8)
 552 #define MSP2XXX_ID              (0x20  << 8)
 553 #define MSPZEUS_ID              (0x10  << 8)
 554
 555 #define MSP2004_SUB_ID          (0x0   << 16)
 556 #define MSP2005_SUB_ID          (0x1   << 16)
 557 #define MSP2006_SUB_ID          (0x1   << 16)
 558 #define MSP2007_SUB_ID          (0x2   << 16)
 559 #define MSP2010_SUB_ID          (0x3   << 16)
 560 #define MSP2015_SUB_ID          (0x4   << 16)
 561 #define MSP2020_SUB_ID          (0x5   << 16)
 562 #define MSP2100_SUB_ID          (0x6   << 16)
 563
 564 /*
 565  ***************************************************************************
 566  * RESET defines                                                           *
 567  ***************************************************************************
 568  */
 569 #define MSP_GR_RST              (0x01 << 0)     /* Global reset bit     */
 570 #define MSP_MR_RST              (0x01 << 1)     /* MIPS reset bit       */
 571 #define MSP_PD_RST              (0x01 << 2)     /* PVC DMA reset bit    */
 572 #define MSP_PP_RST              (0x01 << 3)     /* PVC reset bit        */
 573 /* reserved                                                             */
 574 #define MSP_EA_RST              (0x01 << 6)     /* Mac A reset bit      */
 575 #define MSP_EB_RST              (0x01 << 7)     /* Mac B reset bit      */
 576 #define MSP_SE_RST              (0x01 << 8)     /* Security Eng reset bit */
 577 #define MSP_PB_RST              (0x01 << 9)     /* Per block reset bit  */
 578 #define MSP_EC_RST              (0x01 << 10)    /* Mac C reset bit      */
 579 #define MSP_TW_RST              (0x01 << 11)    /* TWI reset bit        */
 580 #define MSP_SPI_RST             (0x01 << 12)    /* SPI/MPI reset bit    */
 581 #define MSP_U1_RST              (0x01 << 13)    /* UART1 reset bit      */
 582 #define MSP_U0_RST              (0x01 << 14)    /* UART0 reset bit      */
 583
 584 /*
 585  ***************************************************************************
 586  * UART defines                                                            *
 587  ***************************************************************************
 588  */
 589 #define MSP_BASE_BAUD           25000000
 590 #define MSP_UART_REG_LEN        0x20
 591
 592 /*
 593  ***************************************************************************
 594  * ELB defines                                                             *
 595  ***************************************************************************
 596  */
 597 #define PCCARD_32               0x02    /* Set if is PCCARD 32 (Cardbus) */
 598 #define SINGLE_PCCARD           0x01    /* Set to enable single PC card */
 599
 600 /*
 601  ***************************************************************************
 602  * CIC defines                                                             *
 603  ***************************************************************************
 604  */
 605
 606 /* CIC_EXT_CFG_REG */
 607 #define EXT_INT_POL(eirq)                       (1 << (eirq + 8))
 608 #define EXT_INT_EDGE(eirq)                      (1 << eirq)
 609
 610 #define CIC_EXT_SET_TRIGGER_LEVEL(reg, eirq)    (reg &= ~EXT_INT_EDGE(eirq))
 611 #define CIC_EXT_SET_TRIGGER_EDGE(reg, eirq)     (reg |= EXT_INT_EDGE(eirq))
 612 #define CIC_EXT_SET_ACTIVE_HI(reg, eirq)        (reg |= EXT_INT_POL(eirq))
 613 #define CIC_EXT_SET_ACTIVE_LO(reg, eirq)        (reg &= ~EXT_INT_POL(eirq))
 614 #define CIC_EXT_SET_ACTIVE_RISING               CIC_EXT_SET_ACTIVE_HI
 615 #define CIC_EXT_SET_ACTIVE_FALLING              CIC_EXT_SET_ACTIVE_LO
 616
 617 #define CIC_EXT_IS_TRIGGER_LEVEL(reg, eirq) \
 618                                 ((reg & EXT_INT_EDGE(eirq)) == 0)
 619 #define CIC_EXT_IS_TRIGGER_EDGE(reg, eirq)      (reg & EXT_INT_EDGE(eirq))
 620 #define CIC_EXT_IS_ACTIVE_HI(reg, eirq)         (reg & EXT_INT_POL(eirq))
 621 #define CIC_EXT_IS_ACTIVE_LO(reg, eirq) \
 622                                 ((reg & EXT_INT_POL(eirq)) == 0)
 623 #define CIC_EXT_IS_ACTIVE_RISING                CIC_EXT_IS_ACTIVE_HI
 624 #define CIC_EXT_IS_ACTIVE_FALLING               CIC_EXT_IS_ACTIVE_LO
 625
 626 /*
 627  ***************************************************************************
 628  * Memory Controller defines                                               *
 629  ***************************************************************************
 630  */
 631
 632 /* Indirect memory controller registers */
 633 #define DDRC_CFG(n)             (n)
 634 #define DDRC_DEBUG(n)           (0x04 + n)
 635 #define DDRC_CTL(n)             (0x40 + n)
 636
 637 /* Macro to perform DDRC indirect write */
 638 #define DDRC_INDIRECT_WRITE(reg, mask, value) \
 639 ({ \
 640         *MEM_SS_ADDR = (((mask) & 0xf) << 8) | ((reg) & 0xff); \
 641         *MEM_SS_DATA = (value); \
 642         *MEM_SS_WRITE = 1; \
 643 })
 644
 645 /*
 646  ***************************************************************************
 647  * SPI/MPI Mode                                                            *
 648  ***************************************************************************
 649  */
 650 #define SPI_MPI_RX_BUSY         0x00008000      /* SPI/MPI Receive Busy */
 651 #define SPI_MPI_FIFO_EMPTY      0x00004000      /* SPI/MPI Fifo Empty   */
 652 #define SPI_MPI_TX_BUSY         0x00002000      /* SPI/MPI Transmit Busy */
 653 #define SPI_MPI_FIFO_FULL       0x00001000      /* SPI/MPU FIFO full    */
 654
 655 /*
 656  ***************************************************************************
 657  * SPI/MPI Control Register                                                *
 658  ***************************************************************************
 659  */
 660 #define SPI_MPI_RX_START        0x00000004      /* Start receive command */
 661 #define SPI_MPI_FLUSH_Q         0x00000002      /* Flush SPI/MPI Queue */
 662 #define SPI_MPI_TX_START        0x00000001      /* Start Transmit Command */
 663
 664 #endif /* !_ASM_MSP_REGS_H */