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blk: rq_data_dir() should not return a boolean
[cris-mirror.git] / arch / mips / include / asm / mipsregs.h
blobd3cd8eac81e3a76baf455dd95e881cfd9c72eed9
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
15
16 #include <linux/linkage.h>
17 #include <linux/types.h>
18 #include <asm/hazards.h>
19 #include <asm/war.h>
20
21 /*
22 * The following macros are especially useful for __asm__
23 * inline assembler.
24 */
25 #ifndef __STR
26 #define __STR(x) #x
27 #endif
28 #ifndef STR
29 #define STR(x) __STR(x)
30 #endif
31
32 /*
33 * Configure language
34 */
35 #ifdef __ASSEMBLY__
36 #define _ULCAST_
37 #else
38 #define _ULCAST_ (unsigned long)
39 #endif
40
41 /*
42 * Coprocessor 0 register names
43 */
44 #define CP0_INDEX $0
45 #define CP0_RANDOM $1
46 #define CP0_ENTRYLO0 $2
47 #define CP0_ENTRYLO1 $3
48 #define CP0_CONF $3
49 #define CP0_CONTEXT $4
50 #define CP0_PAGEMASK $5
51 #define CP0_WIRED $6
52 #define CP0_INFO $7
53 #define CP0_BADVADDR $8
54 #define CP0_COUNT $9
55 #define CP0_ENTRYHI $10
56 #define CP0_COMPARE $11
57 #define CP0_STATUS $12
58 #define CP0_CAUSE $13
59 #define CP0_EPC $14
60 #define CP0_PRID $15
61 #define CP0_CONFIG $16
62 #define CP0_LLADDR $17
63 #define CP0_WATCHLO $18
64 #define CP0_WATCHHI $19
65 #define CP0_XCONTEXT $20
66 #define CP0_FRAMEMASK $21
67 #define CP0_DIAGNOSTIC $22
68 #define CP0_DEBUG $23
69 #define CP0_DEPC $24
70 #define CP0_PERFORMANCE $25
71 #define CP0_ECC $26
72 #define CP0_CACHEERR $27
73 #define CP0_TAGLO $28
74 #define CP0_TAGHI $29
75 #define CP0_ERROREPC $30
76 #define CP0_DESAVE $31
77
78 /*
79 * R4640/R4650 cp0 register names. These registers are listed
80 * here only for completeness; without MMU these CPUs are not useable
81 * by Linux. A future ELKS port might take make Linux run on them
82 * though ...
83 */
84 #define CP0_IBASE $0
85 #define CP0_IBOUND $1
86 #define CP0_DBASE $2
87 #define CP0_DBOUND $3
88 #define CP0_CALG $17
89 #define CP0_IWATCH $18
90 #define CP0_DWATCH $19
91
92 /*
93 * Coprocessor 0 Set 1 register names
94 */
95 #define CP0_S1_DERRADDR0 $26
96 #define CP0_S1_DERRADDR1 $27
97 #define CP0_S1_INTCONTROL $20
98
99 /*
100 * Coprocessor 0 Set 2 register names
101 */
102 #define CP0_S2_SRSCTL $12 /* MIPSR2 */
103
104 /*
105 * Coprocessor 0 Set 3 register names
106 */
107 #define CP0_S3_SRSMAP $12 /* MIPSR2 */
108
109 /*
110 * TX39 Series
111 */
112 #define CP0_TX39_CACHE $7
113
114
115 /* Generic EntryLo bit definitions */
116 #define ENTRYLO_G (_ULCAST_(1) << 0)
117 #define ENTRYLO_V (_ULCAST_(1) << 1)
118 #define ENTRYLO_D (_ULCAST_(1) << 2)
119 #define ENTRYLO_C_SHIFT 3
120 #define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
121
122 /* R3000 EntryLo bit definitions */
123 #define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
124 #define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
125 #define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
126 #define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
127
128 /* MIPS32/64 EntryLo bit definitions */
129 #ifdef CONFIG_64BIT
130 /* as read by dmfc0 */
131 #define MIPS_ENTRYLO_XI (_ULCAST_(1) << 62)
132 #define MIPS_ENTRYLO_RI (_ULCAST_(1) << 63)
133 #else
134 /* as read by mfc0 */
135 #define MIPS_ENTRYLO_XI (_ULCAST_(1) << 30)
136 #define MIPS_ENTRYLO_RI (_ULCAST_(1) << 31)
137 #endif
138
139 /*
140 * Values for PageMask register
141 */
142 #ifdef CONFIG_CPU_VR41XX
143
144 /* Why doesn't stupidity hurt ... */
145
146 #define PM_1K 0x00000000
147 #define PM_4K 0x00001800
148 #define PM_16K 0x00007800
149 #define PM_64K 0x0001f800
150 #define PM_256K 0x0007f800
151
152 #else
153
154 #define PM_4K 0x00000000
155 #define PM_8K 0x00002000
156 #define PM_16K 0x00006000
157 #define PM_32K 0x0000e000
158 #define PM_64K 0x0001e000
159 #define PM_128K 0x0003e000
160 #define PM_256K 0x0007e000
161 #define PM_512K 0x000fe000
162 #define PM_1M 0x001fe000
163 #define PM_2M 0x003fe000
164 #define PM_4M 0x007fe000
165 #define PM_8M 0x00ffe000
166 #define PM_16M 0x01ffe000
167 #define PM_32M 0x03ffe000
168 #define PM_64M 0x07ffe000
169 #define PM_256M 0x1fffe000
170 #define PM_1G 0x7fffe000
171
172 #endif
173
174 /*
175 * Default page size for a given kernel configuration
176 */
177 #ifdef CONFIG_PAGE_SIZE_4KB
178 #define PM_DEFAULT_MASK PM_4K
179 #elif defined(CONFIG_PAGE_SIZE_8KB)
180 #define PM_DEFAULT_MASK PM_8K
181 #elif defined(CONFIG_PAGE_SIZE_16KB)
182 #define PM_DEFAULT_MASK PM_16K
183 #elif defined(CONFIG_PAGE_SIZE_32KB)
184 #define PM_DEFAULT_MASK PM_32K
185 #elif defined(CONFIG_PAGE_SIZE_64KB)
186 #define PM_DEFAULT_MASK PM_64K
187 #else
188 #error Bad page size configuration!
189 #endif
190
191 /*
192 * Default huge tlb size for a given kernel configuration
193 */
194 #ifdef CONFIG_PAGE_SIZE_4KB
195 #define PM_HUGE_MASK PM_1M
196 #elif defined(CONFIG_PAGE_SIZE_8KB)
197 #define PM_HUGE_MASK PM_4M
198 #elif defined(CONFIG_PAGE_SIZE_16KB)
199 #define PM_HUGE_MASK PM_16M
200 #elif defined(CONFIG_PAGE_SIZE_32KB)
201 #define PM_HUGE_MASK PM_64M
202 #elif defined(CONFIG_PAGE_SIZE_64KB)
203 #define PM_HUGE_MASK PM_256M
204 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
205 #error Bad page size configuration for hugetlbfs!
206 #endif
207
208 /*
209 * Values used for computation of new tlb entries
210 */
211 #define PL_4K 12
212 #define PL_16K 14
213 #define PL_64K 16
214 #define PL_256K 18
215 #define PL_1M 20
216 #define PL_4M 22
217 #define PL_16M 24
218 #define PL_64M 26
219 #define PL_256M 28
220
221 /*
222 * PageGrain bits
223 */
224 #define PG_RIE (_ULCAST_(1) << 31)
225 #define PG_XIE (_ULCAST_(1) << 30)
226 #define PG_ELPA (_ULCAST_(1) << 29)
227 #define PG_ESP (_ULCAST_(1) << 28)
228 #define PG_IEC (_ULCAST_(1) << 27)
229
230 /* MIPS32/64 EntryHI bit definitions */
231 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
232
233 /*
234 * R4x00 interrupt enable / cause bits
235 */
236 #define IE_SW0 (_ULCAST_(1) << 8)
237 #define IE_SW1 (_ULCAST_(1) << 9)
238 #define IE_IRQ0 (_ULCAST_(1) << 10)
239 #define IE_IRQ1 (_ULCAST_(1) << 11)
240 #define IE_IRQ2 (_ULCAST_(1) << 12)
241 #define IE_IRQ3 (_ULCAST_(1) << 13)
242 #define IE_IRQ4 (_ULCAST_(1) << 14)
243 #define IE_IRQ5 (_ULCAST_(1) << 15)
244
245 /*
246 * R4x00 interrupt cause bits
247 */
248 #define C_SW0 (_ULCAST_(1) << 8)
249 #define C_SW1 (_ULCAST_(1) << 9)
250 #define C_IRQ0 (_ULCAST_(1) << 10)
251 #define C_IRQ1 (_ULCAST_(1) << 11)
252 #define C_IRQ2 (_ULCAST_(1) << 12)
253 #define C_IRQ3 (_ULCAST_(1) << 13)
254 #define C_IRQ4 (_ULCAST_(1) << 14)
255 #define C_IRQ5 (_ULCAST_(1) << 15)
256
257 /*
258 * Bitfields in the R4xx0 cp0 status register
259 */
260 #define ST0_IE 0x00000001
261 #define ST0_EXL 0x00000002
262 #define ST0_ERL 0x00000004
263 #define ST0_KSU 0x00000018
264 # define KSU_USER 0x00000010
265 # define KSU_SUPERVISOR 0x00000008
266 # define KSU_KERNEL 0x00000000
267 #define ST0_UX 0x00000020
268 #define ST0_SX 0x00000040
269 #define ST0_KX 0x00000080
270 #define ST0_DE 0x00010000
271 #define ST0_CE 0x00020000
272
273 /*
274 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
275 * cacheops in userspace. This bit exists only on RM7000 and RM9000
276 * processors.
277 */
278 #define ST0_CO 0x08000000
279
280 /*
281 * Bitfields in the R[23]000 cp0 status register.
282 */
283 #define ST0_IEC 0x00000001
284 #define ST0_KUC 0x00000002
285 #define ST0_IEP 0x00000004
286 #define ST0_KUP 0x00000008
287 #define ST0_IEO 0x00000010
288 #define ST0_KUO 0x00000020
289 /* bits 6 & 7 are reserved on R[23]000 */
290 #define ST0_ISC 0x00010000
291 #define ST0_SWC 0x00020000
292 #define ST0_CM 0x00080000
293
294 /*
295 * Bits specific to the R4640/R4650
296 */
297 #define ST0_UM (_ULCAST_(1) << 4)
298 #define ST0_IL (_ULCAST_(1) << 23)
299 #define ST0_DL (_ULCAST_(1) << 24)
300
301 /*
302 * Enable the MIPS MDMX and DSP ASEs
303 */
304 #define ST0_MX 0x01000000
305
306 /*
307 * Status register bits available in all MIPS CPUs.
308 */
309 #define ST0_IM 0x0000ff00
310 #define STATUSB_IP0 8
311 #define STATUSF_IP0 (_ULCAST_(1) << 8)
312 #define STATUSB_IP1 9
313 #define STATUSF_IP1 (_ULCAST_(1) << 9)
314 #define STATUSB_IP2 10
315 #define STATUSF_IP2 (_ULCAST_(1) << 10)
316 #define STATUSB_IP3 11
317 #define STATUSF_IP3 (_ULCAST_(1) << 11)
318 #define STATUSB_IP4 12
319 #define STATUSF_IP4 (_ULCAST_(1) << 12)
320 #define STATUSB_IP5 13
321 #define STATUSF_IP5 (_ULCAST_(1) << 13)
322 #define STATUSB_IP6 14
323 #define STATUSF_IP6 (_ULCAST_(1) << 14)
324 #define STATUSB_IP7 15
325 #define STATUSF_IP7 (_ULCAST_(1) << 15)
326 #define STATUSB_IP8 0
327 #define STATUSF_IP8 (_ULCAST_(1) << 0)
328 #define STATUSB_IP9 1
329 #define STATUSF_IP9 (_ULCAST_(1) << 1)
330 #define STATUSB_IP10 2
331 #define STATUSF_IP10 (_ULCAST_(1) << 2)
332 #define STATUSB_IP11 3
333 #define STATUSF_IP11 (_ULCAST_(1) << 3)
334 #define STATUSB_IP12 4
335 #define STATUSF_IP12 (_ULCAST_(1) << 4)
336 #define STATUSB_IP13 5
337 #define STATUSF_IP13 (_ULCAST_(1) << 5)
338 #define STATUSB_IP14 6
339 #define STATUSF_IP14 (_ULCAST_(1) << 6)
340 #define STATUSB_IP15 7
341 #define STATUSF_IP15 (_ULCAST_(1) << 7)
342 #define ST0_CH 0x00040000
343 #define ST0_NMI 0x00080000
344 #define ST0_SR 0x00100000
345 #define ST0_TS 0x00200000
346 #define ST0_BEV 0x00400000
347 #define ST0_RE 0x02000000
348 #define ST0_FR 0x04000000
349 #define ST0_CU 0xf0000000
350 #define ST0_CU0 0x10000000
351 #define ST0_CU1 0x20000000
352 #define ST0_CU2 0x40000000
353 #define ST0_CU3 0x80000000
354 #define ST0_XX 0x80000000 /* MIPS IV naming */
355
356 /*
357 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
358 */
359 #define INTCTLB_IPFDC 23
360 #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
361 #define INTCTLB_IPPCI 26
362 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
363 #define INTCTLB_IPTI 29
364 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
365
366 /*
367 * Bitfields and bit numbers in the coprocessor 0 cause register.
368 *
369 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
370 */
371 #define CAUSEB_EXCCODE 2
372 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
373 #define CAUSEB_IP 8
374 #define CAUSEF_IP (_ULCAST_(255) << 8)
375 #define CAUSEB_IP0 8
376 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
377 #define CAUSEB_IP1 9
378 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
379 #define CAUSEB_IP2 10
380 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
381 #define CAUSEB_IP3 11
382 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
383 #define CAUSEB_IP4 12
384 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
385 #define CAUSEB_IP5 13
386 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
387 #define CAUSEB_IP6 14
388 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
389 #define CAUSEB_IP7 15
390 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
391 #define CAUSEB_FDCI 21
392 #define CAUSEF_FDCI (_ULCAST_(1) << 21)
393 #define CAUSEB_IV 23
394 #define CAUSEF_IV (_ULCAST_(1) << 23)
395 #define CAUSEB_PCI 26
396 #define CAUSEF_PCI (_ULCAST_(1) << 26)
397 #define CAUSEB_CE 28
398 #define CAUSEF_CE (_ULCAST_(3) << 28)
399 #define CAUSEB_TI 30
400 #define CAUSEF_TI (_ULCAST_(1) << 30)
401 #define CAUSEB_BD 31
402 #define CAUSEF_BD (_ULCAST_(1) << 31)
403
404 /*
405 * Bits in the coprocessor 0 config register.
406 */
407 /* Generic bits. */
408 #define CONF_CM_CACHABLE_NO_WA 0
409 #define CONF_CM_CACHABLE_WA 1
410 #define CONF_CM_UNCACHED 2
411 #define CONF_CM_CACHABLE_NONCOHERENT 3
412 #define CONF_CM_CACHABLE_CE 4
413 #define CONF_CM_CACHABLE_COW 5
414 #define CONF_CM_CACHABLE_CUW 6
415 #define CONF_CM_CACHABLE_ACCELERATED 7
416 #define CONF_CM_CMASK 7
417 #define CONF_BE (_ULCAST_(1) << 15)
418
419 /* Bits common to various processors. */
420 #define CONF_CU (_ULCAST_(1) << 3)
421 #define CONF_DB (_ULCAST_(1) << 4)
422 #define CONF_IB (_ULCAST_(1) << 5)
423 #define CONF_DC (_ULCAST_(7) << 6)
424 #define CONF_IC (_ULCAST_(7) << 9)
425 #define CONF_EB (_ULCAST_(1) << 13)
426 #define CONF_EM (_ULCAST_(1) << 14)
427 #define CONF_SM (_ULCAST_(1) << 16)
428 #define CONF_SC (_ULCAST_(1) << 17)
429 #define CONF_EW (_ULCAST_(3) << 18)
430 #define CONF_EP (_ULCAST_(15)<< 24)
431 #define CONF_EC (_ULCAST_(7) << 28)
432 #define CONF_CM (_ULCAST_(1) << 31)
433
434 /* Bits specific to the R4xx0. */
435 #define R4K_CONF_SW (_ULCAST_(1) << 20)
436 #define R4K_CONF_SS (_ULCAST_(1) << 21)
437 #define R4K_CONF_SB (_ULCAST_(3) << 22)
438
439 /* Bits specific to the R5000. */
440 #define R5K_CONF_SE (_ULCAST_(1) << 12)
441 #define R5K_CONF_SS (_ULCAST_(3) << 20)
442
443 /* Bits specific to the RM7000. */
444 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
445 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
446 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
447 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
448 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
449 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
450
451 /* Bits specific to the R10000. */
452 #define R10K_CONF_DN (_ULCAST_(3) << 3)
453 #define R10K_CONF_CT (_ULCAST_(1) << 5)
454 #define R10K_CONF_PE (_ULCAST_(1) << 6)
455 #define R10K_CONF_PM (_ULCAST_(3) << 7)
456 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
457 #define R10K_CONF_SB (_ULCAST_(1) << 13)
458 #define R10K_CONF_SK (_ULCAST_(1) << 14)
459 #define R10K_CONF_SS (_ULCAST_(7) << 16)
460 #define R10K_CONF_SC (_ULCAST_(7) << 19)
461 #define R10K_CONF_DC (_ULCAST_(7) << 26)
462 #define R10K_CONF_IC (_ULCAST_(7) << 29)
463
464 /* Bits specific to the VR41xx. */
465 #define VR41_CONF_CS (_ULCAST_(1) << 12)
466 #define VR41_CONF_P4K (_ULCAST_(1) << 13)
467 #define VR41_CONF_BP (_ULCAST_(1) << 16)
468 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
469 #define VR41_CONF_AD (_ULCAST_(1) << 23)
470
471 /* Bits specific to the R30xx. */
472 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
473 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
474 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
475 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
476 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
477 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
478 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
479 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
480 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
481
482 /* Bits specific to the TX49. */
483 #define TX49_CONF_DC (_ULCAST_(1) << 16)
484 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
485 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
486 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
487
488 /* Bits specific to the MIPS32/64 PRA. */
489 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
490 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
491 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
492 #define MIPS_CONF_M (_ULCAST_(1) << 31)
493
494 /*
495 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
496 */
497 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
498 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
499 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
500 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
501 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
502 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
503 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
504 #define MIPS_CONF1_DA_SHF 7
505 #define MIPS_CONF1_DA_SZ 3
506 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
507 #define MIPS_CONF1_DL_SHF 10
508 #define MIPS_CONF1_DL_SZ 3
509 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
510 #define MIPS_CONF1_DS_SHF 13
511 #define MIPS_CONF1_DS_SZ 3
512 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
513 #define MIPS_CONF1_IA_SHF 16
514 #define MIPS_CONF1_IA_SZ 3
515 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
516 #define MIPS_CONF1_IL_SHF 19
517 #define MIPS_CONF1_IL_SZ 3
518 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
519 #define MIPS_CONF1_IS_SHF 22
520 #define MIPS_CONF1_IS_SZ 3
521 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
522 #define MIPS_CONF1_TLBS_SHIFT (25)
523 #define MIPS_CONF1_TLBS_SIZE (6)
524 #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
525
526 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
527 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
528 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
529 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
530 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
531 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
532 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
533 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
534
535 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
536 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
537 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
538 #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
539 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
540 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
541 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
542 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
543 #define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
544 #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
545 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
546 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
547 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
548 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
549 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
550 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
551 #define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
552 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
553 #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
554 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
555 #define MIPS_CONF3_PW (_ULCAST_(1) << 24)
556 #define MIPS_CONF3_SC (_ULCAST_(1) << 25)
557 #define MIPS_CONF3_BI (_ULCAST_(1) << 26)
558 #define MIPS_CONF3_BP (_ULCAST_(1) << 27)
559 #define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
560 #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
561 #define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
562
563 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
564 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
565 #define MIPS_CONF4_FTLBSETS_SHIFT (0)
566 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
567 #define MIPS_CONF4_FTLBWAYS_SHIFT (4)
568 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
569 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
570 /* bits 10:8 in FTLB-only configurations */
571 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
572 /* bits 12:8 in VTLB-FTLB only configurations */
573 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
574 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
575 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
576 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
577 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
578 #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16)
579 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
580 #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
581 #define MIPS_CONF4_AE (_ULCAST_(1) << 28)
582 #define MIPS_CONF4_IE (_ULCAST_(3) << 29)
583 #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
584
585 #define MIPS_CONF5_NF (_ULCAST_(1) << 0)
586 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
587 #define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
588 #define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
589 #define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
590 #define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
591 #define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
592 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
593 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
594 #define MIPS_CONF5_CV (_ULCAST_(1) << 29)
595 #define MIPS_CONF5_K (_ULCAST_(1) << 30)
596
597 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
598 /* proAptiv FTLB on/off bit */
599 #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
600 /* FTLB probability bits */
601 #define MIPS_CONF6_FTLBP_SHIFT (16)
602
603 #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
604
605 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
606
607 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
608 #define MIPS_CONF7_AR (_ULCAST_(1) << 16)
609 /* FTLB probability bits for R6 */
610 #define MIPS_CONF7_FTLBP_SHIFT (18)
611
612 /* MAAR bit definitions */
613 #define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
614 #define MIPS_MAAR_ADDR_SHIFT 12
615 #define MIPS_MAAR_S (_ULCAST_(1) << 1)
616 #define MIPS_MAAR_V (_ULCAST_(1) << 0)
617
618 /* CMGCRBase bit definitions */
619 #define MIPS_CMGCRB_BASE 11
620 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
621
622 /*
623 * Bits in the MIPS32 Memory Segmentation registers.
624 */
625 #define MIPS_SEGCFG_PA_SHIFT 9
626 #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
627 #define MIPS_SEGCFG_AM_SHIFT 4
628 #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
629 #define MIPS_SEGCFG_EU_SHIFT 3
630 #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
631 #define MIPS_SEGCFG_C_SHIFT 0
632 #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
633
634 #define MIPS_SEGCFG_UUSK _ULCAST_(7)
635 #define MIPS_SEGCFG_USK _ULCAST_(5)
636 #define MIPS_SEGCFG_MUSUK _ULCAST_(4)
637 #define MIPS_SEGCFG_MUSK _ULCAST_(3)
638 #define MIPS_SEGCFG_MSK _ULCAST_(2)
639 #define MIPS_SEGCFG_MK _ULCAST_(1)
640 #define MIPS_SEGCFG_UK _ULCAST_(0)
641
642 #define MIPS_PWFIELD_GDI_SHIFT 24
643 #define MIPS_PWFIELD_GDI_MASK 0x3f000000
644 #define MIPS_PWFIELD_UDI_SHIFT 18
645 #define MIPS_PWFIELD_UDI_MASK 0x00fc0000
646 #define MIPS_PWFIELD_MDI_SHIFT 12
647 #define MIPS_PWFIELD_MDI_MASK 0x0003f000
648 #define MIPS_PWFIELD_PTI_SHIFT 6
649 #define MIPS_PWFIELD_PTI_MASK 0x00000fc0
650 #define MIPS_PWFIELD_PTEI_SHIFT 0
651 #define MIPS_PWFIELD_PTEI_MASK 0x0000003f
652
653 #define MIPS_PWSIZE_GDW_SHIFT 24
654 #define MIPS_PWSIZE_GDW_MASK 0x3f000000
655 #define MIPS_PWSIZE_UDW_SHIFT 18
656 #define MIPS_PWSIZE_UDW_MASK 0x00fc0000
657 #define MIPS_PWSIZE_MDW_SHIFT 12
658 #define MIPS_PWSIZE_MDW_MASK 0x0003f000
659 #define MIPS_PWSIZE_PTW_SHIFT 6
660 #define MIPS_PWSIZE_PTW_MASK 0x00000fc0
661 #define MIPS_PWSIZE_PTEW_SHIFT 0
662 #define MIPS_PWSIZE_PTEW_MASK 0x0000003f
663
664 #define MIPS_PWCTL_PWEN_SHIFT 31
665 #define MIPS_PWCTL_PWEN_MASK 0x80000000
666 #define MIPS_PWCTL_DPH_SHIFT 7
667 #define MIPS_PWCTL_DPH_MASK 0x00000080
668 #define MIPS_PWCTL_HUGEPG_SHIFT 6
669 #define MIPS_PWCTL_HUGEPG_MASK 0x00000060
670 #define MIPS_PWCTL_PSN_SHIFT 0
671 #define MIPS_PWCTL_PSN_MASK 0x0000003f
672
673 /* CDMMBase register bit definitions */
674 #define MIPS_CDMMBASE_SIZE_SHIFT 0
675 #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
676 #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
677 #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
678 #define MIPS_CDMMBASE_ADDR_SHIFT 11
679 #define MIPS_CDMMBASE_ADDR_START 15
680
681 /*
682 * Bitfields in the TX39 family CP0 Configuration Register 3
683 */
684 #define TX39_CONF_ICS_SHIFT 19
685 #define TX39_CONF_ICS_MASK 0x00380000
686 #define TX39_CONF_ICS_1KB 0x00000000
687 #define TX39_CONF_ICS_2KB 0x00080000
688 #define TX39_CONF_ICS_4KB 0x00100000
689 #define TX39_CONF_ICS_8KB 0x00180000
690 #define TX39_CONF_ICS_16KB 0x00200000
691
692 #define TX39_CONF_DCS_SHIFT 16
693 #define TX39_CONF_DCS_MASK 0x00070000
694 #define TX39_CONF_DCS_1KB 0x00000000
695 #define TX39_CONF_DCS_2KB 0x00010000
696 #define TX39_CONF_DCS_4KB 0x00020000
697 #define TX39_CONF_DCS_8KB 0x00030000
698 #define TX39_CONF_DCS_16KB 0x00040000
699
700 #define TX39_CONF_CWFON 0x00004000
701 #define TX39_CONF_WBON 0x00002000
702 #define TX39_CONF_RF_SHIFT 10
703 #define TX39_CONF_RF_MASK 0x00000c00
704 #define TX39_CONF_DOZE 0x00000200
705 #define TX39_CONF_HALT 0x00000100
706 #define TX39_CONF_LOCK 0x00000080
707 #define TX39_CONF_ICE 0x00000020
708 #define TX39_CONF_DCE 0x00000010
709 #define TX39_CONF_IRSIZE_SHIFT 2
710 #define TX39_CONF_IRSIZE_MASK 0x0000000c
711 #define TX39_CONF_DRSIZE_SHIFT 0
712 #define TX39_CONF_DRSIZE_MASK 0x00000003
713
714 /*
715 * Interesting Bits in the R10K CP0 Branch Diagnostic Register
716 */
717 /* Disable Branch Target Address Cache */
718 #define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
719 /* Enable Branch Prediction Global History */
720 #define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
721 /* Disable Branch Return Cache */
722 #define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
723
724 /*
725 * Coprocessor 1 (FPU) register names
726 */
727 #define CP1_REVISION $0
728 #define CP1_UFR $1
729 #define CP1_UNFR $4
730 #define CP1_FCCR $25
731 #define CP1_FEXR $26
732 #define CP1_FENR $28
733 #define CP1_STATUS $31
734
735
736 /*
737 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
738 */
739 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
740 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
741 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
742 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
743 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
744 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
745 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
746 #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
747 #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
748 #define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
749
750 /*
751 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
752 */
753 #define MIPS_FCCR_CONDX_S 0
754 #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
755 #define MIPS_FCCR_COND0_S 0
756 #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
757 #define MIPS_FCCR_COND1_S 1
758 #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
759 #define MIPS_FCCR_COND2_S 2
760 #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
761 #define MIPS_FCCR_COND3_S 3
762 #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
763 #define MIPS_FCCR_COND4_S 4
764 #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
765 #define MIPS_FCCR_COND5_S 5
766 #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
767 #define MIPS_FCCR_COND6_S 6
768 #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
769 #define MIPS_FCCR_COND7_S 7
770 #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
771
772 /*
773 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
774 */
775 #define MIPS_FENR_FS_S 2
776 #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
777
778 /*
779 * FPU Status Register Values
780 */
781 #define FPU_CSR_COND_S 23 /* $fcc0 */
782 #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
783
784 #define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
785 #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
786
787 #define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
788 #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
789 #define FPU_CSR_COND1_S 25 /* $fcc1 */
790 #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
791 #define FPU_CSR_COND2_S 26 /* $fcc2 */
792 #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
793 #define FPU_CSR_COND3_S 27 /* $fcc3 */
794 #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
795 #define FPU_CSR_COND4_S 28 /* $fcc4 */
796 #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
797 #define FPU_CSR_COND5_S 29 /* $fcc5 */
798 #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
799 #define FPU_CSR_COND6_S 30 /* $fcc6 */
800 #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
801 #define FPU_CSR_COND7_S 31 /* $fcc7 */
802 #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
803
804 /*
805 * Bits 22:20 of the FPU Status Register will be read as 0,
806 * and should be written as zero.
807 */
808 #define FPU_CSR_RSVD (_ULCAST_(7) << 20)
809
810 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
811 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
812
813 /*
814 * X the exception cause indicator
815 * E the exception enable
816 * S the sticky/flag bit
817 */
818 #define FPU_CSR_ALL_X 0x0003f000
819 #define FPU_CSR_UNI_X 0x00020000
820 #define FPU_CSR_INV_X 0x00010000
821 #define FPU_CSR_DIV_X 0x00008000
822 #define FPU_CSR_OVF_X 0x00004000
823 #define FPU_CSR_UDF_X 0x00002000
824 #define FPU_CSR_INE_X 0x00001000
825
826 #define FPU_CSR_ALL_E 0x00000f80
827 #define FPU_CSR_INV_E 0x00000800
828 #define FPU_CSR_DIV_E 0x00000400
829 #define FPU_CSR_OVF_E 0x00000200
830 #define FPU_CSR_UDF_E 0x00000100
831 #define FPU_CSR_INE_E 0x00000080
832
833 #define FPU_CSR_ALL_S 0x0000007c
834 #define FPU_CSR_INV_S 0x00000040
835 #define FPU_CSR_DIV_S 0x00000020
836 #define FPU_CSR_OVF_S 0x00000010
837 #define FPU_CSR_UDF_S 0x00000008
838 #define FPU_CSR_INE_S 0x00000004
839
840 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
841 #define FPU_CSR_RM 0x00000003
842 #define FPU_CSR_RN 0x0 /* nearest */
843 #define FPU_CSR_RZ 0x1 /* towards zero */
844 #define FPU_CSR_RU 0x2 /* towards +Infinity */
845 #define FPU_CSR_RD 0x3 /* towards -Infinity */
846
847
848 #ifndef __ASSEMBLY__
849
850 /*
851 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
852 */
853 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
854 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
855 #define get_isa16_mode(x) ((x) & 0x1)
856 #define msk_isa16_mode(x) ((x) & ~0x1)
857 #define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
858 #else
859 #define get_isa16_mode(x) 0
860 #define msk_isa16_mode(x) (x)
861 #define set_isa16_mode(x) do { } while(0)
862 #endif
863
864 /*
865 * microMIPS instructions can be 16-bit or 32-bit in length. This
866 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
867 */
868 static inline int mm_insn_16bit(u16 insn)
869 {
870 u16 opcode = (insn >> 10) & 0x7;
871
872 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
873 }
874
875 /*
876 * TLB Invalidate Flush
877 */
878 static inline void tlbinvf(void)
879 {
880 __asm__ __volatile__(
881 ".set push\n\t"
882 ".set noreorder\n\t"
883 ".word 0x42000004\n\t" /* tlbinvf */
884 ".set pop");
885 }
886
887
888 /*
889 * Functions to access the R10000 performance counters. These are basically
890 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
891 * performance counter number encoded into bits 1 ... 5 of the instruction.
892 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
893 * disassembler these will look like an access to sel 0 or 1.
894 */
895 #define read_r10k_perf_cntr(counter) \
896 ({ \
897 unsigned int __res; \
898 __asm__ __volatile__( \
899 "mfpc\t%0, %1" \
900 : "=r" (__res) \
901 : "i" (counter)); \
902 \
903 __res; \
904 })
905
906 #define write_r10k_perf_cntr(counter,val) \
907 do { \
908 __asm__ __volatile__( \
909 "mtpc\t%0, %1" \
910 : \
911 : "r" (val), "i" (counter)); \
912 } while (0)
913
914 #define read_r10k_perf_event(counter) \
915 ({ \
916 unsigned int __res; \
917 __asm__ __volatile__( \
918 "mfps\t%0, %1" \
919 : "=r" (__res) \
920 : "i" (counter)); \
921 \
922 __res; \
923 })
924
925 #define write_r10k_perf_cntl(counter,val) \
926 do { \
927 __asm__ __volatile__( \
928 "mtps\t%0, %1" \
929 : \
930 : "r" (val), "i" (counter)); \
931 } while (0)
932
933
934 /*
935 * Macros to access the system control coprocessor
936 */
937
938 #define __read_32bit_c0_register(source, sel) \
939 ({ unsigned int __res; \
940 if (sel == 0) \
941 __asm__ __volatile__( \
942 "mfc0\t%0, " #source "\n\t" \
943 : "=r" (__res)); \
944 else \
945 __asm__ __volatile__( \
946 ".set\tmips32\n\t" \
947 "mfc0\t%0, " #source ", " #sel "\n\t" \
948 ".set\tmips0\n\t" \
949 : "=r" (__res)); \
950 __res; \
951 })
952
953 #define __read_64bit_c0_register(source, sel) \
954 ({ unsigned long long __res; \
955 if (sizeof(unsigned long) == 4) \
956 __res = __read_64bit_c0_split(source, sel); \
957 else if (sel == 0) \
958 __asm__ __volatile__( \
959 ".set\tmips3\n\t" \
960 "dmfc0\t%0, " #source "\n\t" \
961 ".set\tmips0" \
962 : "=r" (__res)); \
963 else \
964 __asm__ __volatile__( \
965 ".set\tmips64\n\t" \
966 "dmfc0\t%0, " #source ", " #sel "\n\t" \
967 ".set\tmips0" \
968 : "=r" (__res)); \
969 __res; \
970 })
971
972 #define __write_32bit_c0_register(register, sel, value) \
973 do { \
974 if (sel == 0) \
975 __asm__ __volatile__( \
976 "mtc0\t%z0, " #register "\n\t" \
977 : : "Jr" ((unsigned int)(value))); \
978 else \
979 __asm__ __volatile__( \
980 ".set\tmips32\n\t" \
981 "mtc0\t%z0, " #register ", " #sel "\n\t" \
982 ".set\tmips0" \
983 : : "Jr" ((unsigned int)(value))); \
984 } while (0)
985
986 #define __write_64bit_c0_register(register, sel, value) \
987 do { \
988 if (sizeof(unsigned long) == 4) \
989 __write_64bit_c0_split(register, sel, value); \
990 else if (sel == 0) \
991 __asm__ __volatile__( \
992 ".set\tmips3\n\t" \
993 "dmtc0\t%z0, " #register "\n\t" \
994 ".set\tmips0" \
995 : : "Jr" (value)); \
996 else \
997 __asm__ __volatile__( \
998 ".set\tmips64\n\t" \
999 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
1000 ".set\tmips0" \
1001 : : "Jr" (value)); \
1002 } while (0)
1003
1004 #define __read_ulong_c0_register(reg, sel) \
1005 ((sizeof(unsigned long) == 4) ? \
1006 (unsigned long) __read_32bit_c0_register(reg, sel) : \
1007 (unsigned long) __read_64bit_c0_register(reg, sel))
1008
1009 #define __write_ulong_c0_register(reg, sel, val) \
1010 do { \
1011 if (sizeof(unsigned long) == 4) \
1012 __write_32bit_c0_register(reg, sel, val); \
1013 else \
1014 __write_64bit_c0_register(reg, sel, val); \
1015 } while (0)
1016
1017 /*
1018 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1019 */
1020 #define __read_32bit_c0_ctrl_register(source) \
1021 ({ unsigned int __res; \
1022 __asm__ __volatile__( \
1023 "cfc0\t%0, " #source "\n\t" \
1024 : "=r" (__res)); \
1025 __res; \
1026 })
1027
1028 #define __write_32bit_c0_ctrl_register(register, value) \
1029 do { \
1030 __asm__ __volatile__( \
1031 "ctc0\t%z0, " #register "\n\t" \
1032 : : "Jr" ((unsigned int)(value))); \
1033 } while (0)
1034
1035 /*
1036 * These versions are only needed for systems with more than 38 bits of
1037 * physical address space running the 32-bit kernel. That's none atm :-)
1038 */
1039 #define __read_64bit_c0_split(source, sel) \
1040 ({ \
1041 unsigned long long __val; \
1042 unsigned long __flags; \
1043 \
1044 local_irq_save(__flags); \
1045 if (sel == 0) \
1046 __asm__ __volatile__( \
1047 ".set\tmips64\n\t" \
1048 "dmfc0\t%M0, " #source "\n\t" \
1049 "dsll\t%L0, %M0, 32\n\t" \
1050 "dsra\t%M0, %M0, 32\n\t" \
1051 "dsra\t%L0, %L0, 32\n\t" \
1052 ".set\tmips0" \
1053 : "=r" (__val)); \
1054 else \
1055 __asm__ __volatile__( \
1056 ".set\tmips64\n\t" \
1057 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
1058 "dsll\t%L0, %M0, 32\n\t" \
1059 "dsra\t%M0, %M0, 32\n\t" \
1060 "dsra\t%L0, %L0, 32\n\t" \
1061 ".set\tmips0" \
1062 : "=r" (__val)); \
1063 local_irq_restore(__flags); \
1064 \
1065 __val; \
1066 })
1067
1068 #define __write_64bit_c0_split(source, sel, val) \
1069 do { \
1070 unsigned long __flags; \
1071 \
1072 local_irq_save(__flags); \
1073 if (sel == 0) \
1074 __asm__ __volatile__( \
1075 ".set\tmips64\n\t" \
1076 "dsll\t%L0, %L0, 32\n\t" \
1077 "dsrl\t%L0, %L0, 32\n\t" \
1078 "dsll\t%M0, %M0, 32\n\t" \
1079 "or\t%L0, %L0, %M0\n\t" \
1080 "dmtc0\t%L0, " #source "\n\t" \
1081 ".set\tmips0" \
1082 : : "r" (val)); \
1083 else \
1084 __asm__ __volatile__( \
1085 ".set\tmips64\n\t" \
1086 "dsll\t%L0, %L0, 32\n\t" \
1087 "dsrl\t%L0, %L0, 32\n\t" \
1088 "dsll\t%M0, %M0, 32\n\t" \
1089 "or\t%L0, %L0, %M0\n\t" \
1090 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1091 ".set\tmips0" \
1092 : : "r" (val)); \
1093 local_irq_restore(__flags); \
1094 } while (0)
1095
1096 #define __readx_32bit_c0_register(source) \
1097 ({ \
1098 unsigned int __res; \
1099 \
1100 __asm__ __volatile__( \
1101 " .set push \n" \
1102 " .set noat \n" \
1103 " .set mips32r2 \n" \
1104 " .insn \n" \
1105 " # mfhc0 $1, %1 \n" \
1106 " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \
1107 " move %0, $1 \n" \
1108 " .set pop \n" \
1109 : "=r" (__res) \
1110 : "i" (source)); \
1111 __res; \
1112 })
1113
1114 #define __writex_32bit_c0_register(register, value) \
1115 do { \
1116 __asm__ __volatile__( \
1117 " .set push \n" \
1118 " .set noat \n" \
1119 " .set mips32r2 \n" \
1120 " move $1, %0 \n" \
1121 " # mthc0 $1, %1 \n" \
1122 " .insn \n" \
1123 " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \
1124 " .set pop \n" \
1125 : \
1126 : "r" (value), "i" (register)); \
1127 } while (0)
1128
1129 #define read_c0_index() __read_32bit_c0_register($0, 0)
1130 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1131
1132 #define read_c0_random() __read_32bit_c0_register($1, 0)
1133 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1134
1135 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1136 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1137
1138 #define readx_c0_entrylo0() __readx_32bit_c0_register(2)
1139 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1140
1141 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1142 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1143
1144 #define readx_c0_entrylo1() __readx_32bit_c0_register(3)
1145 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1146
1147 #define read_c0_conf() __read_32bit_c0_register($3, 0)
1148 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1149
1150 #define read_c0_context() __read_ulong_c0_register($4, 0)
1151 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1152
1153 #define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1154 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1155
1156 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1157 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1158
1159 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1160 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1161
1162 #define read_c0_wired() __read_32bit_c0_register($6, 0)
1163 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1164
1165 #define read_c0_info() __read_32bit_c0_register($7, 0)
1166
1167 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1168 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1169
1170 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1171 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1172
1173 #define read_c0_count() __read_32bit_c0_register($9, 0)
1174 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1175
1176 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
1177 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
1178
1179 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
1180 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
1181
1182 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1183 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1184
1185 #define read_c0_compare() __read_32bit_c0_register($11, 0)
1186 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1187
1188 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
1189 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
1190
1191 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
1192 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1193
1194 #define read_c0_status() __read_32bit_c0_register($12, 0)
1195
1196 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1197
1198 #define read_c0_cause() __read_32bit_c0_register($13, 0)
1199 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1200
1201 #define read_c0_epc() __read_ulong_c0_register($14, 0)
1202 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1203
1204 #define read_c0_prid() __read_32bit_c0_register($15, 0)
1205
1206 #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1207
1208 #define read_c0_config() __read_32bit_c0_register($16, 0)
1209 #define read_c0_config1() __read_32bit_c0_register($16, 1)
1210 #define read_c0_config2() __read_32bit_c0_register($16, 2)
1211 #define read_c0_config3() __read_32bit_c0_register($16, 3)
1212 #define read_c0_config4() __read_32bit_c0_register($16, 4)
1213 #define read_c0_config5() __read_32bit_c0_register($16, 5)
1214 #define read_c0_config6() __read_32bit_c0_register($16, 6)
1215 #define read_c0_config7() __read_32bit_c0_register($16, 7)
1216 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1217 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1218 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1219 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1220 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1221 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1222 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1223 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1224
1225 #define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1226 #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1227 #define read_c0_maar() __read_ulong_c0_register($17, 1)
1228 #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1229 #define read_c0_maari() __read_32bit_c0_register($17, 2)
1230 #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1231
1232 /*
1233 * The WatchLo register. There may be up to 8 of them.
1234 */
1235 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1236 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1237 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1238 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1239 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1240 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1241 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1242 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1243 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1244 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1245 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1246 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1247 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1248 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1249 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1250 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1251
1252 /*
1253 * The WatchHi register. There may be up to 8 of them.
1254 */
1255 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1256 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1257 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1258 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1259 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1260 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1261 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1262 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1263
1264 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1265 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1266 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1267 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1268 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1269 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1270 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1271 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1272
1273 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1274 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1275
1276 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1277 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1278
1279 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
1280 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1281
1282 #define read_c0_diag() __read_32bit_c0_register($22, 0)
1283 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1284
1285 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1286 #define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1287 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1288
1289 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
1290 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1291
1292 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
1293 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1294
1295 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
1296 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1297
1298 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
1299 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1300
1301 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
1302 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1303
1304 #define read_c0_debug() __read_32bit_c0_register($23, 0)
1305 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1306
1307 #define read_c0_depc() __read_ulong_c0_register($24, 0)
1308 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1309
1310 /*
1311 * MIPS32 / MIPS64 performance counters
1312 */
1313 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1314 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1315 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1316 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1317 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1318 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1319 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1320 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1321 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1322 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1323 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1324 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1325 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1326 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1327 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1328 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1329 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1330 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1331 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1332 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1333 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1334 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1335 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1336 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1337
1338 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
1339 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1340
1341 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1342 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1343
1344 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1345
1346 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1347 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1348
1349 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
1350 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1351
1352 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1353 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1354
1355 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1356 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1357
1358 #define read_c0_staglo() __read_32bit_c0_register($28, 4)
1359 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1360
1361 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
1362 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1363
1364 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1365 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1366
1367 /* MIPSR2 */
1368 #define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1369 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1370
1371 #define read_c0_intctl() __read_32bit_c0_register($12, 1)
1372 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1373
1374 #define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1375 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1376
1377 #define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1378 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1379
1380 #define read_c0_ebase() __read_32bit_c0_register($15, 1)
1381 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1382
1383 #define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1384 #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1385
1386 /* MIPSR3 */
1387 #define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1388 #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1389
1390 #define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1391 #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1392
1393 #define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1394 #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1395
1396 /* Hardware Page Table Walker */
1397 #define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1398 #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1399
1400 #define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1401 #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1402
1403 #define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1404 #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1405
1406 #define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1407 #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1408
1409 /* Cavium OCTEON (cnMIPS) */
1410 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1411 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1412
1413 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1414 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1415
1416 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1417 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1418 /*
1419 * The cacheerr registers are not standardized. On OCTEON, they are
1420 * 64 bits wide.
1421 */
1422 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1423 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1424
1425 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1426 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1427
1428 /* BMIPS3300 */
1429 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1430 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1431
1432 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1433 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1434
1435 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1436 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1437
1438 /* BMIPS43xx */
1439 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1440 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1441
1442 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
1443 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1444
1445 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
1446 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1447
1448 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
1449 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1450
1451 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
1452 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1453
1454 /* BMIPS5000 */
1455 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1456 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1457
1458 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
1459 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1460
1461 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
1462 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1463
1464 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
1465 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1466
1467 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
1468 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1469
1470 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
1471 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1472
1473 /*
1474 * Macros to access the floating point coprocessor control registers
1475 */
1476 #define _read_32bit_cp1_register(source, gas_hardfloat) \
1477 ({ \
1478 unsigned int __res; \
1479 \
1480 __asm__ __volatile__( \
1481 " .set push \n" \
1482 " .set reorder \n" \
1483 " # gas fails to assemble cfc1 for some archs, \n" \
1484 " # like Octeon. \n" \
1485 " .set mips1 \n" \
1486 " "STR(gas_hardfloat)" \n" \
1487 " cfc1 %0,"STR(source)" \n" \
1488 " .set pop \n" \
1489 : "=r" (__res)); \
1490 __res; \
1491 })
1492
1493 #define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
1494 do { \
1495 __asm__ __volatile__( \
1496 " .set push \n" \
1497 " .set reorder \n" \
1498 " "STR(gas_hardfloat)" \n" \
1499 " ctc1 %0,"STR(dest)" \n" \
1500 " .set pop \n" \
1501 : : "r" (val)); \
1502 } while (0)
1503
1504 #ifdef GAS_HAS_SET_HARDFLOAT
1505 #define read_32bit_cp1_register(source) \
1506 _read_32bit_cp1_register(source, .set hardfloat)
1507 #define write_32bit_cp1_register(dest, val) \
1508 _write_32bit_cp1_register(dest, val, .set hardfloat)
1509 #else
1510 #define read_32bit_cp1_register(source) \
1511 _read_32bit_cp1_register(source, )
1512 #define write_32bit_cp1_register(dest, val) \
1513 _write_32bit_cp1_register(dest, val, )
1514 #endif
1515
1516 #ifdef HAVE_AS_DSP
1517 #define rddsp(mask) \
1518 ({ \
1519 unsigned int __dspctl; \
1520 \
1521 __asm__ __volatile__( \
1522 " .set push \n" \
1523 " .set dsp \n" \
1524 " rddsp %0, %x1 \n" \
1525 " .set pop \n" \
1526 : "=r" (__dspctl) \
1527 : "i" (mask)); \
1528 __dspctl; \
1529 })
1530
1531 #define wrdsp(val, mask) \
1532 do { \
1533 __asm__ __volatile__( \
1534 " .set push \n" \
1535 " .set dsp \n" \
1536 " wrdsp %0, %x1 \n" \
1537 " .set pop \n" \
1538 : \
1539 : "r" (val), "i" (mask)); \
1540 } while (0)
1541
1542 #define mflo0() \
1543 ({ \
1544 long mflo0; \
1545 __asm__( \
1546 " .set push \n" \
1547 " .set dsp \n" \
1548 " mflo %0, $ac0 \n" \
1549 " .set pop \n" \
1550 : "=r" (mflo0)); \
1551 mflo0; \
1552 })
1553
1554 #define mflo1() \
1555 ({ \
1556 long mflo1; \
1557 __asm__( \
1558 " .set push \n" \
1559 " .set dsp \n" \
1560 " mflo %0, $ac1 \n" \
1561 " .set pop \n" \
1562 : "=r" (mflo1)); \
1563 mflo1; \
1564 })
1565
1566 #define mflo2() \
1567 ({ \
1568 long mflo2; \
1569 __asm__( \
1570 " .set push \n" \
1571 " .set dsp \n" \
1572 " mflo %0, $ac2 \n" \
1573 " .set pop \n" \
1574 : "=r" (mflo2)); \
1575 mflo2; \
1576 })
1577
1578 #define mflo3() \
1579 ({ \
1580 long mflo3; \
1581 __asm__( \
1582 " .set push \n" \
1583 " .set dsp \n" \
1584 " mflo %0, $ac3 \n" \
1585 " .set pop \n" \
1586 : "=r" (mflo3)); \
1587 mflo3; \
1588 })
1589
1590 #define mfhi0() \
1591 ({ \
1592 long mfhi0; \
1593 __asm__( \
1594 " .set push \n" \
1595 " .set dsp \n" \
1596 " mfhi %0, $ac0 \n" \
1597 " .set pop \n" \
1598 : "=r" (mfhi0)); \
1599 mfhi0; \
1600 })
1601
1602 #define mfhi1() \
1603 ({ \
1604 long mfhi1; \
1605 __asm__( \
1606 " .set push \n" \
1607 " .set dsp \n" \
1608 " mfhi %0, $ac1 \n" \
1609 " .set pop \n" \
1610 : "=r" (mfhi1)); \
1611 mfhi1; \
1612 })
1613
1614 #define mfhi2() \
1615 ({ \
1616 long mfhi2; \
1617 __asm__( \
1618 " .set push \n" \
1619 " .set dsp \n" \
1620 " mfhi %0, $ac2 \n" \
1621 " .set pop \n" \
1622 : "=r" (mfhi2)); \
1623 mfhi2; \
1624 })
1625
1626 #define mfhi3() \
1627 ({ \
1628 long mfhi3; \
1629 __asm__( \
1630 " .set push \n" \
1631 " .set dsp \n" \
1632 " mfhi %0, $ac3 \n" \
1633 " .set pop \n" \
1634 : "=r" (mfhi3)); \
1635 mfhi3; \
1636 })
1637
1638
1639 #define mtlo0(x) \
1640 ({ \
1641 __asm__( \
1642 " .set push \n" \
1643 " .set dsp \n" \
1644 " mtlo %0, $ac0 \n" \
1645 " .set pop \n" \
1646 : \
1647 : "r" (x)); \
1648 })
1649
1650 #define mtlo1(x) \
1651 ({ \
1652 __asm__( \
1653 " .set push \n" \
1654 " .set dsp \n" \
1655 " mtlo %0, $ac1 \n" \
1656 " .set pop \n" \
1657 : \
1658 : "r" (x)); \
1659 })
1660
1661 #define mtlo2(x) \
1662 ({ \
1663 __asm__( \
1664 " .set push \n" \
1665 " .set dsp \n" \
1666 " mtlo %0, $ac2 \n" \
1667 " .set pop \n" \
1668 : \
1669 : "r" (x)); \
1670 })
1671
1672 #define mtlo3(x) \
1673 ({ \
1674 __asm__( \
1675 " .set push \n" \
1676 " .set dsp \n" \
1677 " mtlo %0, $ac3 \n" \
1678 " .set pop \n" \
1679 : \
1680 : "r" (x)); \
1681 })
1682
1683 #define mthi0(x) \
1684 ({ \
1685 __asm__( \
1686 " .set push \n" \
1687 " .set dsp \n" \
1688 " mthi %0, $ac0 \n" \
1689 " .set pop \n" \
1690 : \
1691 : "r" (x)); \
1692 })
1693
1694 #define mthi1(x) \
1695 ({ \
1696 __asm__( \
1697 " .set push \n" \
1698 " .set dsp \n" \
1699 " mthi %0, $ac1 \n" \
1700 " .set pop \n" \
1701 : \
1702 : "r" (x)); \
1703 })
1704
1705 #define mthi2(x) \
1706 ({ \
1707 __asm__( \
1708 " .set push \n" \
1709 " .set dsp \n" \
1710 " mthi %0, $ac2 \n" \
1711 " .set pop \n" \
1712 : \
1713 : "r" (x)); \
1714 })
1715
1716 #define mthi3(x) \
1717 ({ \
1718 __asm__( \
1719 " .set push \n" \
1720 " .set dsp \n" \
1721 " mthi %0, $ac3 \n" \
1722 " .set pop \n" \
1723 : \
1724 : "r" (x)); \
1725 })
1726
1727 #else
1728
1729 #ifdef CONFIG_CPU_MICROMIPS
1730 #define rddsp(mask) \
1731 ({ \
1732 unsigned int __res; \
1733 \
1734 __asm__ __volatile__( \
1735 " .set push \n" \
1736 " .set noat \n" \
1737 " # rddsp $1, %x1 \n" \
1738 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \
1739 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \
1740 " move %0, $1 \n" \
1741 " .set pop \n" \
1742 : "=r" (__res) \
1743 : "i" (mask)); \
1744 __res; \
1745 })
1746
1747 #define wrdsp(val, mask) \
1748 do { \
1749 __asm__ __volatile__( \
1750 " .set push \n" \
1751 " .set noat \n" \
1752 " move $1, %0 \n" \
1753 " # wrdsp $1, %x1 \n" \
1754 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \
1755 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \
1756 " .set pop \n" \
1757 : \
1758 : "r" (val), "i" (mask)); \
1759 } while (0)
1760
1761 #define _umips_dsp_mfxxx(ins) \
1762 ({ \
1763 unsigned long __treg; \
1764 \
1765 __asm__ __volatile__( \
1766 " .set push \n" \
1767 " .set noat \n" \
1768 " .hword 0x0001 \n" \
1769 " .hword %x1 \n" \
1770 " move %0, $1 \n" \
1771 " .set pop \n" \
1772 : "=r" (__treg) \
1773 : "i" (ins)); \
1774 __treg; \
1775 })
1776
1777 #define _umips_dsp_mtxxx(val, ins) \
1778 do { \
1779 __asm__ __volatile__( \
1780 " .set push \n" \
1781 " .set noat \n" \
1782 " move $1, %0 \n" \
1783 " .hword 0x0001 \n" \
1784 " .hword %x1 \n" \
1785 " .set pop \n" \
1786 : \
1787 : "r" (val), "i" (ins)); \
1788 } while (0)
1789
1790 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1791 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1792
1793 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1794 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1795
1796 #define mflo0() _umips_dsp_mflo(0)
1797 #define mflo1() _umips_dsp_mflo(1)
1798 #define mflo2() _umips_dsp_mflo(2)
1799 #define mflo3() _umips_dsp_mflo(3)
1800
1801 #define mfhi0() _umips_dsp_mfhi(0)
1802 #define mfhi1() _umips_dsp_mfhi(1)
1803 #define mfhi2() _umips_dsp_mfhi(2)
1804 #define mfhi3() _umips_dsp_mfhi(3)
1805
1806 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1807 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1808 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1809 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1810
1811 #define mthi0(x) _umips_dsp_mthi(x, 0)
1812 #define mthi1(x) _umips_dsp_mthi(x, 1)
1813 #define mthi2(x) _umips_dsp_mthi(x, 2)
1814 #define mthi3(x) _umips_dsp_mthi(x, 3)
1815
1816 #else /* !CONFIG_CPU_MICROMIPS */
1817 #define rddsp(mask) \
1818 ({ \
1819 unsigned int __res; \
1820 \
1821 __asm__ __volatile__( \
1822 " .set push \n" \
1823 " .set noat \n" \
1824 " # rddsp $1, %x1 \n" \
1825 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1826 " move %0, $1 \n" \
1827 " .set pop \n" \
1828 : "=r" (__res) \
1829 : "i" (mask)); \
1830 __res; \
1831 })
1832
1833 #define wrdsp(val, mask) \
1834 do { \
1835 __asm__ __volatile__( \
1836 " .set push \n" \
1837 " .set noat \n" \
1838 " move $1, %0 \n" \
1839 " # wrdsp $1, %x1 \n" \
1840 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1841 " .set pop \n" \
1842 : \
1843 : "r" (val), "i" (mask)); \
1844 } while (0)
1845
1846 #define _dsp_mfxxx(ins) \
1847 ({ \
1848 unsigned long __treg; \
1849 \
1850 __asm__ __volatile__( \
1851 " .set push \n" \
1852 " .set noat \n" \
1853 " .word (0x00000810 | %1) \n" \
1854 " move %0, $1 \n" \
1855 " .set pop \n" \
1856 : "=r" (__treg) \
1857 : "i" (ins)); \
1858 __treg; \
1859 })
1860
1861 #define _dsp_mtxxx(val, ins) \
1862 do { \
1863 __asm__ __volatile__( \
1864 " .set push \n" \
1865 " .set noat \n" \
1866 " move $1, %0 \n" \
1867 " .word (0x00200011 | %1) \n" \
1868 " .set pop \n" \
1869 : \
1870 : "r" (val), "i" (ins)); \
1871 } while (0)
1872
1873 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1874 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1875
1876 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1877 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1878
1879 #define mflo0() _dsp_mflo(0)
1880 #define mflo1() _dsp_mflo(1)
1881 #define mflo2() _dsp_mflo(2)
1882 #define mflo3() _dsp_mflo(3)
1883
1884 #define mfhi0() _dsp_mfhi(0)
1885 #define mfhi1() _dsp_mfhi(1)
1886 #define mfhi2() _dsp_mfhi(2)
1887 #define mfhi3() _dsp_mfhi(3)
1888
1889 #define mtlo0(x) _dsp_mtlo(x, 0)
1890 #define mtlo1(x) _dsp_mtlo(x, 1)
1891 #define mtlo2(x) _dsp_mtlo(x, 2)
1892 #define mtlo3(x) _dsp_mtlo(x, 3)
1893
1894 #define mthi0(x) _dsp_mthi(x, 0)
1895 #define mthi1(x) _dsp_mthi(x, 1)
1896 #define mthi2(x) _dsp_mthi(x, 2)
1897 #define mthi3(x) _dsp_mthi(x, 3)
1898
1899 #endif /* CONFIG_CPU_MICROMIPS */
1900 #endif
1901
1902 /*
1903 * TLB operations.
1904 *
1905 * It is responsibility of the caller to take care of any TLB hazards.
1906 */
1907 static inline void tlb_probe(void)
1908 {
1909 __asm__ __volatile__(
1910 ".set noreorder\n\t"
1911 "tlbp\n\t"
1912 ".set reorder");
1913 }
1914
1915 static inline void tlb_read(void)
1916 {
1917 #if MIPS34K_MISSED_ITLB_WAR
1918 int res = 0;
1919
1920 __asm__ __volatile__(
1921 " .set push \n"
1922 " .set noreorder \n"
1923 " .set noat \n"
1924 " .set mips32r2 \n"
1925 " .word 0x41610001 # dvpe $1 \n"
1926 " move %0, $1 \n"
1927 " ehb \n"
1928 " .set pop \n"
1929 : "=r" (res));
1930
1931 instruction_hazard();
1932 #endif
1933
1934 __asm__ __volatile__(
1935 ".set noreorder\n\t"
1936 "tlbr\n\t"
1937 ".set reorder");
1938
1939 #if MIPS34K_MISSED_ITLB_WAR
1940 if ((res & _ULCAST_(1)))
1941 __asm__ __volatile__(
1942 " .set push \n"
1943 " .set noreorder \n"
1944 " .set noat \n"
1945 " .set mips32r2 \n"
1946 " .word 0x41600021 # evpe \n"
1947 " ehb \n"
1948 " .set pop \n");
1949 #endif
1950 }
1951
1952 static inline void tlb_write_indexed(void)
1953 {
1954 __asm__ __volatile__(
1955 ".set noreorder\n\t"
1956 "tlbwi\n\t"
1957 ".set reorder");
1958 }
1959
1960 static inline void tlb_write_random(void)
1961 {
1962 __asm__ __volatile__(
1963 ".set noreorder\n\t"
1964 "tlbwr\n\t"
1965 ".set reorder");
1966 }
1967
1968 /*
1969 * Manipulate bits in a c0 register.
1970 */
1971 #define __BUILD_SET_C0(name) \
1972 static inline unsigned int \
1973 set_c0_##name(unsigned int set) \
1974 { \
1975 unsigned int res, new; \
1976 \
1977 res = read_c0_##name(); \
1978 new = res | set; \
1979 write_c0_##name(new); \
1980 \
1981 return res; \
1982 } \
1983 \
1984 static inline unsigned int \
1985 clear_c0_##name(unsigned int clear) \
1986 { \
1987 unsigned int res, new; \
1988 \
1989 res = read_c0_##name(); \
1990 new = res & ~clear; \
1991 write_c0_##name(new); \
1992 \
1993 return res; \
1994 } \
1995 \
1996 static inline unsigned int \
1997 change_c0_##name(unsigned int change, unsigned int val) \
1998 { \
1999 unsigned int res, new; \
2000 \
2001 res = read_c0_##name(); \
2002 new = res & ~change; \
2003 new |= (val & change); \
2004 write_c0_##name(new); \
2005 \
2006 return res; \
2007 }
2008
2009 __BUILD_SET_C0(status)
2010 __BUILD_SET_C0(cause)
2011 __BUILD_SET_C0(config)
2012 __BUILD_SET_C0(config5)
2013 __BUILD_SET_C0(intcontrol)
2014 __BUILD_SET_C0(intctl)
2015 __BUILD_SET_C0(srsmap)
2016 __BUILD_SET_C0(pagegrain)
2017 __BUILD_SET_C0(brcm_config_0)
2018 __BUILD_SET_C0(brcm_bus_pll)
2019 __BUILD_SET_C0(brcm_reset)
2020 __BUILD_SET_C0(brcm_cmt_intr)
2021 __BUILD_SET_C0(brcm_cmt_ctrl)
2022 __BUILD_SET_C0(brcm_config)
2023 __BUILD_SET_C0(brcm_mode)
2024
2025 /*
2026 * Return low 10 bits of ebase.
2027 * Note that under KVM (MIPSVZ) this returns vcpu id.
2028 */
2029 static inline unsigned int get_ebase_cpunum(void)
2030 {
2031 return read_c0_ebase() & 0x3ff;
2032 }
2033
2034 #endif /* !__ASSEMBLY__ */
2035
2036 #endif /* _ASM_MIPSREGS_H */
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