arch/mips/include/asm/netlogic/xlr/gpio.h

   1 /*
   2  * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
   3  * reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the NetLogic
   9  * license below:
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in
  19  *    the documentation and/or other materials provided with the
  20  *    distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #ifndef _ASM_NLM_GPIO_H
  36 #define _ASM_NLM_GPIO_H
  37
  38 #define GPIO_INT_EN_REG                 0
  39 #define GPIO_INPUT_INVERSION_REG        1
  40 #define GPIO_IO_DIR_REG                 2
  41 #define GPIO_IO_DATA_WR_REG             3
  42 #define GPIO_IO_DATA_RD_REG             4
  43
  44 #define GPIO_SWRESET_REG                8
  45 #define GPIO_DRAM1_CNTRL_REG            9
  46 #define GPIO_DRAM1_RATIO_REG            10
  47 #define GPIO_DRAM1_RESET_REG            11
  48 #define GPIO_DRAM1_STATUS_REG           12
  49 #define GPIO_DRAM2_CNTRL_REG            13
  50 #define GPIO_DRAM2_RATIO_REG            14
  51 #define GPIO_DRAM2_RESET_REG            15
  52 #define GPIO_DRAM2_STATUS_REG           16
  53
  54 #define GPIO_PWRON_RESET_CFG_REG        21
  55 #define GPIO_BIST_ALL_GO_STATUS_REG     24
  56 #define GPIO_BIST_CPU_GO_STATUS_REG     25
  57 #define GPIO_BIST_DEV_GO_STATUS_REG     26
  58
  59 #define GPIO_FUSE_BANK_REG              35
  60 #define GPIO_CPU_RESET_REG              40
  61 #define GPIO_RNG_REG                    43
  62
  63 #define PWRON_RESET_PCMCIA_BOOT         17
  64
  65 #define GPIO_LED_BITMAP                 0x1700000
  66 #define GPIO_LED_0_SHIFT                20
  67 #define GPIO_LED_1_SHIFT                24
  68
  69 #define GPIO_LED_OUTPUT_CODE_RESET      0x01
  70 #define GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02
  71 #define GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03
  72 #define GPIO_LED_OUTPUT_CODE_MAIN       0x04
  73
  74 #endif