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blk: rq_data_dir() should not return a boolean
[cris-mirror.git] / arch / mips / include / asm / octeon / cvmx-npei-defs.h
blob58114d414356a1b65f6f0efc15c80e56a0292d57
1 /***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2012 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28 #ifndef __CVMX_NPEI_DEFS_H__
29 #define __CVMX_NPEI_DEFS_H__
30
31 #define CVMX_NPEI_BAR1_INDEXX(offset) (0x0000000000000000ull + ((offset) & 31) * 16)
32 #define CVMX_NPEI_BIST_STATUS (0x0000000000000580ull)
33 #define CVMX_NPEI_BIST_STATUS2 (0x0000000000000680ull)
34 #define CVMX_NPEI_CTL_PORT0 (0x0000000000000250ull)
35 #define CVMX_NPEI_CTL_PORT1 (0x0000000000000260ull)
36 #define CVMX_NPEI_CTL_STATUS (0x0000000000000570ull)
37 #define CVMX_NPEI_CTL_STATUS2 (0x0000000000003C00ull)
38 #define CVMX_NPEI_DATA_OUT_CNT (0x00000000000005F0ull)
39 #define CVMX_NPEI_DBG_DATA (0x0000000000000510ull)
40 #define CVMX_NPEI_DBG_SELECT (0x0000000000000500ull)
41 #define CVMX_NPEI_DMA0_INT_LEVEL (0x00000000000005C0ull)
42 #define CVMX_NPEI_DMA1_INT_LEVEL (0x00000000000005D0ull)
43 #define CVMX_NPEI_DMAX_COUNTS(offset) (0x0000000000000450ull + ((offset) & 7) * 16)
44 #define CVMX_NPEI_DMAX_DBELL(offset) (0x00000000000003B0ull + ((offset) & 7) * 16)
45 #define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) (0x0000000000000400ull + ((offset) & 7) * 16)
46 #define CVMX_NPEI_DMAX_NADDR(offset) (0x00000000000004A0ull + ((offset) & 7) * 16)
47 #define CVMX_NPEI_DMA_CNTS (0x00000000000005E0ull)
48 #define CVMX_NPEI_DMA_CONTROL (0x00000000000003A0ull)
49 #define CVMX_NPEI_DMA_PCIE_REQ_NUM (0x00000000000005B0ull)
50 #define CVMX_NPEI_DMA_STATE1 (0x00000000000006C0ull)
51 #define CVMX_NPEI_DMA_STATE1_P1 (0x0000000000000680ull)
52 #define CVMX_NPEI_DMA_STATE2 (0x00000000000006D0ull)
53 #define CVMX_NPEI_DMA_STATE2_P1 (0x0000000000000690ull)
54 #define CVMX_NPEI_DMA_STATE3_P1 (0x00000000000006A0ull)
55 #define CVMX_NPEI_DMA_STATE4_P1 (0x00000000000006B0ull)
56 #define CVMX_NPEI_DMA_STATE5_P1 (0x00000000000006C0ull)
57 #define CVMX_NPEI_INT_A_ENB (0x0000000000000560ull)
58 #define CVMX_NPEI_INT_A_ENB2 (0x0000000000003CE0ull)
59 #define CVMX_NPEI_INT_A_SUM (0x0000000000000550ull)
60 #define CVMX_NPEI_INT_ENB (0x0000000000000540ull)
61 #define CVMX_NPEI_INT_ENB2 (0x0000000000003CD0ull)
62 #define CVMX_NPEI_INT_INFO (0x0000000000000590ull)
63 #define CVMX_NPEI_INT_SUM (0x0000000000000530ull)
64 #define CVMX_NPEI_INT_SUM2 (0x0000000000003CC0ull)
65 #define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
66 #define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
67 #define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
68 #define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000280ull + ((offset) & 31) * 16 - 16*12)
69 #define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
70 #define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
71 #define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
72 #define CVMX_NPEI_MSI_ENB3 (0x0000000000003C80ull)
73 #define CVMX_NPEI_MSI_RCV0 (0x0000000000003C10ull)
74 #define CVMX_NPEI_MSI_RCV1 (0x0000000000003C20ull)
75 #define CVMX_NPEI_MSI_RCV2 (0x0000000000003C30ull)
76 #define CVMX_NPEI_MSI_RCV3 (0x0000000000003C40ull)
77 #define CVMX_NPEI_MSI_RD_MAP (0x0000000000003CA0ull)
78 #define CVMX_NPEI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
79 #define CVMX_NPEI_MSI_W1C_ENB1 (0x0000000000003D00ull)
80 #define CVMX_NPEI_MSI_W1C_ENB2 (0x0000000000003D10ull)
81 #define CVMX_NPEI_MSI_W1C_ENB3 (0x0000000000003D20ull)
82 #define CVMX_NPEI_MSI_W1S_ENB0 (0x0000000000003D30ull)
83 #define CVMX_NPEI_MSI_W1S_ENB1 (0x0000000000003D40ull)
84 #define CVMX_NPEI_MSI_W1S_ENB2 (0x0000000000003D50ull)
85 #define CVMX_NPEI_MSI_W1S_ENB3 (0x0000000000003D60ull)
86 #define CVMX_NPEI_MSI_WR_MAP (0x0000000000003C90ull)
87 #define CVMX_NPEI_PCIE_CREDIT_CNT (0x0000000000003D70ull)
88 #define CVMX_NPEI_PCIE_MSI_RCV (0x0000000000003CB0ull)
89 #define CVMX_NPEI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
90 #define CVMX_NPEI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
91 #define CVMX_NPEI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
92 #define CVMX_NPEI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
93 #define CVMX_NPEI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
94 #define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
95 #define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
96 #define CVMX_NPEI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
97 #define CVMX_NPEI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
98 #define CVMX_NPEI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
99 #define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
100 #define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
101 #define CVMX_NPEI_PKT_CNT_INT (0x0000000000001110ull)
102 #define CVMX_NPEI_PKT_CNT_INT_ENB (0x0000000000001130ull)
103 #define CVMX_NPEI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
104 #define CVMX_NPEI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
105 #define CVMX_NPEI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
106 #define CVMX_NPEI_PKT_DPADDR (0x0000000000001080ull)
107 #define CVMX_NPEI_PKT_INPUT_CONTROL (0x0000000000001150ull)
108 #define CVMX_NPEI_PKT_INSTR_ENB (0x0000000000001000ull)
109 #define CVMX_NPEI_PKT_INSTR_RD_SIZE (0x0000000000001190ull)
110 #define CVMX_NPEI_PKT_INSTR_SIZE (0x0000000000001020ull)
111 #define CVMX_NPEI_PKT_INT_LEVELS (0x0000000000001100ull)
112 #define CVMX_NPEI_PKT_IN_BP (0x00000000000006B0ull)
113 #define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
114 #define CVMX_NPEI_PKT_IN_INSTR_COUNTS (0x00000000000006A0ull)
115 #define CVMX_NPEI_PKT_IN_PCIE_PORT (0x00000000000011A0ull)
116 #define CVMX_NPEI_PKT_IPTR (0x0000000000001070ull)
117 #define CVMX_NPEI_PKT_OUTPUT_WMARK (0x0000000000001160ull)
118 #define CVMX_NPEI_PKT_OUT_BMODE (0x00000000000010D0ull)
119 #define CVMX_NPEI_PKT_OUT_ENB (0x0000000000001010ull)
120 #define CVMX_NPEI_PKT_PCIE_PORT (0x00000000000010E0ull)
121 #define CVMX_NPEI_PKT_PORT_IN_RST (0x0000000000000690ull)
122 #define CVMX_NPEI_PKT_SLIST_ES (0x0000000000001050ull)
123 #define CVMX_NPEI_PKT_SLIST_ID_SIZE (0x0000000000001180ull)
124 #define CVMX_NPEI_PKT_SLIST_NS (0x0000000000001040ull)
125 #define CVMX_NPEI_PKT_SLIST_ROR (0x0000000000001030ull)
126 #define CVMX_NPEI_PKT_TIME_INT (0x0000000000001120ull)
127 #define CVMX_NPEI_PKT_TIME_INT_ENB (0x0000000000001140ull)
128 #define CVMX_NPEI_RSL_INT_BLOCKS (0x0000000000000520ull)
129 #define CVMX_NPEI_SCRATCH_1 (0x0000000000000270ull)
130 #define CVMX_NPEI_STATE1 (0x0000000000000620ull)
131 #define CVMX_NPEI_STATE2 (0x0000000000000630ull)
132 #define CVMX_NPEI_STATE3 (0x0000000000000640ull)
133 #define CVMX_NPEI_WINDOW_CTL (0x0000000000000380ull)
134 #define CVMX_NPEI_WIN_RD_ADDR (0x0000000000000210ull)
135 #define CVMX_NPEI_WIN_RD_DATA (0x0000000000000240ull)
136 #define CVMX_NPEI_WIN_WR_ADDR (0x0000000000000200ull)
137 #define CVMX_NPEI_WIN_WR_DATA (0x0000000000000220ull)
138 #define CVMX_NPEI_WIN_WR_MASK (0x0000000000000230ull)
139
140 union cvmx_npei_bar1_indexx {
141 uint32_t u32;
142 struct cvmx_npei_bar1_indexx_s {
143 #ifdef __BIG_ENDIAN_BITFIELD
144 uint32_t reserved_18_31:14;
145 uint32_t addr_idx:14;
146 uint32_t ca:1;
147 uint32_t end_swp:2;
148 uint32_t addr_v:1;
149 #else
150 uint32_t addr_v:1;
151 uint32_t end_swp:2;
152 uint32_t ca:1;
153 uint32_t addr_idx:14;
154 uint32_t reserved_18_31:14;
155 #endif
156 } s;
157 struct cvmx_npei_bar1_indexx_s cn52xx;
158 struct cvmx_npei_bar1_indexx_s cn52xxp1;
159 struct cvmx_npei_bar1_indexx_s cn56xx;
160 struct cvmx_npei_bar1_indexx_s cn56xxp1;
161 };
162
163 union cvmx_npei_bist_status {
164 uint64_t u64;
165 struct cvmx_npei_bist_status_s {
166 #ifdef __BIG_ENDIAN_BITFIELD
167 uint64_t pkt_rdf:1;
168 uint64_t reserved_60_62:3;
169 uint64_t pcr_gim:1;
170 uint64_t pkt_pif:1;
171 uint64_t pcsr_int:1;
172 uint64_t pcsr_im:1;
173 uint64_t pcsr_cnt:1;
174 uint64_t pcsr_id:1;
175 uint64_t pcsr_sl:1;
176 uint64_t reserved_50_52:3;
177 uint64_t pkt_ind:1;
178 uint64_t pkt_slm:1;
179 uint64_t reserved_36_47:12;
180 uint64_t d0_pst:1;
181 uint64_t d1_pst:1;
182 uint64_t d2_pst:1;
183 uint64_t d3_pst:1;
184 uint64_t reserved_31_31:1;
185 uint64_t n2p0_c:1;
186 uint64_t n2p0_o:1;
187 uint64_t n2p1_c:1;
188 uint64_t n2p1_o:1;
189 uint64_t cpl_p0:1;
190 uint64_t cpl_p1:1;
191 uint64_t p2n1_po:1;
192 uint64_t p2n1_no:1;
193 uint64_t p2n1_co:1;
194 uint64_t p2n0_po:1;
195 uint64_t p2n0_no:1;
196 uint64_t p2n0_co:1;
197 uint64_t p2n0_c0:1;
198 uint64_t p2n0_c1:1;
199 uint64_t p2n0_n:1;
200 uint64_t p2n0_p0:1;
201 uint64_t p2n0_p1:1;
202 uint64_t p2n1_c0:1;
203 uint64_t p2n1_c1:1;
204 uint64_t p2n1_n:1;
205 uint64_t p2n1_p0:1;
206 uint64_t p2n1_p1:1;
207 uint64_t csm0:1;
208 uint64_t csm1:1;
209 uint64_t dif0:1;
210 uint64_t dif1:1;
211 uint64_t dif2:1;
212 uint64_t dif3:1;
213 uint64_t reserved_2_2:1;
214 uint64_t msi:1;
215 uint64_t ncb_cmd:1;
216 #else
217 uint64_t ncb_cmd:1;
218 uint64_t msi:1;
219 uint64_t reserved_2_2:1;
220 uint64_t dif3:1;
221 uint64_t dif2:1;
222 uint64_t dif1:1;
223 uint64_t dif0:1;
224 uint64_t csm1:1;
225 uint64_t csm0:1;
226 uint64_t p2n1_p1:1;
227 uint64_t p2n1_p0:1;
228 uint64_t p2n1_n:1;
229 uint64_t p2n1_c1:1;
230 uint64_t p2n1_c0:1;
231 uint64_t p2n0_p1:1;
232 uint64_t p2n0_p0:1;
233 uint64_t p2n0_n:1;
234 uint64_t p2n0_c1:1;
235 uint64_t p2n0_c0:1;
236 uint64_t p2n0_co:1;
237 uint64_t p2n0_no:1;
238 uint64_t p2n0_po:1;
239 uint64_t p2n1_co:1;
240 uint64_t p2n1_no:1;
241 uint64_t p2n1_po:1;
242 uint64_t cpl_p1:1;
243 uint64_t cpl_p0:1;
244 uint64_t n2p1_o:1;
245 uint64_t n2p1_c:1;
246 uint64_t n2p0_o:1;
247 uint64_t n2p0_c:1;
248 uint64_t reserved_31_31:1;
249 uint64_t d3_pst:1;
250 uint64_t d2_pst:1;
251 uint64_t d1_pst:1;
252 uint64_t d0_pst:1;
253 uint64_t reserved_36_47:12;
254 uint64_t pkt_slm:1;
255 uint64_t pkt_ind:1;
256 uint64_t reserved_50_52:3;
257 uint64_t pcsr_sl:1;
258 uint64_t pcsr_id:1;
259 uint64_t pcsr_cnt:1;
260 uint64_t pcsr_im:1;
261 uint64_t pcsr_int:1;
262 uint64_t pkt_pif:1;
263 uint64_t pcr_gim:1;
264 uint64_t reserved_60_62:3;
265 uint64_t pkt_rdf:1;
266 #endif
267 } s;
268 struct cvmx_npei_bist_status_cn52xx {
269 #ifdef __BIG_ENDIAN_BITFIELD
270 uint64_t pkt_rdf:1;
271 uint64_t reserved_60_62:3;
272 uint64_t pcr_gim:1;
273 uint64_t pkt_pif:1;
274 uint64_t pcsr_int:1;
275 uint64_t pcsr_im:1;
276 uint64_t pcsr_cnt:1;
277 uint64_t pcsr_id:1;
278 uint64_t pcsr_sl:1;
279 uint64_t pkt_imem:1;
280 uint64_t pkt_pfm:1;
281 uint64_t pkt_pof:1;
282 uint64_t reserved_48_49:2;
283 uint64_t pkt_pop0:1;
284 uint64_t pkt_pop1:1;
285 uint64_t d0_mem:1;
286 uint64_t d1_mem:1;
287 uint64_t d2_mem:1;
288 uint64_t d3_mem:1;
289 uint64_t d4_mem:1;
290 uint64_t ds_mem:1;
291 uint64_t reserved_36_39:4;
292 uint64_t d0_pst:1;
293 uint64_t d1_pst:1;
294 uint64_t d2_pst:1;
295 uint64_t d3_pst:1;
296 uint64_t d4_pst:1;
297 uint64_t n2p0_c:1;
298 uint64_t n2p0_o:1;
299 uint64_t n2p1_c:1;
300 uint64_t n2p1_o:1;
301 uint64_t cpl_p0:1;
302 uint64_t cpl_p1:1;
303 uint64_t p2n1_po:1;
304 uint64_t p2n1_no:1;
305 uint64_t p2n1_co:1;
306 uint64_t p2n0_po:1;
307 uint64_t p2n0_no:1;
308 uint64_t p2n0_co:1;
309 uint64_t p2n0_c0:1;
310 uint64_t p2n0_c1:1;
311 uint64_t p2n0_n:1;
312 uint64_t p2n0_p0:1;
313 uint64_t p2n0_p1:1;
314 uint64_t p2n1_c0:1;
315 uint64_t p2n1_c1:1;
316 uint64_t p2n1_n:1;
317 uint64_t p2n1_p0:1;
318 uint64_t p2n1_p1:1;
319 uint64_t csm0:1;
320 uint64_t csm1:1;
321 uint64_t dif0:1;
322 uint64_t dif1:1;
323 uint64_t dif2:1;
324 uint64_t dif3:1;
325 uint64_t dif4:1;
326 uint64_t msi:1;
327 uint64_t ncb_cmd:1;
328 #else
329 uint64_t ncb_cmd:1;
330 uint64_t msi:1;
331 uint64_t dif4:1;
332 uint64_t dif3:1;
333 uint64_t dif2:1;
334 uint64_t dif1:1;
335 uint64_t dif0:1;
336 uint64_t csm1:1;
337 uint64_t csm0:1;
338 uint64_t p2n1_p1:1;
339 uint64_t p2n1_p0:1;
340 uint64_t p2n1_n:1;
341 uint64_t p2n1_c1:1;
342 uint64_t p2n1_c0:1;
343 uint64_t p2n0_p1:1;
344 uint64_t p2n0_p0:1;
345 uint64_t p2n0_n:1;
346 uint64_t p2n0_c1:1;
347 uint64_t p2n0_c0:1;
348 uint64_t p2n0_co:1;
349 uint64_t p2n0_no:1;
350 uint64_t p2n0_po:1;
351 uint64_t p2n1_co:1;
352 uint64_t p2n1_no:1;
353 uint64_t p2n1_po:1;
354 uint64_t cpl_p1:1;
355 uint64_t cpl_p0:1;
356 uint64_t n2p1_o:1;
357 uint64_t n2p1_c:1;
358 uint64_t n2p0_o:1;
359 uint64_t n2p0_c:1;
360 uint64_t d4_pst:1;
361 uint64_t d3_pst:1;
362 uint64_t d2_pst:1;
363 uint64_t d1_pst:1;
364 uint64_t d0_pst:1;
365 uint64_t reserved_36_39:4;
366 uint64_t ds_mem:1;
367 uint64_t d4_mem:1;
368 uint64_t d3_mem:1;
369 uint64_t d2_mem:1;
370 uint64_t d1_mem:1;
371 uint64_t d0_mem:1;
372 uint64_t pkt_pop1:1;
373 uint64_t pkt_pop0:1;
374 uint64_t reserved_48_49:2;
375 uint64_t pkt_pof:1;
376 uint64_t pkt_pfm:1;
377 uint64_t pkt_imem:1;
378 uint64_t pcsr_sl:1;
379 uint64_t pcsr_id:1;
380 uint64_t pcsr_cnt:1;
381 uint64_t pcsr_im:1;
382 uint64_t pcsr_int:1;
383 uint64_t pkt_pif:1;
384 uint64_t pcr_gim:1;
385 uint64_t reserved_60_62:3;
386 uint64_t pkt_rdf:1;
387 #endif
388 } cn52xx;
389 struct cvmx_npei_bist_status_cn52xxp1 {
390 #ifdef __BIG_ENDIAN_BITFIELD
391 uint64_t reserved_46_63:18;
392 uint64_t d0_mem0:1;
393 uint64_t d1_mem1:1;
394 uint64_t d2_mem2:1;
395 uint64_t d3_mem3:1;
396 uint64_t dr0_mem:1;
397 uint64_t d0_mem:1;
398 uint64_t d1_mem:1;
399 uint64_t d2_mem:1;
400 uint64_t d3_mem:1;
401 uint64_t dr1_mem:1;
402 uint64_t d0_pst:1;
403 uint64_t d1_pst:1;
404 uint64_t d2_pst:1;
405 uint64_t d3_pst:1;
406 uint64_t dr2_mem:1;
407 uint64_t n2p0_c:1;
408 uint64_t n2p0_o:1;
409 uint64_t n2p1_c:1;
410 uint64_t n2p1_o:1;
411 uint64_t cpl_p0:1;
412 uint64_t cpl_p1:1;
413 uint64_t p2n1_po:1;
414 uint64_t p2n1_no:1;
415 uint64_t p2n1_co:1;
416 uint64_t p2n0_po:1;
417 uint64_t p2n0_no:1;
418 uint64_t p2n0_co:1;
419 uint64_t p2n0_c0:1;
420 uint64_t p2n0_c1:1;
421 uint64_t p2n0_n:1;
422 uint64_t p2n0_p0:1;
423 uint64_t p2n0_p1:1;
424 uint64_t p2n1_c0:1;
425 uint64_t p2n1_c1:1;
426 uint64_t p2n1_n:1;
427 uint64_t p2n1_p0:1;
428 uint64_t p2n1_p1:1;
429 uint64_t csm0:1;
430 uint64_t csm1:1;
431 uint64_t dif0:1;
432 uint64_t dif1:1;
433 uint64_t dif2:1;
434 uint64_t dif3:1;
435 uint64_t dr3_mem:1;
436 uint64_t msi:1;
437 uint64_t ncb_cmd:1;
438 #else
439 uint64_t ncb_cmd:1;
440 uint64_t msi:1;
441 uint64_t dr3_mem:1;
442 uint64_t dif3:1;
443 uint64_t dif2:1;
444 uint64_t dif1:1;
445 uint64_t dif0:1;
446 uint64_t csm1:1;
447 uint64_t csm0:1;
448 uint64_t p2n1_p1:1;
449 uint64_t p2n1_p0:1;
450 uint64_t p2n1_n:1;
451 uint64_t p2n1_c1:1;
452 uint64_t p2n1_c0:1;
453 uint64_t p2n0_p1:1;
454 uint64_t p2n0_p0:1;
455 uint64_t p2n0_n:1;
456 uint64_t p2n0_c1:1;
457 uint64_t p2n0_c0:1;
458 uint64_t p2n0_co:1;
459 uint64_t p2n0_no:1;
460 uint64_t p2n0_po:1;
461 uint64_t p2n1_co:1;
462 uint64_t p2n1_no:1;
463 uint64_t p2n1_po:1;
464 uint64_t cpl_p1:1;
465 uint64_t cpl_p0:1;
466 uint64_t n2p1_o:1;
467 uint64_t n2p1_c:1;
468 uint64_t n2p0_o:1;
469 uint64_t n2p0_c:1;
470 uint64_t dr2_mem:1;
471 uint64_t d3_pst:1;
472 uint64_t d2_pst:1;
473 uint64_t d1_pst:1;
474 uint64_t d0_pst:1;
475 uint64_t dr1_mem:1;
476 uint64_t d3_mem:1;
477 uint64_t d2_mem:1;
478 uint64_t d1_mem:1;
479 uint64_t d0_mem:1;
480 uint64_t dr0_mem:1;
481 uint64_t d3_mem3:1;
482 uint64_t d2_mem2:1;
483 uint64_t d1_mem1:1;
484 uint64_t d0_mem0:1;
485 uint64_t reserved_46_63:18;
486 #endif
487 } cn52xxp1;
488 struct cvmx_npei_bist_status_cn52xx cn56xx;
489 struct cvmx_npei_bist_status_cn56xxp1 {
490 #ifdef __BIG_ENDIAN_BITFIELD
491 uint64_t reserved_58_63:6;
492 uint64_t pcsr_int:1;
493 uint64_t pcsr_im:1;
494 uint64_t pcsr_cnt:1;
495 uint64_t pcsr_id:1;
496 uint64_t pcsr_sl:1;
497 uint64_t pkt_pout:1;
498 uint64_t pkt_imem:1;
499 uint64_t pkt_cntm:1;
500 uint64_t pkt_ind:1;
501 uint64_t pkt_slm:1;
502 uint64_t pkt_odf:1;
503 uint64_t pkt_oif:1;
504 uint64_t pkt_out:1;
505 uint64_t pkt_i0:1;
506 uint64_t pkt_i1:1;
507 uint64_t pkt_s0:1;
508 uint64_t pkt_s1:1;
509 uint64_t d0_mem:1;
510 uint64_t d1_mem:1;
511 uint64_t d2_mem:1;
512 uint64_t d3_mem:1;
513 uint64_t d4_mem:1;
514 uint64_t d0_pst:1;
515 uint64_t d1_pst:1;
516 uint64_t d2_pst:1;
517 uint64_t d3_pst:1;
518 uint64_t d4_pst:1;
519 uint64_t n2p0_c:1;
520 uint64_t n2p0_o:1;
521 uint64_t n2p1_c:1;
522 uint64_t n2p1_o:1;
523 uint64_t cpl_p0:1;
524 uint64_t cpl_p1:1;
525 uint64_t p2n1_po:1;
526 uint64_t p2n1_no:1;
527 uint64_t p2n1_co:1;
528 uint64_t p2n0_po:1;
529 uint64_t p2n0_no:1;
530 uint64_t p2n0_co:1;
531 uint64_t p2n0_c0:1;
532 uint64_t p2n0_c1:1;
533 uint64_t p2n0_n:1;
534 uint64_t p2n0_p0:1;
535 uint64_t p2n0_p1:1;
536 uint64_t p2n1_c0:1;
537 uint64_t p2n1_c1:1;
538 uint64_t p2n1_n:1;
539 uint64_t p2n1_p0:1;
540 uint64_t p2n1_p1:1;
541 uint64_t csm0:1;
542 uint64_t csm1:1;
543 uint64_t dif0:1;
544 uint64_t dif1:1;
545 uint64_t dif2:1;
546 uint64_t dif3:1;
547 uint64_t dif4:1;
548 uint64_t msi:1;
549 uint64_t ncb_cmd:1;
550 #else
551 uint64_t ncb_cmd:1;
552 uint64_t msi:1;
553 uint64_t dif4:1;
554 uint64_t dif3:1;
555 uint64_t dif2:1;
556 uint64_t dif1:1;
557 uint64_t dif0:1;
558 uint64_t csm1:1;
559 uint64_t csm0:1;
560 uint64_t p2n1_p1:1;
561 uint64_t p2n1_p0:1;
562 uint64_t p2n1_n:1;
563 uint64_t p2n1_c1:1;
564 uint64_t p2n1_c0:1;
565 uint64_t p2n0_p1:1;
566 uint64_t p2n0_p0:1;
567 uint64_t p2n0_n:1;
568 uint64_t p2n0_c1:1;
569 uint64_t p2n0_c0:1;
570 uint64_t p2n0_co:1;
571 uint64_t p2n0_no:1;
572 uint64_t p2n0_po:1;
573 uint64_t p2n1_co:1;
574 uint64_t p2n1_no:1;
575 uint64_t p2n1_po:1;
576 uint64_t cpl_p1:1;
577 uint64_t cpl_p0:1;
578 uint64_t n2p1_o:1;
579 uint64_t n2p1_c:1;
580 uint64_t n2p0_o:1;
581 uint64_t n2p0_c:1;
582 uint64_t d4_pst:1;
583 uint64_t d3_pst:1;
584 uint64_t d2_pst:1;
585 uint64_t d1_pst:1;
586 uint64_t d0_pst:1;
587 uint64_t d4_mem:1;
588 uint64_t d3_mem:1;
589 uint64_t d2_mem:1;
590 uint64_t d1_mem:1;
591 uint64_t d0_mem:1;
592 uint64_t pkt_s1:1;
593 uint64_t pkt_s0:1;
594 uint64_t pkt_i1:1;
595 uint64_t pkt_i0:1;
596 uint64_t pkt_out:1;
597 uint64_t pkt_oif:1;
598 uint64_t pkt_odf:1;
599 uint64_t pkt_slm:1;
600 uint64_t pkt_ind:1;
601 uint64_t pkt_cntm:1;
602 uint64_t pkt_imem:1;
603 uint64_t pkt_pout:1;
604 uint64_t pcsr_sl:1;
605 uint64_t pcsr_id:1;
606 uint64_t pcsr_cnt:1;
607 uint64_t pcsr_im:1;
608 uint64_t pcsr_int:1;
609 uint64_t reserved_58_63:6;
610 #endif
611 } cn56xxp1;
612 };
613
614 union cvmx_npei_bist_status2 {
615 uint64_t u64;
616 struct cvmx_npei_bist_status2_s {
617 #ifdef __BIG_ENDIAN_BITFIELD
618 uint64_t reserved_14_63:50;
619 uint64_t prd_tag:1;
620 uint64_t prd_st0:1;
621 uint64_t prd_st1:1;
622 uint64_t prd_err:1;
623 uint64_t nrd_st:1;
624 uint64_t nwe_st:1;
625 uint64_t nwe_wr0:1;
626 uint64_t nwe_wr1:1;
627 uint64_t pkt_rd:1;
628 uint64_t psc_p0:1;
629 uint64_t psc_p1:1;
630 uint64_t pkt_gd:1;
631 uint64_t pkt_gl:1;
632 uint64_t pkt_blk:1;
633 #else
634 uint64_t pkt_blk:1;
635 uint64_t pkt_gl:1;
636 uint64_t pkt_gd:1;
637 uint64_t psc_p1:1;
638 uint64_t psc_p0:1;
639 uint64_t pkt_rd:1;
640 uint64_t nwe_wr1:1;
641 uint64_t nwe_wr0:1;
642 uint64_t nwe_st:1;
643 uint64_t nrd_st:1;
644 uint64_t prd_err:1;
645 uint64_t prd_st1:1;
646 uint64_t prd_st0:1;
647 uint64_t prd_tag:1;
648 uint64_t reserved_14_63:50;
649 #endif
650 } s;
651 struct cvmx_npei_bist_status2_s cn52xx;
652 struct cvmx_npei_bist_status2_s cn56xx;
653 };
654
655 union cvmx_npei_ctl_port0 {
656 uint64_t u64;
657 struct cvmx_npei_ctl_port0_s {
658 #ifdef __BIG_ENDIAN_BITFIELD
659 uint64_t reserved_21_63:43;
660 uint64_t waitl_com:1;
661 uint64_t intd:1;
662 uint64_t intc:1;
663 uint64_t intb:1;
664 uint64_t inta:1;
665 uint64_t intd_map:2;
666 uint64_t intc_map:2;
667 uint64_t intb_map:2;
668 uint64_t inta_map:2;
669 uint64_t ctlp_ro:1;
670 uint64_t reserved_6_6:1;
671 uint64_t ptlp_ro:1;
672 uint64_t bar2_enb:1;
673 uint64_t bar2_esx:2;
674 uint64_t bar2_cax:1;
675 uint64_t wait_com:1;
676 #else
677 uint64_t wait_com:1;
678 uint64_t bar2_cax:1;
679 uint64_t bar2_esx:2;
680 uint64_t bar2_enb:1;
681 uint64_t ptlp_ro:1;
682 uint64_t reserved_6_6:1;
683 uint64_t ctlp_ro:1;
684 uint64_t inta_map:2;
685 uint64_t intb_map:2;
686 uint64_t intc_map:2;
687 uint64_t intd_map:2;
688 uint64_t inta:1;
689 uint64_t intb:1;
690 uint64_t intc:1;
691 uint64_t intd:1;
692 uint64_t waitl_com:1;
693 uint64_t reserved_21_63:43;
694 #endif
695 } s;
696 struct cvmx_npei_ctl_port0_s cn52xx;
697 struct cvmx_npei_ctl_port0_s cn52xxp1;
698 struct cvmx_npei_ctl_port0_s cn56xx;
699 struct cvmx_npei_ctl_port0_s cn56xxp1;
700 };
701
702 union cvmx_npei_ctl_port1 {
703 uint64_t u64;
704 struct cvmx_npei_ctl_port1_s {
705 #ifdef __BIG_ENDIAN_BITFIELD
706 uint64_t reserved_21_63:43;
707 uint64_t waitl_com:1;
708 uint64_t intd:1;
709 uint64_t intc:1;
710 uint64_t intb:1;
711 uint64_t inta:1;
712 uint64_t intd_map:2;
713 uint64_t intc_map:2;
714 uint64_t intb_map:2;
715 uint64_t inta_map:2;
716 uint64_t ctlp_ro:1;
717 uint64_t reserved_6_6:1;
718 uint64_t ptlp_ro:1;
719 uint64_t bar2_enb:1;
720 uint64_t bar2_esx:2;
721 uint64_t bar2_cax:1;
722 uint64_t wait_com:1;
723 #else
724 uint64_t wait_com:1;
725 uint64_t bar2_cax:1;
726 uint64_t bar2_esx:2;
727 uint64_t bar2_enb:1;
728 uint64_t ptlp_ro:1;
729 uint64_t reserved_6_6:1;
730 uint64_t ctlp_ro:1;
731 uint64_t inta_map:2;
732 uint64_t intb_map:2;
733 uint64_t intc_map:2;
734 uint64_t intd_map:2;
735 uint64_t inta:1;
736 uint64_t intb:1;
737 uint64_t intc:1;
738 uint64_t intd:1;
739 uint64_t waitl_com:1;
740 uint64_t reserved_21_63:43;
741 #endif
742 } s;
743 struct cvmx_npei_ctl_port1_s cn52xx;
744 struct cvmx_npei_ctl_port1_s cn52xxp1;
745 struct cvmx_npei_ctl_port1_s cn56xx;
746 struct cvmx_npei_ctl_port1_s cn56xxp1;
747 };
748
749 union cvmx_npei_ctl_status {
750 uint64_t u64;
751 struct cvmx_npei_ctl_status_s {
752 #ifdef __BIG_ENDIAN_BITFIELD
753 uint64_t reserved_44_63:20;
754 uint64_t p1_ntags:6;
755 uint64_t p0_ntags:6;
756 uint64_t cfg_rtry:16;
757 uint64_t ring_en:1;
758 uint64_t lnk_rst:1;
759 uint64_t arb:1;
760 uint64_t pkt_bp:4;
761 uint64_t host_mode:1;
762 uint64_t chip_rev:8;
763 #else
764 uint64_t chip_rev:8;
765 uint64_t host_mode:1;
766 uint64_t pkt_bp:4;
767 uint64_t arb:1;
768 uint64_t lnk_rst:1;
769 uint64_t ring_en:1;
770 uint64_t cfg_rtry:16;
771 uint64_t p0_ntags:6;
772 uint64_t p1_ntags:6;
773 uint64_t reserved_44_63:20;
774 #endif
775 } s;
776 struct cvmx_npei_ctl_status_s cn52xx;
777 struct cvmx_npei_ctl_status_cn52xxp1 {
778 #ifdef __BIG_ENDIAN_BITFIELD
779 uint64_t reserved_44_63:20;
780 uint64_t p1_ntags:6;
781 uint64_t p0_ntags:6;
782 uint64_t cfg_rtry:16;
783 uint64_t reserved_15_15:1;
784 uint64_t lnk_rst:1;
785 uint64_t arb:1;
786 uint64_t reserved_9_12:4;
787 uint64_t host_mode:1;
788 uint64_t chip_rev:8;
789 #else
790 uint64_t chip_rev:8;
791 uint64_t host_mode:1;
792 uint64_t reserved_9_12:4;
793 uint64_t arb:1;
794 uint64_t lnk_rst:1;
795 uint64_t reserved_15_15:1;
796 uint64_t cfg_rtry:16;
797 uint64_t p0_ntags:6;
798 uint64_t p1_ntags:6;
799 uint64_t reserved_44_63:20;
800 #endif
801 } cn52xxp1;
802 struct cvmx_npei_ctl_status_s cn56xx;
803 struct cvmx_npei_ctl_status_cn56xxp1 {
804 #ifdef __BIG_ENDIAN_BITFIELD
805 uint64_t reserved_15_63:49;
806 uint64_t lnk_rst:1;
807 uint64_t arb:1;
808 uint64_t pkt_bp:4;
809 uint64_t host_mode:1;
810 uint64_t chip_rev:8;
811 #else
812 uint64_t chip_rev:8;
813 uint64_t host_mode:1;
814 uint64_t pkt_bp:4;
815 uint64_t arb:1;
816 uint64_t lnk_rst:1;
817 uint64_t reserved_15_63:49;
818 #endif
819 } cn56xxp1;
820 };
821
822 union cvmx_npei_ctl_status2 {
823 uint64_t u64;
824 struct cvmx_npei_ctl_status2_s {
825 #ifdef __BIG_ENDIAN_BITFIELD
826 uint64_t reserved_16_63:48;
827 uint64_t mps:1;
828 uint64_t mrrs:3;
829 uint64_t c1_w_flt:1;
830 uint64_t c0_w_flt:1;
831 uint64_t c1_b1_s:3;
832 uint64_t c0_b1_s:3;
833 uint64_t c1_wi_d:1;
834 uint64_t c1_b0_d:1;
835 uint64_t c0_wi_d:1;
836 uint64_t c0_b0_d:1;
837 #else
838 uint64_t c0_b0_d:1;
839 uint64_t c0_wi_d:1;
840 uint64_t c1_b0_d:1;
841 uint64_t c1_wi_d:1;
842 uint64_t c0_b1_s:3;
843 uint64_t c1_b1_s:3;
844 uint64_t c0_w_flt:1;
845 uint64_t c1_w_flt:1;
846 uint64_t mrrs:3;
847 uint64_t mps:1;
848 uint64_t reserved_16_63:48;
849 #endif
850 } s;
851 struct cvmx_npei_ctl_status2_s cn52xx;
852 struct cvmx_npei_ctl_status2_s cn52xxp1;
853 struct cvmx_npei_ctl_status2_s cn56xx;
854 struct cvmx_npei_ctl_status2_s cn56xxp1;
855 };
856
857 union cvmx_npei_data_out_cnt {
858 uint64_t u64;
859 struct cvmx_npei_data_out_cnt_s {
860 #ifdef __BIG_ENDIAN_BITFIELD
861 uint64_t reserved_44_63:20;
862 uint64_t p1_ucnt:16;
863 uint64_t p1_fcnt:6;
864 uint64_t p0_ucnt:16;
865 uint64_t p0_fcnt:6;
866 #else
867 uint64_t p0_fcnt:6;
868 uint64_t p0_ucnt:16;
869 uint64_t p1_fcnt:6;
870 uint64_t p1_ucnt:16;
871 uint64_t reserved_44_63:20;
872 #endif
873 } s;
874 struct cvmx_npei_data_out_cnt_s cn52xx;
875 struct cvmx_npei_data_out_cnt_s cn52xxp1;
876 struct cvmx_npei_data_out_cnt_s cn56xx;
877 struct cvmx_npei_data_out_cnt_s cn56xxp1;
878 };
879
880 union cvmx_npei_dbg_data {
881 uint64_t u64;
882 struct cvmx_npei_dbg_data_s {
883 #ifdef __BIG_ENDIAN_BITFIELD
884 uint64_t reserved_28_63:36;
885 uint64_t qlm0_rev_lanes:1;
886 uint64_t reserved_25_26:2;
887 uint64_t qlm1_spd:2;
888 uint64_t c_mul:5;
889 uint64_t dsel_ext:1;
890 uint64_t data:17;
891 #else
892 uint64_t data:17;
893 uint64_t dsel_ext:1;
894 uint64_t c_mul:5;
895 uint64_t qlm1_spd:2;
896 uint64_t reserved_25_26:2;
897 uint64_t qlm0_rev_lanes:1;
898 uint64_t reserved_28_63:36;
899 #endif
900 } s;
901 struct cvmx_npei_dbg_data_cn52xx {
902 #ifdef __BIG_ENDIAN_BITFIELD
903 uint64_t reserved_29_63:35;
904 uint64_t qlm0_link_width:1;
905 uint64_t qlm0_rev_lanes:1;
906 uint64_t qlm1_mode:2;
907 uint64_t qlm1_spd:2;
908 uint64_t c_mul:5;
909 uint64_t dsel_ext:1;
910 uint64_t data:17;
911 #else
912 uint64_t data:17;
913 uint64_t dsel_ext:1;
914 uint64_t c_mul:5;
915 uint64_t qlm1_spd:2;
916 uint64_t qlm1_mode:2;
917 uint64_t qlm0_rev_lanes:1;
918 uint64_t qlm0_link_width:1;
919 uint64_t reserved_29_63:35;
920 #endif
921 } cn52xx;
922 struct cvmx_npei_dbg_data_cn52xx cn52xxp1;
923 struct cvmx_npei_dbg_data_cn56xx {
924 #ifdef __BIG_ENDIAN_BITFIELD
925 uint64_t reserved_29_63:35;
926 uint64_t qlm2_rev_lanes:1;
927 uint64_t qlm0_rev_lanes:1;
928 uint64_t qlm3_spd:2;
929 uint64_t qlm1_spd:2;
930 uint64_t c_mul:5;
931 uint64_t dsel_ext:1;
932 uint64_t data:17;
933 #else
934 uint64_t data:17;
935 uint64_t dsel_ext:1;
936 uint64_t c_mul:5;
937 uint64_t qlm1_spd:2;
938 uint64_t qlm3_spd:2;
939 uint64_t qlm0_rev_lanes:1;
940 uint64_t qlm2_rev_lanes:1;
941 uint64_t reserved_29_63:35;
942 #endif
943 } cn56xx;
944 struct cvmx_npei_dbg_data_cn56xx cn56xxp1;
945 };
946
947 union cvmx_npei_dbg_select {
948 uint64_t u64;
949 struct cvmx_npei_dbg_select_s {
950 #ifdef __BIG_ENDIAN_BITFIELD
951 uint64_t reserved_16_63:48;
952 uint64_t dbg_sel:16;
953 #else
954 uint64_t dbg_sel:16;
955 uint64_t reserved_16_63:48;
956 #endif
957 } s;
958 struct cvmx_npei_dbg_select_s cn52xx;
959 struct cvmx_npei_dbg_select_s cn52xxp1;
960 struct cvmx_npei_dbg_select_s cn56xx;
961 struct cvmx_npei_dbg_select_s cn56xxp1;
962 };
963
964 union cvmx_npei_dmax_counts {
965 uint64_t u64;
966 struct cvmx_npei_dmax_counts_s {
967 #ifdef __BIG_ENDIAN_BITFIELD
968 uint64_t reserved_39_63:25;
969 uint64_t fcnt:7;
970 uint64_t dbell:32;
971 #else
972 uint64_t dbell:32;
973 uint64_t fcnt:7;
974 uint64_t reserved_39_63:25;
975 #endif
976 } s;
977 struct cvmx_npei_dmax_counts_s cn52xx;
978 struct cvmx_npei_dmax_counts_s cn52xxp1;
979 struct cvmx_npei_dmax_counts_s cn56xx;
980 struct cvmx_npei_dmax_counts_s cn56xxp1;
981 };
982
983 union cvmx_npei_dmax_dbell {
984 uint32_t u32;
985 struct cvmx_npei_dmax_dbell_s {
986 #ifdef __BIG_ENDIAN_BITFIELD
987 uint32_t reserved_16_31:16;
988 uint32_t dbell:16;
989 #else
990 uint32_t dbell:16;
991 uint32_t reserved_16_31:16;
992 #endif
993 } s;
994 struct cvmx_npei_dmax_dbell_s cn52xx;
995 struct cvmx_npei_dmax_dbell_s cn52xxp1;
996 struct cvmx_npei_dmax_dbell_s cn56xx;
997 struct cvmx_npei_dmax_dbell_s cn56xxp1;
998 };
999
1000 union cvmx_npei_dmax_ibuff_saddr {
1001 uint64_t u64;
1002 struct cvmx_npei_dmax_ibuff_saddr_s {
1003 #ifdef __BIG_ENDIAN_BITFIELD
1004 uint64_t reserved_37_63:27;
1005 uint64_t idle:1;
1006 uint64_t saddr:29;
1007 uint64_t reserved_0_6:7;
1008 #else
1009 uint64_t reserved_0_6:7;
1010 uint64_t saddr:29;
1011 uint64_t idle:1;
1012 uint64_t reserved_37_63:27;
1013 #endif
1014 } s;
1015 struct cvmx_npei_dmax_ibuff_saddr_s cn52xx;
1016 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 {
1017 #ifdef __BIG_ENDIAN_BITFIELD
1018 uint64_t reserved_36_63:28;
1019 uint64_t saddr:29;
1020 uint64_t reserved_0_6:7;
1021 #else
1022 uint64_t reserved_0_6:7;
1023 uint64_t saddr:29;
1024 uint64_t reserved_36_63:28;
1025 #endif
1026 } cn52xxp1;
1027 struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
1028 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1;
1029 };
1030
1031 union cvmx_npei_dmax_naddr {
1032 uint64_t u64;
1033 struct cvmx_npei_dmax_naddr_s {
1034 #ifdef __BIG_ENDIAN_BITFIELD
1035 uint64_t reserved_36_63:28;
1036 uint64_t addr:36;
1037 #else
1038 uint64_t addr:36;
1039 uint64_t reserved_36_63:28;
1040 #endif
1041 } s;
1042 struct cvmx_npei_dmax_naddr_s cn52xx;
1043 struct cvmx_npei_dmax_naddr_s cn52xxp1;
1044 struct cvmx_npei_dmax_naddr_s cn56xx;
1045 struct cvmx_npei_dmax_naddr_s cn56xxp1;
1046 };
1047
1048 union cvmx_npei_dma0_int_level {
1049 uint64_t u64;
1050 struct cvmx_npei_dma0_int_level_s {
1051 #ifdef __BIG_ENDIAN_BITFIELD
1052 uint64_t time:32;
1053 uint64_t cnt:32;
1054 #else
1055 uint64_t cnt:32;
1056 uint64_t time:32;
1057 #endif
1058 } s;
1059 struct cvmx_npei_dma0_int_level_s cn52xx;
1060 struct cvmx_npei_dma0_int_level_s cn52xxp1;
1061 struct cvmx_npei_dma0_int_level_s cn56xx;
1062 struct cvmx_npei_dma0_int_level_s cn56xxp1;
1063 };
1064
1065 union cvmx_npei_dma1_int_level {
1066 uint64_t u64;
1067 struct cvmx_npei_dma1_int_level_s {
1068 #ifdef __BIG_ENDIAN_BITFIELD
1069 uint64_t time:32;
1070 uint64_t cnt:32;
1071 #else
1072 uint64_t cnt:32;
1073 uint64_t time:32;
1074 #endif
1075 } s;
1076 struct cvmx_npei_dma1_int_level_s cn52xx;
1077 struct cvmx_npei_dma1_int_level_s cn52xxp1;
1078 struct cvmx_npei_dma1_int_level_s cn56xx;
1079 struct cvmx_npei_dma1_int_level_s cn56xxp1;
1080 };
1081
1082 union cvmx_npei_dma_cnts {
1083 uint64_t u64;
1084 struct cvmx_npei_dma_cnts_s {
1085 #ifdef __BIG_ENDIAN_BITFIELD
1086 uint64_t dma1:32;
1087 uint64_t dma0:32;
1088 #else
1089 uint64_t dma0:32;
1090 uint64_t dma1:32;
1091 #endif
1092 } s;
1093 struct cvmx_npei_dma_cnts_s cn52xx;
1094 struct cvmx_npei_dma_cnts_s cn52xxp1;
1095 struct cvmx_npei_dma_cnts_s cn56xx;
1096 struct cvmx_npei_dma_cnts_s cn56xxp1;
1097 };
1098
1099 union cvmx_npei_dma_control {
1100 uint64_t u64;
1101 struct cvmx_npei_dma_control_s {
1102 #ifdef __BIG_ENDIAN_BITFIELD
1103 uint64_t reserved_40_63:24;
1104 uint64_t p_32b_m:1;
1105 uint64_t dma4_enb:1;
1106 uint64_t dma3_enb:1;
1107 uint64_t dma2_enb:1;
1108 uint64_t dma1_enb:1;
1109 uint64_t dma0_enb:1;
1110 uint64_t b0_lend:1;
1111 uint64_t dwb_denb:1;
1112 uint64_t dwb_ichk:9;
1113 uint64_t fpa_que:3;
1114 uint64_t o_add1:1;
1115 uint64_t o_ro:1;
1116 uint64_t o_ns:1;
1117 uint64_t o_es:2;
1118 uint64_t o_mode:1;
1119 uint64_t csize:14;
1120 #else
1121 uint64_t csize:14;
1122 uint64_t o_mode:1;
1123 uint64_t o_es:2;
1124 uint64_t o_ns:1;
1125 uint64_t o_ro:1;
1126 uint64_t o_add1:1;
1127 uint64_t fpa_que:3;
1128 uint64_t dwb_ichk:9;
1129 uint64_t dwb_denb:1;
1130 uint64_t b0_lend:1;
1131 uint64_t dma0_enb:1;
1132 uint64_t dma1_enb:1;
1133 uint64_t dma2_enb:1;
1134 uint64_t dma3_enb:1;
1135 uint64_t dma4_enb:1;
1136 uint64_t p_32b_m:1;
1137 uint64_t reserved_40_63:24;
1138 #endif
1139 } s;
1140 struct cvmx_npei_dma_control_s cn52xx;
1141 struct cvmx_npei_dma_control_cn52xxp1 {
1142 #ifdef __BIG_ENDIAN_BITFIELD
1143 uint64_t reserved_38_63:26;
1144 uint64_t dma3_enb:1;
1145 uint64_t dma2_enb:1;
1146 uint64_t dma1_enb:1;
1147 uint64_t dma0_enb:1;
1148 uint64_t b0_lend:1;
1149 uint64_t dwb_denb:1;
1150 uint64_t dwb_ichk:9;
1151 uint64_t fpa_que:3;
1152 uint64_t o_add1:1;
1153 uint64_t o_ro:1;
1154 uint64_t o_ns:1;
1155 uint64_t o_es:2;
1156 uint64_t o_mode:1;
1157 uint64_t csize:14;
1158 #else
1159 uint64_t csize:14;
1160 uint64_t o_mode:1;
1161 uint64_t o_es:2;
1162 uint64_t o_ns:1;
1163 uint64_t o_ro:1;
1164 uint64_t o_add1:1;
1165 uint64_t fpa_que:3;
1166 uint64_t dwb_ichk:9;
1167 uint64_t dwb_denb:1;
1168 uint64_t b0_lend:1;
1169 uint64_t dma0_enb:1;
1170 uint64_t dma1_enb:1;
1171 uint64_t dma2_enb:1;
1172 uint64_t dma3_enb:1;
1173 uint64_t reserved_38_63:26;
1174 #endif
1175 } cn52xxp1;
1176 struct cvmx_npei_dma_control_s cn56xx;
1177 struct cvmx_npei_dma_control_cn56xxp1 {
1178 #ifdef __BIG_ENDIAN_BITFIELD
1179 uint64_t reserved_39_63:25;
1180 uint64_t dma4_enb:1;
1181 uint64_t dma3_enb:1;
1182 uint64_t dma2_enb:1;
1183 uint64_t dma1_enb:1;
1184 uint64_t dma0_enb:1;
1185 uint64_t b0_lend:1;
1186 uint64_t dwb_denb:1;
1187 uint64_t dwb_ichk:9;
1188 uint64_t fpa_que:3;
1189 uint64_t o_add1:1;
1190 uint64_t o_ro:1;
1191 uint64_t o_ns:1;
1192 uint64_t o_es:2;
1193 uint64_t o_mode:1;
1194 uint64_t csize:14;
1195 #else
1196 uint64_t csize:14;
1197 uint64_t o_mode:1;
1198 uint64_t o_es:2;
1199 uint64_t o_ns:1;
1200 uint64_t o_ro:1;
1201 uint64_t o_add1:1;
1202 uint64_t fpa_que:3;
1203 uint64_t dwb_ichk:9;
1204 uint64_t dwb_denb:1;
1205 uint64_t b0_lend:1;
1206 uint64_t dma0_enb:1;
1207 uint64_t dma1_enb:1;
1208 uint64_t dma2_enb:1;
1209 uint64_t dma3_enb:1;
1210 uint64_t dma4_enb:1;
1211 uint64_t reserved_39_63:25;
1212 #endif
1213 } cn56xxp1;
1214 };
1215
1216 union cvmx_npei_dma_pcie_req_num {
1217 uint64_t u64;
1218 struct cvmx_npei_dma_pcie_req_num_s {
1219 #ifdef __BIG_ENDIAN_BITFIELD
1220 uint64_t dma_arb:1;
1221 uint64_t reserved_53_62:10;
1222 uint64_t pkt_cnt:5;
1223 uint64_t reserved_45_47:3;
1224 uint64_t dma4_cnt:5;
1225 uint64_t reserved_37_39:3;
1226 uint64_t dma3_cnt:5;
1227 uint64_t reserved_29_31:3;
1228 uint64_t dma2_cnt:5;
1229 uint64_t reserved_21_23:3;
1230 uint64_t dma1_cnt:5;
1231 uint64_t reserved_13_15:3;
1232 uint64_t dma0_cnt:5;
1233 uint64_t reserved_5_7:3;
1234 uint64_t dma_cnt:5;
1235 #else
1236 uint64_t dma_cnt:5;
1237 uint64_t reserved_5_7:3;
1238 uint64_t dma0_cnt:5;
1239 uint64_t reserved_13_15:3;
1240 uint64_t dma1_cnt:5;
1241 uint64_t reserved_21_23:3;
1242 uint64_t dma2_cnt:5;
1243 uint64_t reserved_29_31:3;
1244 uint64_t dma3_cnt:5;
1245 uint64_t reserved_37_39:3;
1246 uint64_t dma4_cnt:5;
1247 uint64_t reserved_45_47:3;
1248 uint64_t pkt_cnt:5;
1249 uint64_t reserved_53_62:10;
1250 uint64_t dma_arb:1;
1251 #endif
1252 } s;
1253 struct cvmx_npei_dma_pcie_req_num_s cn52xx;
1254 struct cvmx_npei_dma_pcie_req_num_s cn56xx;
1255 };
1256
1257 union cvmx_npei_dma_state1 {
1258 uint64_t u64;
1259 struct cvmx_npei_dma_state1_s {
1260 #ifdef __BIG_ENDIAN_BITFIELD
1261 uint64_t reserved_40_63:24;
1262 uint64_t d4_dwe:8;
1263 uint64_t d3_dwe:8;
1264 uint64_t d2_dwe:8;
1265 uint64_t d1_dwe:8;
1266 uint64_t d0_dwe:8;
1267 #else
1268 uint64_t d0_dwe:8;
1269 uint64_t d1_dwe:8;
1270 uint64_t d2_dwe:8;
1271 uint64_t d3_dwe:8;
1272 uint64_t d4_dwe:8;
1273 uint64_t reserved_40_63:24;
1274 #endif
1275 } s;
1276 struct cvmx_npei_dma_state1_s cn52xx;
1277 };
1278
1279 union cvmx_npei_dma_state1_p1 {
1280 uint64_t u64;
1281 struct cvmx_npei_dma_state1_p1_s {
1282 #ifdef __BIG_ENDIAN_BITFIELD
1283 uint64_t reserved_60_63:4;
1284 uint64_t d0_difst:7;
1285 uint64_t d1_difst:7;
1286 uint64_t d2_difst:7;
1287 uint64_t d3_difst:7;
1288 uint64_t d4_difst:7;
1289 uint64_t d0_reqst:5;
1290 uint64_t d1_reqst:5;
1291 uint64_t d2_reqst:5;
1292 uint64_t d3_reqst:5;
1293 uint64_t d4_reqst:5;
1294 #else
1295 uint64_t d4_reqst:5;
1296 uint64_t d3_reqst:5;
1297 uint64_t d2_reqst:5;
1298 uint64_t d1_reqst:5;
1299 uint64_t d0_reqst:5;
1300 uint64_t d4_difst:7;
1301 uint64_t d3_difst:7;
1302 uint64_t d2_difst:7;
1303 uint64_t d1_difst:7;
1304 uint64_t d0_difst:7;
1305 uint64_t reserved_60_63:4;
1306 #endif
1307 } s;
1308 struct cvmx_npei_dma_state1_p1_cn52xxp1 {
1309 #ifdef __BIG_ENDIAN_BITFIELD
1310 uint64_t reserved_60_63:4;
1311 uint64_t d0_difst:7;
1312 uint64_t d1_difst:7;
1313 uint64_t d2_difst:7;
1314 uint64_t d3_difst:7;
1315 uint64_t reserved_25_31:7;
1316 uint64_t d0_reqst:5;
1317 uint64_t d1_reqst:5;
1318 uint64_t d2_reqst:5;
1319 uint64_t d3_reqst:5;
1320 uint64_t reserved_0_4:5;
1321 #else
1322 uint64_t reserved_0_4:5;
1323 uint64_t d3_reqst:5;
1324 uint64_t d2_reqst:5;
1325 uint64_t d1_reqst:5;
1326 uint64_t d0_reqst:5;
1327 uint64_t reserved_25_31:7;
1328 uint64_t d3_difst:7;
1329 uint64_t d2_difst:7;
1330 uint64_t d1_difst:7;
1331 uint64_t d0_difst:7;
1332 uint64_t reserved_60_63:4;
1333 #endif
1334 } cn52xxp1;
1335 struct cvmx_npei_dma_state1_p1_s cn56xxp1;
1336 };
1337
1338 union cvmx_npei_dma_state2 {
1339 uint64_t u64;
1340 struct cvmx_npei_dma_state2_s {
1341 #ifdef __BIG_ENDIAN_BITFIELD
1342 uint64_t reserved_28_63:36;
1343 uint64_t ndwe:4;
1344 uint64_t reserved_21_23:3;
1345 uint64_t ndre:5;
1346 uint64_t reserved_10_15:6;
1347 uint64_t prd:10;
1348 #else
1349 uint64_t prd:10;
1350 uint64_t reserved_10_15:6;
1351 uint64_t ndre:5;
1352 uint64_t reserved_21_23:3;
1353 uint64_t ndwe:4;
1354 uint64_t reserved_28_63:36;
1355 #endif
1356 } s;
1357 struct cvmx_npei_dma_state2_s cn52xx;
1358 };
1359
1360 union cvmx_npei_dma_state2_p1 {
1361 uint64_t u64;
1362 struct cvmx_npei_dma_state2_p1_s {
1363 #ifdef __BIG_ENDIAN_BITFIELD
1364 uint64_t reserved_45_63:19;
1365 uint64_t d0_dffst:9;
1366 uint64_t d1_dffst:9;
1367 uint64_t d2_dffst:9;
1368 uint64_t d3_dffst:9;
1369 uint64_t d4_dffst:9;
1370 #else
1371 uint64_t d4_dffst:9;
1372 uint64_t d3_dffst:9;
1373 uint64_t d2_dffst:9;
1374 uint64_t d1_dffst:9;
1375 uint64_t d0_dffst:9;
1376 uint64_t reserved_45_63:19;
1377 #endif
1378 } s;
1379 struct cvmx_npei_dma_state2_p1_cn52xxp1 {
1380 #ifdef __BIG_ENDIAN_BITFIELD
1381 uint64_t reserved_45_63:19;
1382 uint64_t d0_dffst:9;
1383 uint64_t d1_dffst:9;
1384 uint64_t d2_dffst:9;
1385 uint64_t d3_dffst:9;
1386 uint64_t reserved_0_8:9;
1387 #else
1388 uint64_t reserved_0_8:9;
1389 uint64_t d3_dffst:9;
1390 uint64_t d2_dffst:9;
1391 uint64_t d1_dffst:9;
1392 uint64_t d0_dffst:9;
1393 uint64_t reserved_45_63:19;
1394 #endif
1395 } cn52xxp1;
1396 struct cvmx_npei_dma_state2_p1_s cn56xxp1;
1397 };
1398
1399 union cvmx_npei_dma_state3_p1 {
1400 uint64_t u64;
1401 struct cvmx_npei_dma_state3_p1_s {
1402 #ifdef __BIG_ENDIAN_BITFIELD
1403 uint64_t reserved_60_63:4;
1404 uint64_t d0_drest:15;
1405 uint64_t d1_drest:15;
1406 uint64_t d2_drest:15;
1407 uint64_t d3_drest:15;
1408 #else
1409 uint64_t d3_drest:15;
1410 uint64_t d2_drest:15;
1411 uint64_t d1_drest:15;
1412 uint64_t d0_drest:15;
1413 uint64_t reserved_60_63:4;
1414 #endif
1415 } s;
1416 struct cvmx_npei_dma_state3_p1_s cn52xxp1;
1417 struct cvmx_npei_dma_state3_p1_s cn56xxp1;
1418 };
1419
1420 union cvmx_npei_dma_state4_p1 {
1421 uint64_t u64;
1422 struct cvmx_npei_dma_state4_p1_s {
1423 #ifdef __BIG_ENDIAN_BITFIELD
1424 uint64_t reserved_52_63:12;
1425 uint64_t d0_dwest:13;
1426 uint64_t d1_dwest:13;
1427 uint64_t d2_dwest:13;
1428 uint64_t d3_dwest:13;
1429 #else
1430 uint64_t d3_dwest:13;
1431 uint64_t d2_dwest:13;
1432 uint64_t d1_dwest:13;
1433 uint64_t d0_dwest:13;
1434 uint64_t reserved_52_63:12;
1435 #endif
1436 } s;
1437 struct cvmx_npei_dma_state4_p1_s cn52xxp1;
1438 struct cvmx_npei_dma_state4_p1_s cn56xxp1;
1439 };
1440
1441 union cvmx_npei_dma_state5_p1 {
1442 uint64_t u64;
1443 struct cvmx_npei_dma_state5_p1_s {
1444 #ifdef __BIG_ENDIAN_BITFIELD
1445 uint64_t reserved_28_63:36;
1446 uint64_t d4_drest:15;
1447 uint64_t d4_dwest:13;
1448 #else
1449 uint64_t d4_dwest:13;
1450 uint64_t d4_drest:15;
1451 uint64_t reserved_28_63:36;
1452 #endif
1453 } s;
1454 struct cvmx_npei_dma_state5_p1_s cn56xxp1;
1455 };
1456
1457 union cvmx_npei_int_a_enb {
1458 uint64_t u64;
1459 struct cvmx_npei_int_a_enb_s {
1460 #ifdef __BIG_ENDIAN_BITFIELD
1461 uint64_t reserved_10_63:54;
1462 uint64_t pout_err:1;
1463 uint64_t pin_bp:1;
1464 uint64_t p1_rdlk:1;
1465 uint64_t p0_rdlk:1;
1466 uint64_t pgl_err:1;
1467 uint64_t pdi_err:1;
1468 uint64_t pop_err:1;
1469 uint64_t pins_err:1;
1470 uint64_t dma1_cpl:1;
1471 uint64_t dma0_cpl:1;
1472 #else
1473 uint64_t dma0_cpl:1;
1474 uint64_t dma1_cpl:1;
1475 uint64_t pins_err:1;
1476 uint64_t pop_err:1;
1477 uint64_t pdi_err:1;
1478 uint64_t pgl_err:1;
1479 uint64_t p0_rdlk:1;
1480 uint64_t p1_rdlk:1;
1481 uint64_t pin_bp:1;
1482 uint64_t pout_err:1;
1483 uint64_t reserved_10_63:54;
1484 #endif
1485 } s;
1486 struct cvmx_npei_int_a_enb_s cn52xx;
1487 struct cvmx_npei_int_a_enb_cn52xxp1 {
1488 #ifdef __BIG_ENDIAN_BITFIELD
1489 uint64_t reserved_2_63:62;
1490 uint64_t dma1_cpl:1;
1491 uint64_t dma0_cpl:1;
1492 #else
1493 uint64_t dma0_cpl:1;
1494 uint64_t dma1_cpl:1;
1495 uint64_t reserved_2_63:62;
1496 #endif
1497 } cn52xxp1;
1498 struct cvmx_npei_int_a_enb_s cn56xx;
1499 };
1500
1501 union cvmx_npei_int_a_enb2 {
1502 uint64_t u64;
1503 struct cvmx_npei_int_a_enb2_s {
1504 #ifdef __BIG_ENDIAN_BITFIELD
1505 uint64_t reserved_10_63:54;
1506 uint64_t pout_err:1;
1507 uint64_t pin_bp:1;
1508 uint64_t p1_rdlk:1;
1509 uint64_t p0_rdlk:1;
1510 uint64_t pgl_err:1;
1511 uint64_t pdi_err:1;
1512 uint64_t pop_err:1;
1513 uint64_t pins_err:1;
1514 uint64_t dma1_cpl:1;
1515 uint64_t dma0_cpl:1;
1516 #else
1517 uint64_t dma0_cpl:1;
1518 uint64_t dma1_cpl:1;
1519 uint64_t pins_err:1;
1520 uint64_t pop_err:1;
1521 uint64_t pdi_err:1;
1522 uint64_t pgl_err:1;
1523 uint64_t p0_rdlk:1;
1524 uint64_t p1_rdlk:1;
1525 uint64_t pin_bp:1;
1526 uint64_t pout_err:1;
1527 uint64_t reserved_10_63:54;
1528 #endif
1529 } s;
1530 struct cvmx_npei_int_a_enb2_s cn52xx;
1531 struct cvmx_npei_int_a_enb2_cn52xxp1 {
1532 #ifdef __BIG_ENDIAN_BITFIELD
1533 uint64_t reserved_2_63:62;
1534 uint64_t dma1_cpl:1;
1535 uint64_t dma0_cpl:1;
1536 #else
1537 uint64_t dma0_cpl:1;
1538 uint64_t dma1_cpl:1;
1539 uint64_t reserved_2_63:62;
1540 #endif
1541 } cn52xxp1;
1542 struct cvmx_npei_int_a_enb2_s cn56xx;
1543 };
1544
1545 union cvmx_npei_int_a_sum {
1546 uint64_t u64;
1547 struct cvmx_npei_int_a_sum_s {
1548 #ifdef __BIG_ENDIAN_BITFIELD
1549 uint64_t reserved_10_63:54;
1550 uint64_t pout_err:1;
1551 uint64_t pin_bp:1;
1552 uint64_t p1_rdlk:1;
1553 uint64_t p0_rdlk:1;
1554 uint64_t pgl_err:1;
1555 uint64_t pdi_err:1;
1556 uint64_t pop_err:1;
1557 uint64_t pins_err:1;
1558 uint64_t dma1_cpl:1;
1559 uint64_t dma0_cpl:1;
1560 #else
1561 uint64_t dma0_cpl:1;
1562 uint64_t dma1_cpl:1;
1563 uint64_t pins_err:1;
1564 uint64_t pop_err:1;
1565 uint64_t pdi_err:1;
1566 uint64_t pgl_err:1;
1567 uint64_t p0_rdlk:1;
1568 uint64_t p1_rdlk:1;
1569 uint64_t pin_bp:1;
1570 uint64_t pout_err:1;
1571 uint64_t reserved_10_63:54;
1572 #endif
1573 } s;
1574 struct cvmx_npei_int_a_sum_s cn52xx;
1575 struct cvmx_npei_int_a_sum_cn52xxp1 {
1576 #ifdef __BIG_ENDIAN_BITFIELD
1577 uint64_t reserved_2_63:62;
1578 uint64_t dma1_cpl:1;
1579 uint64_t dma0_cpl:1;
1580 #else
1581 uint64_t dma0_cpl:1;
1582 uint64_t dma1_cpl:1;
1583 uint64_t reserved_2_63:62;
1584 #endif
1585 } cn52xxp1;
1586 struct cvmx_npei_int_a_sum_s cn56xx;
1587 };
1588
1589 union cvmx_npei_int_enb {
1590 uint64_t u64;
1591 struct cvmx_npei_int_enb_s {
1592 #ifdef __BIG_ENDIAN_BITFIELD
1593 uint64_t mio_inta:1;
1594 uint64_t reserved_62_62:1;
1595 uint64_t int_a:1;
1596 uint64_t c1_ldwn:1;
1597 uint64_t c0_ldwn:1;
1598 uint64_t c1_exc:1;
1599 uint64_t c0_exc:1;
1600 uint64_t c1_up_wf:1;
1601 uint64_t c0_up_wf:1;
1602 uint64_t c1_un_wf:1;
1603 uint64_t c0_un_wf:1;
1604 uint64_t c1_un_bx:1;
1605 uint64_t c1_un_wi:1;
1606 uint64_t c1_un_b2:1;
1607 uint64_t c1_un_b1:1;
1608 uint64_t c1_un_b0:1;
1609 uint64_t c1_up_bx:1;
1610 uint64_t c1_up_wi:1;
1611 uint64_t c1_up_b2:1;
1612 uint64_t c1_up_b1:1;
1613 uint64_t c1_up_b0:1;
1614 uint64_t c0_un_bx:1;
1615 uint64_t c0_un_wi:1;
1616 uint64_t c0_un_b2:1;
1617 uint64_t c0_un_b1:1;
1618 uint64_t c0_un_b0:1;
1619 uint64_t c0_up_bx:1;
1620 uint64_t c0_up_wi:1;
1621 uint64_t c0_up_b2:1;
1622 uint64_t c0_up_b1:1;
1623 uint64_t c0_up_b0:1;
1624 uint64_t c1_hpint:1;
1625 uint64_t c1_pmei:1;
1626 uint64_t c1_wake:1;
1627 uint64_t crs1_dr:1;
1628 uint64_t c1_se:1;
1629 uint64_t crs1_er:1;
1630 uint64_t c1_aeri:1;
1631 uint64_t c0_hpint:1;
1632 uint64_t c0_pmei:1;
1633 uint64_t c0_wake:1;
1634 uint64_t crs0_dr:1;
1635 uint64_t c0_se:1;
1636 uint64_t crs0_er:1;
1637 uint64_t c0_aeri:1;
1638 uint64_t ptime:1;
1639 uint64_t pcnt:1;
1640 uint64_t pidbof:1;
1641 uint64_t psldbof:1;
1642 uint64_t dtime1:1;
1643 uint64_t dtime0:1;
1644 uint64_t dcnt1:1;
1645 uint64_t dcnt0:1;
1646 uint64_t dma1fi:1;
1647 uint64_t dma0fi:1;
1648 uint64_t dma4dbo:1;
1649 uint64_t dma3dbo:1;
1650 uint64_t dma2dbo:1;
1651 uint64_t dma1dbo:1;
1652 uint64_t dma0dbo:1;
1653 uint64_t iob2big:1;
1654 uint64_t bar0_to:1;
1655 uint64_t rml_wto:1;
1656 uint64_t rml_rto:1;
1657 #else
1658 uint64_t rml_rto:1;
1659 uint64_t rml_wto:1;
1660 uint64_t bar0_to:1;
1661 uint64_t iob2big:1;
1662 uint64_t dma0dbo:1;
1663 uint64_t dma1dbo:1;
1664 uint64_t dma2dbo:1;
1665 uint64_t dma3dbo:1;
1666 uint64_t dma4dbo:1;
1667 uint64_t dma0fi:1;
1668 uint64_t dma1fi:1;
1669 uint64_t dcnt0:1;
1670 uint64_t dcnt1:1;
1671 uint64_t dtime0:1;
1672 uint64_t dtime1:1;
1673 uint64_t psldbof:1;
1674 uint64_t pidbof:1;
1675 uint64_t pcnt:1;
1676 uint64_t ptime:1;
1677 uint64_t c0_aeri:1;
1678 uint64_t crs0_er:1;
1679 uint64_t c0_se:1;
1680 uint64_t crs0_dr:1;
1681 uint64_t c0_wake:1;
1682 uint64_t c0_pmei:1;
1683 uint64_t c0_hpint:1;
1684 uint64_t c1_aeri:1;
1685 uint64_t crs1_er:1;
1686 uint64_t c1_se:1;
1687 uint64_t crs1_dr:1;
1688 uint64_t c1_wake:1;
1689 uint64_t c1_pmei:1;
1690 uint64_t c1_hpint:1;
1691 uint64_t c0_up_b0:1;
1692 uint64_t c0_up_b1:1;
1693 uint64_t c0_up_b2:1;
1694 uint64_t c0_up_wi:1;
1695 uint64_t c0_up_bx:1;
1696 uint64_t c0_un_b0:1;
1697 uint64_t c0_un_b1:1;
1698 uint64_t c0_un_b2:1;
1699 uint64_t c0_un_wi:1;
1700 uint64_t c0_un_bx:1;
1701 uint64_t c1_up_b0:1;
1702 uint64_t c1_up_b1:1;
1703 uint64_t c1_up_b2:1;
1704 uint64_t c1_up_wi:1;
1705 uint64_t c1_up_bx:1;
1706 uint64_t c1_un_b0:1;
1707 uint64_t c1_un_b1:1;
1708 uint64_t c1_un_b2:1;
1709 uint64_t c1_un_wi:1;
1710 uint64_t c1_un_bx:1;
1711 uint64_t c0_un_wf:1;
1712 uint64_t c1_un_wf:1;
1713 uint64_t c0_up_wf:1;
1714 uint64_t c1_up_wf:1;
1715 uint64_t c0_exc:1;
1716 uint64_t c1_exc:1;
1717 uint64_t c0_ldwn:1;
1718 uint64_t c1_ldwn:1;
1719 uint64_t int_a:1;
1720 uint64_t reserved_62_62:1;
1721 uint64_t mio_inta:1;
1722 #endif
1723 } s;
1724 struct cvmx_npei_int_enb_s cn52xx;
1725 struct cvmx_npei_int_enb_cn52xxp1 {
1726 #ifdef __BIG_ENDIAN_BITFIELD
1727 uint64_t mio_inta:1;
1728 uint64_t reserved_62_62:1;
1729 uint64_t int_a:1;
1730 uint64_t c1_ldwn:1;
1731 uint64_t c0_ldwn:1;
1732 uint64_t c1_exc:1;
1733 uint64_t c0_exc:1;
1734 uint64_t c1_up_wf:1;
1735 uint64_t c0_up_wf:1;
1736 uint64_t c1_un_wf:1;
1737 uint64_t c0_un_wf:1;
1738 uint64_t c1_un_bx:1;
1739 uint64_t c1_un_wi:1;
1740 uint64_t c1_un_b2:1;
1741 uint64_t c1_un_b1:1;
1742 uint64_t c1_un_b0:1;
1743 uint64_t c1_up_bx:1;
1744 uint64_t c1_up_wi:1;
1745 uint64_t c1_up_b2:1;
1746 uint64_t c1_up_b1:1;
1747 uint64_t c1_up_b0:1;
1748 uint64_t c0_un_bx:1;
1749 uint64_t c0_un_wi:1;
1750 uint64_t c0_un_b2:1;
1751 uint64_t c0_un_b1:1;
1752 uint64_t c0_un_b0:1;
1753 uint64_t c0_up_bx:1;
1754 uint64_t c0_up_wi:1;
1755 uint64_t c0_up_b2:1;
1756 uint64_t c0_up_b1:1;
1757 uint64_t c0_up_b0:1;
1758 uint64_t c1_hpint:1;
1759 uint64_t c1_pmei:1;
1760 uint64_t c1_wake:1;
1761 uint64_t crs1_dr:1;
1762 uint64_t c1_se:1;
1763 uint64_t crs1_er:1;
1764 uint64_t c1_aeri:1;
1765 uint64_t c0_hpint:1;
1766 uint64_t c0_pmei:1;
1767 uint64_t c0_wake:1;
1768 uint64_t crs0_dr:1;
1769 uint64_t c0_se:1;
1770 uint64_t crs0_er:1;
1771 uint64_t c0_aeri:1;
1772 uint64_t ptime:1;
1773 uint64_t pcnt:1;
1774 uint64_t pidbof:1;
1775 uint64_t psldbof:1;
1776 uint64_t dtime1:1;
1777 uint64_t dtime0:1;
1778 uint64_t dcnt1:1;
1779 uint64_t dcnt0:1;
1780 uint64_t dma1fi:1;
1781 uint64_t dma0fi:1;
1782 uint64_t reserved_8_8:1;
1783 uint64_t dma3dbo:1;
1784 uint64_t dma2dbo:1;
1785 uint64_t dma1dbo:1;
1786 uint64_t dma0dbo:1;
1787 uint64_t iob2big:1;
1788 uint64_t bar0_to:1;
1789 uint64_t rml_wto:1;
1790 uint64_t rml_rto:1;
1791 #else
1792 uint64_t rml_rto:1;
1793 uint64_t rml_wto:1;
1794 uint64_t bar0_to:1;
1795 uint64_t iob2big:1;
1796 uint64_t dma0dbo:1;
1797 uint64_t dma1dbo:1;
1798 uint64_t dma2dbo:1;
1799 uint64_t dma3dbo:1;
1800 uint64_t reserved_8_8:1;
1801 uint64_t dma0fi:1;
1802 uint64_t dma1fi:1;
1803 uint64_t dcnt0:1;
1804 uint64_t dcnt1:1;
1805 uint64_t dtime0:1;
1806 uint64_t dtime1:1;
1807 uint64_t psldbof:1;
1808 uint64_t pidbof:1;
1809 uint64_t pcnt:1;
1810 uint64_t ptime:1;
1811 uint64_t c0_aeri:1;
1812 uint64_t crs0_er:1;
1813 uint64_t c0_se:1;
1814 uint64_t crs0_dr:1;
1815 uint64_t c0_wake:1;
1816 uint64_t c0_pmei:1;
1817 uint64_t c0_hpint:1;
1818 uint64_t c1_aeri:1;
1819 uint64_t crs1_er:1;
1820 uint64_t c1_se:1;
1821 uint64_t crs1_dr:1;
1822 uint64_t c1_wake:1;
1823 uint64_t c1_pmei:1;
1824 uint64_t c1_hpint:1;
1825 uint64_t c0_up_b0:1;
1826 uint64_t c0_up_b1:1;
1827 uint64_t c0_up_b2:1;
1828 uint64_t c0_up_wi:1;
1829 uint64_t c0_up_bx:1;
1830 uint64_t c0_un_b0:1;
1831 uint64_t c0_un_b1:1;
1832 uint64_t c0_un_b2:1;
1833 uint64_t c0_un_wi:1;
1834 uint64_t c0_un_bx:1;
1835 uint64_t c1_up_b0:1;
1836 uint64_t c1_up_b1:1;
1837 uint64_t c1_up_b2:1;
1838 uint64_t c1_up_wi:1;
1839 uint64_t c1_up_bx:1;
1840 uint64_t c1_un_b0:1;
1841 uint64_t c1_un_b1:1;
1842 uint64_t c1_un_b2:1;
1843 uint64_t c1_un_wi:1;
1844 uint64_t c1_un_bx:1;
1845 uint64_t c0_un_wf:1;
1846 uint64_t c1_un_wf:1;
1847 uint64_t c0_up_wf:1;
1848 uint64_t c1_up_wf:1;
1849 uint64_t c0_exc:1;
1850 uint64_t c1_exc:1;
1851 uint64_t c0_ldwn:1;
1852 uint64_t c1_ldwn:1;
1853 uint64_t int_a:1;
1854 uint64_t reserved_62_62:1;
1855 uint64_t mio_inta:1;
1856 #endif
1857 } cn52xxp1;
1858 struct cvmx_npei_int_enb_s cn56xx;
1859 struct cvmx_npei_int_enb_cn56xxp1 {
1860 #ifdef __BIG_ENDIAN_BITFIELD
1861 uint64_t mio_inta:1;
1862 uint64_t reserved_61_62:2;
1863 uint64_t c1_ldwn:1;
1864 uint64_t c0_ldwn:1;
1865 uint64_t c1_exc:1;
1866 uint64_t c0_exc:1;
1867 uint64_t c1_up_wf:1;
1868 uint64_t c0_up_wf:1;
1869 uint64_t c1_un_wf:1;
1870 uint64_t c0_un_wf:1;
1871 uint64_t c1_un_bx:1;
1872 uint64_t c1_un_wi:1;
1873 uint64_t c1_un_b2:1;
1874 uint64_t c1_un_b1:1;
1875 uint64_t c1_un_b0:1;
1876 uint64_t c1_up_bx:1;
1877 uint64_t c1_up_wi:1;
1878 uint64_t c1_up_b2:1;
1879 uint64_t c1_up_b1:1;
1880 uint64_t c1_up_b0:1;
1881 uint64_t c0_un_bx:1;
1882 uint64_t c0_un_wi:1;
1883 uint64_t c0_un_b2:1;
1884 uint64_t c0_un_b1:1;
1885 uint64_t c0_un_b0:1;
1886 uint64_t c0_up_bx:1;
1887 uint64_t c0_up_wi:1;
1888 uint64_t c0_up_b2:1;
1889 uint64_t c0_up_b1:1;
1890 uint64_t c0_up_b0:1;
1891 uint64_t c1_hpint:1;
1892 uint64_t c1_pmei:1;
1893 uint64_t c1_wake:1;
1894 uint64_t reserved_29_29:1;
1895 uint64_t c1_se:1;
1896 uint64_t reserved_27_27:1;
1897 uint64_t c1_aeri:1;
1898 uint64_t c0_hpint:1;
1899 uint64_t c0_pmei:1;
1900 uint64_t c0_wake:1;
1901 uint64_t reserved_22_22:1;
1902 uint64_t c0_se:1;
1903 uint64_t reserved_20_20:1;
1904 uint64_t c0_aeri:1;
1905 uint64_t ptime:1;
1906 uint64_t pcnt:1;
1907 uint64_t pidbof:1;
1908 uint64_t psldbof:1;
1909 uint64_t dtime1:1;
1910 uint64_t dtime0:1;
1911 uint64_t dcnt1:1;
1912 uint64_t dcnt0:1;
1913 uint64_t dma1fi:1;
1914 uint64_t dma0fi:1;
1915 uint64_t dma4dbo:1;
1916 uint64_t dma3dbo:1;
1917 uint64_t dma2dbo:1;
1918 uint64_t dma1dbo:1;
1919 uint64_t dma0dbo:1;
1920 uint64_t iob2big:1;
1921 uint64_t bar0_to:1;
1922 uint64_t rml_wto:1;
1923 uint64_t rml_rto:1;
1924 #else
1925 uint64_t rml_rto:1;
1926 uint64_t rml_wto:1;
1927 uint64_t bar0_to:1;
1928 uint64_t iob2big:1;
1929 uint64_t dma0dbo:1;
1930 uint64_t dma1dbo:1;
1931 uint64_t dma2dbo:1;
1932 uint64_t dma3dbo:1;
1933 uint64_t dma4dbo:1;
1934 uint64_t dma0fi:1;
1935 uint64_t dma1fi:1;
1936 uint64_t dcnt0:1;
1937 uint64_t dcnt1:1;
1938 uint64_t dtime0:1;
1939 uint64_t dtime1:1;
1940 uint64_t psldbof:1;
1941 uint64_t pidbof:1;
1942 uint64_t pcnt:1;
1943 uint64_t ptime:1;
1944 uint64_t c0_aeri:1;
1945 uint64_t reserved_20_20:1;
1946 uint64_t c0_se:1;
1947 uint64_t reserved_22_22:1;
1948 uint64_t c0_wake:1;
1949 uint64_t c0_pmei:1;
1950 uint64_t c0_hpint:1;
1951 uint64_t c1_aeri:1;
1952 uint64_t reserved_27_27:1;
1953 uint64_t c1_se:1;
1954 uint64_t reserved_29_29:1;
1955 uint64_t c1_wake:1;
1956 uint64_t c1_pmei:1;
1957 uint64_t c1_hpint:1;
1958 uint64_t c0_up_b0:1;
1959 uint64_t c0_up_b1:1;
1960 uint64_t c0_up_b2:1;
1961 uint64_t c0_up_wi:1;
1962 uint64_t c0_up_bx:1;
1963 uint64_t c0_un_b0:1;
1964 uint64_t c0_un_b1:1;
1965 uint64_t c0_un_b2:1;
1966 uint64_t c0_un_wi:1;
1967 uint64_t c0_un_bx:1;
1968 uint64_t c1_up_b0:1;
1969 uint64_t c1_up_b1:1;
1970 uint64_t c1_up_b2:1;
1971 uint64_t c1_up_wi:1;
1972 uint64_t c1_up_bx:1;
1973 uint64_t c1_un_b0:1;
1974 uint64_t c1_un_b1:1;
1975 uint64_t c1_un_b2:1;
1976 uint64_t c1_un_wi:1;
1977 uint64_t c1_un_bx:1;
1978 uint64_t c0_un_wf:1;
1979 uint64_t c1_un_wf:1;
1980 uint64_t c0_up_wf:1;
1981 uint64_t c1_up_wf:1;
1982 uint64_t c0_exc:1;
1983 uint64_t c1_exc:1;
1984 uint64_t c0_ldwn:1;
1985 uint64_t c1_ldwn:1;
1986 uint64_t reserved_61_62:2;
1987 uint64_t mio_inta:1;
1988 #endif
1989 } cn56xxp1;
1990 };
1991
1992 union cvmx_npei_int_enb2 {
1993 uint64_t u64;
1994 struct cvmx_npei_int_enb2_s {
1995 #ifdef __BIG_ENDIAN_BITFIELD
1996 uint64_t reserved_62_63:2;
1997 uint64_t int_a:1;
1998 uint64_t c1_ldwn:1;
1999 uint64_t c0_ldwn:1;
2000 uint64_t c1_exc:1;
2001 uint64_t c0_exc:1;
2002 uint64_t c1_up_wf:1;
2003 uint64_t c0_up_wf:1;
2004 uint64_t c1_un_wf:1;
2005 uint64_t c0_un_wf:1;
2006 uint64_t c1_un_bx:1;
2007 uint64_t c1_un_wi:1;
2008 uint64_t c1_un_b2:1;
2009 uint64_t c1_un_b1:1;
2010 uint64_t c1_un_b0:1;
2011 uint64_t c1_up_bx:1;
2012 uint64_t c1_up_wi:1;
2013 uint64_t c1_up_b2:1;
2014 uint64_t c1_up_b1:1;
2015 uint64_t c1_up_b0:1;
2016 uint64_t c0_un_bx:1;
2017 uint64_t c0_un_wi:1;
2018 uint64_t c0_un_b2:1;
2019 uint64_t c0_un_b1:1;
2020 uint64_t c0_un_b0:1;
2021 uint64_t c0_up_bx:1;
2022 uint64_t c0_up_wi:1;
2023 uint64_t c0_up_b2:1;
2024 uint64_t c0_up_b1:1;
2025 uint64_t c0_up_b0:1;
2026 uint64_t c1_hpint:1;
2027 uint64_t c1_pmei:1;
2028 uint64_t c1_wake:1;
2029 uint64_t crs1_dr:1;
2030 uint64_t c1_se:1;
2031 uint64_t crs1_er:1;
2032 uint64_t c1_aeri:1;
2033 uint64_t c0_hpint:1;
2034 uint64_t c0_pmei:1;
2035 uint64_t c0_wake:1;
2036 uint64_t crs0_dr:1;
2037 uint64_t c0_se:1;
2038 uint64_t crs0_er:1;
2039 uint64_t c0_aeri:1;
2040 uint64_t ptime:1;
2041 uint64_t pcnt:1;
2042 uint64_t pidbof:1;
2043 uint64_t psldbof:1;
2044 uint64_t dtime1:1;
2045 uint64_t dtime0:1;
2046 uint64_t dcnt1:1;
2047 uint64_t dcnt0:1;
2048 uint64_t dma1fi:1;
2049 uint64_t dma0fi:1;
2050 uint64_t dma4dbo:1;
2051 uint64_t dma3dbo:1;
2052 uint64_t dma2dbo:1;
2053 uint64_t dma1dbo:1;
2054 uint64_t dma0dbo:1;
2055 uint64_t iob2big:1;
2056 uint64_t bar0_to:1;
2057 uint64_t rml_wto:1;
2058 uint64_t rml_rto:1;
2059 #else
2060 uint64_t rml_rto:1;
2061 uint64_t rml_wto:1;
2062 uint64_t bar0_to:1;
2063 uint64_t iob2big:1;
2064 uint64_t dma0dbo:1;
2065 uint64_t dma1dbo:1;
2066 uint64_t dma2dbo:1;
2067 uint64_t dma3dbo:1;
2068 uint64_t dma4dbo:1;
2069 uint64_t dma0fi:1;
2070 uint64_t dma1fi:1;
2071 uint64_t dcnt0:1;
2072 uint64_t dcnt1:1;
2073 uint64_t dtime0:1;
2074 uint64_t dtime1:1;
2075 uint64_t psldbof:1;
2076 uint64_t pidbof:1;
2077 uint64_t pcnt:1;
2078 uint64_t ptime:1;
2079 uint64_t c0_aeri:1;
2080 uint64_t crs0_er:1;
2081 uint64_t c0_se:1;
2082 uint64_t crs0_dr:1;
2083 uint64_t c0_wake:1;
2084 uint64_t c0_pmei:1;
2085 uint64_t c0_hpint:1;
2086 uint64_t c1_aeri:1;
2087 uint64_t crs1_er:1;
2088 uint64_t c1_se:1;
2089 uint64_t crs1_dr:1;
2090 uint64_t c1_wake:1;
2091 uint64_t c1_pmei:1;
2092 uint64_t c1_hpint:1;
2093 uint64_t c0_up_b0:1;
2094 uint64_t c0_up_b1:1;
2095 uint64_t c0_up_b2:1;
2096 uint64_t c0_up_wi:1;
2097 uint64_t c0_up_bx:1;
2098 uint64_t c0_un_b0:1;
2099 uint64_t c0_un_b1:1;
2100 uint64_t c0_un_b2:1;
2101 uint64_t c0_un_wi:1;
2102 uint64_t c0_un_bx:1;
2103 uint64_t c1_up_b0:1;
2104 uint64_t c1_up_b1:1;
2105 uint64_t c1_up_b2:1;
2106 uint64_t c1_up_wi:1;
2107 uint64_t c1_up_bx:1;
2108 uint64_t c1_un_b0:1;
2109 uint64_t c1_un_b1:1;
2110 uint64_t c1_un_b2:1;
2111 uint64_t c1_un_wi:1;
2112 uint64_t c1_un_bx:1;
2113 uint64_t c0_un_wf:1;
2114 uint64_t c1_un_wf:1;
2115 uint64_t c0_up_wf:1;
2116 uint64_t c1_up_wf:1;
2117 uint64_t c0_exc:1;
2118 uint64_t c1_exc:1;
2119 uint64_t c0_ldwn:1;
2120 uint64_t c1_ldwn:1;
2121 uint64_t int_a:1;
2122 uint64_t reserved_62_63:2;
2123 #endif
2124 } s;
2125 struct cvmx_npei_int_enb2_s cn52xx;
2126 struct cvmx_npei_int_enb2_cn52xxp1 {
2127 #ifdef __BIG_ENDIAN_BITFIELD
2128 uint64_t reserved_62_63:2;
2129 uint64_t int_a:1;
2130 uint64_t c1_ldwn:1;
2131 uint64_t c0_ldwn:1;
2132 uint64_t c1_exc:1;
2133 uint64_t c0_exc:1;
2134 uint64_t c1_up_wf:1;
2135 uint64_t c0_up_wf:1;
2136 uint64_t c1_un_wf:1;
2137 uint64_t c0_un_wf:1;
2138 uint64_t c1_un_bx:1;
2139 uint64_t c1_un_wi:1;
2140 uint64_t c1_un_b2:1;
2141 uint64_t c1_un_b1:1;
2142 uint64_t c1_un_b0:1;
2143 uint64_t c1_up_bx:1;
2144 uint64_t c1_up_wi:1;
2145 uint64_t c1_up_b2:1;
2146 uint64_t c1_up_b1:1;
2147 uint64_t c1_up_b0:1;
2148 uint64_t c0_un_bx:1;
2149 uint64_t c0_un_wi:1;
2150 uint64_t c0_un_b2:1;
2151 uint64_t c0_un_b1:1;
2152 uint64_t c0_un_b0:1;
2153 uint64_t c0_up_bx:1;
2154 uint64_t c0_up_wi:1;
2155 uint64_t c0_up_b2:1;
2156 uint64_t c0_up_b1:1;
2157 uint64_t c0_up_b0:1;
2158 uint64_t c1_hpint:1;
2159 uint64_t c1_pmei:1;
2160 uint64_t c1_wake:1;
2161 uint64_t crs1_dr:1;
2162 uint64_t c1_se:1;
2163 uint64_t crs1_er:1;
2164 uint64_t c1_aeri:1;
2165 uint64_t c0_hpint:1;
2166 uint64_t c0_pmei:1;
2167 uint64_t c0_wake:1;
2168 uint64_t crs0_dr:1;
2169 uint64_t c0_se:1;
2170 uint64_t crs0_er:1;
2171 uint64_t c0_aeri:1;
2172 uint64_t ptime:1;
2173 uint64_t pcnt:1;
2174 uint64_t pidbof:1;
2175 uint64_t psldbof:1;
2176 uint64_t dtime1:1;
2177 uint64_t dtime0:1;
2178 uint64_t dcnt1:1;
2179 uint64_t dcnt0:1;
2180 uint64_t dma1fi:1;
2181 uint64_t dma0fi:1;
2182 uint64_t reserved_8_8:1;
2183 uint64_t dma3dbo:1;
2184 uint64_t dma2dbo:1;
2185 uint64_t dma1dbo:1;
2186 uint64_t dma0dbo:1;
2187 uint64_t iob2big:1;
2188 uint64_t bar0_to:1;
2189 uint64_t rml_wto:1;
2190 uint64_t rml_rto:1;
2191 #else
2192 uint64_t rml_rto:1;
2193 uint64_t rml_wto:1;
2194 uint64_t bar0_to:1;
2195 uint64_t iob2big:1;
2196 uint64_t dma0dbo:1;
2197 uint64_t dma1dbo:1;
2198 uint64_t dma2dbo:1;
2199 uint64_t dma3dbo:1;
2200 uint64_t reserved_8_8:1;
2201 uint64_t dma0fi:1;
2202 uint64_t dma1fi:1;
2203 uint64_t dcnt0:1;
2204 uint64_t dcnt1:1;
2205 uint64_t dtime0:1;
2206 uint64_t dtime1:1;
2207 uint64_t psldbof:1;
2208 uint64_t pidbof:1;
2209 uint64_t pcnt:1;
2210 uint64_t ptime:1;
2211 uint64_t c0_aeri:1;
2212 uint64_t crs0_er:1;
2213 uint64_t c0_se:1;
2214 uint64_t crs0_dr:1;
2215 uint64_t c0_wake:1;
2216 uint64_t c0_pmei:1;
2217 uint64_t c0_hpint:1;
2218 uint64_t c1_aeri:1;
2219 uint64_t crs1_er:1;
2220 uint64_t c1_se:1;
2221 uint64_t crs1_dr:1;
2222 uint64_t c1_wake:1;
2223 uint64_t c1_pmei:1;
2224 uint64_t c1_hpint:1;
2225 uint64_t c0_up_b0:1;
2226 uint64_t c0_up_b1:1;
2227 uint64_t c0_up_b2:1;
2228 uint64_t c0_up_wi:1;
2229 uint64_t c0_up_bx:1;
2230 uint64_t c0_un_b0:1;
2231 uint64_t c0_un_b1:1;
2232 uint64_t c0_un_b2:1;
2233 uint64_t c0_un_wi:1;
2234 uint64_t c0_un_bx:1;
2235 uint64_t c1_up_b0:1;
2236 uint64_t c1_up_b1:1;
2237 uint64_t c1_up_b2:1;
2238 uint64_t c1_up_wi:1;
2239 uint64_t c1_up_bx:1;
2240 uint64_t c1_un_b0:1;
2241 uint64_t c1_un_b1:1;
2242 uint64_t c1_un_b2:1;
2243 uint64_t c1_un_wi:1;
2244 uint64_t c1_un_bx:1;
2245 uint64_t c0_un_wf:1;
2246 uint64_t c1_un_wf:1;
2247 uint64_t c0_up_wf:1;
2248 uint64_t c1_up_wf:1;
2249 uint64_t c0_exc:1;
2250 uint64_t c1_exc:1;
2251 uint64_t c0_ldwn:1;
2252 uint64_t c1_ldwn:1;
2253 uint64_t int_a:1;
2254 uint64_t reserved_62_63:2;
2255 #endif
2256 } cn52xxp1;
2257 struct cvmx_npei_int_enb2_s cn56xx;
2258 struct cvmx_npei_int_enb2_cn56xxp1 {
2259 #ifdef __BIG_ENDIAN_BITFIELD
2260 uint64_t reserved_61_63:3;
2261 uint64_t c1_ldwn:1;
2262 uint64_t c0_ldwn:1;
2263 uint64_t c1_exc:1;
2264 uint64_t c0_exc:1;
2265 uint64_t c1_up_wf:1;
2266 uint64_t c0_up_wf:1;
2267 uint64_t c1_un_wf:1;
2268 uint64_t c0_un_wf:1;
2269 uint64_t c1_un_bx:1;
2270 uint64_t c1_un_wi:1;
2271 uint64_t c1_un_b2:1;
2272 uint64_t c1_un_b1:1;
2273 uint64_t c1_un_b0:1;
2274 uint64_t c1_up_bx:1;
2275 uint64_t c1_up_wi:1;
2276 uint64_t c1_up_b2:1;
2277 uint64_t c1_up_b1:1;
2278 uint64_t c1_up_b0:1;
2279 uint64_t c0_un_bx:1;
2280 uint64_t c0_un_wi:1;
2281 uint64_t c0_un_b2:1;
2282 uint64_t c0_un_b1:1;
2283 uint64_t c0_un_b0:1;
2284 uint64_t c0_up_bx:1;
2285 uint64_t c0_up_wi:1;
2286 uint64_t c0_up_b2:1;
2287 uint64_t c0_up_b1:1;
2288 uint64_t c0_up_b0:1;
2289 uint64_t c1_hpint:1;
2290 uint64_t c1_pmei:1;
2291 uint64_t c1_wake:1;
2292 uint64_t reserved_29_29:1;
2293 uint64_t c1_se:1;
2294 uint64_t reserved_27_27:1;
2295 uint64_t c1_aeri:1;
2296 uint64_t c0_hpint:1;
2297 uint64_t c0_pmei:1;
2298 uint64_t c0_wake:1;
2299 uint64_t reserved_22_22:1;
2300 uint64_t c0_se:1;
2301 uint64_t reserved_20_20:1;
2302 uint64_t c0_aeri:1;
2303 uint64_t ptime:1;
2304 uint64_t pcnt:1;
2305 uint64_t pidbof:1;
2306 uint64_t psldbof:1;
2307 uint64_t dtime1:1;
2308 uint64_t dtime0:1;
2309 uint64_t dcnt1:1;
2310 uint64_t dcnt0:1;
2311 uint64_t dma1fi:1;
2312 uint64_t dma0fi:1;
2313 uint64_t dma4dbo:1;
2314 uint64_t dma3dbo:1;
2315 uint64_t dma2dbo:1;
2316 uint64_t dma1dbo:1;
2317 uint64_t dma0dbo:1;
2318 uint64_t iob2big:1;
2319 uint64_t bar0_to:1;
2320 uint64_t rml_wto:1;
2321 uint64_t rml_rto:1;
2322 #else
2323 uint64_t rml_rto:1;
2324 uint64_t rml_wto:1;
2325 uint64_t bar0_to:1;
2326 uint64_t iob2big:1;
2327 uint64_t dma0dbo:1;
2328 uint64_t dma1dbo:1;
2329 uint64_t dma2dbo:1;
2330 uint64_t dma3dbo:1;
2331 uint64_t dma4dbo:1;
2332 uint64_t dma0fi:1;
2333 uint64_t dma1fi:1;
2334 uint64_t dcnt0:1;
2335 uint64_t dcnt1:1;
2336 uint64_t dtime0:1;
2337 uint64_t dtime1:1;
2338 uint64_t psldbof:1;
2339 uint64_t pidbof:1;
2340 uint64_t pcnt:1;
2341 uint64_t ptime:1;
2342 uint64_t c0_aeri:1;
2343 uint64_t reserved_20_20:1;
2344 uint64_t c0_se:1;
2345 uint64_t reserved_22_22:1;
2346 uint64_t c0_wake:1;
2347 uint64_t c0_pmei:1;
2348 uint64_t c0_hpint:1;
2349 uint64_t c1_aeri:1;
2350 uint64_t reserved_27_27:1;
2351 uint64_t c1_se:1;
2352 uint64_t reserved_29_29:1;
2353 uint64_t c1_wake:1;
2354 uint64_t c1_pmei:1;
2355 uint64_t c1_hpint:1;
2356 uint64_t c0_up_b0:1;
2357 uint64_t c0_up_b1:1;
2358 uint64_t c0_up_b2:1;
2359 uint64_t c0_up_wi:1;
2360 uint64_t c0_up_bx:1;
2361 uint64_t c0_un_b0:1;
2362 uint64_t c0_un_b1:1;
2363 uint64_t c0_un_b2:1;
2364 uint64_t c0_un_wi:1;
2365 uint64_t c0_un_bx:1;
2366 uint64_t c1_up_b0:1;
2367 uint64_t c1_up_b1:1;
2368 uint64_t c1_up_b2:1;
2369 uint64_t c1_up_wi:1;
2370 uint64_t c1_up_bx:1;
2371 uint64_t c1_un_b0:1;
2372 uint64_t c1_un_b1:1;
2373 uint64_t c1_un_b2:1;
2374 uint64_t c1_un_wi:1;
2375 uint64_t c1_un_bx:1;
2376 uint64_t c0_un_wf:1;
2377 uint64_t c1_un_wf:1;
2378 uint64_t c0_up_wf:1;
2379 uint64_t c1_up_wf:1;
2380 uint64_t c0_exc:1;
2381 uint64_t c1_exc:1;
2382 uint64_t c0_ldwn:1;
2383 uint64_t c1_ldwn:1;
2384 uint64_t reserved_61_63:3;
2385 #endif
2386 } cn56xxp1;
2387 };
2388
2389 union cvmx_npei_int_info {
2390 uint64_t u64;
2391 struct cvmx_npei_int_info_s {
2392 #ifdef __BIG_ENDIAN_BITFIELD
2393 uint64_t reserved_12_63:52;
2394 uint64_t pidbof:6;
2395 uint64_t psldbof:6;
2396 #else
2397 uint64_t psldbof:6;
2398 uint64_t pidbof:6;
2399 uint64_t reserved_12_63:52;
2400 #endif
2401 } s;
2402 struct cvmx_npei_int_info_s cn52xx;
2403 struct cvmx_npei_int_info_s cn56xx;
2404 struct cvmx_npei_int_info_s cn56xxp1;
2405 };
2406
2407 union cvmx_npei_int_sum {
2408 uint64_t u64;
2409 struct cvmx_npei_int_sum_s {
2410 #ifdef __BIG_ENDIAN_BITFIELD
2411 uint64_t mio_inta:1;
2412 uint64_t reserved_62_62:1;
2413 uint64_t int_a:1;
2414 uint64_t c1_ldwn:1;
2415 uint64_t c0_ldwn:1;
2416 uint64_t c1_exc:1;
2417 uint64_t c0_exc:1;
2418 uint64_t c1_up_wf:1;
2419 uint64_t c0_up_wf:1;
2420 uint64_t c1_un_wf:1;
2421 uint64_t c0_un_wf:1;
2422 uint64_t c1_un_bx:1;
2423 uint64_t c1_un_wi:1;
2424 uint64_t c1_un_b2:1;
2425 uint64_t c1_un_b1:1;
2426 uint64_t c1_un_b0:1;
2427 uint64_t c1_up_bx:1;
2428 uint64_t c1_up_wi:1;
2429 uint64_t c1_up_b2:1;
2430 uint64_t c1_up_b1:1;
2431 uint64_t c1_up_b0:1;
2432 uint64_t c0_un_bx:1;
2433 uint64_t c0_un_wi:1;
2434 uint64_t c0_un_b2:1;
2435 uint64_t c0_un_b1:1;
2436 uint64_t c0_un_b0:1;
2437 uint64_t c0_up_bx:1;
2438 uint64_t c0_up_wi:1;
2439 uint64_t c0_up_b2:1;
2440 uint64_t c0_up_b1:1;
2441 uint64_t c0_up_b0:1;
2442 uint64_t c1_hpint:1;
2443 uint64_t c1_pmei:1;
2444 uint64_t c1_wake:1;
2445 uint64_t crs1_dr:1;
2446 uint64_t c1_se:1;
2447 uint64_t crs1_er:1;
2448 uint64_t c1_aeri:1;
2449 uint64_t c0_hpint:1;
2450 uint64_t c0_pmei:1;
2451 uint64_t c0_wake:1;
2452 uint64_t crs0_dr:1;
2453 uint64_t c0_se:1;
2454 uint64_t crs0_er:1;
2455 uint64_t c0_aeri:1;
2456 uint64_t ptime:1;
2457 uint64_t pcnt:1;
2458 uint64_t pidbof:1;
2459 uint64_t psldbof:1;
2460 uint64_t dtime1:1;
2461 uint64_t dtime0:1;
2462 uint64_t dcnt1:1;
2463 uint64_t dcnt0:1;
2464 uint64_t dma1fi:1;
2465 uint64_t dma0fi:1;
2466 uint64_t dma4dbo:1;
2467 uint64_t dma3dbo:1;
2468 uint64_t dma2dbo:1;
2469 uint64_t dma1dbo:1;
2470 uint64_t dma0dbo:1;
2471 uint64_t iob2big:1;
2472 uint64_t bar0_to:1;
2473 uint64_t rml_wto:1;
2474 uint64_t rml_rto:1;
2475 #else
2476 uint64_t rml_rto:1;
2477 uint64_t rml_wto:1;
2478 uint64_t bar0_to:1;
2479 uint64_t iob2big:1;
2480 uint64_t dma0dbo:1;
2481 uint64_t dma1dbo:1;
2482 uint64_t dma2dbo:1;
2483 uint64_t dma3dbo:1;
2484 uint64_t dma4dbo:1;
2485 uint64_t dma0fi:1;
2486 uint64_t dma1fi:1;
2487 uint64_t dcnt0:1;
2488 uint64_t dcnt1:1;
2489 uint64_t dtime0:1;
2490 uint64_t dtime1:1;
2491 uint64_t psldbof:1;
2492 uint64_t pidbof:1;
2493 uint64_t pcnt:1;
2494 uint64_t ptime:1;
2495 uint64_t c0_aeri:1;
2496 uint64_t crs0_er:1;
2497 uint64_t c0_se:1;
2498 uint64_t crs0_dr:1;
2499 uint64_t c0_wake:1;
2500 uint64_t c0_pmei:1;
2501 uint64_t c0_hpint:1;
2502 uint64_t c1_aeri:1;
2503 uint64_t crs1_er:1;
2504 uint64_t c1_se:1;
2505 uint64_t crs1_dr:1;
2506 uint64_t c1_wake:1;
2507 uint64_t c1_pmei:1;
2508 uint64_t c1_hpint:1;
2509 uint64_t c0_up_b0:1;
2510 uint64_t c0_up_b1:1;
2511 uint64_t c0_up_b2:1;
2512 uint64_t c0_up_wi:1;
2513 uint64_t c0_up_bx:1;
2514 uint64_t c0_un_b0:1;
2515 uint64_t c0_un_b1:1;
2516 uint64_t c0_un_b2:1;
2517 uint64_t c0_un_wi:1;
2518 uint64_t c0_un_bx:1;
2519 uint64_t c1_up_b0:1;
2520 uint64_t c1_up_b1:1;
2521 uint64_t c1_up_b2:1;
2522 uint64_t c1_up_wi:1;
2523 uint64_t c1_up_bx:1;
2524 uint64_t c1_un_b0:1;
2525 uint64_t c1_un_b1:1;
2526 uint64_t c1_un_b2:1;
2527 uint64_t c1_un_wi:1;
2528 uint64_t c1_un_bx:1;
2529 uint64_t c0_un_wf:1;
2530 uint64_t c1_un_wf:1;
2531 uint64_t c0_up_wf:1;
2532 uint64_t c1_up_wf:1;
2533 uint64_t c0_exc:1;
2534 uint64_t c1_exc:1;
2535 uint64_t c0_ldwn:1;
2536 uint64_t c1_ldwn:1;
2537 uint64_t int_a:1;
2538 uint64_t reserved_62_62:1;
2539 uint64_t mio_inta:1;
2540 #endif
2541 } s;
2542 struct cvmx_npei_int_sum_s cn52xx;
2543 struct cvmx_npei_int_sum_cn52xxp1 {
2544 #ifdef __BIG_ENDIAN_BITFIELD
2545 uint64_t mio_inta:1;
2546 uint64_t reserved_62_62:1;
2547 uint64_t int_a:1;
2548 uint64_t c1_ldwn:1;
2549 uint64_t c0_ldwn:1;
2550 uint64_t c1_exc:1;
2551 uint64_t c0_exc:1;
2552 uint64_t c1_up_wf:1;
2553 uint64_t c0_up_wf:1;
2554 uint64_t c1_un_wf:1;
2555 uint64_t c0_un_wf:1;
2556 uint64_t c1_un_bx:1;
2557 uint64_t c1_un_wi:1;
2558 uint64_t c1_un_b2:1;
2559 uint64_t c1_un_b1:1;
2560 uint64_t c1_un_b0:1;
2561 uint64_t c1_up_bx:1;
2562 uint64_t c1_up_wi:1;
2563 uint64_t c1_up_b2:1;
2564 uint64_t c1_up_b1:1;
2565 uint64_t c1_up_b0:1;
2566 uint64_t c0_un_bx:1;
2567 uint64_t c0_un_wi:1;
2568 uint64_t c0_un_b2:1;
2569 uint64_t c0_un_b1:1;
2570 uint64_t c0_un_b0:1;
2571 uint64_t c0_up_bx:1;
2572 uint64_t c0_up_wi:1;
2573 uint64_t c0_up_b2:1;
2574 uint64_t c0_up_b1:1;
2575 uint64_t c0_up_b0:1;
2576 uint64_t c1_hpint:1;
2577 uint64_t c1_pmei:1;
2578 uint64_t c1_wake:1;
2579 uint64_t crs1_dr:1;
2580 uint64_t c1_se:1;
2581 uint64_t crs1_er:1;
2582 uint64_t c1_aeri:1;
2583 uint64_t c0_hpint:1;
2584 uint64_t c0_pmei:1;
2585 uint64_t c0_wake:1;
2586 uint64_t crs0_dr:1;
2587 uint64_t c0_se:1;
2588 uint64_t crs0_er:1;
2589 uint64_t c0_aeri:1;
2590 uint64_t reserved_15_18:4;
2591 uint64_t dtime1:1;
2592 uint64_t dtime0:1;
2593 uint64_t dcnt1:1;
2594 uint64_t dcnt0:1;
2595 uint64_t dma1fi:1;
2596 uint64_t dma0fi:1;
2597 uint64_t reserved_8_8:1;
2598 uint64_t dma3dbo:1;
2599 uint64_t dma2dbo:1;
2600 uint64_t dma1dbo:1;
2601 uint64_t dma0dbo:1;
2602 uint64_t iob2big:1;
2603 uint64_t bar0_to:1;
2604 uint64_t rml_wto:1;
2605 uint64_t rml_rto:1;
2606 #else
2607 uint64_t rml_rto:1;
2608 uint64_t rml_wto:1;
2609 uint64_t bar0_to:1;
2610 uint64_t iob2big:1;
2611 uint64_t dma0dbo:1;
2612 uint64_t dma1dbo:1;
2613 uint64_t dma2dbo:1;
2614 uint64_t dma3dbo:1;
2615 uint64_t reserved_8_8:1;
2616 uint64_t dma0fi:1;
2617 uint64_t dma1fi:1;
2618 uint64_t dcnt0:1;
2619 uint64_t dcnt1:1;
2620 uint64_t dtime0:1;
2621 uint64_t dtime1:1;
2622 uint64_t reserved_15_18:4;
2623 uint64_t c0_aeri:1;
2624 uint64_t crs0_er:1;
2625 uint64_t c0_se:1;
2626 uint64_t crs0_dr:1;
2627 uint64_t c0_wake:1;
2628 uint64_t c0_pmei:1;
2629 uint64_t c0_hpint:1;
2630 uint64_t c1_aeri:1;
2631 uint64_t crs1_er:1;
2632 uint64_t c1_se:1;
2633 uint64_t crs1_dr:1;
2634 uint64_t c1_wake:1;
2635 uint64_t c1_pmei:1;
2636 uint64_t c1_hpint:1;
2637 uint64_t c0_up_b0:1;
2638 uint64_t c0_up_b1:1;
2639 uint64_t c0_up_b2:1;
2640 uint64_t c0_up_wi:1;
2641 uint64_t c0_up_bx:1;
2642 uint64_t c0_un_b0:1;
2643 uint64_t c0_un_b1:1;
2644 uint64_t c0_un_b2:1;
2645 uint64_t c0_un_wi:1;
2646 uint64_t c0_un_bx:1;
2647 uint64_t c1_up_b0:1;
2648 uint64_t c1_up_b1:1;
2649 uint64_t c1_up_b2:1;
2650 uint64_t c1_up_wi:1;
2651 uint64_t c1_up_bx:1;
2652 uint64_t c1_un_b0:1;
2653 uint64_t c1_un_b1:1;
2654 uint64_t c1_un_b2:1;
2655 uint64_t c1_un_wi:1;
2656 uint64_t c1_un_bx:1;
2657 uint64_t c0_un_wf:1;
2658 uint64_t c1_un_wf:1;
2659 uint64_t c0_up_wf:1;
2660 uint64_t c1_up_wf:1;
2661 uint64_t c0_exc:1;
2662 uint64_t c1_exc:1;
2663 uint64_t c0_ldwn:1;
2664 uint64_t c1_ldwn:1;
2665 uint64_t int_a:1;
2666 uint64_t reserved_62_62:1;
2667 uint64_t mio_inta:1;
2668 #endif
2669 } cn52xxp1;
2670 struct cvmx_npei_int_sum_s cn56xx;
2671 struct cvmx_npei_int_sum_cn56xxp1 {
2672 #ifdef __BIG_ENDIAN_BITFIELD
2673 uint64_t mio_inta:1;
2674 uint64_t reserved_61_62:2;
2675 uint64_t c1_ldwn:1;
2676 uint64_t c0_ldwn:1;
2677 uint64_t c1_exc:1;
2678 uint64_t c0_exc:1;
2679 uint64_t c1_up_wf:1;
2680 uint64_t c0_up_wf:1;
2681 uint64_t c1_un_wf:1;
2682 uint64_t c0_un_wf:1;
2683 uint64_t c1_un_bx:1;
2684 uint64_t c1_un_wi:1;
2685 uint64_t c1_un_b2:1;
2686 uint64_t c1_un_b1:1;
2687 uint64_t c1_un_b0:1;
2688 uint64_t c1_up_bx:1;
2689 uint64_t c1_up_wi:1;
2690 uint64_t c1_up_b2:1;
2691 uint64_t c1_up_b1:1;
2692 uint64_t c1_up_b0:1;
2693 uint64_t c0_un_bx:1;
2694 uint64_t c0_un_wi:1;
2695 uint64_t c0_un_b2:1;
2696 uint64_t c0_un_b1:1;
2697 uint64_t c0_un_b0:1;
2698 uint64_t c0_up_bx:1;
2699 uint64_t c0_up_wi:1;
2700 uint64_t c0_up_b2:1;
2701 uint64_t c0_up_b1:1;
2702 uint64_t c0_up_b0:1;
2703 uint64_t c1_hpint:1;
2704 uint64_t c1_pmei:1;
2705 uint64_t c1_wake:1;
2706 uint64_t reserved_29_29:1;
2707 uint64_t c1_se:1;
2708 uint64_t reserved_27_27:1;
2709 uint64_t c1_aeri:1;
2710 uint64_t c0_hpint:1;
2711 uint64_t c0_pmei:1;
2712 uint64_t c0_wake:1;
2713 uint64_t reserved_22_22:1;
2714 uint64_t c0_se:1;
2715 uint64_t reserved_20_20:1;
2716 uint64_t c0_aeri:1;
2717 uint64_t reserved_15_18:4;
2718 uint64_t dtime1:1;
2719 uint64_t dtime0:1;
2720 uint64_t dcnt1:1;
2721 uint64_t dcnt0:1;
2722 uint64_t dma1fi:1;
2723 uint64_t dma0fi:1;
2724 uint64_t dma4dbo:1;
2725 uint64_t dma3dbo:1;
2726 uint64_t dma2dbo:1;
2727 uint64_t dma1dbo:1;
2728 uint64_t dma0dbo:1;
2729 uint64_t iob2big:1;
2730 uint64_t bar0_to:1;
2731 uint64_t rml_wto:1;
2732 uint64_t rml_rto:1;
2733 #else
2734 uint64_t rml_rto:1;
2735 uint64_t rml_wto:1;
2736 uint64_t bar0_to:1;
2737 uint64_t iob2big:1;
2738 uint64_t dma0dbo:1;
2739 uint64_t dma1dbo:1;
2740 uint64_t dma2dbo:1;
2741 uint64_t dma3dbo:1;
2742 uint64_t dma4dbo:1;
2743 uint64_t dma0fi:1;
2744 uint64_t dma1fi:1;
2745 uint64_t dcnt0:1;
2746 uint64_t dcnt1:1;
2747 uint64_t dtime0:1;
2748 uint64_t dtime1:1;
2749 uint64_t reserved_15_18:4;
2750 uint64_t c0_aeri:1;
2751 uint64_t reserved_20_20:1;
2752 uint64_t c0_se:1;
2753 uint64_t reserved_22_22:1;
2754 uint64_t c0_wake:1;
2755 uint64_t c0_pmei:1;
2756 uint64_t c0_hpint:1;
2757 uint64_t c1_aeri:1;
2758 uint64_t reserved_27_27:1;
2759 uint64_t c1_se:1;
2760 uint64_t reserved_29_29:1;
2761 uint64_t c1_wake:1;
2762 uint64_t c1_pmei:1;
2763 uint64_t c1_hpint:1;
2764 uint64_t c0_up_b0:1;
2765 uint64_t c0_up_b1:1;
2766 uint64_t c0_up_b2:1;
2767 uint64_t c0_up_wi:1;
2768 uint64_t c0_up_bx:1;
2769 uint64_t c0_un_b0:1;
2770 uint64_t c0_un_b1:1;
2771 uint64_t c0_un_b2:1;
2772 uint64_t c0_un_wi:1;
2773 uint64_t c0_un_bx:1;
2774 uint64_t c1_up_b0:1;
2775 uint64_t c1_up_b1:1;
2776 uint64_t c1_up_b2:1;
2777 uint64_t c1_up_wi:1;
2778 uint64_t c1_up_bx:1;
2779 uint64_t c1_un_b0:1;
2780 uint64_t c1_un_b1:1;
2781 uint64_t c1_un_b2:1;
2782 uint64_t c1_un_wi:1;
2783 uint64_t c1_un_bx:1;
2784 uint64_t c0_un_wf:1;
2785 uint64_t c1_un_wf:1;
2786 uint64_t c0_up_wf:1;
2787 uint64_t c1_up_wf:1;
2788 uint64_t c0_exc:1;
2789 uint64_t c1_exc:1;
2790 uint64_t c0_ldwn:1;
2791 uint64_t c1_ldwn:1;
2792 uint64_t reserved_61_62:2;
2793 uint64_t mio_inta:1;
2794 #endif
2795 } cn56xxp1;
2796 };
2797
2798 union cvmx_npei_int_sum2 {
2799 uint64_t u64;
2800 struct cvmx_npei_int_sum2_s {
2801 #ifdef __BIG_ENDIAN_BITFIELD
2802 uint64_t mio_inta:1;
2803 uint64_t reserved_62_62:1;
2804 uint64_t int_a:1;
2805 uint64_t c1_ldwn:1;
2806 uint64_t c0_ldwn:1;
2807 uint64_t c1_exc:1;
2808 uint64_t c0_exc:1;
2809 uint64_t c1_up_wf:1;
2810 uint64_t c0_up_wf:1;
2811 uint64_t c1_un_wf:1;
2812 uint64_t c0_un_wf:1;
2813 uint64_t c1_un_bx:1;
2814 uint64_t c1_un_wi:1;
2815 uint64_t c1_un_b2:1;
2816 uint64_t c1_un_b1:1;
2817 uint64_t c1_un_b0:1;
2818 uint64_t c1_up_bx:1;
2819 uint64_t c1_up_wi:1;
2820 uint64_t c1_up_b2:1;
2821 uint64_t c1_up_b1:1;
2822 uint64_t c1_up_b0:1;
2823 uint64_t c0_un_bx:1;
2824 uint64_t c0_un_wi:1;
2825 uint64_t c0_un_b2:1;
2826 uint64_t c0_un_b1:1;
2827 uint64_t c0_un_b0:1;
2828 uint64_t c0_up_bx:1;
2829 uint64_t c0_up_wi:1;
2830 uint64_t c0_up_b2:1;
2831 uint64_t c0_up_b1:1;
2832 uint64_t c0_up_b0:1;
2833 uint64_t c1_hpint:1;
2834 uint64_t c1_pmei:1;
2835 uint64_t c1_wake:1;
2836 uint64_t crs1_dr:1;
2837 uint64_t c1_se:1;
2838 uint64_t crs1_er:1;
2839 uint64_t c1_aeri:1;
2840 uint64_t c0_hpint:1;
2841 uint64_t c0_pmei:1;
2842 uint64_t c0_wake:1;
2843 uint64_t crs0_dr:1;
2844 uint64_t c0_se:1;
2845 uint64_t crs0_er:1;
2846 uint64_t c0_aeri:1;
2847 uint64_t reserved_15_18:4;
2848 uint64_t dtime1:1;
2849 uint64_t dtime0:1;
2850 uint64_t dcnt1:1;
2851 uint64_t dcnt0:1;
2852 uint64_t dma1fi:1;
2853 uint64_t dma0fi:1;
2854 uint64_t reserved_8_8:1;
2855 uint64_t dma3dbo:1;
2856 uint64_t dma2dbo:1;
2857 uint64_t dma1dbo:1;
2858 uint64_t dma0dbo:1;
2859 uint64_t iob2big:1;
2860 uint64_t bar0_to:1;
2861 uint64_t rml_wto:1;
2862 uint64_t rml_rto:1;
2863 #else
2864 uint64_t rml_rto:1;
2865 uint64_t rml_wto:1;
2866 uint64_t bar0_to:1;
2867 uint64_t iob2big:1;
2868 uint64_t dma0dbo:1;
2869 uint64_t dma1dbo:1;
2870 uint64_t dma2dbo:1;
2871 uint64_t dma3dbo:1;
2872 uint64_t reserved_8_8:1;
2873 uint64_t dma0fi:1;
2874 uint64_t dma1fi:1;
2875 uint64_t dcnt0:1;
2876 uint64_t dcnt1:1;
2877 uint64_t dtime0:1;
2878 uint64_t dtime1:1;
2879 uint64_t reserved_15_18:4;
2880 uint64_t c0_aeri:1;
2881 uint64_t crs0_er:1;
2882 uint64_t c0_se:1;
2883 uint64_t crs0_dr:1;
2884 uint64_t c0_wake:1;
2885 uint64_t c0_pmei:1;
2886 uint64_t c0_hpint:1;
2887 uint64_t c1_aeri:1;
2888 uint64_t crs1_er:1;
2889 uint64_t c1_se:1;
2890 uint64_t crs1_dr:1;
2891 uint64_t c1_wake:1;
2892 uint64_t c1_pmei:1;
2893 uint64_t c1_hpint:1;
2894 uint64_t c0_up_b0:1;
2895 uint64_t c0_up_b1:1;
2896 uint64_t c0_up_b2:1;
2897 uint64_t c0_up_wi:1;
2898 uint64_t c0_up_bx:1;
2899 uint64_t c0_un_b0:1;
2900 uint64_t c0_un_b1:1;
2901 uint64_t c0_un_b2:1;
2902 uint64_t c0_un_wi:1;
2903 uint64_t c0_un_bx:1;
2904 uint64_t c1_up_b0:1;
2905 uint64_t c1_up_b1:1;
2906 uint64_t c1_up_b2:1;
2907 uint64_t c1_up_wi:1;
2908 uint64_t c1_up_bx:1;
2909 uint64_t c1_un_b0:1;
2910 uint64_t c1_un_b1:1;
2911 uint64_t c1_un_b2:1;
2912 uint64_t c1_un_wi:1;
2913 uint64_t c1_un_bx:1;
2914 uint64_t c0_un_wf:1;
2915 uint64_t c1_un_wf:1;
2916 uint64_t c0_up_wf:1;
2917 uint64_t c1_up_wf:1;
2918 uint64_t c0_exc:1;
2919 uint64_t c1_exc:1;
2920 uint64_t c0_ldwn:1;
2921 uint64_t c1_ldwn:1;
2922 uint64_t int_a:1;
2923 uint64_t reserved_62_62:1;
2924 uint64_t mio_inta:1;
2925 #endif
2926 } s;
2927 struct cvmx_npei_int_sum2_s cn52xx;
2928 struct cvmx_npei_int_sum2_s cn52xxp1;
2929 struct cvmx_npei_int_sum2_s cn56xx;
2930 };
2931
2932 union cvmx_npei_last_win_rdata0 {
2933 uint64_t u64;
2934 struct cvmx_npei_last_win_rdata0_s {
2935 #ifdef __BIG_ENDIAN_BITFIELD
2936 uint64_t data:64;
2937 #else
2938 uint64_t data:64;
2939 #endif
2940 } s;
2941 struct cvmx_npei_last_win_rdata0_s cn52xx;
2942 struct cvmx_npei_last_win_rdata0_s cn52xxp1;
2943 struct cvmx_npei_last_win_rdata0_s cn56xx;
2944 struct cvmx_npei_last_win_rdata0_s cn56xxp1;
2945 };
2946
2947 union cvmx_npei_last_win_rdata1 {
2948 uint64_t u64;
2949 struct cvmx_npei_last_win_rdata1_s {
2950 #ifdef __BIG_ENDIAN_BITFIELD
2951 uint64_t data:64;
2952 #else
2953 uint64_t data:64;
2954 #endif
2955 } s;
2956 struct cvmx_npei_last_win_rdata1_s cn52xx;
2957 struct cvmx_npei_last_win_rdata1_s cn52xxp1;
2958 struct cvmx_npei_last_win_rdata1_s cn56xx;
2959 struct cvmx_npei_last_win_rdata1_s cn56xxp1;
2960 };
2961
2962 union cvmx_npei_mem_access_ctl {
2963 uint64_t u64;
2964 struct cvmx_npei_mem_access_ctl_s {
2965 #ifdef __BIG_ENDIAN_BITFIELD
2966 uint64_t reserved_14_63:50;
2967 uint64_t max_word:4;
2968 uint64_t timer:10;
2969 #else
2970 uint64_t timer:10;
2971 uint64_t max_word:4;
2972 uint64_t reserved_14_63:50;
2973 #endif
2974 } s;
2975 struct cvmx_npei_mem_access_ctl_s cn52xx;
2976 struct cvmx_npei_mem_access_ctl_s cn52xxp1;
2977 struct cvmx_npei_mem_access_ctl_s cn56xx;
2978 struct cvmx_npei_mem_access_ctl_s cn56xxp1;
2979 };
2980
2981 union cvmx_npei_mem_access_subidx {
2982 uint64_t u64;
2983 struct cvmx_npei_mem_access_subidx_s {
2984 #ifdef __BIG_ENDIAN_BITFIELD
2985 uint64_t reserved_42_63:22;
2986 uint64_t zero:1;
2987 uint64_t port:2;
2988 uint64_t nmerge:1;
2989 uint64_t esr:2;
2990 uint64_t esw:2;
2991 uint64_t nsr:1;
2992 uint64_t nsw:1;
2993 uint64_t ror:1;
2994 uint64_t row:1;
2995 uint64_t ba:30;
2996 #else
2997 uint64_t ba:30;
2998 uint64_t row:1;
2999 uint64_t ror:1;
3000 uint64_t nsw:1;
3001 uint64_t nsr:1;
3002 uint64_t esw:2;
3003 uint64_t esr:2;
3004 uint64_t nmerge:1;
3005 uint64_t port:2;
3006 uint64_t zero:1;
3007 uint64_t reserved_42_63:22;
3008 #endif
3009 } s;
3010 struct cvmx_npei_mem_access_subidx_s cn52xx;
3011 struct cvmx_npei_mem_access_subidx_s cn52xxp1;
3012 struct cvmx_npei_mem_access_subidx_s cn56xx;
3013 struct cvmx_npei_mem_access_subidx_s cn56xxp1;
3014 };
3015
3016 union cvmx_npei_msi_enb0 {
3017 uint64_t u64;
3018 struct cvmx_npei_msi_enb0_s {
3019 #ifdef __BIG_ENDIAN_BITFIELD
3020 uint64_t enb:64;
3021 #else
3022 uint64_t enb:64;
3023 #endif
3024 } s;
3025 struct cvmx_npei_msi_enb0_s cn52xx;
3026 struct cvmx_npei_msi_enb0_s cn52xxp1;
3027 struct cvmx_npei_msi_enb0_s cn56xx;
3028 struct cvmx_npei_msi_enb0_s cn56xxp1;
3029 };
3030
3031 union cvmx_npei_msi_enb1 {
3032 uint64_t u64;
3033 struct cvmx_npei_msi_enb1_s {
3034 #ifdef __BIG_ENDIAN_BITFIELD
3035 uint64_t enb:64;
3036 #else
3037 uint64_t enb:64;
3038 #endif
3039 } s;
3040 struct cvmx_npei_msi_enb1_s cn52xx;
3041 struct cvmx_npei_msi_enb1_s cn52xxp1;
3042 struct cvmx_npei_msi_enb1_s cn56xx;
3043 struct cvmx_npei_msi_enb1_s cn56xxp1;
3044 };
3045
3046 union cvmx_npei_msi_enb2 {
3047 uint64_t u64;
3048 struct cvmx_npei_msi_enb2_s {
3049 #ifdef __BIG_ENDIAN_BITFIELD
3050 uint64_t enb:64;
3051 #else
3052 uint64_t enb:64;
3053 #endif
3054 } s;
3055 struct cvmx_npei_msi_enb2_s cn52xx;
3056 struct cvmx_npei_msi_enb2_s cn52xxp1;
3057 struct cvmx_npei_msi_enb2_s cn56xx;
3058 struct cvmx_npei_msi_enb2_s cn56xxp1;
3059 };
3060
3061 union cvmx_npei_msi_enb3 {
3062 uint64_t u64;
3063 struct cvmx_npei_msi_enb3_s {
3064 #ifdef __BIG_ENDIAN_BITFIELD
3065 uint64_t enb:64;
3066 #else
3067 uint64_t enb:64;
3068 #endif
3069 } s;
3070 struct cvmx_npei_msi_enb3_s cn52xx;
3071 struct cvmx_npei_msi_enb3_s cn52xxp1;
3072 struct cvmx_npei_msi_enb3_s cn56xx;
3073 struct cvmx_npei_msi_enb3_s cn56xxp1;
3074 };
3075
3076 union cvmx_npei_msi_rcv0 {
3077 uint64_t u64;
3078 struct cvmx_npei_msi_rcv0_s {
3079 #ifdef __BIG_ENDIAN_BITFIELD
3080 uint64_t intr:64;
3081 #else
3082 uint64_t intr:64;
3083 #endif
3084 } s;
3085 struct cvmx_npei_msi_rcv0_s cn52xx;
3086 struct cvmx_npei_msi_rcv0_s cn52xxp1;
3087 struct cvmx_npei_msi_rcv0_s cn56xx;
3088 struct cvmx_npei_msi_rcv0_s cn56xxp1;
3089 };
3090
3091 union cvmx_npei_msi_rcv1 {
3092 uint64_t u64;
3093 struct cvmx_npei_msi_rcv1_s {
3094 #ifdef __BIG_ENDIAN_BITFIELD
3095 uint64_t intr:64;
3096 #else
3097 uint64_t intr:64;
3098 #endif
3099 } s;
3100 struct cvmx_npei_msi_rcv1_s cn52xx;
3101 struct cvmx_npei_msi_rcv1_s cn52xxp1;
3102 struct cvmx_npei_msi_rcv1_s cn56xx;
3103 struct cvmx_npei_msi_rcv1_s cn56xxp1;
3104 };
3105
3106 union cvmx_npei_msi_rcv2 {
3107 uint64_t u64;
3108 struct cvmx_npei_msi_rcv2_s {
3109 #ifdef __BIG_ENDIAN_BITFIELD
3110 uint64_t intr:64;
3111 #else
3112 uint64_t intr:64;
3113 #endif
3114 } s;
3115 struct cvmx_npei_msi_rcv2_s cn52xx;
3116 struct cvmx_npei_msi_rcv2_s cn52xxp1;
3117 struct cvmx_npei_msi_rcv2_s cn56xx;
3118 struct cvmx_npei_msi_rcv2_s cn56xxp1;
3119 };
3120
3121 union cvmx_npei_msi_rcv3 {
3122 uint64_t u64;
3123 struct cvmx_npei_msi_rcv3_s {
3124 #ifdef __BIG_ENDIAN_BITFIELD
3125 uint64_t intr:64;
3126 #else
3127 uint64_t intr:64;
3128 #endif
3129 } s;
3130 struct cvmx_npei_msi_rcv3_s cn52xx;
3131 struct cvmx_npei_msi_rcv3_s cn52xxp1;
3132 struct cvmx_npei_msi_rcv3_s cn56xx;
3133 struct cvmx_npei_msi_rcv3_s cn56xxp1;
3134 };
3135
3136 union cvmx_npei_msi_rd_map {
3137 uint64_t u64;
3138 struct cvmx_npei_msi_rd_map_s {
3139 #ifdef __BIG_ENDIAN_BITFIELD
3140 uint64_t reserved_16_63:48;
3141 uint64_t rd_int:8;
3142 uint64_t msi_int:8;
3143 #else
3144 uint64_t msi_int:8;
3145 uint64_t rd_int:8;
3146 uint64_t reserved_16_63:48;
3147 #endif
3148 } s;
3149 struct cvmx_npei_msi_rd_map_s cn52xx;
3150 struct cvmx_npei_msi_rd_map_s cn52xxp1;
3151 struct cvmx_npei_msi_rd_map_s cn56xx;
3152 struct cvmx_npei_msi_rd_map_s cn56xxp1;
3153 };
3154
3155 union cvmx_npei_msi_w1c_enb0 {
3156 uint64_t u64;
3157 struct cvmx_npei_msi_w1c_enb0_s {
3158 #ifdef __BIG_ENDIAN_BITFIELD
3159 uint64_t clr:64;
3160 #else
3161 uint64_t clr:64;
3162 #endif
3163 } s;
3164 struct cvmx_npei_msi_w1c_enb0_s cn52xx;
3165 struct cvmx_npei_msi_w1c_enb0_s cn56xx;
3166 };
3167
3168 union cvmx_npei_msi_w1c_enb1 {
3169 uint64_t u64;
3170 struct cvmx_npei_msi_w1c_enb1_s {
3171 #ifdef __BIG_ENDIAN_BITFIELD
3172 uint64_t clr:64;
3173 #else
3174 uint64_t clr:64;
3175 #endif
3176 } s;
3177 struct cvmx_npei_msi_w1c_enb1_s cn52xx;
3178 struct cvmx_npei_msi_w1c_enb1_s cn56xx;
3179 };
3180
3181 union cvmx_npei_msi_w1c_enb2 {
3182 uint64_t u64;
3183 struct cvmx_npei_msi_w1c_enb2_s {
3184 #ifdef __BIG_ENDIAN_BITFIELD
3185 uint64_t clr:64;
3186 #else
3187 uint64_t clr:64;
3188 #endif
3189 } s;
3190 struct cvmx_npei_msi_w1c_enb2_s cn52xx;
3191 struct cvmx_npei_msi_w1c_enb2_s cn56xx;
3192 };
3193
3194 union cvmx_npei_msi_w1c_enb3 {
3195 uint64_t u64;
3196 struct cvmx_npei_msi_w1c_enb3_s {
3197 #ifdef __BIG_ENDIAN_BITFIELD
3198 uint64_t clr:64;
3199 #else
3200 uint64_t clr:64;
3201 #endif
3202 } s;
3203 struct cvmx_npei_msi_w1c_enb3_s cn52xx;
3204 struct cvmx_npei_msi_w1c_enb3_s cn56xx;
3205 };
3206
3207 union cvmx_npei_msi_w1s_enb0 {
3208 uint64_t u64;
3209 struct cvmx_npei_msi_w1s_enb0_s {
3210 #ifdef __BIG_ENDIAN_BITFIELD
3211 uint64_t set:64;
3212 #else
3213 uint64_t set:64;
3214 #endif
3215 } s;
3216 struct cvmx_npei_msi_w1s_enb0_s cn52xx;
3217 struct cvmx_npei_msi_w1s_enb0_s cn56xx;
3218 };
3219
3220 union cvmx_npei_msi_w1s_enb1 {
3221 uint64_t u64;
3222 struct cvmx_npei_msi_w1s_enb1_s {
3223 #ifdef __BIG_ENDIAN_BITFIELD
3224 uint64_t set:64;
3225 #else
3226 uint64_t set:64;
3227 #endif
3228 } s;
3229 struct cvmx_npei_msi_w1s_enb1_s cn52xx;
3230 struct cvmx_npei_msi_w1s_enb1_s cn56xx;
3231 };
3232
3233 union cvmx_npei_msi_w1s_enb2 {
3234 uint64_t u64;
3235 struct cvmx_npei_msi_w1s_enb2_s {
3236 #ifdef __BIG_ENDIAN_BITFIELD
3237 uint64_t set:64;
3238 #else
3239 uint64_t set:64;
3240 #endif
3241 } s;
3242 struct cvmx_npei_msi_w1s_enb2_s cn52xx;
3243 struct cvmx_npei_msi_w1s_enb2_s cn56xx;
3244 };
3245
3246 union cvmx_npei_msi_w1s_enb3 {
3247 uint64_t u64;
3248 struct cvmx_npei_msi_w1s_enb3_s {
3249 #ifdef __BIG_ENDIAN_BITFIELD
3250 uint64_t set:64;
3251 #else
3252 uint64_t set:64;
3253 #endif
3254 } s;
3255 struct cvmx_npei_msi_w1s_enb3_s cn52xx;
3256 struct cvmx_npei_msi_w1s_enb3_s cn56xx;
3257 };
3258
3259 union cvmx_npei_msi_wr_map {
3260 uint64_t u64;
3261 struct cvmx_npei_msi_wr_map_s {
3262 #ifdef __BIG_ENDIAN_BITFIELD
3263 uint64_t reserved_16_63:48;
3264 uint64_t ciu_int:8;
3265 uint64_t msi_int:8;
3266 #else
3267 uint64_t msi_int:8;
3268 uint64_t ciu_int:8;
3269 uint64_t reserved_16_63:48;
3270 #endif
3271 } s;
3272 struct cvmx_npei_msi_wr_map_s cn52xx;
3273 struct cvmx_npei_msi_wr_map_s cn52xxp1;
3274 struct cvmx_npei_msi_wr_map_s cn56xx;
3275 struct cvmx_npei_msi_wr_map_s cn56xxp1;
3276 };
3277
3278 union cvmx_npei_pcie_credit_cnt {
3279 uint64_t u64;
3280 struct cvmx_npei_pcie_credit_cnt_s {
3281 #ifdef __BIG_ENDIAN_BITFIELD
3282 uint64_t reserved_48_63:16;
3283 uint64_t p1_ccnt:8;
3284 uint64_t p1_ncnt:8;
3285 uint64_t p1_pcnt:8;
3286 uint64_t p0_ccnt:8;
3287 uint64_t p0_ncnt:8;
3288 uint64_t p0_pcnt:8;
3289 #else
3290 uint64_t p0_pcnt:8;
3291 uint64_t p0_ncnt:8;
3292 uint64_t p0_ccnt:8;
3293 uint64_t p1_pcnt:8;
3294 uint64_t p1_ncnt:8;
3295 uint64_t p1_ccnt:8;
3296 uint64_t reserved_48_63:16;
3297 #endif
3298 } s;
3299 struct cvmx_npei_pcie_credit_cnt_s cn52xx;
3300 struct cvmx_npei_pcie_credit_cnt_s cn56xx;
3301 };
3302
3303 union cvmx_npei_pcie_msi_rcv {
3304 uint64_t u64;
3305 struct cvmx_npei_pcie_msi_rcv_s {
3306 #ifdef __BIG_ENDIAN_BITFIELD
3307 uint64_t reserved_8_63:56;
3308 uint64_t intr:8;
3309 #else
3310 uint64_t intr:8;
3311 uint64_t reserved_8_63:56;
3312 #endif
3313 } s;
3314 struct cvmx_npei_pcie_msi_rcv_s cn52xx;
3315 struct cvmx_npei_pcie_msi_rcv_s cn52xxp1;
3316 struct cvmx_npei_pcie_msi_rcv_s cn56xx;
3317 struct cvmx_npei_pcie_msi_rcv_s cn56xxp1;
3318 };
3319
3320 union cvmx_npei_pcie_msi_rcv_b1 {
3321 uint64_t u64;
3322 struct cvmx_npei_pcie_msi_rcv_b1_s {
3323 #ifdef __BIG_ENDIAN_BITFIELD
3324 uint64_t reserved_16_63:48;
3325 uint64_t intr:8;
3326 uint64_t reserved_0_7:8;
3327 #else
3328 uint64_t reserved_0_7:8;
3329 uint64_t intr:8;
3330 uint64_t reserved_16_63:48;
3331 #endif
3332 } s;
3333 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx;
3334 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1;
3335 struct cvmx_npei_pcie_msi_rcv_b1_s cn56xx;
3336 struct cvmx_npei_pcie_msi_rcv_b1_s cn56xxp1;
3337 };
3338
3339 union cvmx_npei_pcie_msi_rcv_b2 {
3340 uint64_t u64;
3341 struct cvmx_npei_pcie_msi_rcv_b2_s {
3342 #ifdef __BIG_ENDIAN_BITFIELD
3343 uint64_t reserved_24_63:40;
3344 uint64_t intr:8;
3345 uint64_t reserved_0_15:16;
3346 #else
3347 uint64_t reserved_0_15:16;
3348 uint64_t intr:8;
3349 uint64_t reserved_24_63:40;
3350 #endif
3351 } s;
3352 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx;
3353 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1;
3354 struct cvmx_npei_pcie_msi_rcv_b2_s cn56xx;
3355 struct cvmx_npei_pcie_msi_rcv_b2_s cn56xxp1;
3356 };
3357
3358 union cvmx_npei_pcie_msi_rcv_b3 {
3359 uint64_t u64;
3360 struct cvmx_npei_pcie_msi_rcv_b3_s {
3361 #ifdef __BIG_ENDIAN_BITFIELD
3362 uint64_t reserved_32_63:32;
3363 uint64_t intr:8;
3364 uint64_t reserved_0_23:24;
3365 #else
3366 uint64_t reserved_0_23:24;
3367 uint64_t intr:8;
3368 uint64_t reserved_32_63:32;
3369 #endif
3370 } s;
3371 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx;
3372 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1;
3373 struct cvmx_npei_pcie_msi_rcv_b3_s cn56xx;
3374 struct cvmx_npei_pcie_msi_rcv_b3_s cn56xxp1;
3375 };
3376
3377 union cvmx_npei_pktx_cnts {
3378 uint64_t u64;
3379 struct cvmx_npei_pktx_cnts_s {
3380 #ifdef __BIG_ENDIAN_BITFIELD
3381 uint64_t reserved_54_63:10;
3382 uint64_t timer:22;
3383 uint64_t cnt:32;
3384 #else
3385 uint64_t cnt:32;
3386 uint64_t timer:22;
3387 uint64_t reserved_54_63:10;
3388 #endif
3389 } s;
3390 struct cvmx_npei_pktx_cnts_s cn52xx;
3391 struct cvmx_npei_pktx_cnts_s cn56xx;
3392 };
3393
3394 union cvmx_npei_pktx_in_bp {
3395 uint64_t u64;
3396 struct cvmx_npei_pktx_in_bp_s {
3397 #ifdef __BIG_ENDIAN_BITFIELD
3398 uint64_t wmark:32;
3399 uint64_t cnt:32;
3400 #else
3401 uint64_t cnt:32;
3402 uint64_t wmark:32;
3403 #endif
3404 } s;
3405 struct cvmx_npei_pktx_in_bp_s cn52xx;
3406 struct cvmx_npei_pktx_in_bp_s cn56xx;
3407 };
3408
3409 union cvmx_npei_pktx_instr_baddr {
3410 uint64_t u64;
3411 struct cvmx_npei_pktx_instr_baddr_s {
3412 #ifdef __BIG_ENDIAN_BITFIELD
3413 uint64_t addr:61;
3414 uint64_t reserved_0_2:3;
3415 #else
3416 uint64_t reserved_0_2:3;
3417 uint64_t addr:61;
3418 #endif
3419 } s;
3420 struct cvmx_npei_pktx_instr_baddr_s cn52xx;
3421 struct cvmx_npei_pktx_instr_baddr_s cn56xx;
3422 };
3423
3424 union cvmx_npei_pktx_instr_baoff_dbell {
3425 uint64_t u64;
3426 struct cvmx_npei_pktx_instr_baoff_dbell_s {
3427 #ifdef __BIG_ENDIAN_BITFIELD
3428 uint64_t aoff:32;
3429 uint64_t dbell:32;
3430 #else
3431 uint64_t dbell:32;
3432 uint64_t aoff:32;
3433 #endif
3434 } s;
3435 struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
3436 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
3437 };
3438
3439 union cvmx_npei_pktx_instr_fifo_rsize {
3440 uint64_t u64;
3441 struct cvmx_npei_pktx_instr_fifo_rsize_s {
3442 #ifdef __BIG_ENDIAN_BITFIELD
3443 uint64_t max:9;
3444 uint64_t rrp:9;
3445 uint64_t wrp:9;
3446 uint64_t fcnt:5;
3447 uint64_t rsize:32;
3448 #else
3449 uint64_t rsize:32;
3450 uint64_t fcnt:5;
3451 uint64_t wrp:9;
3452 uint64_t rrp:9;
3453 uint64_t max:9;
3454 #endif
3455 } s;
3456 struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
3457 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
3458 };
3459
3460 union cvmx_npei_pktx_instr_header {
3461 uint64_t u64;
3462 struct cvmx_npei_pktx_instr_header_s {
3463 #ifdef __BIG_ENDIAN_BITFIELD
3464 uint64_t reserved_44_63:20;
3465 uint64_t pbp:1;
3466 uint64_t reserved_38_42:5;
3467 uint64_t rparmode:2;
3468 uint64_t reserved_35_35:1;
3469 uint64_t rskp_len:7;
3470 uint64_t reserved_22_27:6;
3471 uint64_t use_ihdr:1;
3472 uint64_t reserved_16_20:5;
3473 uint64_t par_mode:2;
3474 uint64_t reserved_13_13:1;
3475 uint64_t skp_len:7;
3476 uint64_t reserved_0_5:6;
3477 #else
3478 uint64_t reserved_0_5:6;
3479 uint64_t skp_len:7;
3480 uint64_t reserved_13_13:1;
3481 uint64_t par_mode:2;
3482 uint64_t reserved_16_20:5;
3483 uint64_t use_ihdr:1;
3484 uint64_t reserved_22_27:6;
3485 uint64_t rskp_len:7;
3486 uint64_t reserved_35_35:1;
3487 uint64_t rparmode:2;
3488 uint64_t reserved_38_42:5;
3489 uint64_t pbp:1;
3490 uint64_t reserved_44_63:20;
3491 #endif
3492 } s;
3493 struct cvmx_npei_pktx_instr_header_s cn52xx;
3494 struct cvmx_npei_pktx_instr_header_s cn56xx;
3495 };
3496
3497 union cvmx_npei_pktx_slist_baddr {
3498 uint64_t u64;
3499 struct cvmx_npei_pktx_slist_baddr_s {
3500 #ifdef __BIG_ENDIAN_BITFIELD
3501 uint64_t addr:60;
3502 uint64_t reserved_0_3:4;
3503 #else
3504 uint64_t reserved_0_3:4;
3505 uint64_t addr:60;
3506 #endif
3507 } s;
3508 struct cvmx_npei_pktx_slist_baddr_s cn52xx;
3509 struct cvmx_npei_pktx_slist_baddr_s cn56xx;
3510 };
3511
3512 union cvmx_npei_pktx_slist_baoff_dbell {
3513 uint64_t u64;
3514 struct cvmx_npei_pktx_slist_baoff_dbell_s {
3515 #ifdef __BIG_ENDIAN_BITFIELD
3516 uint64_t aoff:32;
3517 uint64_t dbell:32;
3518 #else
3519 uint64_t dbell:32;
3520 uint64_t aoff:32;
3521 #endif
3522 } s;
3523 struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
3524 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
3525 };
3526
3527 union cvmx_npei_pktx_slist_fifo_rsize {
3528 uint64_t u64;
3529 struct cvmx_npei_pktx_slist_fifo_rsize_s {
3530 #ifdef __BIG_ENDIAN_BITFIELD
3531 uint64_t reserved_32_63:32;
3532 uint64_t rsize:32;
3533 #else
3534 uint64_t rsize:32;
3535 uint64_t reserved_32_63:32;
3536 #endif
3537 } s;
3538 struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
3539 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
3540 };
3541
3542 union cvmx_npei_pkt_cnt_int {
3543 uint64_t u64;
3544 struct cvmx_npei_pkt_cnt_int_s {
3545 #ifdef __BIG_ENDIAN_BITFIELD
3546 uint64_t reserved_32_63:32;
3547 uint64_t port:32;
3548 #else
3549 uint64_t port:32;
3550 uint64_t reserved_32_63:32;
3551 #endif
3552 } s;
3553 struct cvmx_npei_pkt_cnt_int_s cn52xx;
3554 struct cvmx_npei_pkt_cnt_int_s cn56xx;
3555 };
3556
3557 union cvmx_npei_pkt_cnt_int_enb {
3558 uint64_t u64;
3559 struct cvmx_npei_pkt_cnt_int_enb_s {
3560 #ifdef __BIG_ENDIAN_BITFIELD
3561 uint64_t reserved_32_63:32;
3562 uint64_t port:32;
3563 #else
3564 uint64_t port:32;
3565 uint64_t reserved_32_63:32;
3566 #endif
3567 } s;
3568 struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
3569 struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
3570 };
3571
3572 union cvmx_npei_pkt_data_out_es {
3573 uint64_t u64;
3574 struct cvmx_npei_pkt_data_out_es_s {
3575 #ifdef __BIG_ENDIAN_BITFIELD
3576 uint64_t es:64;
3577 #else
3578 uint64_t es:64;
3579 #endif
3580 } s;
3581 struct cvmx_npei_pkt_data_out_es_s cn52xx;
3582 struct cvmx_npei_pkt_data_out_es_s cn56xx;
3583 };
3584
3585 union cvmx_npei_pkt_data_out_ns {
3586 uint64_t u64;
3587 struct cvmx_npei_pkt_data_out_ns_s {
3588 #ifdef __BIG_ENDIAN_BITFIELD
3589 uint64_t reserved_32_63:32;
3590 uint64_t nsr:32;
3591 #else
3592 uint64_t nsr:32;
3593 uint64_t reserved_32_63:32;
3594 #endif
3595 } s;
3596 struct cvmx_npei_pkt_data_out_ns_s cn52xx;
3597 struct cvmx_npei_pkt_data_out_ns_s cn56xx;
3598 };
3599
3600 union cvmx_npei_pkt_data_out_ror {
3601 uint64_t u64;
3602 struct cvmx_npei_pkt_data_out_ror_s {
3603 #ifdef __BIG_ENDIAN_BITFIELD
3604 uint64_t reserved_32_63:32;
3605 uint64_t ror:32;
3606 #else
3607 uint64_t ror:32;
3608 uint64_t reserved_32_63:32;
3609 #endif
3610 } s;
3611 struct cvmx_npei_pkt_data_out_ror_s cn52xx;
3612 struct cvmx_npei_pkt_data_out_ror_s cn56xx;
3613 };
3614
3615 union cvmx_npei_pkt_dpaddr {
3616 uint64_t u64;
3617 struct cvmx_npei_pkt_dpaddr_s {
3618 #ifdef __BIG_ENDIAN_BITFIELD
3619 uint64_t reserved_32_63:32;
3620 uint64_t dptr:32;
3621 #else
3622 uint64_t dptr:32;
3623 uint64_t reserved_32_63:32;
3624 #endif
3625 } s;
3626 struct cvmx_npei_pkt_dpaddr_s cn52xx;
3627 struct cvmx_npei_pkt_dpaddr_s cn56xx;
3628 };
3629
3630 union cvmx_npei_pkt_in_bp {
3631 uint64_t u64;
3632 struct cvmx_npei_pkt_in_bp_s {
3633 #ifdef __BIG_ENDIAN_BITFIELD
3634 uint64_t reserved_32_63:32;
3635 uint64_t bp:32;
3636 #else
3637 uint64_t bp:32;
3638 uint64_t reserved_32_63:32;
3639 #endif
3640 } s;
3641 struct cvmx_npei_pkt_in_bp_s cn52xx;
3642 struct cvmx_npei_pkt_in_bp_s cn56xx;
3643 };
3644
3645 union cvmx_npei_pkt_in_donex_cnts {
3646 uint64_t u64;
3647 struct cvmx_npei_pkt_in_donex_cnts_s {
3648 #ifdef __BIG_ENDIAN_BITFIELD
3649 uint64_t reserved_32_63:32;
3650 uint64_t cnt:32;
3651 #else
3652 uint64_t cnt:32;
3653 uint64_t reserved_32_63:32;
3654 #endif
3655 } s;
3656 struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
3657 struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
3658 };
3659
3660 union cvmx_npei_pkt_in_instr_counts {
3661 uint64_t u64;
3662 struct cvmx_npei_pkt_in_instr_counts_s {
3663 #ifdef __BIG_ENDIAN_BITFIELD
3664 uint64_t wr_cnt:32;
3665 uint64_t rd_cnt:32;
3666 #else
3667 uint64_t rd_cnt:32;
3668 uint64_t wr_cnt:32;
3669 #endif
3670 } s;
3671 struct cvmx_npei_pkt_in_instr_counts_s cn52xx;
3672 struct cvmx_npei_pkt_in_instr_counts_s cn56xx;
3673 };
3674
3675 union cvmx_npei_pkt_in_pcie_port {
3676 uint64_t u64;
3677 struct cvmx_npei_pkt_in_pcie_port_s {
3678 #ifdef __BIG_ENDIAN_BITFIELD
3679 uint64_t pp:64;
3680 #else
3681 uint64_t pp:64;
3682 #endif
3683 } s;
3684 struct cvmx_npei_pkt_in_pcie_port_s cn52xx;
3685 struct cvmx_npei_pkt_in_pcie_port_s cn56xx;
3686 };
3687
3688 union cvmx_npei_pkt_input_control {
3689 uint64_t u64;
3690 struct cvmx_npei_pkt_input_control_s {
3691 #ifdef __BIG_ENDIAN_BITFIELD
3692 uint64_t reserved_23_63:41;
3693 uint64_t pkt_rr:1;
3694 uint64_t pbp_dhi:13;
3695 uint64_t d_nsr:1;
3696 uint64_t d_esr:2;
3697 uint64_t d_ror:1;
3698 uint64_t use_csr:1;
3699 uint64_t nsr:1;
3700 uint64_t esr:2;
3701 uint64_t ror:1;
3702 #else
3703 uint64_t ror:1;
3704 uint64_t esr:2;
3705 uint64_t nsr:1;
3706 uint64_t use_csr:1;
3707 uint64_t d_ror:1;
3708 uint64_t d_esr:2;
3709 uint64_t d_nsr:1;
3710 uint64_t pbp_dhi:13;
3711 uint64_t pkt_rr:1;
3712 uint64_t reserved_23_63:41;
3713 #endif
3714 } s;
3715 struct cvmx_npei_pkt_input_control_s cn52xx;
3716 struct cvmx_npei_pkt_input_control_s cn56xx;
3717 };
3718
3719 union cvmx_npei_pkt_instr_enb {
3720 uint64_t u64;
3721 struct cvmx_npei_pkt_instr_enb_s {
3722 #ifdef __BIG_ENDIAN_BITFIELD
3723 uint64_t reserved_32_63:32;
3724 uint64_t enb:32;
3725 #else
3726 uint64_t enb:32;
3727 uint64_t reserved_32_63:32;
3728 #endif
3729 } s;
3730 struct cvmx_npei_pkt_instr_enb_s cn52xx;
3731 struct cvmx_npei_pkt_instr_enb_s cn56xx;
3732 };
3733
3734 union cvmx_npei_pkt_instr_rd_size {
3735 uint64_t u64;
3736 struct cvmx_npei_pkt_instr_rd_size_s {
3737 #ifdef __BIG_ENDIAN_BITFIELD
3738 uint64_t rdsize:64;
3739 #else
3740 uint64_t rdsize:64;
3741 #endif
3742 } s;
3743 struct cvmx_npei_pkt_instr_rd_size_s cn52xx;
3744 struct cvmx_npei_pkt_instr_rd_size_s cn56xx;
3745 };
3746
3747 union cvmx_npei_pkt_instr_size {
3748 uint64_t u64;
3749 struct cvmx_npei_pkt_instr_size_s {
3750 #ifdef __BIG_ENDIAN_BITFIELD
3751 uint64_t reserved_32_63:32;
3752 uint64_t is_64b:32;
3753 #else
3754 uint64_t is_64b:32;
3755 uint64_t reserved_32_63:32;
3756 #endif
3757 } s;
3758 struct cvmx_npei_pkt_instr_size_s cn52xx;
3759 struct cvmx_npei_pkt_instr_size_s cn56xx;
3760 };
3761
3762 union cvmx_npei_pkt_int_levels {
3763 uint64_t u64;
3764 struct cvmx_npei_pkt_int_levels_s {
3765 #ifdef __BIG_ENDIAN_BITFIELD
3766 uint64_t reserved_54_63:10;
3767 uint64_t time:22;
3768 uint64_t cnt:32;
3769 #else
3770 uint64_t cnt:32;
3771 uint64_t time:22;
3772 uint64_t reserved_54_63:10;
3773 #endif
3774 } s;
3775 struct cvmx_npei_pkt_int_levels_s cn52xx;
3776 struct cvmx_npei_pkt_int_levels_s cn56xx;
3777 };
3778
3779 union cvmx_npei_pkt_iptr {
3780 uint64_t u64;
3781 struct cvmx_npei_pkt_iptr_s {
3782 #ifdef __BIG_ENDIAN_BITFIELD
3783 uint64_t reserved_32_63:32;
3784 uint64_t iptr:32;
3785 #else
3786 uint64_t iptr:32;
3787 uint64_t reserved_32_63:32;
3788 #endif
3789 } s;
3790 struct cvmx_npei_pkt_iptr_s cn52xx;
3791 struct cvmx_npei_pkt_iptr_s cn56xx;
3792 };
3793
3794 union cvmx_npei_pkt_out_bmode {
3795 uint64_t u64;
3796 struct cvmx_npei_pkt_out_bmode_s {
3797 #ifdef __BIG_ENDIAN_BITFIELD
3798 uint64_t reserved_32_63:32;
3799 uint64_t bmode:32;
3800 #else
3801 uint64_t bmode:32;
3802 uint64_t reserved_32_63:32;
3803 #endif
3804 } s;
3805 struct cvmx_npei_pkt_out_bmode_s cn52xx;
3806 struct cvmx_npei_pkt_out_bmode_s cn56xx;
3807 };
3808
3809 union cvmx_npei_pkt_out_enb {
3810 uint64_t u64;
3811 struct cvmx_npei_pkt_out_enb_s {
3812 #ifdef __BIG_ENDIAN_BITFIELD
3813 uint64_t reserved_32_63:32;
3814 uint64_t enb:32;
3815 #else
3816 uint64_t enb:32;
3817 uint64_t reserved_32_63:32;
3818 #endif
3819 } s;
3820 struct cvmx_npei_pkt_out_enb_s cn52xx;
3821 struct cvmx_npei_pkt_out_enb_s cn56xx;
3822 };
3823
3824 union cvmx_npei_pkt_output_wmark {
3825 uint64_t u64;
3826 struct cvmx_npei_pkt_output_wmark_s {
3827 #ifdef __BIG_ENDIAN_BITFIELD
3828 uint64_t reserved_32_63:32;
3829 uint64_t wmark:32;
3830 #else
3831 uint64_t wmark:32;
3832 uint64_t reserved_32_63:32;
3833 #endif
3834 } s;
3835 struct cvmx_npei_pkt_output_wmark_s cn52xx;
3836 struct cvmx_npei_pkt_output_wmark_s cn56xx;
3837 };
3838
3839 union cvmx_npei_pkt_pcie_port {
3840 uint64_t u64;
3841 struct cvmx_npei_pkt_pcie_port_s {
3842 #ifdef __BIG_ENDIAN_BITFIELD
3843 uint64_t pp:64;
3844 #else
3845 uint64_t pp:64;
3846 #endif
3847 } s;
3848 struct cvmx_npei_pkt_pcie_port_s cn52xx;
3849 struct cvmx_npei_pkt_pcie_port_s cn56xx;
3850 };
3851
3852 union cvmx_npei_pkt_port_in_rst {
3853 uint64_t u64;
3854 struct cvmx_npei_pkt_port_in_rst_s {
3855 #ifdef __BIG_ENDIAN_BITFIELD
3856 uint64_t in_rst:32;
3857 uint64_t out_rst:32;
3858 #else
3859 uint64_t out_rst:32;
3860 uint64_t in_rst:32;
3861 #endif
3862 } s;
3863 struct cvmx_npei_pkt_port_in_rst_s cn52xx;
3864 struct cvmx_npei_pkt_port_in_rst_s cn56xx;
3865 };
3866
3867 union cvmx_npei_pkt_slist_es {
3868 uint64_t u64;
3869 struct cvmx_npei_pkt_slist_es_s {
3870 #ifdef __BIG_ENDIAN_BITFIELD
3871 uint64_t es:64;
3872 #else
3873 uint64_t es:64;
3874 #endif
3875 } s;
3876 struct cvmx_npei_pkt_slist_es_s cn52xx;
3877 struct cvmx_npei_pkt_slist_es_s cn56xx;
3878 };
3879
3880 union cvmx_npei_pkt_slist_id_size {
3881 uint64_t u64;
3882 struct cvmx_npei_pkt_slist_id_size_s {
3883 #ifdef __BIG_ENDIAN_BITFIELD
3884 uint64_t reserved_23_63:41;
3885 uint64_t isize:7;
3886 uint64_t bsize:16;
3887 #else
3888 uint64_t bsize:16;
3889 uint64_t isize:7;
3890 uint64_t reserved_23_63:41;
3891 #endif
3892 } s;
3893 struct cvmx_npei_pkt_slist_id_size_s cn52xx;
3894 struct cvmx_npei_pkt_slist_id_size_s cn56xx;
3895 };
3896
3897 union cvmx_npei_pkt_slist_ns {
3898 uint64_t u64;
3899 struct cvmx_npei_pkt_slist_ns_s {
3900 #ifdef __BIG_ENDIAN_BITFIELD
3901 uint64_t reserved_32_63:32;
3902 uint64_t nsr:32;
3903 #else
3904 uint64_t nsr:32;
3905 uint64_t reserved_32_63:32;
3906 #endif
3907 } s;
3908 struct cvmx_npei_pkt_slist_ns_s cn52xx;
3909 struct cvmx_npei_pkt_slist_ns_s cn56xx;
3910 };
3911
3912 union cvmx_npei_pkt_slist_ror {
3913 uint64_t u64;
3914 struct cvmx_npei_pkt_slist_ror_s {
3915 #ifdef __BIG_ENDIAN_BITFIELD
3916 uint64_t reserved_32_63:32;
3917 uint64_t ror:32;
3918 #else
3919 uint64_t ror:32;
3920 uint64_t reserved_32_63:32;
3921 #endif
3922 } s;
3923 struct cvmx_npei_pkt_slist_ror_s cn52xx;
3924 struct cvmx_npei_pkt_slist_ror_s cn56xx;
3925 };
3926
3927 union cvmx_npei_pkt_time_int {
3928 uint64_t u64;
3929 struct cvmx_npei_pkt_time_int_s {
3930 #ifdef __BIG_ENDIAN_BITFIELD
3931 uint64_t reserved_32_63:32;
3932 uint64_t port:32;
3933 #else
3934 uint64_t port:32;
3935 uint64_t reserved_32_63:32;
3936 #endif
3937 } s;
3938 struct cvmx_npei_pkt_time_int_s cn52xx;
3939 struct cvmx_npei_pkt_time_int_s cn56xx;
3940 };
3941
3942 union cvmx_npei_pkt_time_int_enb {
3943 uint64_t u64;
3944 struct cvmx_npei_pkt_time_int_enb_s {
3945 #ifdef __BIG_ENDIAN_BITFIELD
3946 uint64_t reserved_32_63:32;
3947 uint64_t port:32;
3948 #else
3949 uint64_t port:32;
3950 uint64_t reserved_32_63:32;
3951 #endif
3952 } s;
3953 struct cvmx_npei_pkt_time_int_enb_s cn52xx;
3954 struct cvmx_npei_pkt_time_int_enb_s cn56xx;
3955 };
3956
3957 union cvmx_npei_rsl_int_blocks {
3958 uint64_t u64;
3959 struct cvmx_npei_rsl_int_blocks_s {
3960 #ifdef __BIG_ENDIAN_BITFIELD
3961 uint64_t reserved_31_63:33;
3962 uint64_t iob:1;
3963 uint64_t lmc1:1;
3964 uint64_t agl:1;
3965 uint64_t reserved_24_27:4;
3966 uint64_t asxpcs1:1;
3967 uint64_t asxpcs0:1;
3968 uint64_t reserved_21_21:1;
3969 uint64_t pip:1;
3970 uint64_t spx1:1;
3971 uint64_t spx0:1;
3972 uint64_t lmc0:1;
3973 uint64_t l2c:1;
3974 uint64_t usb1:1;
3975 uint64_t rad:1;
3976 uint64_t usb:1;
3977 uint64_t pow:1;
3978 uint64_t tim:1;
3979 uint64_t pko:1;
3980 uint64_t ipd:1;
3981 uint64_t reserved_8_8:1;
3982 uint64_t zip:1;
3983 uint64_t dfa:1;
3984 uint64_t fpa:1;
3985 uint64_t key:1;
3986 uint64_t npei:1;
3987 uint64_t gmx1:1;
3988 uint64_t gmx0:1;
3989 uint64_t mio:1;
3990 #else
3991 uint64_t mio:1;
3992 uint64_t gmx0:1;
3993 uint64_t gmx1:1;
3994 uint64_t npei:1;
3995 uint64_t key:1;
3996 uint64_t fpa:1;
3997 uint64_t dfa:1;
3998 uint64_t zip:1;
3999 uint64_t reserved_8_8:1;
4000 uint64_t ipd:1;
4001 uint64_t pko:1;
4002 uint64_t tim:1;
4003 uint64_t pow:1;
4004 uint64_t usb:1;
4005 uint64_t rad:1;
4006 uint64_t usb1:1;
4007 uint64_t l2c:1;
4008 uint64_t lmc0:1;
4009 uint64_t spx0:1;
4010 uint64_t spx1:1;
4011 uint64_t pip:1;
4012 uint64_t reserved_21_21:1;
4013 uint64_t asxpcs0:1;
4014 uint64_t asxpcs1:1;
4015 uint64_t reserved_24_27:4;
4016 uint64_t agl:1;
4017 uint64_t lmc1:1;
4018 uint64_t iob:1;
4019 uint64_t reserved_31_63:33;
4020 #endif
4021 } s;
4022 struct cvmx_npei_rsl_int_blocks_s cn52xx;
4023 struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
4024 struct cvmx_npei_rsl_int_blocks_s cn56xx;
4025 struct cvmx_npei_rsl_int_blocks_s cn56xxp1;
4026 };
4027
4028 union cvmx_npei_scratch_1 {
4029 uint64_t u64;
4030 struct cvmx_npei_scratch_1_s {
4031 #ifdef __BIG_ENDIAN_BITFIELD
4032 uint64_t data:64;
4033 #else
4034 uint64_t data:64;
4035 #endif
4036 } s;
4037 struct cvmx_npei_scratch_1_s cn52xx;
4038 struct cvmx_npei_scratch_1_s cn52xxp1;
4039 struct cvmx_npei_scratch_1_s cn56xx;
4040 struct cvmx_npei_scratch_1_s cn56xxp1;
4041 };
4042
4043 union cvmx_npei_state1 {
4044 uint64_t u64;
4045 struct cvmx_npei_state1_s {
4046 #ifdef __BIG_ENDIAN_BITFIELD
4047 uint64_t cpl1:12;
4048 uint64_t cpl0:12;
4049 uint64_t arb:1;
4050 uint64_t csr:39;
4051 #else
4052 uint64_t csr:39;
4053 uint64_t arb:1;
4054 uint64_t cpl0:12;
4055 uint64_t cpl1:12;
4056 #endif
4057 } s;
4058 struct cvmx_npei_state1_s cn52xx;
4059 struct cvmx_npei_state1_s cn52xxp1;
4060 struct cvmx_npei_state1_s cn56xx;
4061 struct cvmx_npei_state1_s cn56xxp1;
4062 };
4063
4064 union cvmx_npei_state2 {
4065 uint64_t u64;
4066 struct cvmx_npei_state2_s {
4067 #ifdef __BIG_ENDIAN_BITFIELD
4068 uint64_t reserved_48_63:16;
4069 uint64_t npei:1;
4070 uint64_t rac:1;
4071 uint64_t csm1:15;
4072 uint64_t csm0:15;
4073 uint64_t nnp0:8;
4074 uint64_t nnd:8;
4075 #else
4076 uint64_t nnd:8;
4077 uint64_t nnp0:8;
4078 uint64_t csm0:15;
4079 uint64_t csm1:15;
4080 uint64_t rac:1;
4081 uint64_t npei:1;
4082 uint64_t reserved_48_63:16;
4083 #endif
4084 } s;
4085 struct cvmx_npei_state2_s cn52xx;
4086 struct cvmx_npei_state2_s cn52xxp1;
4087 struct cvmx_npei_state2_s cn56xx;
4088 struct cvmx_npei_state2_s cn56xxp1;
4089 };
4090
4091 union cvmx_npei_state3 {
4092 uint64_t u64;
4093 struct cvmx_npei_state3_s {
4094 #ifdef __BIG_ENDIAN_BITFIELD
4095 uint64_t reserved_56_63:8;
4096 uint64_t psm1:15;
4097 uint64_t psm0:15;
4098 uint64_t nsm1:13;
4099 uint64_t nsm0:13;
4100 #else
4101 uint64_t nsm0:13;
4102 uint64_t nsm1:13;
4103 uint64_t psm0:15;
4104 uint64_t psm1:15;
4105 uint64_t reserved_56_63:8;
4106 #endif
4107 } s;
4108 struct cvmx_npei_state3_s cn52xx;
4109 struct cvmx_npei_state3_s cn52xxp1;
4110 struct cvmx_npei_state3_s cn56xx;
4111 struct cvmx_npei_state3_s cn56xxp1;
4112 };
4113
4114 union cvmx_npei_win_rd_addr {
4115 uint64_t u64;
4116 struct cvmx_npei_win_rd_addr_s {
4117 #ifdef __BIG_ENDIAN_BITFIELD
4118 uint64_t reserved_51_63:13;
4119 uint64_t ld_cmd:2;
4120 uint64_t iobit:1;
4121 uint64_t rd_addr:48;
4122 #else
4123 uint64_t rd_addr:48;
4124 uint64_t iobit:1;
4125 uint64_t ld_cmd:2;
4126 uint64_t reserved_51_63:13;
4127 #endif
4128 } s;
4129 struct cvmx_npei_win_rd_addr_s cn52xx;
4130 struct cvmx_npei_win_rd_addr_s cn52xxp1;
4131 struct cvmx_npei_win_rd_addr_s cn56xx;
4132 struct cvmx_npei_win_rd_addr_s cn56xxp1;
4133 };
4134
4135 union cvmx_npei_win_rd_data {
4136 uint64_t u64;
4137 struct cvmx_npei_win_rd_data_s {
4138 #ifdef __BIG_ENDIAN_BITFIELD
4139 uint64_t rd_data:64;
4140 #else
4141 uint64_t rd_data:64;
4142 #endif
4143 } s;
4144 struct cvmx_npei_win_rd_data_s cn52xx;
4145 struct cvmx_npei_win_rd_data_s cn52xxp1;
4146 struct cvmx_npei_win_rd_data_s cn56xx;
4147 struct cvmx_npei_win_rd_data_s cn56xxp1;
4148 };
4149
4150 union cvmx_npei_win_wr_addr {
4151 uint64_t u64;
4152 struct cvmx_npei_win_wr_addr_s {
4153 #ifdef __BIG_ENDIAN_BITFIELD
4154 uint64_t reserved_49_63:15;
4155 uint64_t iobit:1;
4156 uint64_t wr_addr:46;
4157 uint64_t reserved_0_1:2;
4158 #else
4159 uint64_t reserved_0_1:2;
4160 uint64_t wr_addr:46;
4161 uint64_t iobit:1;
4162 uint64_t reserved_49_63:15;
4163 #endif
4164 } s;
4165 struct cvmx_npei_win_wr_addr_s cn52xx;
4166 struct cvmx_npei_win_wr_addr_s cn52xxp1;
4167 struct cvmx_npei_win_wr_addr_s cn56xx;
4168 struct cvmx_npei_win_wr_addr_s cn56xxp1;
4169 };
4170
4171 union cvmx_npei_win_wr_data {
4172 uint64_t u64;
4173 struct cvmx_npei_win_wr_data_s {
4174 #ifdef __BIG_ENDIAN_BITFIELD
4175 uint64_t wr_data:64;
4176 #else
4177 uint64_t wr_data:64;
4178 #endif
4179 } s;
4180 struct cvmx_npei_win_wr_data_s cn52xx;
4181 struct cvmx_npei_win_wr_data_s cn52xxp1;
4182 struct cvmx_npei_win_wr_data_s cn56xx;
4183 struct cvmx_npei_win_wr_data_s cn56xxp1;
4184 };
4185
4186 union cvmx_npei_win_wr_mask {
4187 uint64_t u64;
4188 struct cvmx_npei_win_wr_mask_s {
4189 #ifdef __BIG_ENDIAN_BITFIELD
4190 uint64_t reserved_8_63:56;
4191 uint64_t wr_mask:8;
4192 #else
4193 uint64_t wr_mask:8;
4194 uint64_t reserved_8_63:56;
4195 #endif
4196 } s;
4197 struct cvmx_npei_win_wr_mask_s cn52xx;
4198 struct cvmx_npei_win_wr_mask_s cn52xxp1;
4199 struct cvmx_npei_win_wr_mask_s cn56xx;
4200 struct cvmx_npei_win_wr_mask_s cn56xxp1;
4201 };
4202
4203 union cvmx_npei_window_ctl {
4204 uint64_t u64;
4205 struct cvmx_npei_window_ctl_s {
4206 #ifdef __BIG_ENDIAN_BITFIELD
4207 uint64_t reserved_32_63:32;
4208 uint64_t time:32;
4209 #else
4210 uint64_t time:32;
4211 uint64_t reserved_32_63:32;
4212 #endif
4213 } s;
4214 struct cvmx_npei_window_ctl_s cn52xx;
4215 struct cvmx_npei_window_ctl_s cn52xxp1;
4216 struct cvmx_npei_window_ctl_s cn56xx;
4217 struct cvmx_npei_window_ctl_s cn56xxp1;
4218 };
4219
4220 #endif
CRIS linux kernel tree