1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2008 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
29 * File defining checks for different Octeon features.
32 #ifndef __OCTEON_FEATURE_H__
33 #define __OCTEON_FEATURE_H__
34 #include <asm/octeon/cvmx-mio-defs.h>
35 #include <asm/octeon/cvmx-rnm-defs.h>
38 /* CN68XX uses port kinds for packet interface */
40 /* CN68XX has different fields in word0 - word2 */
41 OCTEON_FEATURE_CN68XX_WQE
,
43 * Octeon models in the CN5XXX family and higher support
44 * atomic add instructions to memory (saa/saad).
47 /* Does this Octeon support the ZIP offload engine? */
49 OCTEON_FEATURE_DORM_CRYPTO
,
50 /* Does this Octeon support PCI express? */
52 /* Does this Octeon support SRIOs */
54 /* Does this Octeon support Interlaken */
56 /* Some Octeon models support internal memory for storing
57 * cryptographic keys */
58 OCTEON_FEATURE_KEY_MEMORY
,
59 /* Octeon has a LED controller for banks of external LEDs */
60 OCTEON_FEATURE_LED_CONTROLLER
,
61 /* Octeon has a trace buffer */
63 /* Octeon has a management port */
64 OCTEON_FEATURE_MGMT_PORT
,
65 /* Octeon has a raid unit */
67 /* Octeon has a builtin USB */
69 /* Octeon IPD can run without using work queue entries */
70 OCTEON_FEATURE_NO_WPTR
,
71 /* Octeon has DFA state machines */
73 /* Octeon MDIO block supports clause 45 transactions for 10
75 OCTEON_FEATURE_MDIO_CLAUSE_45
,
77 * CN52XX and CN56XX used a block named NPEI for PCIe
78 * access. Newer chips replaced this with SLI+DPI.
87 enum octeon_feature_bits
{
88 OCTEON_HAS_CRYPTO
= 0x0001, /* Crypto acceleration using COP2 */
90 extern enum octeon_feature_bits __octeon_feature_bits
;
93 * octeon_has_crypto() - Check if this OCTEON has crypto acceleration support.
95 * Returns: Non-zero if the feature exists. Zero if the feature does not exist.
97 static inline int octeon_has_crypto(void)
99 return __octeon_feature_bits
& OCTEON_HAS_CRYPTO
;
103 * Determine if the current Octeon supports a specific feature. These
104 * checks have been optimized to be fairly quick, but they should still
105 * be kept out of fast path code.
107 * @feature: Feature to check for. This should always be a constant so the
108 * compiler can remove the switch statement through optimization.
110 * Returns Non zero if the feature exists. Zero if the feature does not
113 static inline int octeon_has_feature(enum octeon_feature feature
)
116 case OCTEON_FEATURE_SAAD
:
117 return !OCTEON_IS_MODEL(OCTEON_CN3XXX
);
119 case OCTEON_FEATURE_DORM_CRYPTO
:
120 if (OCTEON_IS_MODEL(OCTEON_CN6XXX
)) {
121 union cvmx_mio_fus_dat2 fus_2
;
122 fus_2
.u64
= cvmx_read_csr(CVMX_MIO_FUS_DAT2
);
123 return !fus_2
.s
.nocrypto
&& !fus_2
.s
.nomul
&& fus_2
.s
.dorm_crypto
;
128 case OCTEON_FEATURE_PCIE
:
129 return OCTEON_IS_MODEL(OCTEON_CN56XX
)
130 || OCTEON_IS_MODEL(OCTEON_CN52XX
)
131 || OCTEON_IS_MODEL(OCTEON_CN6XXX
);
133 case OCTEON_FEATURE_SRIO
:
134 return OCTEON_IS_MODEL(OCTEON_CN63XX
)
135 || OCTEON_IS_MODEL(OCTEON_CN66XX
);
137 case OCTEON_FEATURE_ILK
:
138 return (OCTEON_IS_MODEL(OCTEON_CN68XX
));
140 case OCTEON_FEATURE_KEY_MEMORY
:
141 return OCTEON_IS_MODEL(OCTEON_CN38XX
)
142 || OCTEON_IS_MODEL(OCTEON_CN58XX
)
143 || OCTEON_IS_MODEL(OCTEON_CN56XX
)
144 || OCTEON_IS_MODEL(OCTEON_CN6XXX
);
146 case OCTEON_FEATURE_LED_CONTROLLER
:
147 return OCTEON_IS_MODEL(OCTEON_CN38XX
)
148 || OCTEON_IS_MODEL(OCTEON_CN58XX
)
149 || OCTEON_IS_MODEL(OCTEON_CN56XX
);
151 case OCTEON_FEATURE_TRA
:
152 return !(OCTEON_IS_MODEL(OCTEON_CN30XX
)
153 || OCTEON_IS_MODEL(OCTEON_CN50XX
));
154 case OCTEON_FEATURE_MGMT_PORT
:
155 return OCTEON_IS_MODEL(OCTEON_CN56XX
)
156 || OCTEON_IS_MODEL(OCTEON_CN52XX
)
157 || OCTEON_IS_MODEL(OCTEON_CN6XXX
);
159 case OCTEON_FEATURE_RAID
:
160 return OCTEON_IS_MODEL(OCTEON_CN56XX
)
161 || OCTEON_IS_MODEL(OCTEON_CN52XX
)
162 || OCTEON_IS_MODEL(OCTEON_CN6XXX
);
164 case OCTEON_FEATURE_USB
:
165 return !(OCTEON_IS_MODEL(OCTEON_CN38XX
)
166 || OCTEON_IS_MODEL(OCTEON_CN58XX
));
168 case OCTEON_FEATURE_NO_WPTR
:
169 return (OCTEON_IS_MODEL(OCTEON_CN56XX
)
170 || OCTEON_IS_MODEL(OCTEON_CN52XX
)
171 || OCTEON_IS_MODEL(OCTEON_CN6XXX
))
172 && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X
)
173 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X
);
175 case OCTEON_FEATURE_MDIO_CLAUSE_45
:
176 return !(OCTEON_IS_MODEL(OCTEON_CN3XXX
)
177 || OCTEON_IS_MODEL(OCTEON_CN58XX
)
178 || OCTEON_IS_MODEL(OCTEON_CN50XX
));
180 case OCTEON_FEATURE_NPEI
:
181 return OCTEON_IS_MODEL(OCTEON_CN56XX
)
182 || OCTEON_IS_MODEL(OCTEON_CN52XX
);
184 case OCTEON_FEATURE_PKND
:
185 return OCTEON_IS_MODEL(OCTEON_CN68XX
);
187 case OCTEON_FEATURE_CN68XX_WQE
:
188 return OCTEON_IS_MODEL(OCTEON_CN68XX
);
190 case OCTEON_FEATURE_CIU2
:
191 return OCTEON_IS_MODEL(OCTEON_CN68XX
);
199 #endif /* __OCTEON_FEATURE_H__ */