arch/mips/include/asm/processor.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994 Waldorf GMBH
   7  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
   8  * Copyright (C) 1996 Paul M. Antoine
   9  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  10  */
  11 #ifndef _ASM_PROCESSOR_H
  12 #define _ASM_PROCESSOR_H
  13
  14 #include <linux/cpumask.h>
  15 #include <linux/threads.h>
  16
  17 #include <asm/cachectl.h>
  18 #include <asm/cpu.h>
  19 #include <asm/cpu-info.h>
  20 #include <asm/mipsregs.h>
  21 #include <asm/prefetch.h>
  22
  23 /*
  24  * Return current * instruction pointer ("program counter").
  25  */
  26 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
  27
  28 /*
  29  * System setup and hardware flags..
  30  */
  31
  32 extern unsigned int vced_count, vcei_count;
  33
  34 /*
  35  * MIPS does have an arch_pick_mmap_layout()
  36  */
  37 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
  38
  39 /*
  40  * A special page (the vdso) is mapped into all processes at the very
  41  * top of the virtual memory space.
  42  */
  43 #define SPECIAL_PAGES_SIZE PAGE_SIZE
  44
  45 #ifdef CONFIG_32BIT
  46 #ifdef CONFIG_KVM_GUEST
  47 /* User space process size is limited to 1GB in KVM Guest Mode */
  48 #define TASK_SIZE       0x3fff8000UL
  49 #else
  50 /*
  51  * User space process size: 2GB. This is hardcoded into a few places,
  52  * so don't change it unless you know what you are doing.
  53  */
  54 #define TASK_SIZE       0x7fff8000UL
  55 #endif
  56
  57 #define STACK_TOP_MAX   TASK_SIZE
  58
  59 #define TASK_IS_32BIT_ADDR 1
  60
  61 #endif
  62
  63 #ifdef CONFIG_64BIT
  64 /*
  65  * User space process size: 1TB. This is hardcoded into a few places,
  66  * so don't change it unless you know what you are doing.  TASK_SIZE
  67  * is limited to 1TB by the R4000 architecture; R10000 and better can
  68  * support 16TB; the architectural reserve for future expansion is
  69  * 8192EB ...
  70  */
  71 #define TASK_SIZE32     0x7fff8000UL
  72 #define TASK_SIZE64     0x10000000000UL
  73 #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
  74 #define STACK_TOP_MAX   TASK_SIZE64
  75
  76 #define TASK_SIZE_OF(tsk)                                               \
  77         (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
  78
  79 #define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
  80
  81 #endif
  82
  83 #define STACK_TOP       ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
  84
  85 /*
  86  * This decides where the kernel will search for a free chunk of vm
  87  * space during mmap's.
  88  */
  89 #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
  90
  91
  92 #define NUM_FPU_REGS    32
  93
  94 #ifdef CONFIG_CPU_HAS_MSA
  95 # define FPU_REG_WIDTH  128
  96 #else
  97 # define FPU_REG_WIDTH  64
  98 #endif
  99
 100 union fpureg {
 101         __u32   val32[FPU_REG_WIDTH / 32];
 102         __u64   val64[FPU_REG_WIDTH / 64];
 103 };
 104
 105 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 106 # define FPR_IDX(width, idx)    (idx)
 107 #else
 108 # define FPR_IDX(width, idx)    ((idx) ^ ((64 / (width)) - 1))
 109 #endif
 110
 111 #define BUILD_FPR_ACCESS(width) \
 112 static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx)  \
 113 {                                                                       \
 114         return fpr->val##width[FPR_IDX(width, idx)];                    \
 115 }                                                                       \
 116                                                                         \
 117 static inline void set_fpr##width(union fpureg *fpr, unsigned idx,      \
 118                                   u##width val)                         \
 119 {                                                                       \
 120         fpr->val##width[FPR_IDX(width, idx)] = val;                     \
 121 }
 122
 123 BUILD_FPR_ACCESS(32)
 124 BUILD_FPR_ACCESS(64)
 125
 126 /*
 127  * It would be nice to add some more fields for emulator statistics,
 128  * the additional information is private to the FPU emulator for now.
 129  * See arch/mips/include/asm/fpu_emulator.h.
 130  */
 131
 132 struct mips_fpu_struct {
 133         union fpureg    fpr[NUM_FPU_REGS];
 134         unsigned int    fcr31;
 135         unsigned int    msacsr;
 136 };
 137
 138 #define NUM_DSP_REGS   6
 139
 140 typedef __u32 dspreg_t;
 141
 142 struct mips_dsp_state {
 143         dspreg_t        dspr[NUM_DSP_REGS];
 144         unsigned int    dspcontrol;
 145 };
 146
 147 #define INIT_CPUMASK { \
 148         {0,} \
 149 }
 150
 151 struct mips3264_watch_reg_state {
 152         /* The width of watchlo is 32 in a 32 bit kernel and 64 in a
 153            64 bit kernel.  We use unsigned long as it has the same
 154            property. */
 155         unsigned long watchlo[NUM_WATCH_REGS];
 156         /* Only the mask and IRW bits from watchhi. */
 157         u16 watchhi[NUM_WATCH_REGS];
 158 };
 159
 160 union mips_watch_reg_state {
 161         struct mips3264_watch_reg_state mips3264;
 162 };
 163
 164 #if defined(CONFIG_CPU_CAVIUM_OCTEON)
 165
 166 struct octeon_cop2_state {
 167         /* DMFC2 rt, 0x0201 */
 168         unsigned long   cop2_crc_iv;
 169         /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
 170         unsigned long   cop2_crc_length;
 171         /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
 172         unsigned long   cop2_crc_poly;
 173         /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
 174         unsigned long   cop2_llm_dat[2];
 175        /* DMFC2 rt, 0x0084 */
 176         unsigned long   cop2_3des_iv;
 177         /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
 178         unsigned long   cop2_3des_key[3];
 179         /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
 180         unsigned long   cop2_3des_result;
 181         /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
 182         unsigned long   cop2_aes_inp0;
 183         /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
 184         unsigned long   cop2_aes_iv[2];
 185         /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
 186          * rt, 0x0107 */
 187         unsigned long   cop2_aes_key[4];
 188         /* DMFC2 rt, 0x0110 */
 189         unsigned long   cop2_aes_keylen;
 190         /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
 191         unsigned long   cop2_aes_result[2];
 192         /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
 193          * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
 194          * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
 195          * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
 196          * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
 197         unsigned long   cop2_hsh_datw[15];
 198         /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
 199          * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
 200          * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
 201         unsigned long   cop2_hsh_ivw[8];
 202         /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
 203         unsigned long   cop2_gfm_mult[2];
 204         /* DMFC2 rt, 0x025E - Pass2 */
 205         unsigned long   cop2_gfm_poly;
 206         /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
 207         unsigned long   cop2_gfm_result[2];
 208         /* DMFC2 rt, 0x24F, DMFC2 rt, 0x50, OCTEON III */
 209         unsigned long   cop2_sha3[2];
 210 };
 211 #define COP2_INIT                                               \
 212         .cp2                    = {0,},
 213
 214 struct octeon_cvmseg_state {
 215         unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
 216                             [cpu_dcache_line_size() / sizeof(unsigned long)];
 217 };
 218
 219 #elif defined(CONFIG_CPU_XLP)
 220 struct nlm_cop2_state {
 221         u64     rx[4];
 222         u64     tx[4];
 223         u32     tx_msg_status;
 224         u32     rx_msg_status;
 225 };
 226
 227 #define COP2_INIT                                               \
 228         .cp2                    = {{0}, {0}, 0, 0},
 229 #else
 230 #define COP2_INIT
 231 #endif
 232
 233 typedef struct {
 234         unsigned long seg;
 235 } mm_segment_t;
 236
 237 #ifdef CONFIG_CPU_HAS_MSA
 238 # define ARCH_MIN_TASKALIGN     16
 239 # define FPU_ALIGN              __aligned(16)
 240 #else
 241 # define ARCH_MIN_TASKALIGN     8
 242 # define FPU_ALIGN
 243 #endif
 244
 245 struct mips_abi;
 246
 247 /*
 248  * If you change thread_struct remember to change the #defines below too!
 249  */
 250 struct thread_struct {
 251         /* Saved main processor registers. */
 252         unsigned long reg16;
 253         unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
 254         unsigned long reg29, reg30, reg31;
 255
 256         /* Saved cp0 stuff. */
 257         unsigned long cp0_status;
 258
 259         /* Saved fpu/fpu emulator stuff. */
 260         struct mips_fpu_struct fpu FPU_ALIGN;
 261 #ifdef CONFIG_MIPS_MT_FPAFF
 262         /* Emulated instruction count */
 263         unsigned long emulated_fp;
 264         /* Saved per-thread scheduler affinity mask */
 265         cpumask_t user_cpus_allowed;
 266 #endif /* CONFIG_MIPS_MT_FPAFF */
 267
 268         /* Saved state of the DSP ASE, if available. */
 269         struct mips_dsp_state dsp;
 270
 271         /* Saved watch register state, if available. */
 272         union mips_watch_reg_state watch;
 273
 274         /* Other stuff associated with the thread. */
 275         unsigned long cp0_badvaddr;     /* Last user fault */
 276         unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
 277         unsigned long error_code;
 278         unsigned long trap_nr;
 279 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 280         struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
 281         struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
 282 #endif
 283 #ifdef CONFIG_CPU_XLP
 284         struct nlm_cop2_state cp2;
 285 #endif
 286         struct mips_abi *abi;
 287 };
 288
 289 #ifdef CONFIG_MIPS_MT_FPAFF
 290 #define FPAFF_INIT                                              \
 291         .emulated_fp                    = 0,                    \
 292         .user_cpus_allowed              = INIT_CPUMASK,
 293 #else
 294 #define FPAFF_INIT
 295 #endif /* CONFIG_MIPS_MT_FPAFF */
 296
 297 #define INIT_THREAD  {                                          \
 298         /*                                                      \
 299          * Saved main processor registers                       \
 300          */                                                     \
 301         .reg16                  = 0,                            \
 302         .reg17                  = 0,                            \
 303         .reg18                  = 0,                            \
 304         .reg19                  = 0,                            \
 305         .reg20                  = 0,                            \
 306         .reg21                  = 0,                            \
 307         .reg22                  = 0,                            \
 308         .reg23                  = 0,                            \
 309         .reg29                  = 0,                            \
 310         .reg30                  = 0,                            \
 311         .reg31                  = 0,                            \
 312         /*                                                      \
 313          * Saved cp0 stuff                                      \
 314          */                                                     \
 315         .cp0_status             = 0,                            \
 316         /*                                                      \
 317          * Saved FPU/FPU emulator stuff                         \
 318          */                                                     \
 319         .fpu                    = {                             \
 320                 .fpr            = {{{0,},},},                   \
 321                 .fcr31          = 0,                            \
 322                 .msacsr         = 0,                            \
 323         },                                                      \
 324         /*                                                      \
 325          * FPU affinity state (null if not FPAFF)               \
 326          */                                                     \
 327         FPAFF_INIT                                              \
 328         /*                                                      \
 329          * Saved DSP stuff                                      \
 330          */                                                     \
 331         .dsp                    = {                             \
 332                 .dspr           = {0, },                        \
 333                 .dspcontrol     = 0,                            \
 334         },                                                      \
 335         /*                                                      \
 336          * saved watch register stuff                           \
 337          */                                                     \
 338         .watch = {{{0,},},},                                    \
 339         /*                                                      \
 340          * Other stuff associated with the process              \
 341          */                                                     \
 342         .cp0_badvaddr           = 0,                            \
 343         .cp0_baduaddr           = 0,                            \
 344         .error_code             = 0,                            \
 345         .trap_nr                = 0,                            \
 346         /*                                                      \
 347          * Platform specific cop2 registers(null if no COP2)    \
 348          */                                                     \
 349         COP2_INIT                                               \
 350 }
 351
 352 struct task_struct;
 353
 354 /* Free all resources held by a thread. */
 355 #define release_thread(thread) do { } while(0)
 356
 357 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 358
 359 /*
 360  * Do necessary setup to start up a newly executed thread.
 361  */
 362 extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
 363
 364 unsigned long get_wchan(struct task_struct *p);
 365
 366 #define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
 367                          THREAD_SIZE - 32 - sizeof(struct pt_regs))
 368 #define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
 369 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
 370 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
 371 #define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
 372
 373 #define cpu_relax()     barrier()
 374 #define cpu_relax_lowlatency() cpu_relax()
 375
 376 /*
 377  * Return_address is a replacement for __builtin_return_address(count)
 378  * which on certain architectures cannot reasonably be implemented in GCC
 379  * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
 380  * Note that __builtin_return_address(x>=1) is forbidden because GCC
 381  * aborts compilation on some CPUs.  It's simply not possible to unwind
 382  * some CPU's stackframes.
 383  *
 384  * __builtin_return_address works only for non-leaf functions.  We avoid the
 385  * overhead of a function call by forcing the compiler to save the return
 386  * address register on the stack.
 387  */
 388 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
 389
 390 #ifdef CONFIG_CPU_HAS_PREFETCH
 391
 392 #define ARCH_HAS_PREFETCH
 393 #define prefetch(x) __builtin_prefetch((x), 0, 1)
 394
 395 #define ARCH_HAS_PREFETCHW
 396 #define prefetchw(x) __builtin_prefetch((x), 1, 1)
 397
 398 #endif
 399
 400 /*
 401  * Functions & macros implementing the PR_GET_FP_MODE & PR_SET_FP_MODE options
 402  * to the prctl syscall.
 403  */
 404 extern int mips_get_process_fp_mode(struct task_struct *task);
 405 extern int mips_set_process_fp_mode(struct task_struct *task,
 406                                     unsigned int value);
 407
 408 #define GET_FP_MODE(task)               mips_get_process_fp_mode(task)
 409 #define SET_FP_MODE(task,value)         mips_set_process_fp_mode(task, value)
 410
 411 #endif /* _ASM_PROCESSOR_H */