arch/mips/include/asm/sn/sn0/hubni.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Derived from IRIX <sys/SN/SN0/hubni.h>, Revision 1.27.
   7  *
   8  * Copyright (C) 1992-1997, 1999 Silicon Graphics, Inc.
   9  * Copyright (C) 1999 by Ralf Baechle
  10  */
  11 #ifndef _ASM_SGI_SN0_HUBNI_H
  12 #define _ASM_SGI_SN0_HUBNI_H
  13
  14 #ifndef __ASSEMBLY__
  15 #include <linux/types.h>
  16 #endif
  17
  18 /*
  19  * Hub Network Interface registers
  20  *
  21  * All registers in this file are subject to change until Hub chip tapeout.
  22  */
  23
  24 #define NI_BASE                 0x600000
  25 #define NI_BASE_TABLES          0x630000
  26
  27 #define NI_STATUS_REV_ID        0x600000 /* Hub network status, rev, and ID */
  28 #define NI_PORT_RESET           0x600008 /* Reset the network interface     */
  29 #define NI_PROTECTION           0x600010 /* NI register access permissions  */
  30 #define NI_GLOBAL_PARMS         0x600018 /* LLP parameters                  */
  31 #define NI_SCRATCH_REG0         0x600100 /* Scratch register 0 (64 bits)    */
  32 #define NI_SCRATCH_REG1         0x600108 /* Scratch register 1 (64 bits)    */
  33 #define NI_DIAG_PARMS           0x600110 /* Parameters for diags            */
  34
  35 #define NI_VECTOR_PARMS         0x600200 /* Vector PIO routing parameters   */
  36 #define NI_VECTOR               0x600208 /* Vector PIO route                */
  37 #define NI_VECTOR_DATA          0x600210 /* Vector PIO data                 */
  38 #define NI_VECTOR_STATUS        0x600300 /* Vector PIO return status        */
  39 #define NI_RETURN_VECTOR        0x600308 /* Vector PIO return vector        */
  40 #define NI_VECTOR_READ_DATA     0x600310 /* Vector PIO read data            */
  41 #define NI_VECTOR_CLEAR         0x600380 /* Vector PIO read & clear status  */
  42
  43 #define NI_IO_PROTECT           0x600400 /* PIO protection bits             */
  44 #define NI_IO_PROT_OVRRD        0x600408 /* PIO protection bit override     */
  45
  46 #define NI_AGE_CPU0_MEMORY      0x600500 /* CPU 0 memory age control        */
  47 #define NI_AGE_CPU0_PIO         0x600508 /* CPU 0 PIO age control           */
  48 #define NI_AGE_CPU1_MEMORY      0x600510 /* CPU 1 memory age control        */
  49 #define NI_AGE_CPU1_PIO         0x600518 /* CPU 1 PIO age control           */
  50 #define NI_AGE_GBR_MEMORY       0x600520 /* GBR memory age control          */
  51 #define NI_AGE_GBR_PIO          0x600528 /* GBR PIO age control             */
  52 #define NI_AGE_IO_MEMORY        0x600530 /* IO memory age control           */
  53 #define NI_AGE_IO_PIO           0x600538 /* IO PIO age control              */
  54 #define NI_AGE_REG_MIN          NI_AGE_CPU0_MEMORY
  55 #define NI_AGE_REG_MAX          NI_AGE_IO_PIO
  56
  57 #define NI_PORT_PARMS           0x608000 /* LLP Parameters                  */
  58 #define NI_PORT_ERROR           0x608008 /* LLP Errors                      */
  59 #define NI_PORT_ERROR_CLEAR     0x608088 /* Clear the error bits            */
  60
  61 #define NI_META_TABLE0          0x638000 /* First meta routing table entry  */
  62 #define NI_META_TABLE(_x)       (NI_META_TABLE0 + (8 * (_x)))
  63 #define NI_META_ENTRIES         32
  64
  65 #define NI_LOCAL_TABLE0         0x638100 /* First local routing table entry */
  66 #define NI_LOCAL_TABLE(_x)      (NI_LOCAL_TABLE0 + (8 * (_x)))
  67 #define NI_LOCAL_ENTRIES        16
  68
  69 /*
  70  * NI_STATUS_REV_ID mask and shift definitions
  71  * Have to use UINT64_CAST instead of 'L' suffix, for assembler.
  72  */
  73
  74 #define NSRI_8BITMODE_SHFT      30
  75 #define NSRI_8BITMODE_MASK      (UINT64_CAST 0x1 << 30)
  76 #define NSRI_LINKUP_SHFT        29
  77 #define NSRI_LINKUP_MASK        (UINT64_CAST 0x1 << 29)
  78 #define NSRI_DOWNREASON_SHFT    28              /* 0=failed, 1=never came   */
  79 #define NSRI_DOWNREASON_MASK    (UINT64_CAST 0x1 << 28) /*    out of reset. */
  80 #define NSRI_MORENODES_SHFT     18
  81 #define NSRI_MORENODES_MASK     (UINT64_CAST 1 << 18)   /* Max. # of nodes  */
  82 #define  MORE_MEMORY            0
  83 #define  MORE_NODES             1
  84 #define NSRI_REGIONSIZE_SHFT    17
  85 #define NSRI_REGIONSIZE_MASK    (UINT64_CAST 1 << 17)   /* Granularity      */
  86 #define  REGIONSIZE_FINE        1
  87 #define  REGIONSIZE_COARSE      0
  88 #define NSRI_NODEID_SHFT        8
  89 #define NSRI_NODEID_MASK        (UINT64_CAST 0x1ff << 8)/* Node (Hub) ID    */
  90 #define NSRI_REV_SHFT           4
  91 #define NSRI_REV_MASK           (UINT64_CAST 0xf << 4)  /* Chip Revision    */
  92 #define NSRI_CHIPID_SHFT        0
  93 #define NSRI_CHIPID_MASK        (UINT64_CAST 0xf)       /* Chip type ID     */
  94
  95 /*
  96  * In fine mode, each node is a region.  In coarse mode, there are
  97  * eight nodes per region.
  98  */
  99 #define NASID_TO_FINEREG_SHFT   0
 100 #define NASID_TO_COARSEREG_SHFT 3
 101
 102 /* NI_PORT_RESET mask definitions */
 103
 104 #define NPR_PORTRESET           (UINT64_CAST 1 << 7)    /* Send warm reset  */
 105 #define NPR_LINKRESET           (UINT64_CAST 1 << 1)    /* Send link reset  */
 106 #define NPR_LOCALRESET          (UINT64_CAST 1)         /* Reset entire hub */
 107
 108 /* NI_PROTECTION mask and shift definitions */
 109
 110 #define NPROT_RESETOK           (UINT64_CAST 1)
 111
 112 /* NI_GLOBAL_PARMS mask and shift definitions */
 113
 114 #define NGP_MAXRETRY_SHFT       48              /* Maximum retries          */
 115 #define NGP_MAXRETRY_MASK       (UINT64_CAST 0x3ff << 48)
 116 #define NGP_TAILTOWRAP_SHFT     32              /* Tail timeout wrap        */
 117 #define NGP_TAILTOWRAP_MASK     (UINT64_CAST 0xffff << 32)
 118
 119 #define NGP_CREDITTOVAL_SHFT    16              /* Tail timeout wrap        */
 120 #define NGP_CREDITTOVAL_MASK    (UINT64_CAST 0xf << 16)
 121 #define NGP_TAILTOVAL_SHFT      4               /* Tail timeout value       */
 122 #define NGP_TAILTOVAL_MASK      (UINT64_CAST 0xf << 4)
 123
 124 /* NI_DIAG_PARMS mask and shift definitions */
 125
 126 #define NDP_PORTTORESET         (UINT64_CAST 1 << 18)   /* Port tmout reset */
 127 #define NDP_LLP8BITMODE         (UINT64_CAST 1 << 12)   /* LLP 8-bit mode   */
 128 #define NDP_PORTDISABLE         (UINT64_CAST 1 <<  6)   /* Port disable     */
 129 #define NDP_SENDERROR           (UINT64_CAST 1)         /* Send data error  */
 130
 131 /*
 132  * NI_VECTOR_PARMS mask and shift definitions.
 133  * TYPE may be any of the first four PIOTYPEs defined under NI_VECTOR_STATUS.
 134  */
 135
 136 #define NVP_PIOID_SHFT          40
 137 #define NVP_PIOID_MASK          (UINT64_CAST 0x3ff << 40)
 138 #define NVP_WRITEID_SHFT        32
 139 #define NVP_WRITEID_MASK        (UINT64_CAST 0xff << 32)
 140 #define NVP_ADDRESS_MASK        (UINT64_CAST 0xffff8)   /* Bits 19:3        */
 141 #define NVP_TYPE_SHFT           0
 142 #define NVP_TYPE_MASK           (UINT64_CAST 0x3)
 143
 144 /* NI_VECTOR_STATUS mask and shift definitions */
 145
 146 #define NVS_VALID               (UINT64_CAST 1 << 63)
 147 #define NVS_OVERRUN             (UINT64_CAST 1 << 62)
 148 #define NVS_TARGET_SHFT         51
 149 #define NVS_TARGET_MASK         (UINT64_CAST 0x3ff << 51)
 150 #define NVS_PIOID_SHFT          40
 151 #define NVS_PIOID_MASK          (UINT64_CAST 0x3ff << 40)
 152 #define NVS_WRITEID_SHFT        32
 153 #define NVS_WRITEID_MASK        (UINT64_CAST 0xff << 32)
 154 #define NVS_ADDRESS_MASK        (UINT64_CAST 0xfffffff8)   /* Bits 31:3     */
 155 #define NVS_TYPE_SHFT           0
 156 #define NVS_TYPE_MASK           (UINT64_CAST 0x7)
 157 #define NVS_ERROR_MASK          (UINT64_CAST 0x4)  /* bit set means error */
 158
 159
 160 #define  PIOTYPE_READ           0       /* VECTOR_PARMS and VECTOR_STATUS   */
 161 #define  PIOTYPE_WRITE          1       /* VECTOR_PARMS and VECTOR_STATUS   */
 162 #define  PIOTYPE_UNDEFINED      2       /* VECTOR_PARMS and VECTOR_STATUS   */
 163 #define  PIOTYPE_EXCHANGE       3       /* VECTOR_PARMS and VECTOR_STATUS   */
 164 #define  PIOTYPE_ADDR_ERR       4       /* VECTOR_STATUS only               */
 165 #define  PIOTYPE_CMD_ERR        5       /* VECTOR_STATUS only               */
 166 #define  PIOTYPE_PROT_ERR       6       /* VECTOR_STATUS only               */
 167 #define  PIOTYPE_UNKNOWN        7       /* VECTOR_STATUS only               */
 168
 169 /* NI_AGE_XXX mask and shift definitions */
 170
 171 #define NAGE_VCH_SHFT           10
 172 #define NAGE_VCH_MASK           (UINT64_CAST 3 << 10)
 173 #define NAGE_CC_SHFT            8
 174 #define NAGE_CC_MASK            (UINT64_CAST 3 << 8)
 175 #define NAGE_AGE_SHFT           0
 176 #define NAGE_AGE_MASK           (UINT64_CAST 0xff)
 177 #define NAGE_MASK               (NAGE_VCH_MASK | NAGE_CC_MASK | NAGE_AGE_MASK)
 178
 179 #define  VCHANNEL_A             0
 180 #define  VCHANNEL_B             1
 181 #define  VCHANNEL_ANY           2
 182
 183 /* NI_PORT_PARMS mask and shift definitions */
 184
 185 #define NPP_NULLTO_SHFT         10
 186 #define NPP_NULLTO_MASK         (UINT64_CAST 0x3f << 16)
 187 #define NPP_MAXBURST_SHFT       0
 188 #define NPP_MAXBURST_MASK       (UINT64_CAST 0x3ff)
 189 #define NPP_RESET_DFLT_HUB20    ((UINT64_CAST 1     << NPP_NULLTO_SHFT) | \
 190                                  (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
 191 #define NPP_RESET_DEFAULTS      ((UINT64_CAST 6     << NPP_NULLTO_SHFT) | \
 192                                  (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
 193
 194
 195 /* NI_PORT_ERROR mask and shift definitions */
 196
 197 #define NPE_LINKRESET           (UINT64_CAST 1 << 37)
 198 #define NPE_INTERNALERROR       (UINT64_CAST 1 << 36)
 199 #define NPE_BADMESSAGE          (UINT64_CAST 1 << 35)
 200 #define NPE_BADDEST             (UINT64_CAST 1 << 34)
 201 #define NPE_FIFOOVERFLOW        (UINT64_CAST 1 << 33)
 202 #define NPE_CREDITTO_SHFT       28
 203 #define NPE_CREDITTO_MASK       (UINT64_CAST 0xf << 28)
 204 #define NPE_TAILTO_SHFT         24
 205 #define NPE_TAILTO_MASK         (UINT64_CAST 0xf << 24)
 206 #define NPE_RETRYCOUNT_SHFT     16
 207 #define NPE_RETRYCOUNT_MASK     (UINT64_CAST 0xff << 16)
 208 #define NPE_CBERRCOUNT_SHFT     8
 209 #define NPE_CBERRCOUNT_MASK     (UINT64_CAST 0xff << 8)
 210 #define NPE_SNERRCOUNT_SHFT     0
 211 #define NPE_SNERRCOUNT_MASK     (UINT64_CAST 0xff << 0)
 212 #define NPE_MASK                0x3effffffff
 213
 214 #define NPE_COUNT_MAX           0xff
 215
 216 #define NPE_FATAL_ERRORS        (NPE_LINKRESET | NPE_INTERNALERROR |    \
 217                                  NPE_BADMESSAGE | NPE_BADDEST |         \
 218                                  NPE_FIFOOVERFLOW | NPE_CREDITTO_MASK | \
 219                                  NPE_TAILTO_MASK)
 220
 221 /* NI_META_TABLE mask and shift definitions */
 222
 223 #define NMT_EXIT_PORT_MASK (UINT64_CAST 0xf)
 224
 225 /* NI_LOCAL_TABLE mask and shift definitions */
 226
 227 #define NLT_EXIT_PORT_MASK (UINT64_CAST 0xf)
 228
 229 #ifndef __ASSEMBLY__
 230
 231 typedef union   hubni_port_error_u {
 232         u64     nipe_reg_value;
 233         struct {
 234             u64 nipe_rsvd:      26,     /* unused */
 235                 nipe_lnk_reset:  1,     /* link reset */
 236                 nipe_intl_err:   1,     /* internal error */
 237                 nipe_bad_msg:    1,     /* bad message */
 238                 nipe_bad_dest:   1,     /* bad dest     */
 239                 nipe_fifo_ovfl:  1,     /* fifo overflow */
 240                 nipe_rsvd1:      1,     /* unused */
 241                 nipe_credit_to:  4,     /* credit timeout */
 242                 nipe_tail_to:    4,     /* tail timeout */
 243                 nipe_retry_cnt:  8,     /* retry error count */
 244                 nipe_cb_cnt:     8,     /* checkbit error count */
 245                 nipe_sn_cnt:     8;     /* sequence number count */
 246         } nipe_fields_s;
 247 } hubni_port_error_t;
 248
 249 #define NI_LLP_RETRY_MAX        0xff
 250 #define NI_LLP_CB_MAX           0xff
 251 #define NI_LLP_SN_MAX           0xff
 252
 253 #endif /* !__ASSEMBLY__ */
 254
 255 #endif /* _ASM_SGI_SN0_HUBNI_H */