2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
7 * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle
8 * Copyright 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
9 * Copyright 1999 Hewlett Packard Co.
14 #include <linux/ptrace.h>
15 #include <linux/sched.h>
16 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/uaccess.h>
20 #include <asm/traps.h>
22 /* Various important other fields */
23 #define bit22set(x) (x & 0x00000200)
24 #define bits23_25set(x) (x & 0x000001c0)
25 #define isGraphicsFlushRead(x) ((x & 0xfc003fdf) == 0x04001a80)
26 /* extended opcode is 0x6a */
28 #define BITSSET 0x1c0 /* for identifying LDCW */
31 DEFINE_PER_CPU(struct exception_data
, exception_data
);
33 int show_unhandled_signals
= 1;
36 * parisc_acctyp(unsigned int inst) --
37 * Given a PA-RISC memory access instruction, determine if the
38 * the instruction would perform a memory read or memory write
41 * This function assumes that the given instruction is a memory access
42 * instruction (i.e. you should really only call it if you know that
43 * the instruction has generated some sort of a memory access fault).
46 * VM_READ if read operation
47 * VM_WRITE if write operation
48 * VM_EXEC if execute operation
51 parisc_acctyp(unsigned long code
, unsigned int inst
)
53 if (code
== 6 || code
== 16)
56 switch (inst
& 0xf0000000) {
57 case 0x40000000: /* load */
58 case 0x50000000: /* new load */
61 case 0x60000000: /* store */
62 case 0x70000000: /* new store */
65 case 0x20000000: /* coproc */
66 case 0x30000000: /* coproc2 */
70 case 0x0: /* indexed/memory management */
73 * Check for the 'Graphics Flush Read' instruction.
74 * It resembles an FDC instruction, except for bits
75 * 20 and 21. Any combination other than zero will
76 * utilize the block mover functionality on some
77 * older PA-RISC platforms. The case where a block
78 * move is performed from VM to graphics IO space
79 * should be treated as a READ.
81 * The significance of bits 20,21 in the FDC
84 * 00 Flush data cache (normal instruction behavior)
85 * 01 Graphics flush write (IO space -> VM)
86 * 10 Graphics flush read (VM -> IO space)
87 * 11 Graphics flush read/write (VM <-> IO space)
89 if (isGraphicsFlushRead(inst
))
94 * Check for LDCWX and LDCWS (semaphore instructions).
95 * If bits 23 through 25 are all 1's it is one of
96 * the above two instructions and is a write.
98 * Note: With the limited bits we are looking at,
99 * this will also catch PROBEW and PROBEWI. However,
100 * these should never get in here because they don't
101 * generate exceptions of the type:
102 * Data TLB miss fault/data page fault
103 * Data memory protection trap
105 if (bits23_25set(inst
) == BITSSET
)
108 return VM_READ
; /* Default */
110 return VM_READ
; /* Default */
115 #undef isGraphicsFlushRead
120 /* This is the treewalk to find a vma which is the highest that has
121 * a start < addr. We're using find_vma_prev instead right now, but
122 * we might want to use this at some point in the future. Probably
123 * not, but I want it committed to CVS so I don't lose it :-)
125 while (tree
!= vm_avl_empty
) {
126 if (tree
->vm_start
> addr
) {
127 tree
= tree
->vm_avl_left
;
130 if (prev
->vm_next
== NULL
)
132 if (prev
->vm_next
->vm_start
> addr
)
134 tree
= tree
->vm_avl_right
;
139 int fixup_exception(struct pt_regs
*regs
)
141 const struct exception_table_entry
*fix
;
143 /* If we only stored 32bit addresses in the exception table we can drop
144 * out if we faulted on a 64bit address. */
145 if ((sizeof(regs
->iaoq
[0]) > sizeof(fix
->insn
))
146 && (regs
->iaoq
[0] >> 32))
149 fix
= search_exception_tables(regs
->iaoq
[0]);
151 struct exception_data
*d
;
152 d
= this_cpu_ptr(&exception_data
);
153 d
->fault_ip
= regs
->iaoq
[0];
154 d
->fault_space
= regs
->isr
;
155 d
->fault_addr
= regs
->ior
;
157 regs
->iaoq
[0] = ((fix
->fixup
) & ~3);
159 * NOTE: In some cases the faulting instruction
160 * may be in the delay slot of a branch. We
161 * don't want to take the branch, so we don't
162 * increment iaoq[1], instead we set it to be
163 * iaoq[0]+4, and clear the B bit in the PSW
165 regs
->iaoq
[1] = regs
->iaoq
[0] + 4;
166 regs
->gr
[0] &= ~PSW_B
; /* IPSW in gr[0] */
175 * Print out info about fatal segfaults, if the show_unhandled_signals
179 show_signal_msg(struct pt_regs
*regs
, unsigned long code
,
180 unsigned long address
, struct task_struct
*tsk
,
181 struct vm_area_struct
*vma
)
183 if (!unhandled_signal(tsk
, SIGSEGV
))
186 if (!printk_ratelimit())
190 pr_warn("do_page_fault() command='%s' type=%lu address=0x%08lx",
191 tsk
->comm
, code
, address
);
192 print_vma_addr(KERN_CONT
" in ", regs
->iaoq
[0]);
194 pr_warn(" vm_start = 0x%08lx, vm_end = 0x%08lx\n",
195 vma
->vm_start
, vma
->vm_end
);
200 void do_page_fault(struct pt_regs
*regs
, unsigned long code
,
201 unsigned long address
)
203 struct vm_area_struct
*vma
, *prev_vma
;
204 struct task_struct
*tsk
;
205 struct mm_struct
*mm
;
206 unsigned long acc_type
;
210 if (faulthandler_disabled())
218 flags
= FAULT_FLAG_ALLOW_RETRY
| FAULT_FLAG_KILLABLE
;
220 flags
|= FAULT_FLAG_USER
;
222 acc_type
= parisc_acctyp(code
, regs
->iir
);
223 if (acc_type
& VM_WRITE
)
224 flags
|= FAULT_FLAG_WRITE
;
226 down_read(&mm
->mmap_sem
);
227 vma
= find_vma_prev(mm
, address
, &prev_vma
);
228 if (!vma
|| address
< vma
->vm_start
)
229 goto check_expansion
;
231 * Ok, we have a good vm_area for this memory access. We still need to
232 * check the access permissions.
237 if ((vma
->vm_flags
& acc_type
) != acc_type
)
241 * If for any reason at all we couldn't handle the fault, make
242 * sure we exit gracefully rather than endlessly redo the
246 fault
= handle_mm_fault(mm
, vma
, address
, flags
);
248 if ((fault
& VM_FAULT_RETRY
) && fatal_signal_pending(current
))
251 if (unlikely(fault
& VM_FAULT_ERROR
)) {
253 * We hit a shared mapping outside of the file, or some
254 * other thing happened to us that made us unable to
255 * handle the page fault gracefully.
257 if (fault
& VM_FAULT_OOM
)
259 else if (fault
& VM_FAULT_SIGSEGV
)
261 else if (fault
& VM_FAULT_SIGBUS
)
265 if (flags
& FAULT_FLAG_ALLOW_RETRY
) {
266 if (fault
& VM_FAULT_MAJOR
)
270 if (fault
& VM_FAULT_RETRY
) {
271 flags
&= ~FAULT_FLAG_ALLOW_RETRY
;
274 * No need to up_read(&mm->mmap_sem) as we would
275 * have already released it in __lock_page_or_retry
282 up_read(&mm
->mmap_sem
);
287 if (vma
&& (expand_stack(vma
, address
) == 0))
291 * Something tried to access memory that isn't in our memory map..
294 up_read(&mm
->mmap_sem
);
296 if (user_mode(regs
)) {
299 show_signal_msg(regs
, code
, address
, tsk
, vma
);
302 case 15: /* Data TLB miss fault/Data page fault */
303 /* send SIGSEGV when outside of vma */
305 address
< vma
->vm_start
|| address
> vma
->vm_end
) {
306 si
.si_signo
= SIGSEGV
;
307 si
.si_code
= SEGV_MAPERR
;
311 /* send SIGSEGV for wrong permissions */
312 if ((vma
->vm_flags
& acc_type
) != acc_type
) {
313 si
.si_signo
= SIGSEGV
;
314 si
.si_code
= SEGV_ACCERR
;
318 /* probably address is outside of mapped file */
320 case 17: /* NA data TLB miss / page fault */
321 case 18: /* Unaligned access - PCXS only */
322 si
.si_signo
= SIGBUS
;
323 si
.si_code
= (code
== 18) ? BUS_ADRALN
: BUS_ADRERR
;
325 case 16: /* Non-access instruction TLB miss fault */
326 case 26: /* PCXL: Data memory access rights trap */
328 si
.si_signo
= SIGSEGV
;
329 si
.si_code
= (code
== 26) ? SEGV_ACCERR
: SEGV_MAPERR
;
333 si
.si_addr
= (void __user
*) address
;
334 force_sig_info(si
.si_signo
, &si
, current
);
340 if (!user_mode(regs
) && fixup_exception(regs
)) {
344 parisc_terminate("Bad Address (null pointer deref?)", regs
, code
, address
);
347 up_read(&mm
->mmap_sem
);
348 if (!user_mode(regs
))
350 pagefault_out_of_memory();