1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
2 #define _ASM_POWERPC_PCI_BRIDGE_H
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 #include <linux/pci.h>
11 #include <linux/list.h>
12 #include <linux/ioport.h>
13 #include <asm-generic/pci-bridge.h>
18 * PCI controller operations
20 struct pci_controller_ops
{
21 void (*dma_dev_setup
)(struct pci_dev
*dev
);
22 void (*dma_bus_setup
)(struct pci_bus
*bus
);
24 int (*probe_mode
)(struct pci_bus
*);
26 /* Called when pci_enable_device() is called. Returns true to
27 * allow assignment/enabling of the device. */
28 bool (*enable_device_hook
)(struct pci_dev
*);
30 void (*disable_device
)(struct pci_dev
*);
32 void (*release_device
)(struct pci_dev
*);
34 /* Called during PCI resource reassignment */
35 resource_size_t (*window_alignment
)(struct pci_bus
*, unsigned long type
);
36 void (*reset_secondary_bus
)(struct pci_dev
*dev
);
39 int (*setup_msi_irqs
)(struct pci_dev
*dev
,
41 void (*teardown_msi_irqs
)(struct pci_dev
*dev
);
44 int (*dma_set_mask
)(struct pci_dev
*dev
, u64 dma_mask
);
45 u64 (*dma_get_required_mask
)(struct pci_dev
*dev
);
47 void (*shutdown
)(struct pci_controller
*);
51 * Structure of a PCI controller (host bridge)
53 struct pci_controller
{
59 struct device_node
*dn
;
60 struct list_head list_node
;
61 struct device
*parent
;
68 void __iomem
*io_base_virt
;
72 resource_size_t io_base_phys
;
73 resource_size_t pci_io_size
;
75 /* Some machines have a special region to forward the ISA
76 * "memory" cycles such as VGA memory regions. Left to 0
79 resource_size_t isa_mem_phys
;
80 resource_size_t isa_mem_size
;
82 struct pci_controller_ops controller_ops
;
84 unsigned int __iomem
*cfg_addr
;
85 void __iomem
*cfg_data
;
88 * Used for variants of PCI indirect handling and possible quirks:
89 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
90 * EXT_REG - provides access to PCI-e extended registers
91 * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
92 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
93 * to determine which bus number to match on when generating type0
95 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
96 * hanging if we don't have link and try to do config cycles to
97 * anything but the PHB. Only allow talking to the PHB if this is
99 * BIG_ENDIAN - cfg_addr is a big endian register
100 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
101 * the PLB4. Effectively disable MRM commands by setting this.
102 * FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
103 * link status is in a RC PCIe cfg register (vs being a SoC register)
105 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
106 #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
107 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
108 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
109 #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
110 #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
111 #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
113 /* Currently, we limit ourselves to 1 IO range and 3 mem
114 * ranges since the common pci_bus structure can't handle more
116 struct resource io_resource
;
117 struct resource mem_resources
[3];
118 resource_size_t mem_offset
[3];
119 int global_number
; /* PCI domain number */
121 resource_size_t dma_window_base_cur
;
122 resource_size_t dma_window_size
;
126 struct pci_dn
*pci_data
;
127 #endif /* CONFIG_PPC64 */
132 /* These are used for config access before all the PCI probing
134 extern int early_read_config_byte(struct pci_controller
*hose
, int bus
,
135 int dev_fn
, int where
, u8
*val
);
136 extern int early_read_config_word(struct pci_controller
*hose
, int bus
,
137 int dev_fn
, int where
, u16
*val
);
138 extern int early_read_config_dword(struct pci_controller
*hose
, int bus
,
139 int dev_fn
, int where
, u32
*val
);
140 extern int early_write_config_byte(struct pci_controller
*hose
, int bus
,
141 int dev_fn
, int where
, u8 val
);
142 extern int early_write_config_word(struct pci_controller
*hose
, int bus
,
143 int dev_fn
, int where
, u16 val
);
144 extern int early_write_config_dword(struct pci_controller
*hose
, int bus
,
145 int dev_fn
, int where
, u32 val
);
147 extern int early_find_capability(struct pci_controller
*hose
, int bus
,
148 int dev_fn
, int cap
);
150 extern void setup_indirect_pci(struct pci_controller
* hose
,
151 resource_size_t cfg_addr
,
152 resource_size_t cfg_data
, u32 flags
);
154 extern int indirect_read_config(struct pci_bus
*bus
, unsigned int devfn
,
155 int offset
, int len
, u32
*val
);
157 extern int __indirect_read_config(struct pci_controller
*hose
,
158 unsigned char bus_number
, unsigned int devfn
,
159 int offset
, int len
, u32
*val
);
161 extern int indirect_write_config(struct pci_bus
*bus
, unsigned int devfn
,
162 int offset
, int len
, u32 val
);
164 static inline struct pci_controller
*pci_bus_to_host(const struct pci_bus
*bus
)
171 extern int pci_device_from_OF_node(struct device_node
*node
,
173 extern void pci_create_OF_bus_map(void);
175 static inline int isa_vaddr_is_ioport(void __iomem
*address
)
177 /* No specific ISA handling on ppc32 at this stage, it
178 * all goes through PCI
183 #else /* CONFIG_PPC64 */
186 * PCI stuff, for nodes representing PCI devices, pointed to
187 * by device_node->data.
193 #define PCI_DN_FLAG_IOV_VF 0x01
195 int busno
; /* pci bus number */
196 int devfn
; /* pci device and function number */
197 int vendor_id
; /* Vendor ID */
198 int device_id
; /* Device ID */
199 int class_code
; /* Device class code */
201 struct pci_dn
*parent
;
202 struct pci_controller
*phb
; /* for pci devices */
203 struct iommu_table_group
*table_group
; /* for phb's or bridges */
204 struct device_node
*node
; /* back-pointer to the device_node */
206 int pci_ext_config_space
; /* for pci devices */
209 struct eeh_dev
*edev
; /* eeh device */
211 #define IODA_INVALID_PE (-1)
212 #ifdef CONFIG_PPC_POWERNV
214 #ifdef CONFIG_PCI_IOV
215 u16 vfs_expanded
; /* number of VFs IOV BAR expanded */
216 u16 num_vfs
; /* number of VFs enabled*/
217 int offset
; /* PE# for the first VF PE */
218 #define M64_PER_IOV 4
220 #define IODA_INVALID_M64 (-1)
221 int m64_wins
[PCI_SRIOV_NUM_BARS
][M64_PER_IOV
];
222 #endif /* CONFIG_PCI_IOV */
224 struct list_head child_list
;
225 struct list_head list
;
228 /* Get the pointer to a device_node's pci_dn */
229 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
231 extern struct pci_dn
*pci_get_pdn_by_devfn(struct pci_bus
*bus
,
233 extern struct pci_dn
*pci_get_pdn(struct pci_dev
*pdev
);
234 extern struct pci_dn
*add_dev_pci_data(struct pci_dev
*pdev
);
235 extern void remove_dev_pci_data(struct pci_dev
*pdev
);
236 extern void *update_dn_pci_info(struct device_node
*dn
, void *data
);
238 static inline int pci_device_from_OF_node(struct device_node
*np
,
243 *bus
= PCI_DN(np
)->busno
;
244 *devfn
= PCI_DN(np
)->devfn
;
248 #if defined(CONFIG_EEH)
249 static inline struct eeh_dev
*pdn_to_eeh_dev(struct pci_dn
*pdn
)
251 return pdn
? pdn
->edev
: NULL
;
254 #define pdn_to_eeh_dev(x) (NULL)
257 /** Find the bus corresponding to the indicated device node */
258 extern struct pci_bus
*pcibios_find_pci_bus(struct device_node
*dn
);
260 /** Remove all of the PCI devices under this bus */
261 extern void pcibios_remove_pci_devices(struct pci_bus
*bus
);
263 /** Discover new pci devices under this bus, and add them */
264 extern void pcibios_add_pci_devices(struct pci_bus
*bus
);
267 extern void isa_bridge_find_early(struct pci_controller
*hose
);
269 static inline int isa_vaddr_is_ioport(void __iomem
*address
)
271 /* Check if address hits the reserved legacy IO range */
272 unsigned long ea
= (unsigned long)address
;
273 return ea
>= ISA_IO_BASE
&& ea
< ISA_IO_END
;
276 extern int pcibios_unmap_io_space(struct pci_bus
*bus
);
277 extern int pcibios_map_io_space(struct pci_bus
*bus
);
280 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
282 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
285 #endif /* CONFIG_PPC64 */
287 /* Get the PCI host controller for an OF device */
288 extern struct pci_controller
*pci_find_hose_for_OF_device(
289 struct device_node
* node
);
291 /* Fill up host controller resources from the OF node */
292 extern void pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
293 struct device_node
*dev
, int primary
);
295 /* Allocate & free a PCI host bridge structure */
296 extern struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
);
297 extern void pcibios_free_controller(struct pci_controller
*phb
);
300 extern int pcibios_vaddr_is_ioport(void __iomem
*address
);
302 static inline int pcibios_vaddr_is_ioport(void __iomem
*address
)
306 #endif /* CONFIG_PCI */
308 #endif /* __KERNEL__ */
309 #endif /* _ASM_POWERPC_PCI_BRIDGE_H */