arch/powerpc/sysdev/i8259.c

   1 /*
   2  * i8259 interrupt controller driver.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9 #undef DEBUG
  10
  11 #include <linux/ioport.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/kernel.h>
  14 #include <linux/delay.h>
  15 #include <asm/io.h>
  16 #include <asm/i8259.h>
  17 #include <asm/prom.h>
  18
  19 static volatile void __iomem *pci_intack; /* RO, gives us the irq vector */
  20
  21 static unsigned char cached_8259[2] = { 0xff, 0xff };
  22 #define cached_A1 (cached_8259[0])
  23 #define cached_21 (cached_8259[1])
  24
  25 static DEFINE_RAW_SPINLOCK(i8259_lock);
  26
  27 static struct irq_domain *i8259_host;
  28
  29 /*
  30  * Acknowledge the IRQ using either the PCI host bridge's interrupt
  31  * acknowledge feature or poll.  How i8259_init() is called determines
  32  * which is called.  It should be noted that polling is broken on some
  33  * IBM and Motorola PReP boxes so we must use the int-ack feature on them.
  34  */
  35 unsigned int i8259_irq(void)
  36 {
  37         int irq;
  38         int lock = 0;
  39
  40         /* Either int-ack or poll for the IRQ */
  41         if (pci_intack)
  42                 irq = readb(pci_intack);
  43         else {
  44                 raw_spin_lock(&i8259_lock);
  45                 lock = 1;
  46
  47                 /* Perform an interrupt acknowledge cycle on controller 1. */
  48                 outb(0x0C, 0x20);               /* prepare for poll */
  49                 irq = inb(0x20) & 7;
  50                 if (irq == 2 ) {
  51                         /*
  52                          * Interrupt is cascaded so perform interrupt
  53                          * acknowledge on controller 2.
  54                          */
  55                         outb(0x0C, 0xA0);       /* prepare for poll */
  56                         irq = (inb(0xA0) & 7) + 8;
  57                 }
  58         }
  59
  60         if (irq == 7) {
  61                 /*
  62                  * This may be a spurious interrupt.
  63                  *
  64                  * Read the interrupt status register (ISR). If the most
  65                  * significant bit is not set then there is no valid
  66                  * interrupt.
  67                  */
  68                 if (!pci_intack)
  69                         outb(0x0B, 0x20);       /* ISR register */
  70                 if(~inb(0x20) & 0x80)
  71                         irq = NO_IRQ;
  72         } else if (irq == 0xff)
  73                 irq = NO_IRQ;
  74
  75         if (lock)
  76                 raw_spin_unlock(&i8259_lock);
  77         return irq;
  78 }
  79
  80 static void i8259_mask_and_ack_irq(struct irq_data *d)
  81 {
  82         unsigned long flags;
  83
  84         raw_spin_lock_irqsave(&i8259_lock, flags);
  85         if (d->irq > 7) {
  86                 cached_A1 |= 1 << (d->irq-8);
  87                 inb(0xA1);      /* DUMMY */
  88                 outb(cached_A1, 0xA1);
  89                 outb(0x20, 0xA0);       /* Non-specific EOI */
  90                 outb(0x20, 0x20);       /* Non-specific EOI to cascade */
  91         } else {
  92                 cached_21 |= 1 << d->irq;
  93                 inb(0x21);      /* DUMMY */
  94                 outb(cached_21, 0x21);
  95                 outb(0x20, 0x20);       /* Non-specific EOI */
  96         }
  97         raw_spin_unlock_irqrestore(&i8259_lock, flags);
  98 }
  99
 100 static void i8259_set_irq_mask(int irq_nr)
 101 {
 102         outb(cached_A1,0xA1);
 103         outb(cached_21,0x21);
 104 }
 105
 106 static void i8259_mask_irq(struct irq_data *d)
 107 {
 108         unsigned long flags;
 109
 110         pr_debug("i8259_mask_irq(%d)\n", d->irq);
 111
 112         raw_spin_lock_irqsave(&i8259_lock, flags);
 113         if (d->irq < 8)
 114                 cached_21 |= 1 << d->irq;
 115         else
 116                 cached_A1 |= 1 << (d->irq-8);
 117         i8259_set_irq_mask(d->irq);
 118         raw_spin_unlock_irqrestore(&i8259_lock, flags);
 119 }
 120
 121 static void i8259_unmask_irq(struct irq_data *d)
 122 {
 123         unsigned long flags;
 124
 125         pr_debug("i8259_unmask_irq(%d)\n", d->irq);
 126
 127         raw_spin_lock_irqsave(&i8259_lock, flags);
 128         if (d->irq < 8)
 129                 cached_21 &= ~(1 << d->irq);
 130         else
 131                 cached_A1 &= ~(1 << (d->irq-8));
 132         i8259_set_irq_mask(d->irq);
 133         raw_spin_unlock_irqrestore(&i8259_lock, flags);
 134 }
 135
 136 static struct irq_chip i8259_pic = {
 137         .name           = "i8259",
 138         .irq_mask       = i8259_mask_irq,
 139         .irq_disable    = i8259_mask_irq,
 140         .irq_unmask     = i8259_unmask_irq,
 141         .irq_mask_ack   = i8259_mask_and_ack_irq,
 142 };
 143
 144 static struct resource pic1_iores = {
 145         .name = "8259 (master)",
 146         .start = 0x20,
 147         .end = 0x21,
 148         .flags = IORESOURCE_BUSY,
 149 };
 150
 151 static struct resource pic2_iores = {
 152         .name = "8259 (slave)",
 153         .start = 0xa0,
 154         .end = 0xa1,
 155         .flags = IORESOURCE_BUSY,
 156 };
 157
 158 static struct resource pic_edgectrl_iores = {
 159         .name = "8259 edge control",
 160         .start = 0x4d0,
 161         .end = 0x4d1,
 162         .flags = IORESOURCE_BUSY,
 163 };
 164
 165 static int i8259_host_match(struct irq_domain *h, struct device_node *node,
 166                             enum irq_domain_bus_token bus_token)
 167 {
 168         return h->of_node == NULL || h->of_node == node;
 169 }
 170
 171 static int i8259_host_map(struct irq_domain *h, unsigned int virq,
 172                           irq_hw_number_t hw)
 173 {
 174         pr_debug("i8259_host_map(%d, 0x%lx)\n", virq, hw);
 175
 176         /* We block the internal cascade */
 177         if (hw == 2)
 178                 irq_set_status_flags(virq, IRQ_NOREQUEST);
 179
 180         /* We use the level handler only for now, we might want to
 181          * be more cautious here but that works for now
 182          */
 183         irq_set_status_flags(virq, IRQ_LEVEL);
 184         irq_set_chip_and_handler(virq, &i8259_pic, handle_level_irq);
 185         return 0;
 186 }
 187
 188 static int i8259_host_xlate(struct irq_domain *h, struct device_node *ct,
 189                             const u32 *intspec, unsigned int intsize,
 190                             irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 191 {
 192         static unsigned char map_isa_senses[4] = {
 193                 IRQ_TYPE_LEVEL_LOW,
 194                 IRQ_TYPE_LEVEL_HIGH,
 195                 IRQ_TYPE_EDGE_FALLING,
 196                 IRQ_TYPE_EDGE_RISING,
 197         };
 198
 199         *out_hwirq = intspec[0];
 200         if (intsize > 1 && intspec[1] < 4)
 201                 *out_flags = map_isa_senses[intspec[1]];
 202         else
 203                 *out_flags = IRQ_TYPE_NONE;
 204
 205         return 0;
 206 }
 207
 208 static const struct irq_domain_ops i8259_host_ops = {
 209         .match = i8259_host_match,
 210         .map = i8259_host_map,
 211         .xlate = i8259_host_xlate,
 212 };
 213
 214 struct irq_domain *i8259_get_host(void)
 215 {
 216         return i8259_host;
 217 }
 218
 219 /**
 220  * i8259_init - Initialize the legacy controller
 221  * @node: device node of the legacy PIC (can be NULL, but then, it will match
 222  *        all interrupts, so beware)
 223  * @intack_addr: PCI interrupt acknowledge (real) address which will return
 224  *               the active irq from the 8259
 225  */
 226 void i8259_init(struct device_node *node, unsigned long intack_addr)
 227 {
 228         unsigned long flags;
 229
 230         /* initialize the controller */
 231         raw_spin_lock_irqsave(&i8259_lock, flags);
 232
 233         /* Mask all first */
 234         outb(0xff, 0xA1);
 235         outb(0xff, 0x21);
 236
 237         /* init master interrupt controller */
 238         outb(0x11, 0x20); /* Start init sequence */
 239         outb(0x00, 0x21); /* Vector base */
 240         outb(0x04, 0x21); /* edge tiggered, Cascade (slave) on IRQ2 */
 241         outb(0x01, 0x21); /* Select 8086 mode */
 242
 243         /* init slave interrupt controller */
 244         outb(0x11, 0xA0); /* Start init sequence */
 245         outb(0x08, 0xA1); /* Vector base */
 246         outb(0x02, 0xA1); /* edge triggered, Cascade (slave) on IRQ2 */
 247         outb(0x01, 0xA1); /* Select 8086 mode */
 248
 249         /* That thing is slow */
 250         udelay(100);
 251
 252         /* always read ISR */
 253         outb(0x0B, 0x20);
 254         outb(0x0B, 0xA0);
 255
 256         /* Unmask the internal cascade */
 257         cached_21 &= ~(1 << 2);
 258
 259         /* Set interrupt masks */
 260         outb(cached_A1, 0xA1);
 261         outb(cached_21, 0x21);
 262
 263         raw_spin_unlock_irqrestore(&i8259_lock, flags);
 264
 265         /* create a legacy host */
 266         i8259_host = irq_domain_add_legacy_isa(node, &i8259_host_ops, NULL);
 267         if (i8259_host == NULL) {
 268                 printk(KERN_ERR "i8259: failed to allocate irq host !\n");
 269                 return;
 270         }
 271
 272         /* reserve our resources */
 273         /* XXX should we continue doing that ? it seems to cause problems
 274          * with further requesting of PCI IO resources for that range...
 275          * need to look into it.
 276          */
 277         request_resource(&ioport_resource, &pic1_iores);
 278         request_resource(&ioport_resource, &pic2_iores);
 279         request_resource(&ioport_resource, &pic_edgectrl_iores);
 280
 281         if (intack_addr != 0)
 282                 pci_intack = ioremap(intack_addr, 1);
 283
 284         printk(KERN_INFO "i8259 legacy interrupt controller initialized\n");
 285 }