arch/sh/kernel/cpu/sh2/setup-sh7619.c

   1 /*
   2  * SH7619 Setup
   3  *
   4  *  Copyright (C) 2006  Yoshinori Sato
   5  *  Copyright (C) 2009  Paul Mundt
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #include <linux/platform_device.h>
  12 #include <linux/init.h>
  13 #include <linux/serial.h>
  14 #include <linux/serial_sci.h>
  15 #include <linux/sh_eth.h>
  16 #include <linux/sh_timer.h>
  17 #include <linux/io.h>
  18
  19 enum {
  20         UNUSED = 0,
  21
  22         /* interrupt sources */
  23         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  24         WDT, EDMAC, CMT0, CMT1,
  25         SCIF0, SCIF1, SCIF2,
  26         HIF_HIFI, HIF_HIFBI,
  27         DMAC0, DMAC1, DMAC2, DMAC3,
  28         SIOF,
  29 };
  30
  31 static struct intc_vect vectors[] __initdata = {
  32         INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
  33         INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
  34         INTC_IRQ(IRQ4, 80), INTC_IRQ(IRQ5, 81),
  35         INTC_IRQ(IRQ6, 82), INTC_IRQ(IRQ7, 83),
  36         INTC_IRQ(WDT, 84), INTC_IRQ(EDMAC, 85),
  37         INTC_IRQ(CMT0, 86), INTC_IRQ(CMT1, 87),
  38         INTC_IRQ(SCIF0, 88), INTC_IRQ(SCIF0, 89),
  39         INTC_IRQ(SCIF0, 90), INTC_IRQ(SCIF0, 91),
  40         INTC_IRQ(SCIF1, 92), INTC_IRQ(SCIF1, 93),
  41         INTC_IRQ(SCIF1, 94), INTC_IRQ(SCIF1, 95),
  42         INTC_IRQ(SCIF2, 96), INTC_IRQ(SCIF2, 97),
  43         INTC_IRQ(SCIF2, 98), INTC_IRQ(SCIF2, 99),
  44         INTC_IRQ(HIF_HIFI, 100), INTC_IRQ(HIF_HIFBI, 101),
  45         INTC_IRQ(DMAC0, 104), INTC_IRQ(DMAC1, 105),
  46         INTC_IRQ(DMAC2, 106), INTC_IRQ(DMAC3, 107),
  47         INTC_IRQ(SIOF, 108),
  48 };
  49
  50 static struct intc_prio_reg prio_registers[] __initdata = {
  51         { 0xf8140006, 0, 16, 4, /* IPRA */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
  52         { 0xf8140008, 0, 16, 4, /* IPRB */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
  53         { 0xf8080000, 0, 16, 4, /* IPRC */ { WDT, EDMAC, CMT0, CMT1 } },
  54         { 0xf8080002, 0, 16, 4, /* IPRD */ { SCIF0, SCIF1, SCIF2 } },
  55         { 0xf8080004, 0, 16, 4, /* IPRE */ { HIF_HIFI, HIF_HIFBI } },
  56         { 0xf8080006, 0, 16, 4, /* IPRF */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
  57         { 0xf8080008, 0, 16, 4, /* IPRG */ { SIOF } },
  58 };
  59
  60 static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL,
  61                          NULL, prio_registers, NULL);
  62
  63 static struct plat_sci_port scif0_platform_data = {
  64         .flags          = UPF_BOOT_AUTOCONF,
  65         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  66         .type           = PORT_SCIF,
  67 };
  68
  69 static struct resource scif0_resources[] = {
  70         DEFINE_RES_MEM(0xf8400000, 0x100),
  71         DEFINE_RES_IRQ(88),
  72 };
  73
  74 static struct platform_device scif0_device = {
  75         .name           = "sh-sci",
  76         .id             = 0,
  77         .resource       = scif0_resources,
  78         .num_resources  = ARRAY_SIZE(scif0_resources),
  79         .dev            = {
  80                 .platform_data  = &scif0_platform_data,
  81         },
  82 };
  83
  84 static struct plat_sci_port scif1_platform_data = {
  85         .flags          = UPF_BOOT_AUTOCONF,
  86         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  87         .type           = PORT_SCIF,
  88 };
  89
  90 static struct resource scif1_resources[] = {
  91         DEFINE_RES_MEM(0xf8410000, 0x100),
  92         DEFINE_RES_IRQ(92),
  93 };
  94
  95 static struct platform_device scif1_device = {
  96         .name           = "sh-sci",
  97         .id             = 1,
  98         .resource       = scif1_resources,
  99         .num_resources  = ARRAY_SIZE(scif1_resources),
 100         .dev            = {
 101                 .platform_data  = &scif1_platform_data,
 102         },
 103 };
 104
 105 static struct plat_sci_port scif2_platform_data = {
 106         .flags          = UPF_BOOT_AUTOCONF,
 107         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 108         .type           = PORT_SCIF,
 109 };
 110
 111 static struct resource scif2_resources[] = {
 112         DEFINE_RES_MEM(0xf8420000, 0x100),
 113         DEFINE_RES_IRQ(96),
 114 };
 115
 116 static struct platform_device scif2_device = {
 117         .name           = "sh-sci",
 118         .id             = 2,
 119         .resource       = scif2_resources,
 120         .num_resources  = ARRAY_SIZE(scif2_resources),
 121         .dev            = {
 122                 .platform_data  = &scif2_platform_data,
 123         },
 124 };
 125
 126 static struct sh_eth_plat_data eth_platform_data = {
 127         .phy            = 1,
 128         .edmac_endian   = EDMAC_LITTLE_ENDIAN,
 129         .phy_interface  = PHY_INTERFACE_MODE_MII,
 130 };
 131
 132 static struct resource eth_resources[] = {
 133         [0] = {
 134                 .start = 0xfb000000,
 135                 .end = 0xfb0001c7,
 136                 .flags = IORESOURCE_MEM,
 137         },
 138         [1] = {
 139                 .start = 85,
 140                 .end = 85,
 141                 .flags = IORESOURCE_IRQ,
 142         },
 143 };
 144
 145 static struct platform_device eth_device = {
 146         .name = "sh7619-ether",
 147         .id = -1,
 148         .dev = {
 149                 .platform_data = &eth_platform_data,
 150         },
 151         .num_resources = ARRAY_SIZE(eth_resources),
 152         .resource = eth_resources,
 153 };
 154
 155 static struct sh_timer_config cmt_platform_data = {
 156         .channels_mask = 3,
 157 };
 158
 159 static struct resource cmt_resources[] = {
 160         DEFINE_RES_MEM(0xf84a0070, 0x10),
 161         DEFINE_RES_IRQ(86),
 162         DEFINE_RES_IRQ(87),
 163 };
 164
 165 static struct platform_device cmt_device = {
 166         .name           = "sh-cmt-16",
 167         .id             = 0,
 168         .dev = {
 169                 .platform_data  = &cmt_platform_data,
 170         },
 171         .resource       = cmt_resources,
 172         .num_resources  = ARRAY_SIZE(cmt_resources),
 173 };
 174
 175 static struct platform_device *sh7619_devices[] __initdata = {
 176         &scif0_device,
 177         &scif1_device,
 178         &scif2_device,
 179         &eth_device,
 180         &cmt_device,
 181 };
 182
 183 static int __init sh7619_devices_setup(void)
 184 {
 185         return platform_add_devices(sh7619_devices,
 186                                     ARRAY_SIZE(sh7619_devices));
 187 }
 188 arch_initcall(sh7619_devices_setup);
 189
 190 void __init plat_irq_setup(void)
 191 {
 192         register_intc_controller(&intc_desc);
 193 }
 194
 195 static struct platform_device *sh7619_early_devices[] __initdata = {
 196         &scif0_device,
 197         &scif1_device,
 198         &scif2_device,
 199         &cmt_device,
 200 };
 201
 202 #define STBCR3 0xf80a0000
 203
 204 void __init plat_early_device_setup(void)
 205 {
 206         /* enable CMT clock */
 207         __raw_writeb(__raw_readb(STBCR3) & ~0x10, STBCR3);
 208
 209         early_platform_add_devices(sh7619_early_devices,
 210                                    ARRAY_SIZE(sh7619_early_devices));
 211 }