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blk: rq_data_dir() should not return a boolean
[cris-mirror.git] / arch / tile / kernel / pci_gx.c
blobb3f73fd764a35b60002b507ea029c732363d4a6f
1 /*
2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/mmzone.h>
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/capability.h>
22 #include <linux/sched.h>
23 #include <linux/errno.h>
24 #include <linux/irq.h>
25 #include <linux/msi.h>
26 #include <linux/io.h>
27 #include <linux/uaccess.h>
28 #include <linux/ctype.h>
29
30 #include <asm/processor.h>
31 #include <asm/sections.h>
32 #include <asm/byteorder.h>
33
34 #include <gxio/iorpc_globals.h>
35 #include <gxio/kiorpc.h>
36 #include <gxio/trio.h>
37 #include <gxio/iorpc_trio.h>
38 #include <hv/drv_trio_intf.h>
39
40 #include <arch/sim.h>
41
42 /*
43 * This file containes the routines to search for PCI buses,
44 * enumerate the buses, and configure any attached devices.
45 */
46
47 #define DEBUG_PCI_CFG 0
48
49 #if DEBUG_PCI_CFG
50 #define TRACE_CFG_WR(size, val, bus, dev, func, offset) \
51 pr_info("CFG WR %d-byte VAL %#x to bus %d dev %d func %d addr %u\n", \
52 size, val, bus, dev, func, offset & 0xFFF);
53 #define TRACE_CFG_RD(size, val, bus, dev, func, offset) \
54 pr_info("CFG RD %d-byte VAL %#x from bus %d dev %d func %d addr %u\n", \
55 size, val, bus, dev, func, offset & 0xFFF);
56 #else
57 #define TRACE_CFG_WR(...)
58 #define TRACE_CFG_RD(...)
59 #endif
60
61 static int pci_probe = 1;
62
63 /* Information on the PCIe RC ports configuration. */
64 static int pcie_rc[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
65
66 /*
67 * On some platforms with one or more Gx endpoint ports, we need to
68 * delay the PCIe RC port probe for a few seconds to work around
69 * a HW PCIe link-training bug. The exact delay is specified with
70 * a kernel boot argument in the form of "pcie_rc_delay=T,P,S",
71 * where T is the TRIO instance number, P is the port number and S is
72 * the delay in seconds. If the argument is specified, but the delay is
73 * not provided, the value will be DEFAULT_RC_DELAY.
74 */
75 static int rc_delay[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
76
77 /* Default number of seconds that the PCIe RC port probe can be delayed. */
78 #define DEFAULT_RC_DELAY 10
79
80 /* The PCI I/O space size in each PCI domain. */
81 #define IO_SPACE_SIZE 0x10000
82
83 /* Provide shorter versions of some very long constant names. */
84 #define AUTO_CONFIG_RC \
85 TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC
86 #define AUTO_CONFIG_RC_G1 \
87 TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC_G1
88 #define AUTO_CONFIG_EP \
89 TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT
90 #define AUTO_CONFIG_EP_G1 \
91 TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT_G1
92
93 /* Array of the PCIe ports configuration info obtained from the BIB. */
94 struct pcie_trio_ports_property pcie_ports[TILEGX_NUM_TRIO];
95
96 /* Number of configured TRIO instances. */
97 int num_trio_shims;
98
99 /* All drivers share the TRIO contexts defined here. */
100 gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO];
101
102 /* Pointer to an array of PCIe RC controllers. */
103 struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES];
104 int num_rc_controllers;
105
106 static struct pci_ops tile_cfg_ops;
107
108 /* Mask of CPUs that should receive PCIe interrupts. */
109 static struct cpumask intr_cpus_map;
110
111 /* We don't need to worry about the alignment of resources. */
112 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
113 resource_size_t size,
114 resource_size_t align)
115 {
116 return res->start;
117 }
118 EXPORT_SYMBOL(pcibios_align_resource);
119
120 /*
121 * Pick a CPU to receive and handle the PCIe interrupts, based on the IRQ #.
122 * For now, we simply send interrupts to non-dataplane CPUs.
123 * We may implement methods to allow user to specify the target CPUs,
124 * e.g. via boot arguments.
125 */
126 static int tile_irq_cpu(int irq)
127 {
128 unsigned int count;
129 int i = 0;
130 int cpu;
131
132 count = cpumask_weight(&intr_cpus_map);
133 if (unlikely(count == 0)) {
134 pr_warn("intr_cpus_map empty, interrupts will be delievered to dataplane tiles\n");
135 return irq % (smp_height * smp_width);
136 }
137
138 count = irq % count;
139 for_each_cpu(cpu, &intr_cpus_map) {
140 if (i++ == count)
141 break;
142 }
143 return cpu;
144 }
145
146 /* Open a file descriptor to the TRIO shim. */
147 static int tile_pcie_open(int trio_index)
148 {
149 gxio_trio_context_t *context = &trio_contexts[trio_index];
150 int ret;
151 int mac;
152
153 /* This opens a file descriptor to the TRIO shim. */
154 ret = gxio_trio_init(context, trio_index);
155 if (ret < 0)
156 goto gxio_trio_init_failure;
157
158 /* Allocate an ASID for the kernel. */
159 ret = gxio_trio_alloc_asids(context, 1, 0, 0);
160 if (ret < 0) {
161 pr_err("PCI: ASID alloc failure on TRIO %d, give up\n",
162 trio_index);
163 goto asid_alloc_failure;
164 }
165
166 context->asid = ret;
167
168 #ifdef USE_SHARED_PCIE_CONFIG_REGION
169 /*
170 * Alloc a PIO region for config access, shared by all MACs per TRIO.
171 * This shouldn't fail since the kernel is supposed to the first
172 * client of the TRIO's PIO regions.
173 */
174 ret = gxio_trio_alloc_pio_regions(context, 1, 0, 0);
175 if (ret < 0) {
176 pr_err("PCI: CFG PIO alloc failure on TRIO %d, give up\n",
177 trio_index);
178 goto pio_alloc_failure;
179 }
180
181 context->pio_cfg_index = ret;
182
183 /*
184 * For PIO CFG, the bus_address_hi parameter is 0. The mac parameter
185 * is also 0 because it is specified in PIO_REGION_SETUP_CFG_ADDR.
186 */
187 ret = gxio_trio_init_pio_region_aux(context, context->pio_cfg_index,
188 0, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE);
189 if (ret < 0) {
190 pr_err("PCI: CFG PIO init failure on TRIO %d, give up\n",
191 trio_index);
192 goto pio_alloc_failure;
193 }
194 #endif
195
196 /* Get the properties of the PCIe ports on this TRIO instance. */
197 ret = gxio_trio_get_port_property(context, &pcie_ports[trio_index]);
198 if (ret < 0) {
199 pr_err("PCI: PCIE_GET_PORT_PROPERTY failure, error %d, on TRIO %d\n",
200 ret, trio_index);
201 goto get_port_property_failure;
202 }
203
204 context->mmio_base_mac =
205 iorpc_ioremap(context->fd, 0, HV_TRIO_CONFIG_IOREMAP_SIZE);
206 if (context->mmio_base_mac == NULL) {
207 pr_err("PCI: TRIO config space mapping failure, error %d, on TRIO %d\n",
208 ret, trio_index);
209 ret = -ENOMEM;
210
211 goto trio_mmio_mapping_failure;
212 }
213
214 /* Check the port strap state which will override the BIB setting. */
215 for (mac = 0; mac < TILEGX_TRIO_PCIES; mac++) {
216 TRIO_PCIE_INTFC_PORT_CONFIG_t port_config;
217 unsigned int reg_offset;
218
219 /* Ignore ports that are not specified in the BIB. */
220 if (!pcie_ports[trio_index].ports[mac].allow_rc &&
221 !pcie_ports[trio_index].ports[mac].allow_ep)
222 continue;
223
224 reg_offset =
225 (TRIO_PCIE_INTFC_PORT_CONFIG <<
226 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
227 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
228 TRIO_CFG_REGION_ADDR__INTFC_SHIFT) |
229 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
230
231 port_config.word =
232 __gxio_mmio_read(context->mmio_base_mac + reg_offset);
233
234 if (port_config.strap_state != AUTO_CONFIG_RC &&
235 port_config.strap_state != AUTO_CONFIG_RC_G1) {
236 /*
237 * If this is really intended to be an EP port, record
238 * it so that the endpoint driver will know about it.
239 */
240 if (port_config.strap_state == AUTO_CONFIG_EP ||
241 port_config.strap_state == AUTO_CONFIG_EP_G1)
242 pcie_ports[trio_index].ports[mac].allow_ep = 1;
243 }
244 }
245
246 return ret;
247
248 trio_mmio_mapping_failure:
249 get_port_property_failure:
250 asid_alloc_failure:
251 #ifdef USE_SHARED_PCIE_CONFIG_REGION
252 pio_alloc_failure:
253 #endif
254 hv_dev_close(context->fd);
255 gxio_trio_init_failure:
256 context->fd = -1;
257
258 return ret;
259 }
260
261 static int __init tile_trio_init(void)
262 {
263 int i;
264
265 /* We loop over all the TRIO shims. */
266 for (i = 0; i < TILEGX_NUM_TRIO; i++) {
267 if (tile_pcie_open(i) < 0)
268 continue;
269 num_trio_shims++;
270 }
271
272 return 0;
273 }
274 postcore_initcall(tile_trio_init);
275
276 static void tilegx_legacy_irq_ack(struct irq_data *d)
277 {
278 __insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq);
279 }
280
281 static void tilegx_legacy_irq_mask(struct irq_data *d)
282 {
283 __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq);
284 }
285
286 static void tilegx_legacy_irq_unmask(struct irq_data *d)
287 {
288 __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq);
289 }
290
291 static struct irq_chip tilegx_legacy_irq_chip = {
292 .name = "tilegx_legacy_irq",
293 .irq_ack = tilegx_legacy_irq_ack,
294 .irq_mask = tilegx_legacy_irq_mask,
295 .irq_unmask = tilegx_legacy_irq_unmask,
296
297 /* TBD: support set_affinity. */
298 };
299
300 /*
301 * This is a wrapper function of the kernel level-trigger interrupt
302 * handler handle_level_irq() for PCI legacy interrupts. The TRIO
303 * is configured such that only INTx Assert interrupts are proxied
304 * to Linux which just calls handle_level_irq() after clearing the
305 * MAC INTx Assert status bit associated with this interrupt.
306 */
307 static void trio_handle_level_irq(unsigned int __irq, struct irq_desc *desc)
308 {
309 struct pci_controller *controller = irq_desc_get_handler_data(desc);
310 gxio_trio_context_t *trio_context = controller->trio;
311 uint64_t intx = (uint64_t)irq_desc_get_chip_data(desc);
312 unsigned int irq = irq_desc_get_irq(desc);
313 int mac = controller->mac;
314 unsigned int reg_offset;
315 uint64_t level_mask;
316
317 handle_level_irq(irq, desc);
318
319 /*
320 * Clear the INTx Level status, otherwise future interrupts are
321 * not sent.
322 */
323 reg_offset = (TRIO_PCIE_INTFC_MAC_INT_STS <<
324 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
325 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
326 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
327 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
328
329 level_mask = TRIO_PCIE_INTFC_MAC_INT_STS__INT_LEVEL_MASK << intx;
330
331 __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset, level_mask);
332 }
333
334 /*
335 * Create kernel irqs and set up the handlers for the legacy interrupts.
336 * Also some minimum initialization for the MSI support.
337 */
338 static int tile_init_irqs(struct pci_controller *controller)
339 {
340 int i;
341 int j;
342 int irq;
343 int result;
344
345 cpumask_copy(&intr_cpus_map, cpu_online_mask);
346
347
348 for (i = 0; i < 4; i++) {
349 gxio_trio_context_t *context = controller->trio;
350 int cpu;
351
352 /* Ask the kernel to allocate an IRQ. */
353 irq = irq_alloc_hwirq(-1);
354 if (!irq) {
355 pr_err("PCI: no free irq vectors, failed for %d\n", i);
356 goto free_irqs;
357 }
358 controller->irq_intx_table[i] = irq;
359
360 /* Distribute the 4 IRQs to different tiles. */
361 cpu = tile_irq_cpu(irq);
362
363 /* Configure the TRIO intr binding for this IRQ. */
364 result = gxio_trio_config_legacy_intr(context, cpu_x(cpu),
365 cpu_y(cpu), KERNEL_PL,
366 irq, controller->mac, i);
367 if (result < 0) {
368 pr_err("PCI: MAC intx config failed for %d\n", i);
369
370 goto free_irqs;
371 }
372
373 /* Register the IRQ handler with the kernel. */
374 irq_set_chip_and_handler(irq, &tilegx_legacy_irq_chip,
375 trio_handle_level_irq);
376 irq_set_chip_data(irq, (void *)(uint64_t)i);
377 irq_set_handler_data(irq, controller);
378 }
379
380 return 0;
381
382 free_irqs:
383 for (j = 0; j < i; j++)
384 irq_free_hwirq(controller->irq_intx_table[j]);
385
386 return -1;
387 }
388
389 /*
390 * Return 1 if the port is strapped to operate in RC mode.
391 */
392 static int
393 strapped_for_rc(gxio_trio_context_t *trio_context, int mac)
394 {
395 TRIO_PCIE_INTFC_PORT_CONFIG_t port_config;
396 unsigned int reg_offset;
397
398 /* Check the port configuration. */
399 reg_offset =
400 (TRIO_PCIE_INTFC_PORT_CONFIG <<
401 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
402 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
403 TRIO_CFG_REGION_ADDR__INTFC_SHIFT) |
404 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
405 port_config.word =
406 __gxio_mmio_read(trio_context->mmio_base_mac + reg_offset);
407
408 if (port_config.strap_state == AUTO_CONFIG_RC ||
409 port_config.strap_state == AUTO_CONFIG_RC_G1)
410 return 1;
411 else
412 return 0;
413 }
414
415 /*
416 * Find valid controllers and fill in pci_controller structs for each
417 * of them.
418 *
419 * Return the number of controllers discovered.
420 */
421 int __init tile_pci_init(void)
422 {
423 int ctl_index = 0;
424 int i, j;
425
426 if (!pci_probe) {
427 pr_info("PCI: disabled by boot argument\n");
428 return 0;
429 }
430
431 pr_info("PCI: Searching for controllers...\n");
432
433 if (num_trio_shims == 0 || sim_is_simulator())
434 return 0;
435
436 /*
437 * Now determine which PCIe ports are configured to operate in RC
438 * mode. There is a differece in the port configuration capability
439 * between the Gx36 and Gx72 devices.
440 *
441 * The Gx36 has configuration capability for each of the 3 PCIe
442 * interfaces (disable, auto endpoint, auto RC, etc.).
443 * On the Gx72, you can only select one of the 3 PCIe interfaces per
444 * TRIO to train automatically. Further, the allowable training modes
445 * are reduced to four options (auto endpoint, auto RC, stream x1,
446 * stream x4).
447 *
448 * For Gx36 ports, it must be allowed to be in RC mode by the
449 * Board Information Block, and the hardware strapping pins must be
450 * set to RC mode.
451 *
452 * For Gx72 ports, the port will operate in RC mode if either of the
453 * following is true:
454 * 1. It is allowed to be in RC mode by the Board Information Block,
455 * and the BIB doesn't allow the EP mode.
456 * 2. It is allowed to be in either the RC or the EP mode by the BIB,
457 * and the hardware strapping pin is set to RC mode.
458 */
459 for (i = 0; i < TILEGX_NUM_TRIO; i++) {
460 gxio_trio_context_t *context = &trio_contexts[i];
461
462 if (context->fd < 0)
463 continue;
464
465 for (j = 0; j < TILEGX_TRIO_PCIES; j++) {
466 int is_rc = 0;
467
468 if (pcie_ports[i].is_gx72 &&
469 pcie_ports[i].ports[j].allow_rc) {
470 if (!pcie_ports[i].ports[j].allow_ep ||
471 strapped_for_rc(context, j))
472 is_rc = 1;
473 } else if (pcie_ports[i].ports[j].allow_rc &&
474 strapped_for_rc(context, j)) {
475 is_rc = 1;
476 }
477 if (is_rc) {
478 pcie_rc[i][j] = 1;
479 num_rc_controllers++;
480 }
481 }
482 }
483
484 /* Return if no PCIe ports are configured to operate in RC mode. */
485 if (num_rc_controllers == 0)
486 return 0;
487
488 /* Set the TRIO pointer and MAC index for each PCIe RC port. */
489 for (i = 0; i < TILEGX_NUM_TRIO; i++) {
490 for (j = 0; j < TILEGX_TRIO_PCIES; j++) {
491 if (pcie_rc[i][j]) {
492 pci_controllers[ctl_index].trio =
493 &trio_contexts[i];
494 pci_controllers[ctl_index].mac = j;
495 pci_controllers[ctl_index].trio_index = i;
496 ctl_index++;
497 if (ctl_index == num_rc_controllers)
498 goto out;
499 }
500 }
501 }
502
503 out:
504 /* Configure each PCIe RC port. */
505 for (i = 0; i < num_rc_controllers; i++) {
506
507 /* Configure the PCIe MAC to run in RC mode. */
508 struct pci_controller *controller = &pci_controllers[i];
509
510 controller->index = i;
511 controller->ops = &tile_cfg_ops;
512
513 controller->io_space.start = PCIBIOS_MIN_IO +
514 (i * IO_SPACE_SIZE);
515 controller->io_space.end = controller->io_space.start +
516 IO_SPACE_SIZE - 1;
517 BUG_ON(controller->io_space.end > IO_SPACE_LIMIT);
518 controller->io_space.flags = IORESOURCE_IO;
519 snprintf(controller->io_space_name,
520 sizeof(controller->io_space_name),
521 "PCI I/O domain %d", i);
522 controller->io_space.name = controller->io_space_name;
523
524 /*
525 * The PCI memory resource is located above the PA space.
526 * For every host bridge, the BAR window or the MMIO aperture
527 * is in range [3GB, 4GB - 1] of a 4GB space beyond the
528 * PA space.
529 */
530 controller->mem_offset = TILE_PCI_MEM_START +
531 (i * TILE_PCI_BAR_WINDOW_TOP);
532 controller->mem_space.start = controller->mem_offset +
533 TILE_PCI_BAR_WINDOW_TOP - TILE_PCI_BAR_WINDOW_SIZE;
534 controller->mem_space.end = controller->mem_offset +
535 TILE_PCI_BAR_WINDOW_TOP - 1;
536 controller->mem_space.flags = IORESOURCE_MEM;
537 snprintf(controller->mem_space_name,
538 sizeof(controller->mem_space_name),
539 "PCI mem domain %d", i);
540 controller->mem_space.name = controller->mem_space_name;
541 }
542
543 return num_rc_controllers;
544 }
545
546 /*
547 * (pin - 1) converts from the PCI standard's [1:4] convention to
548 * a normal [0:3] range.
549 */
550 static int tile_map_irq(const struct pci_dev *dev, u8 device, u8 pin)
551 {
552 struct pci_controller *controller =
553 (struct pci_controller *)dev->sysdata;
554 return controller->irq_intx_table[pin - 1];
555 }
556
557 static void fixup_read_and_payload_sizes(struct pci_controller *controller)
558 {
559 gxio_trio_context_t *trio_context = controller->trio;
560 struct pci_bus *root_bus = controller->root_bus;
561 TRIO_PCIE_RC_DEVICE_CONTROL_t dev_control;
562 TRIO_PCIE_RC_DEVICE_CAP_t rc_dev_cap;
563 unsigned int reg_offset;
564 struct pci_bus *child;
565 int mac;
566 int err;
567
568 mac = controller->mac;
569
570 /* Set our max read request size to be 4KB. */
571 reg_offset =
572 (TRIO_PCIE_RC_DEVICE_CONTROL <<
573 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
574 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
575 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
576 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
577
578 dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
579 reg_offset);
580 dev_control.max_read_req_sz = 5;
581 __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
582 dev_control.word);
583
584 /*
585 * Set the max payload size supported by this Gx PCIe MAC.
586 * Though Gx PCIe supports Max Payload Size of up to 1024 bytes,
587 * experiments have shown that setting MPS to 256 yields the
588 * best performance.
589 */
590 reg_offset =
591 (TRIO_PCIE_RC_DEVICE_CAP <<
592 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
593 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
594 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
595 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
596
597 rc_dev_cap.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
598 reg_offset);
599 rc_dev_cap.mps_sup = 1;
600 __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
601 rc_dev_cap.word);
602
603 /* Configure PCI Express MPS setting. */
604 list_for_each_entry(child, &root_bus->children, node)
605 pcie_bus_configure_settings(child);
606
607 /*
608 * Set the mac_config register in trio based on the MPS/MRS of the link.
609 */
610 reg_offset =
611 (TRIO_PCIE_RC_DEVICE_CONTROL <<
612 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
613 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
614 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
615 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
616
617 dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
618 reg_offset);
619
620 err = gxio_trio_set_mps_mrs(trio_context,
621 dev_control.max_payload_size,
622 dev_control.max_read_req_sz,
623 mac);
624 if (err < 0) {
625 pr_err("PCI: PCIE_CONFIGURE_MAC_MPS_MRS failure, MAC %d on TRIO %d\n",
626 mac, controller->trio_index);
627 }
628 }
629
630 static int setup_pcie_rc_delay(char *str)
631 {
632 unsigned long delay = 0;
633 unsigned long trio_index;
634 unsigned long mac;
635
636 if (str == NULL || !isdigit(*str))
637 return -EINVAL;
638 trio_index = simple_strtoul(str, (char **)&str, 10);
639 if (trio_index >= TILEGX_NUM_TRIO)
640 return -EINVAL;
641
642 if (*str != ',')
643 return -EINVAL;
644
645 str++;
646 if (!isdigit(*str))
647 return -EINVAL;
648 mac = simple_strtoul(str, (char **)&str, 10);
649 if (mac >= TILEGX_TRIO_PCIES)
650 return -EINVAL;
651
652 if (*str != '\0') {
653 if (*str != ',')
654 return -EINVAL;
655
656 str++;
657 if (!isdigit(*str))
658 return -EINVAL;
659 delay = simple_strtoul(str, (char **)&str, 10);
660 }
661
662 rc_delay[trio_index][mac] = delay ? : DEFAULT_RC_DELAY;
663 return 0;
664 }
665 early_param("pcie_rc_delay", setup_pcie_rc_delay);
666
667 /* PCI initialization entry point, called by subsys_initcall. */
668 int __init pcibios_init(void)
669 {
670 resource_size_t offset;
671 LIST_HEAD(resources);
672 int next_busno;
673 int i;
674
675 tile_pci_init();
676
677 if (num_rc_controllers == 0)
678 return 0;
679
680 /*
681 * Delay a bit in case devices aren't ready. Some devices are
682 * known to require at least 20ms here, but we use a more
683 * conservative value.
684 */
685 msleep(250);
686
687 /* Scan all of the recorded PCI controllers. */
688 for (next_busno = 0, i = 0; i < num_rc_controllers; i++) {
689 struct pci_controller *controller = &pci_controllers[i];
690 gxio_trio_context_t *trio_context = controller->trio;
691 TRIO_PCIE_INTFC_PORT_STATUS_t port_status;
692 TRIO_PCIE_INTFC_TX_FIFO_CTL_t tx_fifo_ctl;
693 struct pci_bus *bus;
694 unsigned int reg_offset;
695 unsigned int class_code_revision;
696 int trio_index;
697 int mac;
698 int ret;
699
700 if (trio_context->fd < 0)
701 continue;
702
703 trio_index = controller->trio_index;
704 mac = controller->mac;
705
706 /*
707 * Check for PCIe link-up status to decide if we need
708 * to force the link to come up.
709 */
710 reg_offset =
711 (TRIO_PCIE_INTFC_PORT_STATUS <<
712 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
713 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
714 TRIO_CFG_REGION_ADDR__INTFC_SHIFT) |
715 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
716
717 port_status.word =
718 __gxio_mmio_read(trio_context->mmio_base_mac +
719 reg_offset);
720 if (!port_status.dl_up) {
721 if (rc_delay[trio_index][mac]) {
722 pr_info("Delaying PCIe RC TRIO init %d sec on MAC %d on TRIO %d\n",
723 rc_delay[trio_index][mac], mac,
724 trio_index);
725 msleep(rc_delay[trio_index][mac] * 1000);
726 }
727 ret = gxio_trio_force_rc_link_up(trio_context, mac);
728 if (ret < 0)
729 pr_err("PCI: PCIE_FORCE_LINK_UP failure, MAC %d on TRIO %d\n",
730 mac, trio_index);
731 }
732
733 pr_info("PCI: Found PCI controller #%d on TRIO %d MAC %d\n",
734 i, trio_index, controller->mac);
735
736 /* Delay the bus probe if needed. */
737 if (rc_delay[trio_index][mac]) {
738 pr_info("Delaying PCIe RC bus enumerating %d sec on MAC %d on TRIO %d\n",
739 rc_delay[trio_index][mac], mac, trio_index);
740 msleep(rc_delay[trio_index][mac] * 1000);
741 } else {
742 /*
743 * Wait a bit here because some EP devices
744 * take longer to come up.
745 */
746 msleep(1000);
747 }
748
749 /* Check for PCIe link-up status again. */
750 port_status.word =
751 __gxio_mmio_read(trio_context->mmio_base_mac +
752 reg_offset);
753 if (!port_status.dl_up) {
754 if (pcie_ports[trio_index].ports[mac].removable) {
755 pr_info("PCI: link is down, MAC %d on TRIO %d\n",
756 mac, trio_index);
757 pr_info("This is expected if no PCIe card is connected to this link\n");
758 } else
759 pr_err("PCI: link is down, MAC %d on TRIO %d\n",
760 mac, trio_index);
761 continue;
762 }
763
764 /*
765 * Ensure that the link can come out of L1 power down state.
766 * Strictly speaking, this is needed only in the case of
767 * heavy RC-initiated DMAs.
768 */
769 reg_offset =
770 (TRIO_PCIE_INTFC_TX_FIFO_CTL <<
771 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
772 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
773 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
774 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
775 tx_fifo_ctl.word =
776 __gxio_mmio_read(trio_context->mmio_base_mac +
777 reg_offset);
778 tx_fifo_ctl.min_p_credits = 0;
779 __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset,
780 tx_fifo_ctl.word);
781
782 /*
783 * Change the device ID so that Linux bus crawl doesn't confuse
784 * the internal bridge with any Tilera endpoints.
785 */
786 reg_offset =
787 (TRIO_PCIE_RC_DEVICE_ID_VEN_ID <<
788 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
789 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
790 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
791 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
792
793 __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
794 (TILERA_GX36_RC_DEV_ID <<
795 TRIO_PCIE_RC_DEVICE_ID_VEN_ID__DEV_ID_SHIFT) |
796 TILERA_VENDOR_ID);
797
798 /* Set the internal P2P bridge class code. */
799 reg_offset =
800 (TRIO_PCIE_RC_REVISION_ID <<
801 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
802 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
803 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
804 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
805
806 class_code_revision =
807 __gxio_mmio_read32(trio_context->mmio_base_mac +
808 reg_offset);
809 class_code_revision = (class_code_revision & 0xff) |
810 (PCI_CLASS_BRIDGE_PCI << 16);
811
812 __gxio_mmio_write32(trio_context->mmio_base_mac +
813 reg_offset, class_code_revision);
814
815 #ifdef USE_SHARED_PCIE_CONFIG_REGION
816
817 /* Map in the MMIO space for the PIO region. */
818 offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index) |
819 (((unsigned long long)mac) <<
820 TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT);
821
822 #else
823
824 /* Alloc a PIO region for PCI config access per MAC. */
825 ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
826 if (ret < 0) {
827 pr_err("PCI: PCI CFG PIO alloc failure for mac %d on TRIO %d, give up\n",
828 mac, trio_index);
829
830 continue;
831 }
832
833 trio_context->pio_cfg_index[mac] = ret;
834
835 /* For PIO CFG, the bus_address_hi parameter is 0. */
836 ret = gxio_trio_init_pio_region_aux(trio_context,
837 trio_context->pio_cfg_index[mac],
838 mac, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE);
839 if (ret < 0) {
840 pr_err("PCI: PCI CFG PIO init failure for mac %d on TRIO %d, give up\n",
841 mac, trio_index);
842
843 continue;
844 }
845
846 offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index[mac]) |
847 (((unsigned long long)mac) <<
848 TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT);
849
850 #endif
851
852 /*
853 * To save VMALLOC space, we take advantage of the fact that
854 * bit 29 in the PIO CFG address format is reserved 0. With
855 * TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT being 30,
856 * this cuts VMALLOC space usage from 1GB to 512MB per mac.
857 */
858 trio_context->mmio_base_pio_cfg[mac] =
859 iorpc_ioremap(trio_context->fd, offset, (1UL <<
860 (TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT - 1)));
861 if (trio_context->mmio_base_pio_cfg[mac] == NULL) {
862 pr_err("PCI: PIO map failure for mac %d on TRIO %d\n",
863 mac, trio_index);
864
865 continue;
866 }
867
868 /* Initialize the PCIe interrupts. */
869 if (tile_init_irqs(controller)) {
870 pr_err("PCI: IRQs init failure for mac %d on TRIO %d\n",
871 mac, trio_index);
872
873 continue;
874 }
875
876 /*
877 * The PCI memory resource is located above the PA space.
878 * The memory range for the PCI root bus should not overlap
879 * with the physical RAM.
880 */
881 pci_add_resource_offset(&resources, &controller->mem_space,
882 controller->mem_offset);
883 pci_add_resource(&resources, &controller->io_space);
884 controller->first_busno = next_busno;
885 bus = pci_scan_root_bus(NULL, next_busno, controller->ops,
886 controller, &resources);
887 controller->root_bus = bus;
888 next_busno = bus->busn_res.end + 1;
889 }
890
891 /* Do machine dependent PCI interrupt routing */
892 pci_fixup_irqs(pci_common_swizzle, tile_map_irq);
893
894 /*
895 * This comes from the generic Linux PCI driver.
896 *
897 * It allocates all of the resources (I/O memory, etc)
898 * associated with the devices read in above.
899 */
900 pci_assign_unassigned_resources();
901
902 /* Record the I/O resources in the PCI controller structure. */
903 for (i = 0; i < num_rc_controllers; i++) {
904 struct pci_controller *controller = &pci_controllers[i];
905 gxio_trio_context_t *trio_context = controller->trio;
906 struct pci_bus *root_bus = pci_controllers[i].root_bus;
907 int ret;
908 int j;
909
910 /*
911 * Skip controllers that are not properly initialized or
912 * have down links.
913 */
914 if (root_bus == NULL)
915 continue;
916
917 /* Configure the max_payload_size values for this domain. */
918 fixup_read_and_payload_sizes(controller);
919
920 /* Alloc a PIO region for PCI memory access for each RC port. */
921 ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
922 if (ret < 0) {
923 pr_err("PCI: MEM PIO alloc failure on TRIO %d mac %d, give up\n",
924 controller->trio_index, controller->mac);
925
926 continue;
927 }
928
929 controller->pio_mem_index = ret;
930
931 /*
932 * For PIO MEM, the bus_address_hi parameter is hard-coded 0
933 * because we always assign 32-bit PCI bus BAR ranges.
934 */
935 ret = gxio_trio_init_pio_region_aux(trio_context,
936 controller->pio_mem_index,
937 controller->mac,
938 0,
939 0);
940 if (ret < 0) {
941 pr_err("PCI: MEM PIO init failure on TRIO %d mac %d, give up\n",
942 controller->trio_index, controller->mac);
943
944 continue;
945 }
946
947 #ifdef CONFIG_TILE_PCI_IO
948 /*
949 * Alloc a PIO region for PCI I/O space access for each RC port.
950 */
951 ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
952 if (ret < 0) {
953 pr_err("PCI: I/O PIO alloc failure on TRIO %d mac %d, give up\n",
954 controller->trio_index, controller->mac);
955
956 continue;
957 }
958
959 controller->pio_io_index = ret;
960
961 /*
962 * For PIO IO, the bus_address_hi parameter is hard-coded 0
963 * because PCI I/O address space is 32-bit.
964 */
965 ret = gxio_trio_init_pio_region_aux(trio_context,
966 controller->pio_io_index,
967 controller->mac,
968 0,
969 HV_TRIO_PIO_FLAG_IO_SPACE);
970 if (ret < 0) {
971 pr_err("PCI: I/O PIO init failure on TRIO %d mac %d, give up\n",
972 controller->trio_index, controller->mac);
973
974 continue;
975 }
976 #endif
977
978 /*
979 * Configure a Mem-Map region for each memory controller so
980 * that Linux can map all of its PA space to the PCI bus.
981 * Use the IOMMU to handle hash-for-home memory.
982 */
983 for_each_online_node(j) {
984 unsigned long start_pfn = node_start_pfn[j];
985 unsigned long end_pfn = node_end_pfn[j];
986 unsigned long nr_pages = end_pfn - start_pfn;
987
988 ret = gxio_trio_alloc_memory_maps(trio_context, 1, 0,
989 0);
990 if (ret < 0) {
991 pr_err("PCI: Mem-Map alloc failure on TRIO %d mac %d for MC %d, give up\n",
992 controller->trio_index, controller->mac,
993 j);
994
995 goto alloc_mem_map_failed;
996 }
997
998 controller->mem_maps[j] = ret;
999
1000 /*
1001 * Initialize the Mem-Map and the I/O MMU so that all
1002 * the physical memory can be accessed by the endpoint
1003 * devices. The base bus address is set to the base CPA
1004 * of this memory controller plus an offset (see pci.h).
1005 * The region's base VA is set to the base CPA. The
1006 * I/O MMU table essentially translates the CPA to
1007 * the real PA. Implicitly, for node 0, we create
1008 * a separate Mem-Map region that serves as the inbound
1009 * window for legacy 32-bit devices. This is a direct
1010 * map of the low 4GB CPA space.
1011 */
1012 ret = gxio_trio_init_memory_map_mmu_aux(trio_context,
1013 controller->mem_maps[j],
1014 start_pfn << PAGE_SHIFT,
1015 nr_pages << PAGE_SHIFT,
1016 trio_context->asid,
1017 controller->mac,
1018 (start_pfn << PAGE_SHIFT) +
1019 TILE_PCI_MEM_MAP_BASE_OFFSET,
1020 j,
1021 GXIO_TRIO_ORDER_MODE_UNORDERED);
1022 if (ret < 0) {
1023 pr_err("PCI: Mem-Map init failure on TRIO %d mac %d for MC %d, give up\n",
1024 controller->trio_index, controller->mac,
1025 j);
1026
1027 goto alloc_mem_map_failed;
1028 }
1029 continue;
1030
1031 alloc_mem_map_failed:
1032 break;
1033 }
1034
1035 pci_bus_add_devices(root_bus);
1036 }
1037
1038 return 0;
1039 }
1040 subsys_initcall(pcibios_init);
1041
1042 /* No bus fixups needed. */
1043 void pcibios_fixup_bus(struct pci_bus *bus)
1044 {
1045 }
1046
1047 /* Process any "pci=" kernel boot arguments. */
1048 char *__init pcibios_setup(char *str)
1049 {
1050 if (!strcmp(str, "off")) {
1051 pci_probe = 0;
1052 return NULL;
1053 }
1054 return str;
1055 }
1056
1057 /*
1058 * Called for each device after PCI setup is done.
1059 * We initialize the PCI device capabilities conservatively, assuming that
1060 * all devices can only address the 32-bit DMA space. The exception here is
1061 * that the device dma_offset is set to the value that matches the 64-bit
1062 * capable devices. This is OK because dma_offset is not used by legacy
1063 * dma_ops, nor by the hybrid dma_ops's streaming DMAs, which are 64-bit ops.
1064 * This implementation matches the kernel design of setting PCI devices'
1065 * coherent_dma_mask to 0xffffffffull by default, allowing the device drivers
1066 * to skip calling pci_set_consistent_dma_mask(DMA_BIT_MASK(32)).
1067 */
1068 static void pcibios_fixup_final(struct pci_dev *pdev)
1069 {
1070 set_dma_ops(&pdev->dev, gx_legacy_pci_dma_map_ops);
1071 set_dma_offset(&pdev->dev, TILE_PCI_MEM_MAP_BASE_OFFSET);
1072 pdev->dev.archdata.max_direct_dma_addr =
1073 TILE_PCI_MAX_DIRECT_DMA_ADDRESS;
1074 pdev->dev.coherent_dma_mask = TILE_PCI_MAX_DIRECT_DMA_ADDRESS;
1075 }
1076 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
1077
1078 /* Map a PCI MMIO bus address into VA space. */
1079 void __iomem *ioremap(resource_size_t phys_addr, unsigned long size)
1080 {
1081 struct pci_controller *controller = NULL;
1082 resource_size_t bar_start;
1083 resource_size_t bar_end;
1084 resource_size_t offset;
1085 resource_size_t start;
1086 resource_size_t end;
1087 int trio_fd;
1088 int i;
1089
1090 start = phys_addr;
1091 end = phys_addr + size - 1;
1092
1093 /*
1094 * By searching phys_addr in each controller's mem_space, we can
1095 * determine the controller that should accept the PCI memory access.
1096 */
1097 for (i = 0; i < num_rc_controllers; i++) {
1098 /*
1099 * Skip controllers that are not properly initialized or
1100 * have down links.
1101 */
1102 if (pci_controllers[i].root_bus == NULL)
1103 continue;
1104
1105 bar_start = pci_controllers[i].mem_space.start;
1106 bar_end = pci_controllers[i].mem_space.end;
1107
1108 if ((start >= bar_start) && (end <= bar_end)) {
1109 controller = &pci_controllers[i];
1110 break;
1111 }
1112 }
1113
1114 if (controller == NULL)
1115 return NULL;
1116
1117 trio_fd = controller->trio->fd;
1118
1119 /* Convert the resource start to the bus address offset. */
1120 start = phys_addr - controller->mem_offset;
1121
1122 offset = HV_TRIO_PIO_OFFSET(controller->pio_mem_index) + start;
1123
1124 /* We need to keep the PCI bus address's in-page offset in the VA. */
1125 return iorpc_ioremap(trio_fd, offset, size) +
1126 (start & (PAGE_SIZE - 1));
1127 }
1128 EXPORT_SYMBOL(ioremap);
1129
1130 #ifdef CONFIG_TILE_PCI_IO
1131 /* Map a PCI I/O address into VA space. */
1132 void __iomem *ioport_map(unsigned long port, unsigned int size)
1133 {
1134 struct pci_controller *controller = NULL;
1135 resource_size_t bar_start;
1136 resource_size_t bar_end;
1137 resource_size_t offset;
1138 resource_size_t start;
1139 resource_size_t end;
1140 int trio_fd;
1141 int i;
1142
1143 start = port;
1144 end = port + size - 1;
1145
1146 /*
1147 * By searching the port in each controller's io_space, we can
1148 * determine the controller that should accept the PCI I/O access.
1149 */
1150 for (i = 0; i < num_rc_controllers; i++) {
1151 /*
1152 * Skip controllers that are not properly initialized or
1153 * have down links.
1154 */
1155 if (pci_controllers[i].root_bus == NULL)
1156 continue;
1157
1158 bar_start = pci_controllers[i].io_space.start;
1159 bar_end = pci_controllers[i].io_space.end;
1160
1161 if ((start >= bar_start) && (end <= bar_end)) {
1162 controller = &pci_controllers[i];
1163 break;
1164 }
1165 }
1166
1167 if (controller == NULL)
1168 return NULL;
1169
1170 trio_fd = controller->trio->fd;
1171
1172 /* Convert the resource start to the bus address offset. */
1173 port -= controller->io_space.start;
1174
1175 offset = HV_TRIO_PIO_OFFSET(controller->pio_io_index) + port;
1176
1177 /* We need to keep the PCI bus address's in-page offset in the VA. */
1178 return iorpc_ioremap(trio_fd, offset, size) + (port & (PAGE_SIZE - 1));
1179 }
1180 EXPORT_SYMBOL(ioport_map);
1181
1182 void ioport_unmap(void __iomem *addr)
1183 {
1184 iounmap(addr);
1185 }
1186 EXPORT_SYMBOL(ioport_unmap);
1187 #endif
1188
1189 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
1190 {
1191 iounmap(addr);
1192 }
1193 EXPORT_SYMBOL(pci_iounmap);
1194
1195 /****************************************************************
1196 *
1197 * Tile PCI config space read/write routines
1198 *
1199 ****************************************************************/
1200
1201 /*
1202 * These are the normal read and write ops
1203 * These are expanded with macros from pci_bus_read_config_byte() etc.
1204 *
1205 * devfn is the combined PCI device & function.
1206 *
1207 * offset is in bytes, from the start of config space for the
1208 * specified bus & device.
1209 */
1210 static int tile_cfg_read(struct pci_bus *bus, unsigned int devfn, int offset,
1211 int size, u32 *val)
1212 {
1213 struct pci_controller *controller = bus->sysdata;
1214 gxio_trio_context_t *trio_context = controller->trio;
1215 int busnum = bus->number & 0xff;
1216 int device = PCI_SLOT(devfn);
1217 int function = PCI_FUNC(devfn);
1218 int config_type = 1;
1219 TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr;
1220 void *mmio_addr;
1221
1222 /*
1223 * Map all accesses to the local device on root bus into the
1224 * MMIO space of the MAC. Accesses to the downstream devices
1225 * go to the PIO space.
1226 */
1227 if (pci_is_root_bus(bus)) {
1228 if (device == 0) {
1229 /*
1230 * This is the internal downstream P2P bridge,
1231 * access directly.
1232 */
1233 unsigned int reg_offset;
1234
1235 reg_offset = ((offset & 0xFFF) <<
1236 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
1237 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED
1238 << TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
1239 (controller->mac <<
1240 TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
1241
1242 mmio_addr = trio_context->mmio_base_mac + reg_offset;
1243
1244 goto valid_device;
1245
1246 } else {
1247 /*
1248 * We fake an empty device for (device > 0),
1249 * since there is only one device on bus 0.
1250 */
1251 goto invalid_device;
1252 }
1253 }
1254
1255 /*
1256 * Accesses to the directly attached device have to be
1257 * sent as type-0 configs.
1258 */
1259 if (busnum == (controller->first_busno + 1)) {
1260 /*
1261 * There is only one device off of our built-in P2P bridge.
1262 */
1263 if (device != 0)
1264 goto invalid_device;
1265
1266 config_type = 0;
1267 }
1268
1269 cfg_addr.word = 0;
1270 cfg_addr.reg_addr = (offset & 0xFFF);
1271 cfg_addr.fn = function;
1272 cfg_addr.dev = device;
1273 cfg_addr.bus = busnum;
1274 cfg_addr.type = config_type;
1275
1276 /*
1277 * Note that we don't set the mac field in cfg_addr because the
1278 * mapping is per port.
1279 */
1280 mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] +
1281 cfg_addr.word;
1282
1283 valid_device:
1284
1285 switch (size) {
1286 case 4:
1287 *val = __gxio_mmio_read32(mmio_addr);
1288 break;
1289
1290 case 2:
1291 *val = __gxio_mmio_read16(mmio_addr);
1292 break;
1293
1294 case 1:
1295 *val = __gxio_mmio_read8(mmio_addr);
1296 break;
1297
1298 default:
1299 return PCIBIOS_FUNC_NOT_SUPPORTED;
1300 }
1301
1302 TRACE_CFG_RD(size, *val, busnum, device, function, offset);
1303
1304 return 0;
1305
1306 invalid_device:
1307
1308 switch (size) {
1309 case 4:
1310 *val = 0xFFFFFFFF;
1311 break;
1312
1313 case 2:
1314 *val = 0xFFFF;
1315 break;
1316
1317 case 1:
1318 *val = 0xFF;
1319 break;
1320
1321 default:
1322 return PCIBIOS_FUNC_NOT_SUPPORTED;
1323 }
1324
1325 return 0;
1326 }
1327
1328
1329 /*
1330 * See tile_cfg_read() for relevent comments.
1331 * Note that "val" is the value to write, not a pointer to that value.
1332 */
1333 static int tile_cfg_write(struct pci_bus *bus, unsigned int devfn, int offset,
1334 int size, u32 val)
1335 {
1336 struct pci_controller *controller = bus->sysdata;
1337 gxio_trio_context_t *trio_context = controller->trio;
1338 int busnum = bus->number & 0xff;
1339 int device = PCI_SLOT(devfn);
1340 int function = PCI_FUNC(devfn);
1341 int config_type = 1;
1342 TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr;
1343 void *mmio_addr;
1344 u32 val_32 = (u32)val;
1345 u16 val_16 = (u16)val;
1346 u8 val_8 = (u8)val;
1347
1348 /*
1349 * Map all accesses to the local device on root bus into the
1350 * MMIO space of the MAC. Accesses to the downstream devices
1351 * go to the PIO space.
1352 */
1353 if (pci_is_root_bus(bus)) {
1354 if (device == 0) {
1355 /*
1356 * This is the internal downstream P2P bridge,
1357 * access directly.
1358 */
1359 unsigned int reg_offset;
1360
1361 reg_offset = ((offset & 0xFFF) <<
1362 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
1363 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED
1364 << TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
1365 (controller->mac <<
1366 TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
1367
1368 mmio_addr = trio_context->mmio_base_mac + reg_offset;
1369
1370 goto valid_device;
1371
1372 } else {
1373 /*
1374 * We fake an empty device for (device > 0),
1375 * since there is only one device on bus 0.
1376 */
1377 goto invalid_device;
1378 }
1379 }
1380
1381 /*
1382 * Accesses to the directly attached device have to be
1383 * sent as type-0 configs.
1384 */
1385 if (busnum == (controller->first_busno + 1)) {
1386 /*
1387 * There is only one device off of our built-in P2P bridge.
1388 */
1389 if (device != 0)
1390 goto invalid_device;
1391
1392 config_type = 0;
1393 }
1394
1395 cfg_addr.word = 0;
1396 cfg_addr.reg_addr = (offset & 0xFFF);
1397 cfg_addr.fn = function;
1398 cfg_addr.dev = device;
1399 cfg_addr.bus = busnum;
1400 cfg_addr.type = config_type;
1401
1402 /*
1403 * Note that we don't set the mac field in cfg_addr because the
1404 * mapping is per port.
1405 */
1406 mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] +
1407 cfg_addr.word;
1408
1409 valid_device:
1410
1411 switch (size) {
1412 case 4:
1413 __gxio_mmio_write32(mmio_addr, val_32);
1414 TRACE_CFG_WR(size, val_32, busnum, device, function, offset);
1415 break;
1416
1417 case 2:
1418 __gxio_mmio_write16(mmio_addr, val_16);
1419 TRACE_CFG_WR(size, val_16, busnum, device, function, offset);
1420 break;
1421
1422 case 1:
1423 __gxio_mmio_write8(mmio_addr, val_8);
1424 TRACE_CFG_WR(size, val_8, busnum, device, function, offset);
1425 break;
1426
1427 default:
1428 return PCIBIOS_FUNC_NOT_SUPPORTED;
1429 }
1430
1431 invalid_device:
1432
1433 return 0;
1434 }
1435
1436
1437 static struct pci_ops tile_cfg_ops = {
1438 .read = tile_cfg_read,
1439 .write = tile_cfg_write,
1440 };
1441
1442
1443 /* MSI support starts here. */
1444 static unsigned int tilegx_msi_startup(struct irq_data *d)
1445 {
1446 if (irq_data_get_msi_desc(d))
1447 pci_msi_unmask_irq(d);
1448
1449 return 0;
1450 }
1451
1452 static void tilegx_msi_ack(struct irq_data *d)
1453 {
1454 __insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq);
1455 }
1456
1457 static void tilegx_msi_mask(struct irq_data *d)
1458 {
1459 pci_msi_mask_irq(d);
1460 __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq);
1461 }
1462
1463 static void tilegx_msi_unmask(struct irq_data *d)
1464 {
1465 __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq);
1466 pci_msi_unmask_irq(d);
1467 }
1468
1469 static struct irq_chip tilegx_msi_chip = {
1470 .name = "tilegx_msi",
1471 .irq_startup = tilegx_msi_startup,
1472 .irq_ack = tilegx_msi_ack,
1473 .irq_mask = tilegx_msi_mask,
1474 .irq_unmask = tilegx_msi_unmask,
1475
1476 /* TBD: support set_affinity. */
1477 };
1478
1479 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1480 {
1481 struct pci_controller *controller;
1482 gxio_trio_context_t *trio_context;
1483 struct msi_msg msg;
1484 int default_irq;
1485 uint64_t mem_map_base;
1486 uint64_t mem_map_limit;
1487 u64 msi_addr;
1488 int mem_map;
1489 int cpu;
1490 int irq;
1491 int ret;
1492
1493 irq = irq_alloc_hwirq(-1);
1494 if (!irq)
1495 return -ENOSPC;
1496
1497 /*
1498 * Since we use a 64-bit Mem-Map to accept the MSI write, we fail
1499 * devices that are not capable of generating a 64-bit message address.
1500 * These devices will fall back to using the legacy interrupts.
1501 * Most PCIe endpoint devices do support 64-bit message addressing.
1502 */
1503 if (desc->msi_attrib.is_64 == 0) {
1504 dev_info(&pdev->dev, "64-bit MSI message address not supported, falling back to legacy interrupts\n");
1505
1506 ret = -ENOMEM;
1507 goto is_64_failure;
1508 }
1509
1510 default_irq = desc->msi_attrib.default_irq;
1511 controller = irq_get_handler_data(default_irq);
1512
1513 BUG_ON(!controller);
1514
1515 trio_context = controller->trio;
1516
1517 /*
1518 * Allocate a scatter-queue that will accept the MSI write and
1519 * trigger the TILE-side interrupts. We use the scatter-queue regions
1520 * before the mem map regions, because the latter are needed by more
1521 * applications.
1522 */
1523 mem_map = gxio_trio_alloc_scatter_queues(trio_context, 1, 0, 0);
1524 if (mem_map >= 0) {
1525 TRIO_MAP_SQ_DOORBELL_FMT_t doorbell_template = {{
1526 .pop = 0,
1527 .doorbell = 1,
1528 }};
1529
1530 mem_map += TRIO_NUM_MAP_MEM_REGIONS;
1531 mem_map_base = MEM_MAP_INTR_REGIONS_BASE +
1532 mem_map * MEM_MAP_INTR_REGION_SIZE;
1533 mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1;
1534
1535 msi_addr = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 8;
1536 msg.data = (unsigned int)doorbell_template.word;
1537 } else {
1538 /* SQ regions are out, allocate from map mem regions. */
1539 mem_map = gxio_trio_alloc_memory_maps(trio_context, 1, 0, 0);
1540 if (mem_map < 0) {
1541 dev_info(&pdev->dev, "%s Mem-Map alloc failure - failed to initialize MSI interrupts - falling back to legacy interrupts\n",
1542 desc->msi_attrib.is_msix ? "MSI-X" : "MSI");
1543 ret = -ENOMEM;
1544 goto msi_mem_map_alloc_failure;
1545 }
1546
1547 mem_map_base = MEM_MAP_INTR_REGIONS_BASE +
1548 mem_map * MEM_MAP_INTR_REGION_SIZE;
1549 mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1;
1550
1551 msi_addr = mem_map_base + TRIO_MAP_MEM_REG_INT3 -
1552 TRIO_MAP_MEM_REG_INT0;
1553
1554 msg.data = mem_map;
1555 }
1556
1557 /* We try to distribute different IRQs to different tiles. */
1558 cpu = tile_irq_cpu(irq);
1559
1560 /*
1561 * Now call up to the HV to configure the MSI interrupt and
1562 * set up the IPI binding.
1563 */
1564 ret = gxio_trio_config_msi_intr(trio_context, cpu_x(cpu), cpu_y(cpu),
1565 KERNEL_PL, irq, controller->mac,
1566 mem_map, mem_map_base, mem_map_limit,
1567 trio_context->asid);
1568 if (ret < 0) {
1569 dev_info(&pdev->dev, "HV MSI config failed\n");
1570
1571 goto hv_msi_config_failure;
1572 }
1573
1574 irq_set_msi_desc(irq, desc);
1575
1576 msg.address_hi = msi_addr >> 32;
1577 msg.address_lo = msi_addr & 0xffffffff;
1578
1579 pci_write_msi_msg(irq, &msg);
1580 irq_set_chip_and_handler(irq, &tilegx_msi_chip, handle_level_irq);
1581 irq_set_handler_data(irq, controller);
1582
1583 return 0;
1584
1585 hv_msi_config_failure:
1586 /* Free mem-map */
1587 msi_mem_map_alloc_failure:
1588 is_64_failure:
1589 irq_free_hwirq(irq);
1590 return ret;
1591 }
1592
1593 void arch_teardown_msi_irq(unsigned int irq)
1594 {
1595 irq_free_hwirq(irq);
1596 }
CRIS linux kernel tree