arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_bar_defs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __marb_bar_defs_h
   3 #define __marb_bar_defs_h
   4
   5 /*
   6  * This file is autogenerated from
   7  *   file:           marb_bar.r
   8  *
   9  *   by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r
  10  * Any changes here will be lost.
  11  *
  12  * -*- buffer-read-only: t -*-
  13  */
  14 /* Main access macros */
  15 #ifndef REG_RD
  16 #define REG_RD( scope, inst, reg ) \
  17   REG_READ( reg_##scope##_##reg, \
  18             (inst) + REG_RD_ADDR_##scope##_##reg )
  19 #endif
  20
  21 #ifndef REG_WR
  22 #define REG_WR( scope, inst, reg, val ) \
  23   REG_WRITE( reg_##scope##_##reg, \
  24              (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  25 #endif
  26
  27 #ifndef REG_RD_VECT
  28 #define REG_RD_VECT( scope, inst, reg, index ) \
  29   REG_READ( reg_##scope##_##reg, \
  30             (inst) + REG_RD_ADDR_##scope##_##reg + \
  31             (index) * STRIDE_##scope##_##reg )
  32 #endif
  33
  34 #ifndef REG_WR_VECT
  35 #define REG_WR_VECT( scope, inst, reg, index, val ) \
  36   REG_WRITE( reg_##scope##_##reg, \
  37              (inst) + REG_WR_ADDR_##scope##_##reg + \
  38              (index) * STRIDE_##scope##_##reg, (val) )
  39 #endif
  40
  41 #ifndef REG_RD_INT
  42 #define REG_RD_INT( scope, inst, reg ) \
  43   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  44 #endif
  45
  46 #ifndef REG_WR_INT
  47 #define REG_WR_INT( scope, inst, reg, val ) \
  48   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  49 #endif
  50
  51 #ifndef REG_RD_INT_VECT
  52 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
  53   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  54             (index) * STRIDE_##scope##_##reg )
  55 #endif
  56
  57 #ifndef REG_WR_INT_VECT
  58 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  59   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  60              (index) * STRIDE_##scope##_##reg, (val) )
  61 #endif
  62
  63 #ifndef REG_TYPE_CONV
  64 #define REG_TYPE_CONV( type, orgtype, val ) \
  65   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  66 #endif
  67
  68 #ifndef reg_page_size
  69 #define reg_page_size 8192
  70 #endif
  71
  72 #ifndef REG_ADDR
  73 #define REG_ADDR( scope, inst, reg ) \
  74   ( (inst) + REG_RD_ADDR_##scope##_##reg )
  75 #endif
  76
  77 #ifndef REG_ADDR_VECT
  78 #define REG_ADDR_VECT( scope, inst, reg, index ) \
  79   ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  80     (index) * STRIDE_##scope##_##reg )
  81 #endif
  82
  83 /* C-code for register scope marb_bar */
  84
  85 #define STRIDE_marb_bar_rw_ddr2_slots 4
  86 /* Register rw_ddr2_slots, scope marb_bar, type rw */
  87 typedef struct {
  88   unsigned int owner : 4;
  89   unsigned int dummy1 : 28;
  90 } reg_marb_bar_rw_ddr2_slots;
  91 #define REG_RD_ADDR_marb_bar_rw_ddr2_slots 0
  92 #define REG_WR_ADDR_marb_bar_rw_ddr2_slots 0
  93
  94 /* Register rw_h264_rd_burst, scope marb_bar, type rw */
  95 typedef struct {
  96   unsigned int ddr2_bsize : 2;
  97   unsigned int dummy1     : 30;
  98 } reg_marb_bar_rw_h264_rd_burst;
  99 #define REG_RD_ADDR_marb_bar_rw_h264_rd_burst 256
 100 #define REG_WR_ADDR_marb_bar_rw_h264_rd_burst 256
 101
 102 /* Register rw_h264_wr_burst, scope marb_bar, type rw */
 103 typedef struct {
 104   unsigned int ddr2_bsize : 2;
 105   unsigned int dummy1     : 30;
 106 } reg_marb_bar_rw_h264_wr_burst;
 107 #define REG_RD_ADDR_marb_bar_rw_h264_wr_burst 260
 108 #define REG_WR_ADDR_marb_bar_rw_h264_wr_burst 260
 109
 110 /* Register rw_ccd_burst, scope marb_bar, type rw */
 111 typedef struct {
 112   unsigned int ddr2_bsize : 2;
 113   unsigned int dummy1     : 30;
 114 } reg_marb_bar_rw_ccd_burst;
 115 #define REG_RD_ADDR_marb_bar_rw_ccd_burst 264
 116 #define REG_WR_ADDR_marb_bar_rw_ccd_burst 264
 117
 118 /* Register rw_vin_wr_burst, scope marb_bar, type rw */
 119 typedef struct {
 120   unsigned int ddr2_bsize : 2;
 121   unsigned int dummy1     : 30;
 122 } reg_marb_bar_rw_vin_wr_burst;
 123 #define REG_RD_ADDR_marb_bar_rw_vin_wr_burst 268
 124 #define REG_WR_ADDR_marb_bar_rw_vin_wr_burst 268
 125
 126 /* Register rw_vin_rd_burst, scope marb_bar, type rw */
 127 typedef struct {
 128   unsigned int ddr2_bsize : 2;
 129   unsigned int dummy1     : 30;
 130 } reg_marb_bar_rw_vin_rd_burst;
 131 #define REG_RD_ADDR_marb_bar_rw_vin_rd_burst 272
 132 #define REG_WR_ADDR_marb_bar_rw_vin_rd_burst 272
 133
 134 /* Register rw_sclr_rd_burst, scope marb_bar, type rw */
 135 typedef struct {
 136   unsigned int ddr2_bsize : 2;
 137   unsigned int dummy1     : 30;
 138 } reg_marb_bar_rw_sclr_rd_burst;
 139 #define REG_RD_ADDR_marb_bar_rw_sclr_rd_burst 276
 140 #define REG_WR_ADDR_marb_bar_rw_sclr_rd_burst 276
 141
 142 /* Register rw_vout_burst, scope marb_bar, type rw */
 143 typedef struct {
 144   unsigned int ddr2_bsize : 2;
 145   unsigned int dummy1     : 30;
 146 } reg_marb_bar_rw_vout_burst;
 147 #define REG_RD_ADDR_marb_bar_rw_vout_burst 280
 148 #define REG_WR_ADDR_marb_bar_rw_vout_burst 280
 149
 150 /* Register rw_sclr_fifo_burst, scope marb_bar, type rw */
 151 typedef struct {
 152   unsigned int ddr2_bsize : 2;
 153   unsigned int dummy1     : 30;
 154 } reg_marb_bar_rw_sclr_fifo_burst;
 155 #define REG_RD_ADDR_marb_bar_rw_sclr_fifo_burst 284
 156 #define REG_WR_ADDR_marb_bar_rw_sclr_fifo_burst 284
 157
 158 /* Register rw_l2cache_burst, scope marb_bar, type rw */
 159 typedef struct {
 160   unsigned int ddr2_bsize : 2;
 161   unsigned int dummy1     : 30;
 162 } reg_marb_bar_rw_l2cache_burst;
 163 #define REG_RD_ADDR_marb_bar_rw_l2cache_burst 288
 164 #define REG_WR_ADDR_marb_bar_rw_l2cache_burst 288
 165
 166 /* Register rw_intr_mask, scope marb_bar, type rw */
 167 typedef struct {
 168   unsigned int bp0 : 1;
 169   unsigned int bp1 : 1;
 170   unsigned int bp2 : 1;
 171   unsigned int bp3 : 1;
 172   unsigned int dummy1 : 28;
 173 } reg_marb_bar_rw_intr_mask;
 174 #define REG_RD_ADDR_marb_bar_rw_intr_mask 292
 175 #define REG_WR_ADDR_marb_bar_rw_intr_mask 292
 176
 177 /* Register rw_ack_intr, scope marb_bar, type rw */
 178 typedef struct {
 179   unsigned int bp0 : 1;
 180   unsigned int bp1 : 1;
 181   unsigned int bp2 : 1;
 182   unsigned int bp3 : 1;
 183   unsigned int dummy1 : 28;
 184 } reg_marb_bar_rw_ack_intr;
 185 #define REG_RD_ADDR_marb_bar_rw_ack_intr 296
 186 #define REG_WR_ADDR_marb_bar_rw_ack_intr 296
 187
 188 /* Register r_intr, scope marb_bar, type r */
 189 typedef struct {
 190   unsigned int bp0 : 1;
 191   unsigned int bp1 : 1;
 192   unsigned int bp2 : 1;
 193   unsigned int bp3 : 1;
 194   unsigned int dummy1 : 28;
 195 } reg_marb_bar_r_intr;
 196 #define REG_RD_ADDR_marb_bar_r_intr 300
 197
 198 /* Register r_masked_intr, scope marb_bar, type r */
 199 typedef struct {
 200   unsigned int bp0 : 1;
 201   unsigned int bp1 : 1;
 202   unsigned int bp2 : 1;
 203   unsigned int bp3 : 1;
 204   unsigned int dummy1 : 28;
 205 } reg_marb_bar_r_masked_intr;
 206 #define REG_RD_ADDR_marb_bar_r_masked_intr 304
 207
 208 /* Register rw_stop_mask, scope marb_bar, type rw */
 209 typedef struct {
 210   unsigned int h264_rd   : 1;
 211   unsigned int h264_wr   : 1;
 212   unsigned int ccd       : 1;
 213   unsigned int vin_wr    : 1;
 214   unsigned int vin_rd    : 1;
 215   unsigned int sclr_rd   : 1;
 216   unsigned int vout      : 1;
 217   unsigned int sclr_fifo : 1;
 218   unsigned int l2cache   : 1;
 219   unsigned int dummy1    : 23;
 220 } reg_marb_bar_rw_stop_mask;
 221 #define REG_RD_ADDR_marb_bar_rw_stop_mask 308
 222 #define REG_WR_ADDR_marb_bar_rw_stop_mask 308
 223
 224 /* Register r_stopped, scope marb_bar, type r */
 225 typedef struct {
 226   unsigned int h264_rd   : 1;
 227   unsigned int h264_wr   : 1;
 228   unsigned int ccd       : 1;
 229   unsigned int vin_wr    : 1;
 230   unsigned int vin_rd    : 1;
 231   unsigned int sclr_rd   : 1;
 232   unsigned int vout      : 1;
 233   unsigned int sclr_fifo : 1;
 234   unsigned int l2cache   : 1;
 235   unsigned int dummy1    : 23;
 236 } reg_marb_bar_r_stopped;
 237 #define REG_RD_ADDR_marb_bar_r_stopped 312
 238
 239 /* Register rw_no_snoop, scope marb_bar, type rw */
 240 typedef struct {
 241   unsigned int h264_rd   : 1;
 242   unsigned int h264_wr   : 1;
 243   unsigned int ccd       : 1;
 244   unsigned int vin_wr    : 1;
 245   unsigned int vin_rd    : 1;
 246   unsigned int sclr_rd   : 1;
 247   unsigned int vout      : 1;
 248   unsigned int sclr_fifo : 1;
 249   unsigned int l2cache   : 1;
 250   unsigned int dummy1    : 23;
 251 } reg_marb_bar_rw_no_snoop;
 252 #define REG_RD_ADDR_marb_bar_rw_no_snoop 576
 253 #define REG_WR_ADDR_marb_bar_rw_no_snoop 576
 254
 255
 256 /* Constants */
 257 enum {
 258   regk_marb_bar_ccd                        = 0x00000002,
 259   regk_marb_bar_h264_rd                    = 0x00000000,
 260   regk_marb_bar_h264_wr                    = 0x00000001,
 261   regk_marb_bar_l2cache                    = 0x00000008,
 262   regk_marb_bar_no                         = 0x00000000,
 263   regk_marb_bar_r_stopped_default          = 0x00000000,
 264   regk_marb_bar_rw_ccd_burst_default       = 0x00000000,
 265   regk_marb_bar_rw_ddr2_slots_default      = 0x00000000,
 266   regk_marb_bar_rw_ddr2_slots_size         = 0x00000040,
 267   regk_marb_bar_rw_h264_rd_burst_default   = 0x00000000,
 268   regk_marb_bar_rw_h264_wr_burst_default   = 0x00000000,
 269   regk_marb_bar_rw_intr_mask_default       = 0x00000000,
 270   regk_marb_bar_rw_l2cache_burst_default   = 0x00000000,
 271   regk_marb_bar_rw_no_snoop_default        = 0x00000000,
 272   regk_marb_bar_rw_sclr_fifo_burst_default = 0x00000000,
 273   regk_marb_bar_rw_sclr_rd_burst_default   = 0x00000000,
 274   regk_marb_bar_rw_stop_mask_default       = 0x00000000,
 275   regk_marb_bar_rw_vin_rd_burst_default    = 0x00000000,
 276   regk_marb_bar_rw_vin_wr_burst_default    = 0x00000000,
 277   regk_marb_bar_rw_vout_burst_default      = 0x00000000,
 278   regk_marb_bar_sclr_fifo                  = 0x00000007,
 279   regk_marb_bar_sclr_rd                    = 0x00000005,
 280   regk_marb_bar_vin_rd                     = 0x00000004,
 281   regk_marb_bar_vin_wr                     = 0x00000003,
 282   regk_marb_bar_vout                       = 0x00000006,
 283   regk_marb_bar_yes                        = 0x00000001
 284 };
 285 #endif /* __marb_bar_defs_h */
 286 #ifndef __marb_bar_bp_defs_h
 287 #define __marb_bar_bp_defs_h
 288
 289 /*
 290  * This file is autogenerated from
 291  *   file:           marb_bar.r
 292  *
 293  *   by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r
 294  * Any changes here will be lost.
 295  *
 296  * -*- buffer-read-only: t -*-
 297  */
 298 /* Main access macros */
 299 #ifndef REG_RD
 300 #define REG_RD( scope, inst, reg ) \
 301   REG_READ( reg_##scope##_##reg, \
 302             (inst) + REG_RD_ADDR_##scope##_##reg )
 303 #endif
 304
 305 #ifndef REG_WR
 306 #define REG_WR( scope, inst, reg, val ) \
 307   REG_WRITE( reg_##scope##_##reg, \
 308              (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
 309 #endif
 310
 311 #ifndef REG_RD_VECT
 312 #define REG_RD_VECT( scope, inst, reg, index ) \
 313   REG_READ( reg_##scope##_##reg, \
 314             (inst) + REG_RD_ADDR_##scope##_##reg + \
 315             (index) * STRIDE_##scope##_##reg )
 316 #endif
 317
 318 #ifndef REG_WR_VECT
 319 #define REG_WR_VECT( scope, inst, reg, index, val ) \
 320   REG_WRITE( reg_##scope##_##reg, \
 321              (inst) + REG_WR_ADDR_##scope##_##reg + \
 322              (index) * STRIDE_##scope##_##reg, (val) )
 323 #endif
 324
 325 #ifndef REG_RD_INT
 326 #define REG_RD_INT( scope, inst, reg ) \
 327   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
 328 #endif
 329
 330 #ifndef REG_WR_INT
 331 #define REG_WR_INT( scope, inst, reg, val ) \
 332   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
 333 #endif
 334
 335 #ifndef REG_RD_INT_VECT
 336 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
 337   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
 338             (index) * STRIDE_##scope##_##reg )
 339 #endif
 340
 341 #ifndef REG_WR_INT_VECT
 342 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
 343   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
 344              (index) * STRIDE_##scope##_##reg, (val) )
 345 #endif
 346
 347 #ifndef REG_TYPE_CONV
 348 #define REG_TYPE_CONV( type, orgtype, val ) \
 349   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
 350 #endif
 351
 352 #ifndef reg_page_size
 353 #define reg_page_size 8192
 354 #endif
 355
 356 #ifndef REG_ADDR
 357 #define REG_ADDR( scope, inst, reg ) \
 358   ( (inst) + REG_RD_ADDR_##scope##_##reg )
 359 #endif
 360
 361 #ifndef REG_ADDR_VECT
 362 #define REG_ADDR_VECT( scope, inst, reg, index ) \
 363   ( (inst) + REG_RD_ADDR_##scope##_##reg + \
 364     (index) * STRIDE_##scope##_##reg )
 365 #endif
 366
 367 /* C-code for register scope marb_bar_bp */
 368
 369 /* Register rw_first_addr, scope marb_bar_bp, type rw */
 370 typedef unsigned int reg_marb_bar_bp_rw_first_addr;
 371 #define REG_RD_ADDR_marb_bar_bp_rw_first_addr 0
 372 #define REG_WR_ADDR_marb_bar_bp_rw_first_addr 0
 373
 374 /* Register rw_last_addr, scope marb_bar_bp, type rw */
 375 typedef unsigned int reg_marb_bar_bp_rw_last_addr;
 376 #define REG_RD_ADDR_marb_bar_bp_rw_last_addr 4
 377 #define REG_WR_ADDR_marb_bar_bp_rw_last_addr 4
 378
 379 /* Register rw_op, scope marb_bar_bp, type rw */
 380 typedef struct {
 381   unsigned int rd         : 1;
 382   unsigned int wr         : 1;
 383   unsigned int rd_excl    : 1;
 384   unsigned int pri_wr     : 1;
 385   unsigned int us_rd      : 1;
 386   unsigned int us_wr      : 1;
 387   unsigned int us_rd_excl : 1;
 388   unsigned int us_pri_wr  : 1;
 389   unsigned int dummy1     : 24;
 390 } reg_marb_bar_bp_rw_op;
 391 #define REG_RD_ADDR_marb_bar_bp_rw_op 8
 392 #define REG_WR_ADDR_marb_bar_bp_rw_op 8
 393
 394 /* Register rw_clients, scope marb_bar_bp, type rw */
 395 typedef struct {
 396   unsigned int h264_rd   : 1;
 397   unsigned int h264_wr   : 1;
 398   unsigned int ccd       : 1;
 399   unsigned int vin_wr    : 1;
 400   unsigned int vin_rd    : 1;
 401   unsigned int sclr_rd   : 1;
 402   unsigned int vout      : 1;
 403   unsigned int sclr_fifo : 1;
 404   unsigned int l2cache   : 1;
 405   unsigned int dummy1    : 23;
 406 } reg_marb_bar_bp_rw_clients;
 407 #define REG_RD_ADDR_marb_bar_bp_rw_clients 12
 408 #define REG_WR_ADDR_marb_bar_bp_rw_clients 12
 409
 410 /* Register rw_options, scope marb_bar_bp, type rw */
 411 typedef struct {
 412   unsigned int wrap : 1;
 413   unsigned int dummy1 : 31;
 414 } reg_marb_bar_bp_rw_options;
 415 #define REG_RD_ADDR_marb_bar_bp_rw_options 16
 416 #define REG_WR_ADDR_marb_bar_bp_rw_options 16
 417
 418 /* Register r_brk_addr, scope marb_bar_bp, type r */
 419 typedef unsigned int reg_marb_bar_bp_r_brk_addr;
 420 #define REG_RD_ADDR_marb_bar_bp_r_brk_addr 20
 421
 422 /* Register r_brk_op, scope marb_bar_bp, type r */
 423 typedef struct {
 424   unsigned int rd         : 1;
 425   unsigned int wr         : 1;
 426   unsigned int rd_excl    : 1;
 427   unsigned int pri_wr     : 1;
 428   unsigned int us_rd      : 1;
 429   unsigned int us_wr      : 1;
 430   unsigned int us_rd_excl : 1;
 431   unsigned int us_pri_wr  : 1;
 432   unsigned int dummy1     : 24;
 433 } reg_marb_bar_bp_r_brk_op;
 434 #define REG_RD_ADDR_marb_bar_bp_r_brk_op 24
 435
 436 /* Register r_brk_clients, scope marb_bar_bp, type r */
 437 typedef struct {
 438   unsigned int h264_rd   : 1;
 439   unsigned int h264_wr   : 1;
 440   unsigned int ccd       : 1;
 441   unsigned int vin_wr    : 1;
 442   unsigned int vin_rd    : 1;
 443   unsigned int sclr_rd   : 1;
 444   unsigned int vout      : 1;
 445   unsigned int sclr_fifo : 1;
 446   unsigned int l2cache   : 1;
 447   unsigned int dummy1    : 23;
 448 } reg_marb_bar_bp_r_brk_clients;
 449 #define REG_RD_ADDR_marb_bar_bp_r_brk_clients 28
 450
 451 /* Register r_brk_first_client, scope marb_bar_bp, type r */
 452 typedef struct {
 453   unsigned int h264_rd   : 1;
 454   unsigned int h264_wr   : 1;
 455   unsigned int ccd       : 1;
 456   unsigned int vin_wr    : 1;
 457   unsigned int vin_rd    : 1;
 458   unsigned int sclr_rd   : 1;
 459   unsigned int vout      : 1;
 460   unsigned int sclr_fifo : 1;
 461   unsigned int l2cache   : 1;
 462   unsigned int dummy1    : 23;
 463 } reg_marb_bar_bp_r_brk_first_client;
 464 #define REG_RD_ADDR_marb_bar_bp_r_brk_first_client 32
 465
 466 /* Register r_brk_size, scope marb_bar_bp, type r */
 467 typedef unsigned int reg_marb_bar_bp_r_brk_size;
 468 #define REG_RD_ADDR_marb_bar_bp_r_brk_size 36
 469
 470 /* Register rw_ack, scope marb_bar_bp, type rw */
 471 typedef unsigned int reg_marb_bar_bp_rw_ack;
 472 #define REG_RD_ADDR_marb_bar_bp_rw_ack 40
 473 #define REG_WR_ADDR_marb_bar_bp_rw_ack 40
 474
 475
 476 /* Constants */
 477 enum {
 478   regk_marb_bar_bp_no                      = 0x00000000,
 479   regk_marb_bar_bp_rw_op_default           = 0x00000000,
 480   regk_marb_bar_bp_rw_options_default      = 0x00000000,
 481   regk_marb_bar_bp_yes                     = 0x00000001
 482 };
 483 #endif /* __marb_bar_bp_defs_h */