drivers/ata/pata_optidma.c

   1 /*
   2  * pata_optidma.c       - Opti DMA PATA for new ATA layer
   3  *                        (C) 2006 Red Hat Inc
   4  *                        Alan Cox <alan@redhat.com>
   5  *
   6  *      The Opti DMA controllers are related to the older PIO PCI controllers
   7  *      and indeed the VLB ones. The main differences are that the timing
   8  *      numbers are now based off PCI clocks not VLB and differ, and that
   9  *      MWDMA is supported.
  10  *
  11  *      This driver should support Viper-N+, FireStar, FireStar Plus.
  12  *
  13  *      These devices support virtual DMA for read (aka the CS5520). Later
  14  *      chips support UDMA33, but only if the rest of the board logic does,
  15  *      so you have to get this right. We don't support the virtual DMA
  16  *      but we do handle UDMA.
  17  *
  18  *      Bits that are worth knowing
  19  *              Most control registers are shadowed into I/O registers
  20  *              0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
  21  *              Virtual DMA registers *move* between rev 0x02 and rev 0x10
  22  *              UDMA requires a 66MHz FSB
  23  *
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include <linux/init.h>
  30 #include <linux/blkdev.h>
  31 #include <linux/delay.h>
  32 #include <scsi/scsi_host.h>
  33 #include <linux/libata.h>
  34
  35 #define DRV_NAME "pata_optidma"
  36 #define DRV_VERSION "0.3.2"
  37
  38 enum {
  39         READ_REG        = 0,    /* index of Read cycle timing register */
  40         WRITE_REG       = 1,    /* index of Write cycle timing register */
  41         CNTRL_REG       = 3,    /* index of Control register */
  42         STRAP_REG       = 5,    /* index of Strap register */
  43         MISC_REG        = 6     /* index of Miscellaneous register */
  44 };
  45
  46 static int pci_clock;   /* 0 = 33 1 = 25 */
  47
  48 /**
  49  *      optidma_pre_reset               -       probe begin
  50  *      @link: ATA link
  51  *      @deadline: deadline jiffies for the operation
  52  *
  53  *      Set up cable type and use generic probe init
  54  */
  55
  56 static int optidma_pre_reset(struct ata_link *link, unsigned long deadline)
  57 {
  58         struct ata_port *ap = link->ap;
  59         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  60         static const struct pci_bits optidma_enable_bits = {
  61                 0x40, 1, 0x08, 0x00
  62         };
  63
  64         if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits))
  65                 return -ENOENT;
  66
  67         return ata_sff_prereset(link, deadline);
  68 }
  69
  70 /**
  71  *      optidma_unlock          -       unlock control registers
  72  *      @ap: ATA port
  73  *
  74  *      Unlock the control register block for this adapter. Registers must not
  75  *      be unlocked in a situation where libata might look at them.
  76  */
  77
  78 static void optidma_unlock(struct ata_port *ap)
  79 {
  80         void __iomem *regio = ap->ioaddr.cmd_addr;
  81
  82         /* These 3 unlock the control register access */
  83         ioread16(regio + 1);
  84         ioread16(regio + 1);
  85         iowrite8(3, regio + 2);
  86 }
  87
  88 /**
  89  *      optidma_lock            -       issue temporary relock
  90  *      @ap: ATA port
  91  *
  92  *      Re-lock the configuration register settings.
  93  */
  94
  95 static void optidma_lock(struct ata_port *ap)
  96 {
  97         void __iomem *regio = ap->ioaddr.cmd_addr;
  98
  99         /* Relock */
 100         iowrite8(0x83, regio + 2);
 101 }
 102
 103 /**
 104  *      optidma_mode_setup      -       set mode data
 105  *      @ap: ATA interface
 106  *      @adev: ATA device
 107  *      @mode: Mode to set
 108  *
 109  *      Called to do the DMA or PIO mode setup. Timing numbers are all
 110  *      pre computed to keep the code clean. There are two tables depending
 111  *      on the hardware clock speed.
 112  *
 113  *      WARNING: While we do this the IDE registers vanish. If we take an
 114  *      IRQ here we depend on the host set locking to avoid catastrophe.
 115  */
 116
 117 static void optidma_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
 118 {
 119         struct ata_device *pair = ata_dev_pair(adev);
 120         int pio = adev->pio_mode - XFER_PIO_0;
 121         int dma = adev->dma_mode - XFER_MW_DMA_0;
 122         void __iomem *regio = ap->ioaddr.cmd_addr;
 123         u8 addr;
 124
 125         /* Address table precomputed with a DCLK of 2 */
 126         static const u8 addr_timing[2][5] = {
 127                 { 0x30, 0x20, 0x20, 0x10, 0x10 },
 128                 { 0x20, 0x20, 0x10, 0x10, 0x10 }
 129         };
 130         static const u8 data_rec_timing[2][5] = {
 131                 { 0x59, 0x46, 0x30, 0x20, 0x20 },
 132                 { 0x46, 0x32, 0x20, 0x20, 0x10 }
 133         };
 134         static const u8 dma_data_rec_timing[2][3] = {
 135                 { 0x76, 0x20, 0x20 },
 136                 { 0x54, 0x20, 0x10 }
 137         };
 138
 139         /* Switch from IDE to control mode */
 140         optidma_unlock(ap);
 141
 142
 143         /*
 144          *      As with many controllers the address setup time is shared
 145          *      and must suit both devices if present. FIXME: Check if we
 146          *      need to look at slowest of PIO/DMA mode of either device
 147          */
 148
 149         if (mode >= XFER_MW_DMA_0)
 150                 addr = 0;
 151         else
 152                 addr = addr_timing[pci_clock][pio];
 153
 154         if (pair) {
 155                 u8 pair_addr;
 156                 /* Hardware constraint */
 157                 if (pair->dma_mode)
 158                         pair_addr = 0;
 159                 else
 160                         pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0];
 161                 if (pair_addr > addr)
 162                         addr = pair_addr;
 163         }
 164
 165         /* Commence primary programming sequence */
 166         /* First we load the device number into the timing select */
 167         iowrite8(adev->devno, regio + MISC_REG);
 168         /* Now we load the data timings into read data/write data */
 169         if (mode < XFER_MW_DMA_0) {
 170                 iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG);
 171                 iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
 172         } else if (mode < XFER_UDMA_0) {
 173                 iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
 174                 iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
 175         }
 176         /* Finally we load the address setup into the misc register */
 177         iowrite8(addr | adev->devno, regio + MISC_REG);
 178
 179         /* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */
 180         iowrite8(0x85, regio + CNTRL_REG);
 181
 182         /* Switch back to IDE mode */
 183         optidma_lock(ap);
 184
 185         /* Note: at this point our programming is incomplete. We are
 186            not supposed to program PCI 0x43 "things we hacked onto the chip"
 187            until we've done both sets of PIO/DMA timings */
 188 }
 189
 190 /**
 191  *      optiplus_mode_setup     -       DMA setup for Firestar Plus
 192  *      @ap: ATA port
 193  *      @adev: device
 194  *      @mode: desired mode
 195  *
 196  *      The Firestar plus has additional UDMA functionality for UDMA0-2 and
 197  *      requires we do some additional work. Because the base work we must do
 198  *      is mostly shared we wrap the Firestar setup functionality in this
 199  *      one
 200  */
 201
 202 static void optiplus_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
 203 {
 204         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 205         u8 udcfg;
 206         u8 udslave;
 207         int dev2 = 2 * adev->devno;
 208         int unit = 2 * ap->port_no + adev->devno;
 209         int udma = mode - XFER_UDMA_0;
 210
 211         pci_read_config_byte(pdev, 0x44, &udcfg);
 212         if (mode <= XFER_UDMA_0) {
 213                 udcfg &= ~(1 << unit);
 214                 optidma_mode_setup(ap, adev, adev->dma_mode);
 215         } else {
 216                 udcfg |=  (1 << unit);
 217                 if (ap->port_no) {
 218                         pci_read_config_byte(pdev, 0x45, &udslave);
 219                         udslave &= ~(0x03 << dev2);
 220                         udslave |= (udma << dev2);
 221                         pci_write_config_byte(pdev, 0x45, udslave);
 222                 } else {
 223                         udcfg &= ~(0x30 << dev2);
 224                         udcfg |= (udma << dev2);
 225                 }
 226         }
 227         pci_write_config_byte(pdev, 0x44, udcfg);
 228 }
 229
 230 /**
 231  *      optidma_set_pio_mode    -       PIO setup callback
 232  *      @ap: ATA port
 233  *      @adev: Device
 234  *
 235  *      The libata core provides separate functions for handling PIO and
 236  *      DMA programming. The architecture of the Firestar makes it easier
 237  *      for us to have a common function so we provide wrappers
 238  */
 239
 240 static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
 241 {
 242         optidma_mode_setup(ap, adev, adev->pio_mode);
 243 }
 244
 245 /**
 246  *      optidma_set_dma_mode    -       DMA setup callback
 247  *      @ap: ATA port
 248  *      @adev: Device
 249  *
 250  *      The libata core provides separate functions for handling PIO and
 251  *      DMA programming. The architecture of the Firestar makes it easier
 252  *      for us to have a common function so we provide wrappers
 253  */
 254
 255 static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
 256 {
 257         optidma_mode_setup(ap, adev, adev->dma_mode);
 258 }
 259
 260 /**
 261  *      optiplus_set_pio_mode   -       PIO setup callback
 262  *      @ap: ATA port
 263  *      @adev: Device
 264  *
 265  *      The libata core provides separate functions for handling PIO and
 266  *      DMA programming. The architecture of the Firestar makes it easier
 267  *      for us to have a common function so we provide wrappers
 268  */
 269
 270 static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
 271 {
 272         optiplus_mode_setup(ap, adev, adev->pio_mode);
 273 }
 274
 275 /**
 276  *      optiplus_set_dma_mode   -       DMA setup callback
 277  *      @ap: ATA port
 278  *      @adev: Device
 279  *
 280  *      The libata core provides separate functions for handling PIO and
 281  *      DMA programming. The architecture of the Firestar makes it easier
 282  *      for us to have a common function so we provide wrappers
 283  */
 284
 285 static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
 286 {
 287         optiplus_mode_setup(ap, adev, adev->dma_mode);
 288 }
 289
 290 /**
 291  *      optidma_make_bits       -       PCI setup helper
 292  *      @adev: ATA device
 293  *
 294  *      Turn the ATA device setup into PCI configuration bits
 295  *      for register 0x43 and return the two bits needed.
 296  */
 297
 298 static u8 optidma_make_bits43(struct ata_device *adev)
 299 {
 300         static const u8 bits43[5] = {
 301                 0, 0, 0, 1, 2
 302         };
 303         if (!ata_dev_enabled(adev))
 304                 return 0;
 305         if (adev->dma_mode)
 306                 return adev->dma_mode - XFER_MW_DMA_0;
 307         return bits43[adev->pio_mode - XFER_PIO_0];
 308 }
 309
 310 /**
 311  *      optidma_set_mode        -       mode setup
 312  *      @link: link to set up
 313  *
 314  *      Use the standard setup to tune the chipset and then finalise the
 315  *      configuration by writing the nibble of extra bits of data into
 316  *      the chip.
 317  */
 318
 319 static int optidma_set_mode(struct ata_link *link, struct ata_device **r_failed)
 320 {
 321         struct ata_port *ap = link->ap;
 322         u8 r;
 323         int nybble = 4 * ap->port_no;
 324         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 325         int rc  = ata_do_set_mode(link, r_failed);
 326         if (rc == 0) {
 327                 pci_read_config_byte(pdev, 0x43, &r);
 328
 329                 r &= (0x0F << nybble);
 330                 r |= (optidma_make_bits43(&link->device[0]) +
 331                      (optidma_make_bits43(&link->device[0]) << 2)) << nybble;
 332                 pci_write_config_byte(pdev, 0x43, r);
 333         }
 334         return rc;
 335 }
 336
 337 static struct scsi_host_template optidma_sht = {
 338         ATA_BMDMA_SHT(DRV_NAME),
 339 };
 340
 341 static struct ata_port_operations optidma_port_ops = {
 342         .inherits       = &ata_bmdma_port_ops,
 343         .cable_detect   = ata_cable_40wire,
 344         .set_piomode    = optidma_set_pio_mode,
 345         .set_dmamode    = optidma_set_dma_mode,
 346         .set_mode       = optidma_set_mode,
 347         .prereset       = optidma_pre_reset,
 348 };
 349
 350 static struct ata_port_operations optiplus_port_ops = {
 351         .inherits       = &optidma_port_ops,
 352         .set_piomode    = optiplus_set_pio_mode,
 353         .set_dmamode    = optiplus_set_dma_mode,
 354 };
 355
 356 /**
 357  *      optiplus_with_udma      -       Look for UDMA capable setup
 358  *      @pdev; ATA controller
 359  */
 360
 361 static int optiplus_with_udma(struct pci_dev *pdev)
 362 {
 363         u8 r;
 364         int ret = 0;
 365         int ioport = 0x22;
 366         struct pci_dev *dev1;
 367
 368         /* Find function 1 */
 369         dev1 = pci_get_device(0x1045, 0xC701, NULL);
 370         if (dev1 == NULL)
 371                 return 0;
 372
 373         /* Rev must be >= 0x10 */
 374         pci_read_config_byte(dev1, 0x08, &r);
 375         if (r < 0x10)
 376                 goto done_nomsg;
 377         /* Read the chipset system configuration to check our mode */
 378         pci_read_config_byte(dev1, 0x5F, &r);
 379         ioport |= (r << 8);
 380         outb(0x10, ioport);
 381         /* Must be 66Mhz sync */
 382         if ((inb(ioport + 2) & 1) == 0)
 383                 goto done;
 384
 385         /* Check the ATA arbitration/timing is suitable */
 386         pci_read_config_byte(pdev, 0x42, &r);
 387         if ((r & 0x36) != 0x36)
 388                 goto done;
 389         pci_read_config_byte(dev1, 0x52, &r);
 390         if (r & 0x80)   /* IDEDIR disabled */
 391                 ret = 1;
 392 done:
 393         printk(KERN_WARNING "UDMA not supported in this configuration.\n");
 394 done_nomsg:             /* Wrong chip revision */
 395         pci_dev_put(dev1);
 396         return ret;
 397 }
 398
 399 static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 400 {
 401         static const struct ata_port_info info_82c700 = {
 402                 .flags = ATA_FLAG_SLAVE_POSS,
 403                 .pio_mask = 0x1f,
 404                 .mwdma_mask = 0x07,
 405                 .port_ops = &optidma_port_ops
 406         };
 407         static const struct ata_port_info info_82c700_udma = {
 408                 .flags = ATA_FLAG_SLAVE_POSS,
 409                 .pio_mask = 0x1f,
 410                 .mwdma_mask = 0x07,
 411                 .udma_mask = 0x07,
 412                 .port_ops = &optiplus_port_ops
 413         };
 414         const struct ata_port_info *ppi[] = { &info_82c700, NULL };
 415         static int printed_version;
 416         int rc;
 417
 418         if (!printed_version++)
 419                 dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
 420
 421         rc = pcim_enable_device(dev);
 422         if (rc)
 423                 return rc;
 424
 425         /* Fixed location chipset magic */
 426         inw(0x1F1);
 427         inw(0x1F1);
 428         pci_clock = inb(0x1F5) & 1;             /* 0 = 33Mhz, 1 = 25Mhz */
 429
 430         if (optiplus_with_udma(dev))
 431                 ppi[0] = &info_82c700_udma;
 432
 433         return ata_pci_sff_init_one(dev, ppi, &optidma_sht, NULL);
 434 }
 435
 436 static const struct pci_device_id optidma[] = {
 437         { PCI_VDEVICE(OPTI, 0xD568), },         /* Opti 82C700 */
 438
 439         { },
 440 };
 441
 442 static struct pci_driver optidma_pci_driver = {
 443         .name           = DRV_NAME,
 444         .id_table       = optidma,
 445         .probe          = optidma_init_one,
 446         .remove         = ata_pci_remove_one,
 447 #ifdef CONFIG_PM
 448         .suspend        = ata_pci_device_suspend,
 449         .resume         = ata_pci_device_resume,
 450 #endif
 451 };
 452
 453 static int __init optidma_init(void)
 454 {
 455         return pci_register_driver(&optidma_pci_driver);
 456 }
 457
 458 static void __exit optidma_exit(void)
 459 {
 460         pci_unregister_driver(&optidma_pci_driver);
 461 }
 462
 463 MODULE_AUTHOR("Alan Cox");
 464 MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus");
 465 MODULE_LICENSE("GPL");
 466 MODULE_DEVICE_TABLE(pci, optidma);
 467 MODULE_VERSION(DRV_VERSION);
 468
 469 module_init(optidma_init);
 470 module_exit(optidma_exit);