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proc: Fix proc_sys_prune_dcache to hold a sb reference
[cris-mirror.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_atombios.c
blob1cf78f4dd339f93ddd971088ec42a5146b9820fe
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/amdgpu_drm.h>
28 #include "amdgpu.h"
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_i2c.h"
31
32 #include "atom.h"
33 #include "atom-bits.h"
34 #include "atombios_encoders.h"
35 #include "bif/bif_4_1_d.h"
36
37 static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev,
38 ATOM_GPIO_I2C_ASSIGMENT *gpio,
39 u8 index)
40 {
41
42 }
43
44 static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
45 {
46 struct amdgpu_i2c_bus_rec i2c;
47
48 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
49
50 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex);
51 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex);
52 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex);
53 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex);
54 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex);
55 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex);
56 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex);
57 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex);
58 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
59 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
60 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
61 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
62 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
63 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
64 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
65 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
66
67 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
68 i2c.hw_capable = true;
69 else
70 i2c.hw_capable = false;
71
72 if (gpio->sucI2cId.ucAccess == 0xa0)
73 i2c.mm_i2c = true;
74 else
75 i2c.mm_i2c = false;
76
77 i2c.i2c_id = gpio->sucI2cId.ucAccess;
78
79 if (i2c.mask_clk_reg)
80 i2c.valid = true;
81 else
82 i2c.valid = false;
83
84 return i2c;
85 }
86
87 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
88 uint8_t id)
89 {
90 struct atom_context *ctx = adev->mode_info.atom_context;
91 ATOM_GPIO_I2C_ASSIGMENT *gpio;
92 struct amdgpu_i2c_bus_rec i2c;
93 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
94 struct _ATOM_GPIO_I2C_INFO *i2c_info;
95 uint16_t data_offset, size;
96 int i, num_indices;
97
98 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
99 i2c.valid = false;
100
101 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
102 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
103
104 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
105 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
106
107 gpio = &i2c_info->asGPIO_Info[0];
108 for (i = 0; i < num_indices; i++) {
109
110 amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
111
112 if (gpio->sucI2cId.ucAccess == id) {
113 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
114 break;
115 }
116 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
117 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
118 }
119 }
120
121 return i2c;
122 }
123
124 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev)
125 {
126 struct atom_context *ctx = adev->mode_info.atom_context;
127 ATOM_GPIO_I2C_ASSIGMENT *gpio;
128 struct amdgpu_i2c_bus_rec i2c;
129 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
130 struct _ATOM_GPIO_I2C_INFO *i2c_info;
131 uint16_t data_offset, size;
132 int i, num_indices;
133 char stmp[32];
134
135 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
136 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
137
138 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
139 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
140
141 gpio = &i2c_info->asGPIO_Info[0];
142 for (i = 0; i < num_indices; i++) {
143 amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
144
145 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
146
147 if (i2c.valid) {
148 sprintf(stmp, "0x%x", i2c.i2c_id);
149 adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp);
150 }
151 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
152 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
153 }
154 }
155 }
156
157 struct amdgpu_gpio_rec
158 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
159 u8 id)
160 {
161 struct atom_context *ctx = adev->mode_info.atom_context;
162 struct amdgpu_gpio_rec gpio;
163 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
164 struct _ATOM_GPIO_PIN_LUT *gpio_info;
165 ATOM_GPIO_PIN_ASSIGNMENT *pin;
166 u16 data_offset, size;
167 int i, num_indices;
168
169 memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec));
170 gpio.valid = false;
171
172 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
173 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
174
175 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
176 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
177
178 pin = gpio_info->asGPIO_Pin;
179 for (i = 0; i < num_indices; i++) {
180 if (id == pin->ucGPIO_ID) {
181 gpio.id = pin->ucGPIO_ID;
182 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex);
183 gpio.shift = pin->ucGpioPinBitShift;
184 gpio.mask = (1 << pin->ucGpioPinBitShift);
185 gpio.valid = true;
186 break;
187 }
188 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
189 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
190 }
191 }
192
193 return gpio;
194 }
195
196 static struct amdgpu_hpd
197 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev,
198 struct amdgpu_gpio_rec *gpio)
199 {
200 struct amdgpu_hpd hpd;
201 u32 reg;
202
203 memset(&hpd, 0, sizeof(struct amdgpu_hpd));
204
205 reg = amdgpu_display_hpd_get_gpio_reg(adev);
206
207 hpd.gpio = *gpio;
208 if (gpio->reg == reg) {
209 switch(gpio->mask) {
210 case (1 << 0):
211 hpd.hpd = AMDGPU_HPD_1;
212 break;
213 case (1 << 8):
214 hpd.hpd = AMDGPU_HPD_2;
215 break;
216 case (1 << 16):
217 hpd.hpd = AMDGPU_HPD_3;
218 break;
219 case (1 << 24):
220 hpd.hpd = AMDGPU_HPD_4;
221 break;
222 case (1 << 26):
223 hpd.hpd = AMDGPU_HPD_5;
224 break;
225 case (1 << 28):
226 hpd.hpd = AMDGPU_HPD_6;
227 break;
228 default:
229 hpd.hpd = AMDGPU_HPD_NONE;
230 break;
231 }
232 } else
233 hpd.hpd = AMDGPU_HPD_NONE;
234 return hpd;
235 }
236
237 static const int object_connector_convert[] = {
238 DRM_MODE_CONNECTOR_Unknown,
239 DRM_MODE_CONNECTOR_DVII,
240 DRM_MODE_CONNECTOR_DVII,
241 DRM_MODE_CONNECTOR_DVID,
242 DRM_MODE_CONNECTOR_DVID,
243 DRM_MODE_CONNECTOR_VGA,
244 DRM_MODE_CONNECTOR_Composite,
245 DRM_MODE_CONNECTOR_SVIDEO,
246 DRM_MODE_CONNECTOR_Unknown,
247 DRM_MODE_CONNECTOR_Unknown,
248 DRM_MODE_CONNECTOR_9PinDIN,
249 DRM_MODE_CONNECTOR_Unknown,
250 DRM_MODE_CONNECTOR_HDMIA,
251 DRM_MODE_CONNECTOR_HDMIB,
252 DRM_MODE_CONNECTOR_LVDS,
253 DRM_MODE_CONNECTOR_9PinDIN,
254 DRM_MODE_CONNECTOR_Unknown,
255 DRM_MODE_CONNECTOR_Unknown,
256 DRM_MODE_CONNECTOR_Unknown,
257 DRM_MODE_CONNECTOR_DisplayPort,
258 DRM_MODE_CONNECTOR_eDP,
259 DRM_MODE_CONNECTOR_Unknown
260 };
261
262 bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev)
263 {
264 struct amdgpu_mode_info *mode_info = &adev->mode_info;
265 struct atom_context *ctx = mode_info->atom_context;
266 int index = GetIndexIntoMasterTable(DATA, Object_Header);
267 u16 size, data_offset;
268 u8 frev, crev;
269 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
270 ATOM_OBJECT_HEADER *obj_header;
271
272 if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
273 return false;
274
275 if (crev < 2)
276 return false;
277
278 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
279 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
280 (ctx->bios + data_offset +
281 le16_to_cpu(obj_header->usDisplayPathTableOffset));
282
283 if (path_obj->ucNumOfDispPath)
284 return true;
285 else
286 return false;
287 }
288
289 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev)
290 {
291 struct amdgpu_mode_info *mode_info = &adev->mode_info;
292 struct atom_context *ctx = mode_info->atom_context;
293 int index = GetIndexIntoMasterTable(DATA, Object_Header);
294 u16 size, data_offset;
295 u8 frev, crev;
296 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
297 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
298 ATOM_OBJECT_TABLE *router_obj;
299 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
300 ATOM_OBJECT_HEADER *obj_header;
301 int i, j, k, path_size, device_support;
302 int connector_type;
303 u16 conn_id, connector_object_id;
304 struct amdgpu_i2c_bus_rec ddc_bus;
305 struct amdgpu_router router;
306 struct amdgpu_gpio_rec gpio;
307 struct amdgpu_hpd hpd;
308
309 if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
310 return false;
311
312 if (crev < 2)
313 return false;
314
315 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
316 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
317 (ctx->bios + data_offset +
318 le16_to_cpu(obj_header->usDisplayPathTableOffset));
319 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
320 (ctx->bios + data_offset +
321 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
322 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
323 (ctx->bios + data_offset +
324 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
325 router_obj = (ATOM_OBJECT_TABLE *)
326 (ctx->bios + data_offset +
327 le16_to_cpu(obj_header->usRouterObjectTableOffset));
328 device_support = le16_to_cpu(obj_header->usDeviceSupport);
329
330 path_size = 0;
331 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
332 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
333 ATOM_DISPLAY_OBJECT_PATH *path;
334 addr += path_size;
335 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
336 path_size += le16_to_cpu(path->usSize);
337
338 if (device_support & le16_to_cpu(path->usDeviceTag)) {
339 uint8_t con_obj_id, con_obj_num, con_obj_type;
340
341 con_obj_id =
342 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
343 >> OBJECT_ID_SHIFT;
344 con_obj_num =
345 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
346 >> ENUM_ID_SHIFT;
347 con_obj_type =
348 (le16_to_cpu(path->usConnObjectId) &
349 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
350
351 /* Skip TV/CV support */
352 if ((le16_to_cpu(path->usDeviceTag) ==
353 ATOM_DEVICE_TV1_SUPPORT) ||
354 (le16_to_cpu(path->usDeviceTag) ==
355 ATOM_DEVICE_CV_SUPPORT))
356 continue;
357
358 if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) {
359 DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n",
360 con_obj_id, le16_to_cpu(path->usDeviceTag));
361 continue;
362 }
363
364 connector_type =
365 object_connector_convert[con_obj_id];
366 connector_object_id = con_obj_id;
367
368 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
369 continue;
370
371 router.ddc_valid = false;
372 router.cd_valid = false;
373 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
374 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
375
376 grph_obj_id =
377 (le16_to_cpu(path->usGraphicObjIds[j]) &
378 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
379 grph_obj_num =
380 (le16_to_cpu(path->usGraphicObjIds[j]) &
381 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
382 grph_obj_type =
383 (le16_to_cpu(path->usGraphicObjIds[j]) &
384 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
385
386 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
387 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
388 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
389 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
390 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
391 (ctx->bios + data_offset +
392 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
393 ATOM_ENCODER_CAP_RECORD *cap_record;
394 u16 caps = 0;
395
396 while (record->ucRecordSize > 0 &&
397 record->ucRecordType > 0 &&
398 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
399 switch (record->ucRecordType) {
400 case ATOM_ENCODER_CAP_RECORD_TYPE:
401 cap_record =(ATOM_ENCODER_CAP_RECORD *)
402 record;
403 caps = le16_to_cpu(cap_record->usEncoderCap);
404 break;
405 }
406 record = (ATOM_COMMON_RECORD_HEADER *)
407 ((char *)record + record->ucRecordSize);
408 }
409 amdgpu_display_add_encoder(adev, encoder_obj,
410 le16_to_cpu(path->usDeviceTag),
411 caps);
412 }
413 }
414 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
415 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
416 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
417 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
418 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
419 (ctx->bios + data_offset +
420 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
421 ATOM_I2C_RECORD *i2c_record;
422 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
423 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
424 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
425 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
426 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
427 (ctx->bios + data_offset +
428 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
429 u8 *num_dst_objs = (u8 *)
430 ((u8 *)router_src_dst_table + 1 +
431 (router_src_dst_table->ucNumberOfSrc * 2));
432 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
433 int enum_id;
434
435 router.router_id = router_obj_id;
436 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
437 if (le16_to_cpu(path->usConnObjectId) ==
438 le16_to_cpu(dst_objs[enum_id]))
439 break;
440 }
441
442 while (record->ucRecordSize > 0 &&
443 record->ucRecordType > 0 &&
444 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
445 switch (record->ucRecordType) {
446 case ATOM_I2C_RECORD_TYPE:
447 i2c_record =
448 (ATOM_I2C_RECORD *)
449 record;
450 i2c_config =
451 (ATOM_I2C_ID_CONFIG_ACCESS *)
452 &i2c_record->sucI2cId;
453 router.i2c_info =
454 amdgpu_atombios_lookup_i2c_gpio(adev,
455 i2c_config->
456 ucAccess);
457 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
458 break;
459 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
460 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
461 record;
462 router.ddc_valid = true;
463 router.ddc_mux_type = ddc_path->ucMuxType;
464 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
465 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
466 break;
467 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
468 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
469 record;
470 router.cd_valid = true;
471 router.cd_mux_type = cd_path->ucMuxType;
472 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
473 router.cd_mux_state = cd_path->ucMuxState[enum_id];
474 break;
475 }
476 record = (ATOM_COMMON_RECORD_HEADER *)
477 ((char *)record + record->ucRecordSize);
478 }
479 }
480 }
481 }
482 }
483
484 /* look up gpio for ddc, hpd */
485 ddc_bus.valid = false;
486 hpd.hpd = AMDGPU_HPD_NONE;
487 if ((le16_to_cpu(path->usDeviceTag) &
488 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
489 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
490 if (le16_to_cpu(path->usConnObjectId) ==
491 le16_to_cpu(con_obj->asObjects[j].
492 usObjectID)) {
493 ATOM_COMMON_RECORD_HEADER
494 *record =
495 (ATOM_COMMON_RECORD_HEADER
496 *)
497 (ctx->bios + data_offset +
498 le16_to_cpu(con_obj->
499 asObjects[j].
500 usRecordOffset));
501 ATOM_I2C_RECORD *i2c_record;
502 ATOM_HPD_INT_RECORD *hpd_record;
503 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
504
505 while (record->ucRecordSize > 0 &&
506 record->ucRecordType > 0 &&
507 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
508 switch (record->ucRecordType) {
509 case ATOM_I2C_RECORD_TYPE:
510 i2c_record =
511 (ATOM_I2C_RECORD *)
512 record;
513 i2c_config =
514 (ATOM_I2C_ID_CONFIG_ACCESS *)
515 &i2c_record->sucI2cId;
516 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev,
517 i2c_config->
518 ucAccess);
519 break;
520 case ATOM_HPD_INT_RECORD_TYPE:
521 hpd_record =
522 (ATOM_HPD_INT_RECORD *)
523 record;
524 gpio = amdgpu_atombios_lookup_gpio(adev,
525 hpd_record->ucHPDIntGPIOID);
526 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio);
527 hpd.plugged_state = hpd_record->ucPlugged_PinState;
528 break;
529 }
530 record =
531 (ATOM_COMMON_RECORD_HEADER
532 *) ((char *)record
533 +
534 record->
535 ucRecordSize);
536 }
537 break;
538 }
539 }
540 }
541
542 /* needed for aux chan transactions */
543 ddc_bus.hpd = hpd.hpd;
544
545 conn_id = le16_to_cpu(path->usConnObjectId);
546
547 amdgpu_display_add_connector(adev,
548 conn_id,
549 le16_to_cpu(path->usDeviceTag),
550 connector_type, &ddc_bus,
551 connector_object_id,
552 &hpd,
553 &router);
554
555 }
556 }
557
558 amdgpu_link_encoder_connector(adev->ddev);
559
560 return true;
561 }
562
563 union firmware_info {
564 ATOM_FIRMWARE_INFO info;
565 ATOM_FIRMWARE_INFO_V1_2 info_12;
566 ATOM_FIRMWARE_INFO_V1_3 info_13;
567 ATOM_FIRMWARE_INFO_V1_4 info_14;
568 ATOM_FIRMWARE_INFO_V2_1 info_21;
569 ATOM_FIRMWARE_INFO_V2_2 info_22;
570 };
571
572 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
573 {
574 struct amdgpu_mode_info *mode_info = &adev->mode_info;
575 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
576 uint8_t frev, crev;
577 uint16_t data_offset;
578 int ret = -EINVAL;
579
580 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
581 &frev, &crev, &data_offset)) {
582 int i;
583 struct amdgpu_pll *ppll = &adev->clock.ppll[0];
584 struct amdgpu_pll *spll = &adev->clock.spll;
585 struct amdgpu_pll *mpll = &adev->clock.mpll;
586 union firmware_info *firmware_info =
587 (union firmware_info *)(mode_info->atom_context->bios +
588 data_offset);
589 /* pixel clocks */
590 ppll->reference_freq =
591 le16_to_cpu(firmware_info->info.usReferenceClock);
592 ppll->reference_div = 0;
593
594 ppll->pll_out_min =
595 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
596 ppll->pll_out_max =
597 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
598
599 ppll->lcd_pll_out_min =
600 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
601 if (ppll->lcd_pll_out_min == 0)
602 ppll->lcd_pll_out_min = ppll->pll_out_min;
603 ppll->lcd_pll_out_max =
604 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
605 if (ppll->lcd_pll_out_max == 0)
606 ppll->lcd_pll_out_max = ppll->pll_out_max;
607
608 if (ppll->pll_out_min == 0)
609 ppll->pll_out_min = 64800;
610
611 ppll->pll_in_min =
612 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
613 ppll->pll_in_max =
614 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
615
616 ppll->min_post_div = 2;
617 ppll->max_post_div = 0x7f;
618 ppll->min_frac_feedback_div = 0;
619 ppll->max_frac_feedback_div = 9;
620 ppll->min_ref_div = 2;
621 ppll->max_ref_div = 0x3ff;
622 ppll->min_feedback_div = 4;
623 ppll->max_feedback_div = 0xfff;
624 ppll->best_vco = 0;
625
626 for (i = 1; i < AMDGPU_MAX_PPLL; i++)
627 adev->clock.ppll[i] = *ppll;
628
629 /* system clock */
630 spll->reference_freq =
631 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
632 spll->reference_div = 0;
633
634 spll->pll_out_min =
635 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
636 spll->pll_out_max =
637 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
638
639 /* ??? */
640 if (spll->pll_out_min == 0)
641 spll->pll_out_min = 64800;
642
643 spll->pll_in_min =
644 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
645 spll->pll_in_max =
646 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
647
648 spll->min_post_div = 1;
649 spll->max_post_div = 1;
650 spll->min_ref_div = 2;
651 spll->max_ref_div = 0xff;
652 spll->min_feedback_div = 4;
653 spll->max_feedback_div = 0xff;
654 spll->best_vco = 0;
655
656 /* memory clock */
657 mpll->reference_freq =
658 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
659 mpll->reference_div = 0;
660
661 mpll->pll_out_min =
662 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
663 mpll->pll_out_max =
664 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
665
666 /* ??? */
667 if (mpll->pll_out_min == 0)
668 mpll->pll_out_min = 64800;
669
670 mpll->pll_in_min =
671 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
672 mpll->pll_in_max =
673 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
674
675 adev->clock.default_sclk =
676 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
677 adev->clock.default_mclk =
678 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
679
680 mpll->min_post_div = 1;
681 mpll->max_post_div = 1;
682 mpll->min_ref_div = 2;
683 mpll->max_ref_div = 0xff;
684 mpll->min_feedback_div = 4;
685 mpll->max_feedback_div = 0xff;
686 mpll->best_vco = 0;
687
688 /* disp clock */
689 adev->clock.default_dispclk =
690 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
691 /* set a reasonable default for DP */
692 if (adev->clock.default_dispclk < 53900) {
693 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
694 adev->clock.default_dispclk / 100);
695 adev->clock.default_dispclk = 60000;
696 }
697 adev->clock.dp_extclk =
698 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
699 adev->clock.current_dispclk = adev->clock.default_dispclk;
700
701 adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
702 if (adev->clock.max_pixel_clock == 0)
703 adev->clock.max_pixel_clock = 40000;
704
705 /* not technically a clock, but... */
706 adev->mode_info.firmware_flags =
707 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
708
709 ret = 0;
710 }
711
712 adev->pm.current_sclk = adev->clock.default_sclk;
713 adev->pm.current_mclk = adev->clock.default_mclk;
714
715 return ret;
716 }
717
718 union gfx_info {
719 ATOM_GFX_INFO_V2_1 info;
720 };
721
722 int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev)
723 {
724 struct amdgpu_mode_info *mode_info = &adev->mode_info;
725 int index = GetIndexIntoMasterTable(DATA, GFX_Info);
726 uint8_t frev, crev;
727 uint16_t data_offset;
728 int ret = -EINVAL;
729
730 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
731 &frev, &crev, &data_offset)) {
732 union gfx_info *gfx_info = (union gfx_info *)
733 (mode_info->atom_context->bios + data_offset);
734
735 adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines;
736 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes;
737 adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh;
738 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se;
739 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se;
740 adev->gfx.config.max_texture_channel_caches =
741 gfx_info->info.max_texture_channel_caches;
742
743 ret = 0;
744 }
745 return ret;
746 }
747
748 union igp_info {
749 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
750 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
751 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
752 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
753 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
754 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
755 };
756
757 /*
758 * Return vram width from integrated system info table, if available,
759 * or 0 if not.
760 */
761 int amdgpu_atombios_get_vram_width(struct amdgpu_device *adev)
762 {
763 struct amdgpu_mode_info *mode_info = &adev->mode_info;
764 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
765 u16 data_offset, size;
766 union igp_info *igp_info;
767 u8 frev, crev;
768
769 /* get any igp specific overrides */
770 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
771 &frev, &crev, &data_offset)) {
772 igp_info = (union igp_info *)
773 (mode_info->atom_context->bios + data_offset);
774 switch (crev) {
775 case 8:
776 case 9:
777 return igp_info->info_8.ucUMAChannelNumber * 64;
778 default:
779 return 0;
780 }
781 }
782
783 return 0;
784 }
785
786 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev,
787 struct amdgpu_atom_ss *ss,
788 int id)
789 {
790 struct amdgpu_mode_info *mode_info = &adev->mode_info;
791 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
792 u16 data_offset, size;
793 union igp_info *igp_info;
794 u8 frev, crev;
795 u16 percentage = 0, rate = 0;
796
797 /* get any igp specific overrides */
798 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
799 &frev, &crev, &data_offset)) {
800 igp_info = (union igp_info *)
801 (mode_info->atom_context->bios + data_offset);
802 switch (crev) {
803 case 6:
804 switch (id) {
805 case ASIC_INTERNAL_SS_ON_TMDS:
806 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
807 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
808 break;
809 case ASIC_INTERNAL_SS_ON_HDMI:
810 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
811 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
812 break;
813 case ASIC_INTERNAL_SS_ON_LVDS:
814 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
815 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
816 break;
817 }
818 break;
819 case 7:
820 switch (id) {
821 case ASIC_INTERNAL_SS_ON_TMDS:
822 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
823 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
824 break;
825 case ASIC_INTERNAL_SS_ON_HDMI:
826 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
827 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
828 break;
829 case ASIC_INTERNAL_SS_ON_LVDS:
830 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
831 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
832 break;
833 }
834 break;
835 case 8:
836 switch (id) {
837 case ASIC_INTERNAL_SS_ON_TMDS:
838 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
839 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
840 break;
841 case ASIC_INTERNAL_SS_ON_HDMI:
842 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
843 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
844 break;
845 case ASIC_INTERNAL_SS_ON_LVDS:
846 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
847 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
848 break;
849 }
850 break;
851 case 9:
852 switch (id) {
853 case ASIC_INTERNAL_SS_ON_TMDS:
854 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage);
855 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz);
856 break;
857 case ASIC_INTERNAL_SS_ON_HDMI:
858 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage);
859 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz);
860 break;
861 case ASIC_INTERNAL_SS_ON_LVDS:
862 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage);
863 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz);
864 break;
865 }
866 break;
867 default:
868 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
869 break;
870 }
871 if (percentage)
872 ss->percentage = percentage;
873 if (rate)
874 ss->rate = rate;
875 }
876 }
877
878 union asic_ss_info {
879 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
880 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
881 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
882 };
883
884 union asic_ss_assignment {
885 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
886 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
887 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
888 };
889
890 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
891 struct amdgpu_atom_ss *ss,
892 int id, u32 clock)
893 {
894 struct amdgpu_mode_info *mode_info = &adev->mode_info;
895 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
896 uint16_t data_offset, size;
897 union asic_ss_info *ss_info;
898 union asic_ss_assignment *ss_assign;
899 uint8_t frev, crev;
900 int i, num_indices;
901
902 if (id == ASIC_INTERNAL_MEMORY_SS) {
903 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
904 return false;
905 }
906 if (id == ASIC_INTERNAL_ENGINE_SS) {
907 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
908 return false;
909 }
910
911 memset(ss, 0, sizeof(struct amdgpu_atom_ss));
912 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
913 &frev, &crev, &data_offset)) {
914
915 ss_info =
916 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
917
918 switch (frev) {
919 case 1:
920 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
921 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
922
923 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
924 for (i = 0; i < num_indices; i++) {
925 if ((ss_assign->v1.ucClockIndication == id) &&
926 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
927 ss->percentage =
928 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
929 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
930 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
931 ss->percentage_divider = 100;
932 return true;
933 }
934 ss_assign = (union asic_ss_assignment *)
935 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
936 }
937 break;
938 case 2:
939 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
940 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
941 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
942 for (i = 0; i < num_indices; i++) {
943 if ((ss_assign->v2.ucClockIndication == id) &&
944 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
945 ss->percentage =
946 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
947 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
948 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
949 ss->percentage_divider = 100;
950 if ((crev == 2) &&
951 ((id == ASIC_INTERNAL_ENGINE_SS) ||
952 (id == ASIC_INTERNAL_MEMORY_SS)))
953 ss->rate /= 100;
954 return true;
955 }
956 ss_assign = (union asic_ss_assignment *)
957 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
958 }
959 break;
960 case 3:
961 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
962 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
963 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
964 for (i = 0; i < num_indices; i++) {
965 if ((ss_assign->v3.ucClockIndication == id) &&
966 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
967 ss->percentage =
968 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
969 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
970 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
971 if (ss_assign->v3.ucSpreadSpectrumMode &
972 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
973 ss->percentage_divider = 1000;
974 else
975 ss->percentage_divider = 100;
976 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
977 (id == ASIC_INTERNAL_MEMORY_SS))
978 ss->rate /= 100;
979 if (adev->flags & AMD_IS_APU)
980 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id);
981 return true;
982 }
983 ss_assign = (union asic_ss_assignment *)
984 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
985 }
986 break;
987 default:
988 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
989 break;
990 }
991
992 }
993 return false;
994 }
995
996 union get_clock_dividers {
997 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
998 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
999 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
1000 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
1001 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
1002 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
1003 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
1004 };
1005
1006 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
1007 u8 clock_type,
1008 u32 clock,
1009 bool strobe_mode,
1010 struct atom_clock_dividers *dividers)
1011 {
1012 union get_clock_dividers args;
1013 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
1014 u8 frev, crev;
1015
1016 memset(&args, 0, sizeof(args));
1017 memset(dividers, 0, sizeof(struct atom_clock_dividers));
1018
1019 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1020 return -EINVAL;
1021
1022 switch (crev) {
1023 case 2:
1024 case 3:
1025 case 5:
1026 /* r6xx, r7xx, evergreen, ni, si.
1027 * TODO: add support for asic_type <= CHIP_RV770*/
1028 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
1029 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1030
1031 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1032
1033 dividers->post_div = args.v3.ucPostDiv;
1034 dividers->enable_post_div = (args.v3.ucCntlFlag &
1035 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
1036 dividers->enable_dithen = (args.v3.ucCntlFlag &
1037 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
1038 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
1039 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
1040 dividers->ref_div = args.v3.ucRefDiv;
1041 dividers->vco_mode = (args.v3.ucCntlFlag &
1042 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1043 } else {
1044 /* for SI we use ComputeMemoryClockParam for memory plls */
1045 if (adev->asic_type >= CHIP_TAHITI)
1046 return -EINVAL;
1047 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1048 if (strobe_mode)
1049 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
1050
1051 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1052
1053 dividers->post_div = args.v5.ucPostDiv;
1054 dividers->enable_post_div = (args.v5.ucCntlFlag &
1055 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
1056 dividers->enable_dithen = (args.v5.ucCntlFlag &
1057 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
1058 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
1059 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
1060 dividers->ref_div = args.v5.ucRefDiv;
1061 dividers->vco_mode = (args.v5.ucCntlFlag &
1062 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1063 }
1064 break;
1065 case 4:
1066 /* fusion */
1067 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
1068
1069 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1070
1071 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
1072 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
1073 break;
1074 case 6:
1075 /* CI */
1076 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
1077 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
1078 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
1079
1080 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1081
1082 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
1083 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
1084 dividers->ref_div = args.v6_out.ucPllRefDiv;
1085 dividers->post_div = args.v6_out.ucPllPostDiv;
1086 dividers->flags = args.v6_out.ucPllCntlFlag;
1087 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
1088 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
1089 break;
1090 default:
1091 return -EINVAL;
1092 }
1093 return 0;
1094 }
1095
1096 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
1097 u32 clock,
1098 bool strobe_mode,
1099 struct atom_mpll_param *mpll_param)
1100 {
1101 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
1102 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
1103 u8 frev, crev;
1104
1105 memset(&args, 0, sizeof(args));
1106 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
1107
1108 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1109 return -EINVAL;
1110
1111 switch (frev) {
1112 case 2:
1113 switch (crev) {
1114 case 1:
1115 /* SI */
1116 args.ulClock = cpu_to_le32(clock); /* 10 khz */
1117 args.ucInputFlag = 0;
1118 if (strobe_mode)
1119 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
1120
1121 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1122
1123 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
1124 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
1125 mpll_param->post_div = args.ucPostDiv;
1126 mpll_param->dll_speed = args.ucDllSpeed;
1127 mpll_param->bwcntl = args.ucBWCntl;
1128 mpll_param->vco_mode =
1129 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
1130 mpll_param->yclk_sel =
1131 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
1132 mpll_param->qdr =
1133 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
1134 mpll_param->half_rate =
1135 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
1136 break;
1137 default:
1138 return -EINVAL;
1139 }
1140 break;
1141 default:
1142 return -EINVAL;
1143 }
1144 return 0;
1145 }
1146
1147 void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
1148 u32 eng_clock, u32 mem_clock)
1149 {
1150 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1151 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
1152 u32 tmp;
1153
1154 memset(&args, 0, sizeof(args));
1155
1156 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
1157 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
1158
1159 args.ulTargetEngineClock = cpu_to_le32(tmp);
1160 if (mem_clock)
1161 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
1162
1163 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1164 }
1165
1166 void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev,
1167 u16 *vddc, u16 *vddci, u16 *mvdd)
1168 {
1169 struct amdgpu_mode_info *mode_info = &adev->mode_info;
1170 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1171 u8 frev, crev;
1172 u16 data_offset;
1173 union firmware_info *firmware_info;
1174
1175 *vddc = 0;
1176 *vddci = 0;
1177 *mvdd = 0;
1178
1179 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
1180 &frev, &crev, &data_offset)) {
1181 firmware_info =
1182 (union firmware_info *)(mode_info->atom_context->bios +
1183 data_offset);
1184 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
1185 if ((frev == 2) && (crev >= 2)) {
1186 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
1187 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
1188 }
1189 }
1190 }
1191
1192 union set_voltage {
1193 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
1194 struct _SET_VOLTAGE_PARAMETERS v1;
1195 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
1196 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
1197 };
1198
1199 int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,
1200 u16 voltage_id, u16 *voltage)
1201 {
1202 union set_voltage args;
1203 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1204 u8 frev, crev;
1205
1206 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1207 return -EINVAL;
1208
1209 switch (crev) {
1210 case 1:
1211 return -EINVAL;
1212 case 2:
1213 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
1214 args.v2.ucVoltageMode = 0;
1215 args.v2.usVoltageLevel = 0;
1216
1217 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1218
1219 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
1220 break;
1221 case 3:
1222 args.v3.ucVoltageType = voltage_type;
1223 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
1224 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
1225
1226 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1227
1228 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
1229 break;
1230 default:
1231 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1232 return -EINVAL;
1233 }
1234
1235 return 0;
1236 }
1237
1238 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev,
1239 u16 *voltage,
1240 u16 leakage_idx)
1241 {
1242 return amdgpu_atombios_get_max_vddc(adev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
1243 }
1244
1245 int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev,
1246 u16 *leakage_id)
1247 {
1248 union set_voltage args;
1249 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1250 u8 frev, crev;
1251
1252 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1253 return -EINVAL;
1254
1255 switch (crev) {
1256 case 3:
1257 case 4:
1258 args.v3.ucVoltageType = 0;
1259 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
1260 args.v3.usVoltageLevel = 0;
1261
1262 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1263
1264 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
1265 break;
1266 default:
1267 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1268 return -EINVAL;
1269 }
1270
1271 return 0;
1272 }
1273
1274 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev,
1275 u16 *vddc, u16 *vddci,
1276 u16 virtual_voltage_id,
1277 u16 vbios_voltage_id)
1278 {
1279 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
1280 u8 frev, crev;
1281 u16 data_offset, size;
1282 int i, j;
1283 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
1284 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
1285
1286 *vddc = 0;
1287 *vddci = 0;
1288
1289 if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1290 &frev, &crev, &data_offset))
1291 return -EINVAL;
1292
1293 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
1294 (adev->mode_info.atom_context->bios + data_offset);
1295
1296 switch (frev) {
1297 case 1:
1298 return -EINVAL;
1299 case 2:
1300 switch (crev) {
1301 case 1:
1302 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
1303 return -EINVAL;
1304 leakage_bin = (u16 *)
1305 (adev->mode_info.atom_context->bios + data_offset +
1306 le16_to_cpu(profile->usLeakageBinArrayOffset));
1307 vddc_id_buf = (u16 *)
1308 (adev->mode_info.atom_context->bios + data_offset +
1309 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
1310 vddc_buf = (u16 *)
1311 (adev->mode_info.atom_context->bios + data_offset +
1312 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
1313 vddci_id_buf = (u16 *)
1314 (adev->mode_info.atom_context->bios + data_offset +
1315 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
1316 vddci_buf = (u16 *)
1317 (adev->mode_info.atom_context->bios + data_offset +
1318 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
1319
1320 if (profile->ucElbVDDC_Num > 0) {
1321 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
1322 if (vddc_id_buf[i] == virtual_voltage_id) {
1323 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1324 if (vbios_voltage_id <= leakage_bin[j]) {
1325 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
1326 break;
1327 }
1328 }
1329 break;
1330 }
1331 }
1332 }
1333 if (profile->ucElbVDDCI_Num > 0) {
1334 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
1335 if (vddci_id_buf[i] == virtual_voltage_id) {
1336 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1337 if (vbios_voltage_id <= leakage_bin[j]) {
1338 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
1339 break;
1340 }
1341 }
1342 break;
1343 }
1344 }
1345 }
1346 break;
1347 default:
1348 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1349 return -EINVAL;
1350 }
1351 break;
1352 default:
1353 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1354 return -EINVAL;
1355 }
1356
1357 return 0;
1358 }
1359
1360 union get_voltage_info {
1361 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
1362 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
1363 };
1364
1365 int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev,
1366 u16 virtual_voltage_id,
1367 u16 *voltage)
1368 {
1369 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
1370 u32 entry_id;
1371 u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
1372 union get_voltage_info args;
1373
1374 for (entry_id = 0; entry_id < count; entry_id++) {
1375 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
1376 virtual_voltage_id)
1377 break;
1378 }
1379
1380 if (entry_id >= count)
1381 return -EINVAL;
1382
1383 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
1384 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
1385 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
1386 args.in.ulSCLKFreq =
1387 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
1388
1389 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1390
1391 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
1392
1393 return 0;
1394 }
1395
1396 union voltage_object_info {
1397 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
1398 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
1399 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
1400 };
1401
1402 union voltage_object {
1403 struct _ATOM_VOLTAGE_OBJECT v1;
1404 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
1405 union _ATOM_VOLTAGE_OBJECT_V3 v3;
1406 };
1407
1408
1409 static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
1410 u8 voltage_type, u8 voltage_mode)
1411 {
1412 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
1413 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
1414 u8 *start = (u8*)v3;
1415
1416 while (offset < size) {
1417 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
1418 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
1419 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
1420 return vo;
1421 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
1422 }
1423 return NULL;
1424 }
1425
1426 int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev,
1427 u8 voltage_type,
1428 u8 *svd_gpio_id, u8 *svc_gpio_id)
1429 {
1430 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1431 u8 frev, crev;
1432 u16 data_offset, size;
1433 union voltage_object_info *voltage_info;
1434 union voltage_object *voltage_object = NULL;
1435
1436 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1437 &frev, &crev, &data_offset)) {
1438 voltage_info = (union voltage_object_info *)
1439 (adev->mode_info.atom_context->bios + data_offset);
1440
1441 switch (frev) {
1442 case 3:
1443 switch (crev) {
1444 case 1:
1445 voltage_object = (union voltage_object *)
1446 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1447 voltage_type,
1448 VOLTAGE_OBJ_SVID2);
1449 if (voltage_object) {
1450 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
1451 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
1452 } else {
1453 return -EINVAL;
1454 }
1455 break;
1456 default:
1457 DRM_ERROR("unknown voltage object table\n");
1458 return -EINVAL;
1459 }
1460 break;
1461 default:
1462 DRM_ERROR("unknown voltage object table\n");
1463 return -EINVAL;
1464 }
1465
1466 }
1467 return 0;
1468 }
1469
1470 bool
1471 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
1472 u8 voltage_type, u8 voltage_mode)
1473 {
1474 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1475 u8 frev, crev;
1476 u16 data_offset, size;
1477 union voltage_object_info *voltage_info;
1478
1479 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1480 &frev, &crev, &data_offset)) {
1481 voltage_info = (union voltage_object_info *)
1482 (adev->mode_info.atom_context->bios + data_offset);
1483
1484 switch (frev) {
1485 case 3:
1486 switch (crev) {
1487 case 1:
1488 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1489 voltage_type, voltage_mode))
1490 return true;
1491 break;
1492 default:
1493 DRM_ERROR("unknown voltage object table\n");
1494 return false;
1495 }
1496 break;
1497 default:
1498 DRM_ERROR("unknown voltage object table\n");
1499 return false;
1500 }
1501
1502 }
1503 return false;
1504 }
1505
1506 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
1507 u8 voltage_type, u8 voltage_mode,
1508 struct atom_voltage_table *voltage_table)
1509 {
1510 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1511 u8 frev, crev;
1512 u16 data_offset, size;
1513 int i;
1514 union voltage_object_info *voltage_info;
1515 union voltage_object *voltage_object = NULL;
1516
1517 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1518 &frev, &crev, &data_offset)) {
1519 voltage_info = (union voltage_object_info *)
1520 (adev->mode_info.atom_context->bios + data_offset);
1521
1522 switch (frev) {
1523 case 3:
1524 switch (crev) {
1525 case 1:
1526 voltage_object = (union voltage_object *)
1527 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1528 voltage_type, voltage_mode);
1529 if (voltage_object) {
1530 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
1531 &voltage_object->v3.asGpioVoltageObj;
1532 VOLTAGE_LUT_ENTRY_V2 *lut;
1533 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
1534 return -EINVAL;
1535 lut = &gpio->asVolGpioLut[0];
1536 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
1537 voltage_table->entries[i].value =
1538 le16_to_cpu(lut->usVoltageValue);
1539 voltage_table->entries[i].smio_low =
1540 le32_to_cpu(lut->ulVoltageId);
1541 lut = (VOLTAGE_LUT_ENTRY_V2 *)
1542 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
1543 }
1544 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
1545 voltage_table->count = gpio->ucGpioEntryNum;
1546 voltage_table->phase_delay = gpio->ucPhaseDelay;
1547 return 0;
1548 }
1549 break;
1550 default:
1551 DRM_ERROR("unknown voltage object table\n");
1552 return -EINVAL;
1553 }
1554 break;
1555 default:
1556 DRM_ERROR("unknown voltage object table\n");
1557 return -EINVAL;
1558 }
1559 }
1560 return -EINVAL;
1561 }
1562
1563 union vram_info {
1564 struct _ATOM_VRAM_INFO_V3 v1_3;
1565 struct _ATOM_VRAM_INFO_V4 v1_4;
1566 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
1567 };
1568
1569 #define MEM_ID_MASK 0xff000000
1570 #define MEM_ID_SHIFT 24
1571 #define CLOCK_RANGE_MASK 0x00ffffff
1572 #define CLOCK_RANGE_SHIFT 0
1573 #define LOW_NIBBLE_MASK 0xf
1574 #define DATA_EQU_PREV 0
1575 #define DATA_FROM_TABLE 4
1576
1577 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
1578 u8 module_index,
1579 struct atom_mc_reg_table *reg_table)
1580 {
1581 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
1582 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
1583 u32 i = 0, j;
1584 u16 data_offset, size;
1585 union vram_info *vram_info;
1586
1587 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
1588
1589 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1590 &frev, &crev, &data_offset)) {
1591 vram_info = (union vram_info *)
1592 (adev->mode_info.atom_context->bios + data_offset);
1593 switch (frev) {
1594 case 1:
1595 DRM_ERROR("old table version %d, %d\n", frev, crev);
1596 return -EINVAL;
1597 case 2:
1598 switch (crev) {
1599 case 1:
1600 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
1601 ATOM_INIT_REG_BLOCK *reg_block =
1602 (ATOM_INIT_REG_BLOCK *)
1603 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
1604 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
1605 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1606 ((u8 *)reg_block + (2 * sizeof(u16)) +
1607 le16_to_cpu(reg_block->usRegIndexTblSize));
1608 ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
1609 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
1610 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
1611 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
1612 return -EINVAL;
1613 while (i < num_entries) {
1614 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
1615 break;
1616 reg_table->mc_reg_address[i].s1 =
1617 (u16)(le16_to_cpu(format->usRegIndex));
1618 reg_table->mc_reg_address[i].pre_reg_data =
1619 (u8)(format->ucPreRegDataLength);
1620 i++;
1621 format = (ATOM_INIT_REG_INDEX_FORMAT *)
1622 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
1623 }
1624 reg_table->last = i;
1625 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
1626 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
1627 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
1628 >> MEM_ID_SHIFT);
1629 if (module_index == t_mem_id) {
1630 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
1631 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
1632 >> CLOCK_RANGE_SHIFT);
1633 for (i = 0, j = 1; i < reg_table->last; i++) {
1634 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
1635 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1636 (u32)le32_to_cpu(*((u32 *)reg_data + j));
1637 j++;
1638 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
1639 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1640 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
1641 }
1642 }
1643 num_ranges++;
1644 }
1645 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1646 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
1647 }
1648 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
1649 return -EINVAL;
1650 reg_table->num_entries = num_ranges;
1651 } else
1652 return -EINVAL;
1653 break;
1654 default:
1655 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1656 return -EINVAL;
1657 }
1658 break;
1659 default:
1660 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1661 return -EINVAL;
1662 }
1663 return 0;
1664 }
1665 return -EINVAL;
1666 }
1667
1668 bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev)
1669 {
1670 int index = GetIndexIntoMasterTable(DATA, GPUVirtualizationInfo);
1671 u8 frev, crev;
1672 u16 data_offset, size;
1673
1674 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1675 &frev, &crev, &data_offset))
1676 return true;
1677
1678 return false;
1679 }
1680
1681 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock)
1682 {
1683 uint32_t bios_6_scratch;
1684
1685 bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
1686
1687 if (lock) {
1688 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1689 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
1690 } else {
1691 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1692 bios_6_scratch |= ATOM_S6_ACC_MODE;
1693 }
1694
1695 WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
1696 }
1697
1698 void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
1699 {
1700 uint32_t bios_2_scratch, bios_6_scratch;
1701
1702 bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);
1703 bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
1704
1705 /* let the bios control the backlight */
1706 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1707
1708 /* tell the bios not to handle mode switching */
1709 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
1710
1711 /* clear the vbios dpms state */
1712 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
1713
1714 WREG32(mmBIOS_SCRATCH_2, bios_2_scratch);
1715 WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
1716 }
1717
1718 void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev)
1719 {
1720 int i;
1721
1722 for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1723 adev->bios_scratch[i] = RREG32(mmBIOS_SCRATCH_0 + i);
1724 }
1725
1726 void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev)
1727 {
1728 int i;
1729
1730 /*
1731 * VBIOS will check ASIC_INIT_COMPLETE bit to decide if
1732 * execute ASIC_Init posting via driver
1733 */
1734 adev->bios_scratch[7] &= ~ATOM_S7_ASIC_INIT_COMPLETE_MASK;
1735
1736 for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1737 WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]);
1738 }
1739
1740 void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
1741 bool hung)
1742 {
1743 u32 tmp = RREG32(mmBIOS_SCRATCH_3);
1744
1745 if (hung)
1746 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1747 else
1748 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1749
1750 WREG32(mmBIOS_SCRATCH_3, tmp);
1751 }
1752
1753 /* Atom needs data in little endian format
1754 * so swap as appropriate when copying data to
1755 * or from atom. Note that atom operates on
1756 * dw units.
1757 */
1758 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
1759 {
1760 #ifdef __BIG_ENDIAN
1761 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
1762 u32 *dst32, *src32;
1763 int i;
1764
1765 memcpy(src_tmp, src, num_bytes);
1766 src32 = (u32 *)src_tmp;
1767 dst32 = (u32 *)dst_tmp;
1768 if (to_le) {
1769 for (i = 0; i < ((num_bytes + 3) / 4); i++)
1770 dst32[i] = cpu_to_le32(src32[i]);
1771 memcpy(dst, dst_tmp, num_bytes);
1772 } else {
1773 u8 dws = num_bytes & ~3;
1774 for (i = 0; i < ((num_bytes + 3) / 4); i++)
1775 dst32[i] = le32_to_cpu(src32[i]);
1776 memcpy(dst, dst_tmp, dws);
1777 if (num_bytes % 4) {
1778 for (i = 0; i < (num_bytes % 4); i++)
1779 dst[dws+i] = dst_tmp[dws+i];
1780 }
1781 }
1782 #else
1783 memcpy(dst, src, num_bytes);
1784 #endif
1785 }
1786
1787 int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev)
1788 {
1789 struct atom_context *ctx = adev->mode_info.atom_context;
1790 int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);
1791 uint16_t data_offset;
1792 int usage_bytes = 0;
1793 struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
1794
1795 if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
1796 firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
1797
1798 DRM_DEBUG("atom firmware requested %08x %dkb\n",
1799 le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
1800 le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
1801
1802 usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
1803 }
1804 ctx->scratch_size_bytes = 0;
1805 if (usage_bytes == 0)
1806 usage_bytes = 20 * 1024;
1807 /* allocate some scratch memory */
1808 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
1809 if (!ctx->scratch)
1810 return -ENOMEM;
1811 ctx->scratch_size_bytes = usage_bytes;
1812 return 0;
1813 }
CRIS linux kernel tree