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proc: Fix proc_sys_prune_dcache to hold a sb reference
[cris-mirror.git] / drivers / gpu / drm / amd / amdgpu / si_dpm.c
blob7c1c5d127281cdbb1a970d8492344043fd61f7fc
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "drmP.h"
25 #include "amdgpu.h"
26 #include "amdgpu_pm.h"
27 #include "amdgpu_dpm.h"
28 #include "amdgpu_atombios.h"
29 #include "sid.h"
30 #include "r600_dpm.h"
31 #include "si_dpm.h"
32 #include "atom.h"
33 #include "../include/pptable.h"
34 #include <linux/math64.h>
35 #include <linux/seq_file.h>
36 #include <linux/firmware.h>
37
38 #define MC_CG_ARB_FREQ_F0 0x0a
39 #define MC_CG_ARB_FREQ_F1 0x0b
40 #define MC_CG_ARB_FREQ_F2 0x0c
41 #define MC_CG_ARB_FREQ_F3 0x0d
42
43 #define SMC_RAM_END 0x20000
44
45 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
46
47
48 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
49 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
50 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
51 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
52 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
53 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
54 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
55
56 #define BIOS_SCRATCH_4 0x5cd
57
58 MODULE_FIRMWARE("radeon/tahiti_smc.bin");
59 MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
60 MODULE_FIRMWARE("radeon/pitcairn_k_smc.bin");
61 MODULE_FIRMWARE("radeon/verde_smc.bin");
62 MODULE_FIRMWARE("radeon/verde_k_smc.bin");
63 MODULE_FIRMWARE("radeon/oland_smc.bin");
64 MODULE_FIRMWARE("radeon/oland_k_smc.bin");
65 MODULE_FIRMWARE("radeon/hainan_smc.bin");
66 MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
67 MODULE_FIRMWARE("radeon/banks_k_2_smc.bin");
68
69 union power_info {
70 struct _ATOM_POWERPLAY_INFO info;
71 struct _ATOM_POWERPLAY_INFO_V2 info_2;
72 struct _ATOM_POWERPLAY_INFO_V3 info_3;
73 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
74 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
75 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
76 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
77 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
78 };
79
80 union fan_info {
81 struct _ATOM_PPLIB_FANTABLE fan;
82 struct _ATOM_PPLIB_FANTABLE2 fan2;
83 struct _ATOM_PPLIB_FANTABLE3 fan3;
84 };
85
86 union pplib_clock_info {
87 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
88 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
89 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
90 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
91 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
92 };
93
94 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
95 {
96 R600_UTC_DFLT_00,
97 R600_UTC_DFLT_01,
98 R600_UTC_DFLT_02,
99 R600_UTC_DFLT_03,
100 R600_UTC_DFLT_04,
101 R600_UTC_DFLT_05,
102 R600_UTC_DFLT_06,
103 R600_UTC_DFLT_07,
104 R600_UTC_DFLT_08,
105 R600_UTC_DFLT_09,
106 R600_UTC_DFLT_10,
107 R600_UTC_DFLT_11,
108 R600_UTC_DFLT_12,
109 R600_UTC_DFLT_13,
110 R600_UTC_DFLT_14,
111 };
112
113 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
114 {
115 R600_DTC_DFLT_00,
116 R600_DTC_DFLT_01,
117 R600_DTC_DFLT_02,
118 R600_DTC_DFLT_03,
119 R600_DTC_DFLT_04,
120 R600_DTC_DFLT_05,
121 R600_DTC_DFLT_06,
122 R600_DTC_DFLT_07,
123 R600_DTC_DFLT_08,
124 R600_DTC_DFLT_09,
125 R600_DTC_DFLT_10,
126 R600_DTC_DFLT_11,
127 R600_DTC_DFLT_12,
128 R600_DTC_DFLT_13,
129 R600_DTC_DFLT_14,
130 };
131
132 static const struct si_cac_config_reg cac_weights_tahiti[] =
133 {
134 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
135 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
136 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
137 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
138 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
139 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
140 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
141 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
142 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
143 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
144 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
145 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
146 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
147 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
148 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
149 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
150 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
151 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
152 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
153 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
154 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
155 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
156 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
157 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
158 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
159 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
160 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
161 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
162 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
163 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
164 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
165 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
166 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
167 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
168 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
169 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
170 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
171 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
172 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
173 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
174 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
175 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
176 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
177 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
178 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
179 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
180 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
181 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
182 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
183 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
184 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
185 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
186 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
187 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
188 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
189 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
190 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
191 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
192 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
193 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
194 { 0xFFFFFFFF }
195 };
196
197 static const struct si_cac_config_reg lcac_tahiti[] =
198 {
199 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
200 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
201 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
202 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
203 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
204 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
205 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
206 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
207 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
208 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
209 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
210 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
211 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
212 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
213 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
214 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
215 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
216 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
217 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
218 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
219 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
220 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
221 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
222 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
223 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
224 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
225 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
226 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
227 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
228 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
229 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
230 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
231 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
232 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
233 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
234 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
235 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
236 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
237 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
238 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
239 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
240 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
241 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
242 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
243 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
244 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
245 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
246 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
247 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
248 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
249 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
250 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
251 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
252 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
253 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
254 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
255 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
256 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
257 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
258 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
259 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
260 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
261 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
262 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
263 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
264 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
265 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
266 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
267 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
268 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
269 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
270 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
271 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
272 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
273 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
274 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
275 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
276 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
277 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
278 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
279 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
280 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
281 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
282 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
283 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
284 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
285 { 0xFFFFFFFF }
286
287 };
288
289 static const struct si_cac_config_reg cac_override_tahiti[] =
290 {
291 { 0xFFFFFFFF }
292 };
293
294 static const struct si_powertune_data powertune_data_tahiti =
295 {
296 ((1 << 16) | 27027),
297 6,
298 0,
299 4,
300 95,
301 {
302 0UL,
303 0UL,
304 4521550UL,
305 309631529UL,
306 -1270850L,
307 4513710L,
308 40
309 },
310 595000000UL,
311 12,
312 {
313 0,
314 0,
315 0,
316 0,
317 0,
318 0,
319 0,
320 0
321 },
322 true
323 };
324
325 static const struct si_dte_data dte_data_tahiti =
326 {
327 { 1159409, 0, 0, 0, 0 },
328 { 777, 0, 0, 0, 0 },
329 2,
330 54000,
331 127000,
332 25,
333 2,
334 10,
335 13,
336 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
337 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
338 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
339 85,
340 false
341 };
342
343 #if 0
344 static const struct si_dte_data dte_data_tahiti_le =
345 {
346 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
347 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
348 0x5,
349 0xAFC8,
350 0x64,
351 0x32,
352 1,
353 0,
354 0x10,
355 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
356 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
357 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
358 85,
359 true
360 };
361 #endif
362
363 static const struct si_dte_data dte_data_tahiti_pro =
364 {
365 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
366 { 0x0, 0x0, 0x0, 0x0, 0x0 },
367 5,
368 45000,
369 100,
370 0xA,
371 1,
372 0,
373 0x10,
374 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
375 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
376 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
377 90,
378 true
379 };
380
381 static const struct si_dte_data dte_data_new_zealand =
382 {
383 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
384 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
385 0x5,
386 0xAFC8,
387 0x69,
388 0x32,
389 1,
390 0,
391 0x10,
392 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
393 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
394 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
395 85,
396 true
397 };
398
399 static const struct si_dte_data dte_data_aruba_pro =
400 {
401 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
402 { 0x0, 0x0, 0x0, 0x0, 0x0 },
403 5,
404 45000,
405 100,
406 0xA,
407 1,
408 0,
409 0x10,
410 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
411 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
412 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
413 90,
414 true
415 };
416
417 static const struct si_dte_data dte_data_malta =
418 {
419 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
420 { 0x0, 0x0, 0x0, 0x0, 0x0 },
421 5,
422 45000,
423 100,
424 0xA,
425 1,
426 0,
427 0x10,
428 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
429 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
430 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
431 90,
432 true
433 };
434
435 static const struct si_cac_config_reg cac_weights_pitcairn[] =
436 {
437 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
438 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
439 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
440 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
441 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
442 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
443 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
444 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
445 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
446 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
447 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
448 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
449 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
450 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
451 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
452 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
453 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
454 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
455 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
456 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
457 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
458 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
459 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
460 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
461 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
462 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
463 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
464 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
465 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
466 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
467 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
468 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
469 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
470 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
471 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
472 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
473 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
474 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
475 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
476 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
477 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
478 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
479 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
480 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
481 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
482 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
483 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
484 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
485 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
486 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
487 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
488 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
489 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
490 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
491 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
492 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
493 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
494 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
495 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
496 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
497 { 0xFFFFFFFF }
498 };
499
500 static const struct si_cac_config_reg lcac_pitcairn[] =
501 {
502 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
503 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
504 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
505 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
506 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
507 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
508 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
509 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
510 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
511 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
512 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
513 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
514 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
515 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
516 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
517 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
518 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
519 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
520 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
521 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
522 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
523 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
524 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
525 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
526 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
527 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
528 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
529 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
530 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
531 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
532 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
533 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
534 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
535 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
536 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
537 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
538 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
539 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
540 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
541 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
542 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
543 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
544 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
545 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
546 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
547 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
548 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
549 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
550 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
551 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
552 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
553 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
554 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
555 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
556 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
557 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
558 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
559 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
560 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
561 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
562 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
563 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
564 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
565 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
566 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
567 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
568 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
569 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
570 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
571 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
572 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
573 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
574 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
575 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
576 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
577 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
578 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
579 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
580 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
581 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
582 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
583 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
584 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
585 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
586 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
587 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
588 { 0xFFFFFFFF }
589 };
590
591 static const struct si_cac_config_reg cac_override_pitcairn[] =
592 {
593 { 0xFFFFFFFF }
594 };
595
596 static const struct si_powertune_data powertune_data_pitcairn =
597 {
598 ((1 << 16) | 27027),
599 5,
600 0,
601 6,
602 100,
603 {
604 51600000UL,
605 1800000UL,
606 7194395UL,
607 309631529UL,
608 -1270850L,
609 4513710L,
610 100
611 },
612 117830498UL,
613 12,
614 {
615 0,
616 0,
617 0,
618 0,
619 0,
620 0,
621 0,
622 0
623 },
624 true
625 };
626
627 static const struct si_dte_data dte_data_pitcairn =
628 {
629 { 0, 0, 0, 0, 0 },
630 { 0, 0, 0, 0, 0 },
631 0,
632 0,
633 0,
634 0,
635 0,
636 0,
637 0,
638 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
639 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
640 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
641 0,
642 false
643 };
644
645 static const struct si_dte_data dte_data_curacao_xt =
646 {
647 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
648 { 0x0, 0x0, 0x0, 0x0, 0x0 },
649 5,
650 45000,
651 100,
652 0xA,
653 1,
654 0,
655 0x10,
656 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
657 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
658 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
659 90,
660 true
661 };
662
663 static const struct si_dte_data dte_data_curacao_pro =
664 {
665 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
666 { 0x0, 0x0, 0x0, 0x0, 0x0 },
667 5,
668 45000,
669 100,
670 0xA,
671 1,
672 0,
673 0x10,
674 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
675 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
676 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
677 90,
678 true
679 };
680
681 static const struct si_dte_data dte_data_neptune_xt =
682 {
683 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
684 { 0x0, 0x0, 0x0, 0x0, 0x0 },
685 5,
686 45000,
687 100,
688 0xA,
689 1,
690 0,
691 0x10,
692 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
693 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
694 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
695 90,
696 true
697 };
698
699 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
700 {
701 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
702 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
703 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
704 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
705 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
706 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
707 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
708 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
709 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
710 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
711 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
712 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
713 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
714 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
715 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
716 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
717 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
718 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
719 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
720 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
721 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
722 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
723 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
724 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
725 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
726 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
727 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
728 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
729 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
730 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
731 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
732 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
733 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
734 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
735 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
736 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
737 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
738 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
739 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
740 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
741 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
742 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
743 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
744 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
745 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
746 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
747 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
748 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
749 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
750 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
751 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
752 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
753 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
754 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
755 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
756 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
757 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
758 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
759 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
760 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
761 { 0xFFFFFFFF }
762 };
763
764 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
765 {
766 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
767 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
768 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
769 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
770 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
771 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
772 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
773 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
774 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
775 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
776 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
777 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
778 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
779 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
780 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
781 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
782 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
783 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
784 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
785 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
786 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
787 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
788 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
789 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
790 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
791 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
792 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
793 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
794 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
795 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
796 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
797 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
798 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
799 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
800 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
801 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
802 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
803 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
804 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
805 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
806 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
807 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
808 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
809 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
810 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
811 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
812 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
813 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
814 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
815 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
816 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
817 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
818 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
819 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
820 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
821 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
822 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
823 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
824 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
825 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
826 { 0xFFFFFFFF }
827 };
828
829 static const struct si_cac_config_reg cac_weights_heathrow[] =
830 {
831 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
832 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
833 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
834 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
835 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
836 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
837 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
838 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
839 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
840 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
841 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
842 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
843 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
844 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
845 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
846 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
847 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
848 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
849 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
850 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
851 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
852 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
853 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
854 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
855 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
856 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
857 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
858 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
859 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
860 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
861 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
862 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
863 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
864 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
865 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
866 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
867 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
868 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
869 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
870 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
871 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
872 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
873 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
874 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
875 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
876 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
877 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
878 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
879 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
880 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
881 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
882 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
883 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
884 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
885 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
886 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
887 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
888 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
889 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
890 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
891 { 0xFFFFFFFF }
892 };
893
894 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
895 {
896 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
897 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
898 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
899 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
900 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
901 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
902 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
903 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
904 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
905 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
906 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
907 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
908 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
909 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
910 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
911 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
912 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
913 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
914 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
915 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
916 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
917 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
918 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
919 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
920 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
921 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
922 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
923 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
924 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
925 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
926 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
927 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
928 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
929 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
930 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
931 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
932 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
933 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
934 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
935 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
936 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
937 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
938 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
939 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
940 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
941 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
942 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
943 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
944 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
945 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
946 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
947 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
948 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
949 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
950 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
951 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
952 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
953 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
954 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
955 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
956 { 0xFFFFFFFF }
957 };
958
959 static const struct si_cac_config_reg cac_weights_cape_verde[] =
960 {
961 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
962 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
963 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
964 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
965 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
966 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
967 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
968 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
969 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
970 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
971 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
972 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
973 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
974 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
975 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
976 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
977 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
978 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
979 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
980 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
981 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
982 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
983 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
984 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
985 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
986 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
987 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
988 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
989 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
990 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
991 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
992 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
993 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
994 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
995 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
996 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
997 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
998 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
999 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1000 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1001 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1002 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1003 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1004 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1005 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1006 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1007 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1008 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1009 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1010 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1011 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1012 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1013 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1014 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1015 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1016 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1017 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1018 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1019 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1020 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1021 { 0xFFFFFFFF }
1022 };
1023
1024 static const struct si_cac_config_reg lcac_cape_verde[] =
1025 {
1026 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1027 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1028 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1029 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1030 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1031 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1032 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1033 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1034 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1035 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1036 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1037 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1038 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1039 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1040 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1041 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1042 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1043 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1044 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1045 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1046 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1047 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1048 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1049 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1050 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1051 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1052 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1053 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1054 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1055 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1056 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1057 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1058 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1059 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1060 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1061 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1062 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1063 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1064 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1065 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1066 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1067 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1068 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1069 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1070 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1071 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1072 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1073 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1074 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1075 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1076 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1077 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1078 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1079 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1080 { 0xFFFFFFFF }
1081 };
1082
1083 static const struct si_cac_config_reg cac_override_cape_verde[] =
1084 {
1085 { 0xFFFFFFFF }
1086 };
1087
1088 static const struct si_powertune_data powertune_data_cape_verde =
1089 {
1090 ((1 << 16) | 0x6993),
1091 5,
1092 0,
1093 7,
1094 105,
1095 {
1096 0UL,
1097 0UL,
1098 7194395UL,
1099 309631529UL,
1100 -1270850L,
1101 4513710L,
1102 100
1103 },
1104 117830498UL,
1105 12,
1106 {
1107 0,
1108 0,
1109 0,
1110 0,
1111 0,
1112 0,
1113 0,
1114 0
1115 },
1116 true
1117 };
1118
1119 static const struct si_dte_data dte_data_cape_verde =
1120 {
1121 { 0, 0, 0, 0, 0 },
1122 { 0, 0, 0, 0, 0 },
1123 0,
1124 0,
1125 0,
1126 0,
1127 0,
1128 0,
1129 0,
1130 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1131 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1132 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1133 0,
1134 false
1135 };
1136
1137 static const struct si_dte_data dte_data_venus_xtx =
1138 {
1139 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1140 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1141 5,
1142 55000,
1143 0x69,
1144 0xA,
1145 1,
1146 0,
1147 0x3,
1148 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1149 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1150 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1151 90,
1152 true
1153 };
1154
1155 static const struct si_dte_data dte_data_venus_xt =
1156 {
1157 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1158 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1159 5,
1160 55000,
1161 0x69,
1162 0xA,
1163 1,
1164 0,
1165 0x3,
1166 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1167 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1168 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1169 90,
1170 true
1171 };
1172
1173 static const struct si_dte_data dte_data_venus_pro =
1174 {
1175 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1176 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1177 5,
1178 55000,
1179 0x69,
1180 0xA,
1181 1,
1182 0,
1183 0x3,
1184 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1185 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1186 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1187 90,
1188 true
1189 };
1190
1191 static const struct si_cac_config_reg cac_weights_oland[] =
1192 {
1193 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1194 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1195 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1196 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1197 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1198 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1199 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1200 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1201 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1202 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1203 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1204 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1205 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1206 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1207 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1208 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1209 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1210 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1211 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1212 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1213 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1214 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1215 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1216 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1217 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1218 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1219 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1220 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1222 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1223 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1224 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1225 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1226 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1227 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1228 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1229 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1230 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1231 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1232 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1233 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1234 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1235 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1236 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1238 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1239 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1240 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1241 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1242 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1243 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1244 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1245 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1246 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1247 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1248 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1249 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1250 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1251 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1252 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1253 { 0xFFFFFFFF }
1254 };
1255
1256 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1257 {
1258 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1259 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1260 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1261 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1262 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1263 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1264 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1265 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1266 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1267 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1268 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1269 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1270 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1271 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1272 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1273 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1274 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1275 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1276 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1277 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1278 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1279 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1280 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1281 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1282 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1283 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1284 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1285 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1286 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1287 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1288 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1289 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1290 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1291 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1292 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1293 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1294 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1295 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1296 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1297 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1298 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1299 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1300 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1303 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1304 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1305 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1306 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1307 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1308 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1309 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1310 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1311 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1312 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1313 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1314 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1315 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1316 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1317 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1318 { 0xFFFFFFFF }
1319 };
1320
1321 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1322 {
1323 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1324 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1325 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1326 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1327 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1328 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1329 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1330 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1331 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1332 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1333 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1334 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1335 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1336 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1337 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1338 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1339 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1340 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1341 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1342 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1343 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1344 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1345 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1346 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1347 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1348 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1349 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1350 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1351 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1352 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1353 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1354 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1355 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1356 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1357 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1358 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1359 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1360 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1361 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1362 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1363 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1364 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1365 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1368 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1369 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1370 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1371 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1372 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1373 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1374 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1375 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1376 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1377 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1378 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1379 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1380 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1381 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1382 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1383 { 0xFFFFFFFF }
1384 };
1385
1386 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1387 {
1388 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1389 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1390 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1391 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1392 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1393 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1394 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1395 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1396 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1397 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1398 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1399 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1400 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1401 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1402 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1403 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1404 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1405 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1406 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1407 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1408 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1409 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1410 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1411 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1412 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1413 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1414 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1415 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1416 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1417 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1418 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1419 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1420 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1421 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1422 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1423 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1424 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1425 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1426 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1427 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1428 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1429 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1430 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1431 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1432 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1433 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1434 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1435 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1436 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1437 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1438 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1439 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1440 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1441 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1442 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1443 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1444 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1445 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1446 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1447 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1448 { 0xFFFFFFFF }
1449 };
1450
1451 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1452 {
1453 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1454 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1455 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1456 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1457 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1458 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1459 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1460 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1461 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1462 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1463 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1464 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1465 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1466 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1467 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1468 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1469 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1470 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1471 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1472 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1473 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1474 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1475 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1476 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1477 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1478 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1479 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1480 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1481 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1483 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1484 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1485 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1486 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1487 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1488 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1489 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1490 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1491 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1492 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1493 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1494 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1495 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1496 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1497 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1498 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1499 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1500 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1501 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1502 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1503 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1504 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1505 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1506 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1507 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1508 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1509 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1510 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1511 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1512 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1513 { 0xFFFFFFFF }
1514 };
1515
1516 static const struct si_cac_config_reg lcac_oland[] =
1517 {
1518 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1519 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1520 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1521 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1522 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1523 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1524 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1525 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1526 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1527 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1528 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1529 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1530 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1531 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1532 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1533 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1534 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1535 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1536 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1537 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1538 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1539 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1540 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1541 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1542 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1543 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1544 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1545 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1546 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1547 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1548 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1549 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1550 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1551 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1552 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1553 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1554 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1555 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1556 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1557 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1558 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1559 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1560 { 0xFFFFFFFF }
1561 };
1562
1563 static const struct si_cac_config_reg lcac_mars_pro[] =
1564 {
1565 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1566 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1567 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1568 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1569 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1570 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1571 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1572 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1573 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1574 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1575 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1576 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1577 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1578 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1579 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1580 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1581 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1582 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1583 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1584 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1585 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1586 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1587 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1588 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1589 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1590 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1591 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1592 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1593 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1594 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1595 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1596 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1597 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1598 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1599 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1600 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1601 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1602 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1603 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1604 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1605 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1606 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1607 { 0xFFFFFFFF }
1608 };
1609
1610 static const struct si_cac_config_reg cac_override_oland[] =
1611 {
1612 { 0xFFFFFFFF }
1613 };
1614
1615 static const struct si_powertune_data powertune_data_oland =
1616 {
1617 ((1 << 16) | 0x6993),
1618 5,
1619 0,
1620 7,
1621 105,
1622 {
1623 0UL,
1624 0UL,
1625 7194395UL,
1626 309631529UL,
1627 -1270850L,
1628 4513710L,
1629 100
1630 },
1631 117830498UL,
1632 12,
1633 {
1634 0,
1635 0,
1636 0,
1637 0,
1638 0,
1639 0,
1640 0,
1641 0
1642 },
1643 true
1644 };
1645
1646 static const struct si_powertune_data powertune_data_mars_pro =
1647 {
1648 ((1 << 16) | 0x6993),
1649 5,
1650 0,
1651 7,
1652 105,
1653 {
1654 0UL,
1655 0UL,
1656 7194395UL,
1657 309631529UL,
1658 -1270850L,
1659 4513710L,
1660 100
1661 },
1662 117830498UL,
1663 12,
1664 {
1665 0,
1666 0,
1667 0,
1668 0,
1669 0,
1670 0,
1671 0,
1672 0
1673 },
1674 true
1675 };
1676
1677 static const struct si_dte_data dte_data_oland =
1678 {
1679 { 0, 0, 0, 0, 0 },
1680 { 0, 0, 0, 0, 0 },
1681 0,
1682 0,
1683 0,
1684 0,
1685 0,
1686 0,
1687 0,
1688 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1689 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1690 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1691 0,
1692 false
1693 };
1694
1695 static const struct si_dte_data dte_data_mars_pro =
1696 {
1697 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1698 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1699 5,
1700 55000,
1701 105,
1702 0xA,
1703 1,
1704 0,
1705 0x10,
1706 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1707 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1708 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1709 90,
1710 true
1711 };
1712
1713 static const struct si_dte_data dte_data_sun_xt =
1714 {
1715 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1716 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1717 5,
1718 55000,
1719 105,
1720 0xA,
1721 1,
1722 0,
1723 0x10,
1724 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1725 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1726 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1727 90,
1728 true
1729 };
1730
1731
1732 static const struct si_cac_config_reg cac_weights_hainan[] =
1733 {
1734 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1735 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1736 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1737 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1738 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1739 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1740 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1741 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1742 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1743 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1744 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1745 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1746 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1747 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1748 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1749 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1750 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1751 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1752 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1753 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1754 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1755 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1756 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1757 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1758 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1759 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1760 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1761 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1762 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1763 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1764 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1765 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1766 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1767 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1768 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1769 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1770 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1771 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1772 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1773 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1774 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1775 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1776 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1777 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1778 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1779 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1780 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1781 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1782 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1783 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1784 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1785 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1786 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1787 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1788 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1789 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1790 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1791 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1792 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1793 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1794 { 0xFFFFFFFF }
1795 };
1796
1797 static const struct si_powertune_data powertune_data_hainan =
1798 {
1799 ((1 << 16) | 0x6993),
1800 5,
1801 0,
1802 9,
1803 105,
1804 {
1805 0UL,
1806 0UL,
1807 7194395UL,
1808 309631529UL,
1809 -1270850L,
1810 4513710L,
1811 100
1812 },
1813 117830498UL,
1814 12,
1815 {
1816 0,
1817 0,
1818 0,
1819 0,
1820 0,
1821 0,
1822 0,
1823 0
1824 },
1825 true
1826 };
1827
1828 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1829 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1830 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1831 static struct si_ps *si_get_ps(struct amdgpu_ps *rps);
1832
1833 static int si_populate_voltage_value(struct amdgpu_device *adev,
1834 const struct atom_voltage_table *table,
1835 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1836 static int si_get_std_voltage_value(struct amdgpu_device *adev,
1837 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1838 u16 *std_voltage);
1839 static int si_write_smc_soft_register(struct amdgpu_device *adev,
1840 u16 reg_offset, u32 value);
1841 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1842 struct rv7xx_pl *pl,
1843 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1844 static int si_calculate_sclk_params(struct amdgpu_device *adev,
1845 u32 engine_clock,
1846 SISLANDS_SMC_SCLK_VALUE *sclk);
1847
1848 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1849 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1850 static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev);
1851 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1852
1853 static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1854 {
1855 struct si_power_info *pi = adev->pm.dpm.priv;
1856 return pi;
1857 }
1858
1859 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1860 u16 v, s32 t, u32 ileakage, u32 *leakage)
1861 {
1862 s64 kt, kv, leakage_w, i_leakage, vddc;
1863 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1864 s64 tmp;
1865
1866 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1867 vddc = div64_s64(drm_int2fixp(v), 1000);
1868 temperature = div64_s64(drm_int2fixp(t), 1000);
1869
1870 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1871 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1872 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1873 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1874 t_ref = drm_int2fixp(coeff->t_ref);
1875
1876 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1877 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1878 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1879 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1880
1881 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1882
1883 *leakage = drm_fixp2int(leakage_w * 1000);
1884 }
1885
1886 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1887 const struct ni_leakage_coeffients *coeff,
1888 u16 v,
1889 s32 t,
1890 u32 i_leakage,
1891 u32 *leakage)
1892 {
1893 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1894 }
1895
1896 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1897 const u32 fixed_kt, u16 v,
1898 u32 ileakage, u32 *leakage)
1899 {
1900 s64 kt, kv, leakage_w, i_leakage, vddc;
1901
1902 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1903 vddc = div64_s64(drm_int2fixp(v), 1000);
1904
1905 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1906 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1907 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1908
1909 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1910
1911 *leakage = drm_fixp2int(leakage_w * 1000);
1912 }
1913
1914 static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1915 const struct ni_leakage_coeffients *coeff,
1916 const u32 fixed_kt,
1917 u16 v,
1918 u32 i_leakage,
1919 u32 *leakage)
1920 {
1921 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1922 }
1923
1924
1925 static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1926 struct si_dte_data *dte_data)
1927 {
1928 u32 p_limit1 = adev->pm.dpm.tdp_limit;
1929 u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1930 u32 k = dte_data->k;
1931 u32 t_max = dte_data->max_t;
1932 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1933 u32 t_0 = dte_data->t0;
1934 u32 i;
1935
1936 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1937 dte_data->tdep_count = 3;
1938
1939 for (i = 0; i < k; i++) {
1940 dte_data->r[i] =
1941 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1942 (p_limit2 * (u32)100);
1943 }
1944
1945 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1946
1947 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1948 dte_data->tdep_r[i] = dte_data->r[4];
1949 }
1950 } else {
1951 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1952 }
1953 }
1954
1955 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1956 {
1957 struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1958
1959 return pi;
1960 }
1961
1962 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1963 {
1964 struct ni_power_info *pi = adev->pm.dpm.priv;
1965
1966 return pi;
1967 }
1968
1969 static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1970 {
1971 struct si_ps *ps = aps->ps_priv;
1972
1973 return ps;
1974 }
1975
1976 static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1977 {
1978 struct ni_power_info *ni_pi = ni_get_pi(adev);
1979 struct si_power_info *si_pi = si_get_pi(adev);
1980 bool update_dte_from_pl2 = false;
1981
1982 if (adev->asic_type == CHIP_TAHITI) {
1983 si_pi->cac_weights = cac_weights_tahiti;
1984 si_pi->lcac_config = lcac_tahiti;
1985 si_pi->cac_override = cac_override_tahiti;
1986 si_pi->powertune_data = &powertune_data_tahiti;
1987 si_pi->dte_data = dte_data_tahiti;
1988
1989 switch (adev->pdev->device) {
1990 case 0x6798:
1991 si_pi->dte_data.enable_dte_by_default = true;
1992 break;
1993 case 0x6799:
1994 si_pi->dte_data = dte_data_new_zealand;
1995 break;
1996 case 0x6790:
1997 case 0x6791:
1998 case 0x6792:
1999 case 0x679E:
2000 si_pi->dte_data = dte_data_aruba_pro;
2001 update_dte_from_pl2 = true;
2002 break;
2003 case 0x679B:
2004 si_pi->dte_data = dte_data_malta;
2005 update_dte_from_pl2 = true;
2006 break;
2007 case 0x679A:
2008 si_pi->dte_data = dte_data_tahiti_pro;
2009 update_dte_from_pl2 = true;
2010 break;
2011 default:
2012 if (si_pi->dte_data.enable_dte_by_default == true)
2013 DRM_ERROR("DTE is not enabled!\n");
2014 break;
2015 }
2016 } else if (adev->asic_type == CHIP_PITCAIRN) {
2017 si_pi->cac_weights = cac_weights_pitcairn;
2018 si_pi->lcac_config = lcac_pitcairn;
2019 si_pi->cac_override = cac_override_pitcairn;
2020 si_pi->powertune_data = &powertune_data_pitcairn;
2021
2022 switch (adev->pdev->device) {
2023 case 0x6810:
2024 case 0x6818:
2025 si_pi->dte_data = dte_data_curacao_xt;
2026 update_dte_from_pl2 = true;
2027 break;
2028 case 0x6819:
2029 case 0x6811:
2030 si_pi->dte_data = dte_data_curacao_pro;
2031 update_dte_from_pl2 = true;
2032 break;
2033 case 0x6800:
2034 case 0x6806:
2035 si_pi->dte_data = dte_data_neptune_xt;
2036 update_dte_from_pl2 = true;
2037 break;
2038 default:
2039 si_pi->dte_data = dte_data_pitcairn;
2040 break;
2041 }
2042 } else if (adev->asic_type == CHIP_VERDE) {
2043 si_pi->lcac_config = lcac_cape_verde;
2044 si_pi->cac_override = cac_override_cape_verde;
2045 si_pi->powertune_data = &powertune_data_cape_verde;
2046
2047 switch (adev->pdev->device) {
2048 case 0x683B:
2049 case 0x683F:
2050 case 0x6829:
2051 case 0x6835:
2052 si_pi->cac_weights = cac_weights_cape_verde_pro;
2053 si_pi->dte_data = dte_data_cape_verde;
2054 break;
2055 case 0x682C:
2056 si_pi->cac_weights = cac_weights_cape_verde_pro;
2057 si_pi->dte_data = dte_data_sun_xt;
2058 break;
2059 case 0x6825:
2060 case 0x6827:
2061 si_pi->cac_weights = cac_weights_heathrow;
2062 si_pi->dte_data = dte_data_cape_verde;
2063 break;
2064 case 0x6824:
2065 case 0x682D:
2066 si_pi->cac_weights = cac_weights_chelsea_xt;
2067 si_pi->dte_data = dte_data_cape_verde;
2068 break;
2069 case 0x682F:
2070 si_pi->cac_weights = cac_weights_chelsea_pro;
2071 si_pi->dte_data = dte_data_cape_verde;
2072 break;
2073 case 0x6820:
2074 si_pi->cac_weights = cac_weights_heathrow;
2075 si_pi->dte_data = dte_data_venus_xtx;
2076 break;
2077 case 0x6821:
2078 si_pi->cac_weights = cac_weights_heathrow;
2079 si_pi->dte_data = dte_data_venus_xt;
2080 break;
2081 case 0x6823:
2082 case 0x682B:
2083 case 0x6822:
2084 case 0x682A:
2085 si_pi->cac_weights = cac_weights_chelsea_pro;
2086 si_pi->dte_data = dte_data_venus_pro;
2087 break;
2088 default:
2089 si_pi->cac_weights = cac_weights_cape_verde;
2090 si_pi->dte_data = dte_data_cape_verde;
2091 break;
2092 }
2093 } else if (adev->asic_type == CHIP_OLAND) {
2094 si_pi->lcac_config = lcac_mars_pro;
2095 si_pi->cac_override = cac_override_oland;
2096 si_pi->powertune_data = &powertune_data_mars_pro;
2097 si_pi->dte_data = dte_data_mars_pro;
2098
2099 switch (adev->pdev->device) {
2100 case 0x6601:
2101 case 0x6621:
2102 case 0x6603:
2103 case 0x6605:
2104 si_pi->cac_weights = cac_weights_mars_pro;
2105 update_dte_from_pl2 = true;
2106 break;
2107 case 0x6600:
2108 case 0x6606:
2109 case 0x6620:
2110 case 0x6604:
2111 si_pi->cac_weights = cac_weights_mars_xt;
2112 update_dte_from_pl2 = true;
2113 break;
2114 case 0x6611:
2115 case 0x6613:
2116 case 0x6608:
2117 si_pi->cac_weights = cac_weights_oland_pro;
2118 update_dte_from_pl2 = true;
2119 break;
2120 case 0x6610:
2121 si_pi->cac_weights = cac_weights_oland_xt;
2122 update_dte_from_pl2 = true;
2123 break;
2124 default:
2125 si_pi->cac_weights = cac_weights_oland;
2126 si_pi->lcac_config = lcac_oland;
2127 si_pi->cac_override = cac_override_oland;
2128 si_pi->powertune_data = &powertune_data_oland;
2129 si_pi->dte_data = dte_data_oland;
2130 break;
2131 }
2132 } else if (adev->asic_type == CHIP_HAINAN) {
2133 si_pi->cac_weights = cac_weights_hainan;
2134 si_pi->lcac_config = lcac_oland;
2135 si_pi->cac_override = cac_override_oland;
2136 si_pi->powertune_data = &powertune_data_hainan;
2137 si_pi->dte_data = dte_data_sun_xt;
2138 update_dte_from_pl2 = true;
2139 } else {
2140 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2141 return;
2142 }
2143
2144 ni_pi->enable_power_containment = false;
2145 ni_pi->enable_cac = false;
2146 ni_pi->enable_sq_ramping = false;
2147 si_pi->enable_dte = false;
2148
2149 if (si_pi->powertune_data->enable_powertune_by_default) {
2150 ni_pi->enable_power_containment = true;
2151 ni_pi->enable_cac = true;
2152 if (si_pi->dte_data.enable_dte_by_default) {
2153 si_pi->enable_dte = true;
2154 if (update_dte_from_pl2)
2155 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2156
2157 }
2158 ni_pi->enable_sq_ramping = true;
2159 }
2160
2161 ni_pi->driver_calculate_cac_leakage = true;
2162 ni_pi->cac_configuration_required = true;
2163
2164 if (ni_pi->cac_configuration_required) {
2165 ni_pi->support_cac_long_term_average = true;
2166 si_pi->dyn_powertune_data.l2_lta_window_size =
2167 si_pi->powertune_data->l2_lta_window_size_default;
2168 si_pi->dyn_powertune_data.lts_truncate =
2169 si_pi->powertune_data->lts_truncate_default;
2170 } else {
2171 ni_pi->support_cac_long_term_average = false;
2172 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2173 si_pi->dyn_powertune_data.lts_truncate = 0;
2174 }
2175
2176 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2177 }
2178
2179 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2180 {
2181 return 1;
2182 }
2183
2184 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2185 {
2186 u32 xclk;
2187 u32 wintime;
2188 u32 cac_window;
2189 u32 cac_window_size;
2190
2191 xclk = amdgpu_asic_get_xclk(adev);
2192
2193 if (xclk == 0)
2194 return 0;
2195
2196 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2197 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2198
2199 wintime = (cac_window_size * 100) / xclk;
2200
2201 return wintime;
2202 }
2203
2204 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2205 {
2206 return power_in_watts;
2207 }
2208
2209 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2210 bool adjust_polarity,
2211 u32 tdp_adjustment,
2212 u32 *tdp_limit,
2213 u32 *near_tdp_limit)
2214 {
2215 u32 adjustment_delta, max_tdp_limit;
2216
2217 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2218 return -EINVAL;
2219
2220 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2221
2222 if (adjust_polarity) {
2223 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2224 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2225 } else {
2226 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2227 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit;
2228 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2229 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2230 else
2231 *near_tdp_limit = 0;
2232 }
2233
2234 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2235 return -EINVAL;
2236 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2237 return -EINVAL;
2238
2239 return 0;
2240 }
2241
2242 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2243 struct amdgpu_ps *amdgpu_state)
2244 {
2245 struct ni_power_info *ni_pi = ni_get_pi(adev);
2246 struct si_power_info *si_pi = si_get_pi(adev);
2247
2248 if (ni_pi->enable_power_containment) {
2249 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2250 PP_SIslands_PAPMParameters *papm_parm;
2251 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2252 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2253 u32 tdp_limit;
2254 u32 near_tdp_limit;
2255 int ret;
2256
2257 if (scaling_factor == 0)
2258 return -EINVAL;
2259
2260 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2261
2262 ret = si_calculate_adjusted_tdp_limits(adev,
2263 false, /* ??? */
2264 adev->pm.dpm.tdp_adjustment,
2265 &tdp_limit,
2266 &near_tdp_limit);
2267 if (ret)
2268 return ret;
2269
2270 smc_table->dpm2Params.TDPLimit =
2271 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2272 smc_table->dpm2Params.NearTDPLimit =
2273 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2274 smc_table->dpm2Params.SafePowerLimit =
2275 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2276
2277 ret = amdgpu_si_copy_bytes_to_smc(adev,
2278 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2279 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2280 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2281 sizeof(u32) * 3,
2282 si_pi->sram_end);
2283 if (ret)
2284 return ret;
2285
2286 if (si_pi->enable_ppm) {
2287 papm_parm = &si_pi->papm_parm;
2288 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2289 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2290 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2291 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2292 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2293 papm_parm->PlatformPowerLimit = 0xffffffff;
2294 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2295
2296 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2297 (u8 *)papm_parm,
2298 sizeof(PP_SIslands_PAPMParameters),
2299 si_pi->sram_end);
2300 if (ret)
2301 return ret;
2302 }
2303 }
2304 return 0;
2305 }
2306
2307 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2308 struct amdgpu_ps *amdgpu_state)
2309 {
2310 struct ni_power_info *ni_pi = ni_get_pi(adev);
2311 struct si_power_info *si_pi = si_get_pi(adev);
2312
2313 if (ni_pi->enable_power_containment) {
2314 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2315 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2316 int ret;
2317
2318 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2319
2320 smc_table->dpm2Params.NearTDPLimit =
2321 cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2322 smc_table->dpm2Params.SafePowerLimit =
2323 cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2324
2325 ret = amdgpu_si_copy_bytes_to_smc(adev,
2326 (si_pi->state_table_start +
2327 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2328 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2329 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2330 sizeof(u32) * 2,
2331 si_pi->sram_end);
2332 if (ret)
2333 return ret;
2334 }
2335
2336 return 0;
2337 }
2338
2339 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2340 const u16 prev_std_vddc,
2341 const u16 curr_std_vddc)
2342 {
2343 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2344 u64 prev_vddc = (u64)prev_std_vddc;
2345 u64 curr_vddc = (u64)curr_std_vddc;
2346 u64 pwr_efficiency_ratio, n, d;
2347
2348 if ((prev_vddc == 0) || (curr_vddc == 0))
2349 return 0;
2350
2351 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2352 d = prev_vddc * prev_vddc;
2353 pwr_efficiency_ratio = div64_u64(n, d);
2354
2355 if (pwr_efficiency_ratio > (u64)0xFFFF)
2356 return 0;
2357
2358 return (u16)pwr_efficiency_ratio;
2359 }
2360
2361 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2362 struct amdgpu_ps *amdgpu_state)
2363 {
2364 struct si_power_info *si_pi = si_get_pi(adev);
2365
2366 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2367 amdgpu_state->vclk && amdgpu_state->dclk)
2368 return true;
2369
2370 return false;
2371 }
2372
2373 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2374 {
2375 struct evergreen_power_info *pi = adev->pm.dpm.priv;
2376
2377 return pi;
2378 }
2379
2380 static int si_populate_power_containment_values(struct amdgpu_device *adev,
2381 struct amdgpu_ps *amdgpu_state,
2382 SISLANDS_SMC_SWSTATE *smc_state)
2383 {
2384 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2385 struct ni_power_info *ni_pi = ni_get_pi(adev);
2386 struct si_ps *state = si_get_ps(amdgpu_state);
2387 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2388 u32 prev_sclk;
2389 u32 max_sclk;
2390 u32 min_sclk;
2391 u16 prev_std_vddc;
2392 u16 curr_std_vddc;
2393 int i;
2394 u16 pwr_efficiency_ratio;
2395 u8 max_ps_percent;
2396 bool disable_uvd_power_tune;
2397 int ret;
2398
2399 if (ni_pi->enable_power_containment == false)
2400 return 0;
2401
2402 if (state->performance_level_count == 0)
2403 return -EINVAL;
2404
2405 if (smc_state->levelCount != state->performance_level_count)
2406 return -EINVAL;
2407
2408 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2409
2410 smc_state->levels[0].dpm2.MaxPS = 0;
2411 smc_state->levels[0].dpm2.NearTDPDec = 0;
2412 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2413 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2414 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2415
2416 for (i = 1; i < state->performance_level_count; i++) {
2417 prev_sclk = state->performance_levels[i-1].sclk;
2418 max_sclk = state->performance_levels[i].sclk;
2419 if (i == 1)
2420 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2421 else
2422 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2423
2424 if (prev_sclk > max_sclk)
2425 return -EINVAL;
2426
2427 if ((max_ps_percent == 0) ||
2428 (prev_sclk == max_sclk) ||
2429 disable_uvd_power_tune)
2430 min_sclk = max_sclk;
2431 else if (i == 1)
2432 min_sclk = prev_sclk;
2433 else
2434 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2435
2436 if (min_sclk < state->performance_levels[0].sclk)
2437 min_sclk = state->performance_levels[0].sclk;
2438
2439 if (min_sclk == 0)
2440 return -EINVAL;
2441
2442 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2443 state->performance_levels[i-1].vddc, &vddc);
2444 if (ret)
2445 return ret;
2446
2447 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2448 if (ret)
2449 return ret;
2450
2451 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2452 state->performance_levels[i].vddc, &vddc);
2453 if (ret)
2454 return ret;
2455
2456 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2457 if (ret)
2458 return ret;
2459
2460 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2461 prev_std_vddc, curr_std_vddc);
2462
2463 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2464 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2465 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2466 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2467 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2468 }
2469
2470 return 0;
2471 }
2472
2473 static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2474 struct amdgpu_ps *amdgpu_state,
2475 SISLANDS_SMC_SWSTATE *smc_state)
2476 {
2477 struct ni_power_info *ni_pi = ni_get_pi(adev);
2478 struct si_ps *state = si_get_ps(amdgpu_state);
2479 u32 sq_power_throttle, sq_power_throttle2;
2480 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2481 int i;
2482
2483 if (state->performance_level_count == 0)
2484 return -EINVAL;
2485
2486 if (smc_state->levelCount != state->performance_level_count)
2487 return -EINVAL;
2488
2489 if (adev->pm.dpm.sq_ramping_threshold == 0)
2490 return -EINVAL;
2491
2492 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2493 enable_sq_ramping = false;
2494
2495 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2496 enable_sq_ramping = false;
2497
2498 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2499 enable_sq_ramping = false;
2500
2501 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2502 enable_sq_ramping = false;
2503
2504 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2505 enable_sq_ramping = false;
2506
2507 for (i = 0; i < state->performance_level_count; i++) {
2508 sq_power_throttle = 0;
2509 sq_power_throttle2 = 0;
2510
2511 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2512 enable_sq_ramping) {
2513 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2514 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2515 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2516 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2517 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2518 } else {
2519 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2520 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2521 }
2522
2523 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2524 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2525 }
2526
2527 return 0;
2528 }
2529
2530 static int si_enable_power_containment(struct amdgpu_device *adev,
2531 struct amdgpu_ps *amdgpu_new_state,
2532 bool enable)
2533 {
2534 struct ni_power_info *ni_pi = ni_get_pi(adev);
2535 PPSMC_Result smc_result;
2536 int ret = 0;
2537
2538 if (ni_pi->enable_power_containment) {
2539 if (enable) {
2540 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2541 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2542 if (smc_result != PPSMC_Result_OK) {
2543 ret = -EINVAL;
2544 ni_pi->pc_enabled = false;
2545 } else {
2546 ni_pi->pc_enabled = true;
2547 }
2548 }
2549 } else {
2550 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2551 if (smc_result != PPSMC_Result_OK)
2552 ret = -EINVAL;
2553 ni_pi->pc_enabled = false;
2554 }
2555 }
2556
2557 return ret;
2558 }
2559
2560 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2561 {
2562 struct si_power_info *si_pi = si_get_pi(adev);
2563 int ret = 0;
2564 struct si_dte_data *dte_data = &si_pi->dte_data;
2565 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2566 u32 table_size;
2567 u8 tdep_count;
2568 u32 i;
2569
2570 if (dte_data == NULL)
2571 si_pi->enable_dte = false;
2572
2573 if (si_pi->enable_dte == false)
2574 return 0;
2575
2576 if (dte_data->k <= 0)
2577 return -EINVAL;
2578
2579 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2580 if (dte_tables == NULL) {
2581 si_pi->enable_dte = false;
2582 return -ENOMEM;
2583 }
2584
2585 table_size = dte_data->k;
2586
2587 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2588 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2589
2590 tdep_count = dte_data->tdep_count;
2591 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2592 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2593
2594 dte_tables->K = cpu_to_be32(table_size);
2595 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2596 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2597 dte_tables->WindowSize = dte_data->window_size;
2598 dte_tables->temp_select = dte_data->temp_select;
2599 dte_tables->DTE_mode = dte_data->dte_mode;
2600 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2601
2602 if (tdep_count > 0)
2603 table_size--;
2604
2605 for (i = 0; i < table_size; i++) {
2606 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2607 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2608 }
2609
2610 dte_tables->Tdep_count = tdep_count;
2611
2612 for (i = 0; i < (u32)tdep_count; i++) {
2613 dte_tables->T_limits[i] = dte_data->t_limits[i];
2614 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2615 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2616 }
2617
2618 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2619 (u8 *)dte_tables,
2620 sizeof(Smc_SIslands_DTE_Configuration),
2621 si_pi->sram_end);
2622 kfree(dte_tables);
2623
2624 return ret;
2625 }
2626
2627 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2628 u16 *max, u16 *min)
2629 {
2630 struct si_power_info *si_pi = si_get_pi(adev);
2631 struct amdgpu_cac_leakage_table *table =
2632 &adev->pm.dpm.dyn_state.cac_leakage_table;
2633 u32 i;
2634 u32 v0_loadline;
2635
2636 if (table == NULL)
2637 return -EINVAL;
2638
2639 *max = 0;
2640 *min = 0xFFFF;
2641
2642 for (i = 0; i < table->count; i++) {
2643 if (table->entries[i].vddc > *max)
2644 *max = table->entries[i].vddc;
2645 if (table->entries[i].vddc < *min)
2646 *min = table->entries[i].vddc;
2647 }
2648
2649 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2650 return -EINVAL;
2651
2652 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2653
2654 if (v0_loadline > 0xFFFFUL)
2655 return -EINVAL;
2656
2657 *min = (u16)v0_loadline;
2658
2659 if ((*min > *max) || (*max == 0) || (*min == 0))
2660 return -EINVAL;
2661
2662 return 0;
2663 }
2664
2665 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2666 {
2667 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2668 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2669 }
2670
2671 static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2672 PP_SIslands_CacConfig *cac_tables,
2673 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2674 u16 t0, u16 t_step)
2675 {
2676 struct si_power_info *si_pi = si_get_pi(adev);
2677 u32 leakage;
2678 unsigned int i, j;
2679 s32 t;
2680 u32 smc_leakage;
2681 u32 scaling_factor;
2682 u16 voltage;
2683
2684 scaling_factor = si_get_smc_power_scaling_factor(adev);
2685
2686 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2687 t = (1000 * (i * t_step + t0));
2688
2689 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2690 voltage = vddc_max - (vddc_step * j);
2691
2692 si_calculate_leakage_for_v_and_t(adev,
2693 &si_pi->powertune_data->leakage_coefficients,
2694 voltage,
2695 t,
2696 si_pi->dyn_powertune_data.cac_leakage,
2697 &leakage);
2698
2699 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2700
2701 if (smc_leakage > 0xFFFF)
2702 smc_leakage = 0xFFFF;
2703
2704 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2705 cpu_to_be16((u16)smc_leakage);
2706 }
2707 }
2708 return 0;
2709 }
2710
2711 static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2712 PP_SIslands_CacConfig *cac_tables,
2713 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2714 {
2715 struct si_power_info *si_pi = si_get_pi(adev);
2716 u32 leakage;
2717 unsigned int i, j;
2718 u32 smc_leakage;
2719 u32 scaling_factor;
2720 u16 voltage;
2721
2722 scaling_factor = si_get_smc_power_scaling_factor(adev);
2723
2724 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2725 voltage = vddc_max - (vddc_step * j);
2726
2727 si_calculate_leakage_for_v(adev,
2728 &si_pi->powertune_data->leakage_coefficients,
2729 si_pi->powertune_data->fixed_kt,
2730 voltage,
2731 si_pi->dyn_powertune_data.cac_leakage,
2732 &leakage);
2733
2734 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2735
2736 if (smc_leakage > 0xFFFF)
2737 smc_leakage = 0xFFFF;
2738
2739 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2740 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2741 cpu_to_be16((u16)smc_leakage);
2742 }
2743 return 0;
2744 }
2745
2746 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2747 {
2748 struct ni_power_info *ni_pi = ni_get_pi(adev);
2749 struct si_power_info *si_pi = si_get_pi(adev);
2750 PP_SIslands_CacConfig *cac_tables = NULL;
2751 u16 vddc_max, vddc_min, vddc_step;
2752 u16 t0, t_step;
2753 u32 load_line_slope, reg;
2754 int ret = 0;
2755 u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2756
2757 if (ni_pi->enable_cac == false)
2758 return 0;
2759
2760 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2761 if (!cac_tables)
2762 return -ENOMEM;
2763
2764 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2765 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2766 WREG32(CG_CAC_CTRL, reg);
2767
2768 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2769 si_pi->dyn_powertune_data.dc_pwr_value =
2770 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2771 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2772 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2773
2774 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2775
2776 ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2777 if (ret)
2778 goto done_free;
2779
2780 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2781 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2782 t_step = 4;
2783 t0 = 60;
2784
2785 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2786 ret = si_init_dte_leakage_table(adev, cac_tables,
2787 vddc_max, vddc_min, vddc_step,
2788 t0, t_step);
2789 else
2790 ret = si_init_simplified_leakage_table(adev, cac_tables,
2791 vddc_max, vddc_min, vddc_step);
2792 if (ret)
2793 goto done_free;
2794
2795 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2796
2797 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2798 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2799 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2800 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2801 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2802 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2803 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2804 cac_tables->calculation_repeats = cpu_to_be32(2);
2805 cac_tables->dc_cac = cpu_to_be32(0);
2806 cac_tables->log2_PG_LKG_SCALE = 12;
2807 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2808 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2809 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2810
2811 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2812 (u8 *)cac_tables,
2813 sizeof(PP_SIslands_CacConfig),
2814 si_pi->sram_end);
2815
2816 if (ret)
2817 goto done_free;
2818
2819 ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2820
2821 done_free:
2822 if (ret) {
2823 ni_pi->enable_cac = false;
2824 ni_pi->enable_power_containment = false;
2825 }
2826
2827 kfree(cac_tables);
2828
2829 return ret;
2830 }
2831
2832 static int si_program_cac_config_registers(struct amdgpu_device *adev,
2833 const struct si_cac_config_reg *cac_config_regs)
2834 {
2835 const struct si_cac_config_reg *config_regs = cac_config_regs;
2836 u32 data = 0, offset;
2837
2838 if (!config_regs)
2839 return -EINVAL;
2840
2841 while (config_regs->offset != 0xFFFFFFFF) {
2842 switch (config_regs->type) {
2843 case SISLANDS_CACCONFIG_CGIND:
2844 offset = SMC_CG_IND_START + config_regs->offset;
2845 if (offset < SMC_CG_IND_END)
2846 data = RREG32_SMC(offset);
2847 break;
2848 default:
2849 data = RREG32(config_regs->offset);
2850 break;
2851 }
2852
2853 data &= ~config_regs->mask;
2854 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2855
2856 switch (config_regs->type) {
2857 case SISLANDS_CACCONFIG_CGIND:
2858 offset = SMC_CG_IND_START + config_regs->offset;
2859 if (offset < SMC_CG_IND_END)
2860 WREG32_SMC(offset, data);
2861 break;
2862 default:
2863 WREG32(config_regs->offset, data);
2864 break;
2865 }
2866 config_regs++;
2867 }
2868 return 0;
2869 }
2870
2871 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2872 {
2873 struct ni_power_info *ni_pi = ni_get_pi(adev);
2874 struct si_power_info *si_pi = si_get_pi(adev);
2875 int ret;
2876
2877 if ((ni_pi->enable_cac == false) ||
2878 (ni_pi->cac_configuration_required == false))
2879 return 0;
2880
2881 ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2882 if (ret)
2883 return ret;
2884 ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2885 if (ret)
2886 return ret;
2887 ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2888 if (ret)
2889 return ret;
2890
2891 return 0;
2892 }
2893
2894 static int si_enable_smc_cac(struct amdgpu_device *adev,
2895 struct amdgpu_ps *amdgpu_new_state,
2896 bool enable)
2897 {
2898 struct ni_power_info *ni_pi = ni_get_pi(adev);
2899 struct si_power_info *si_pi = si_get_pi(adev);
2900 PPSMC_Result smc_result;
2901 int ret = 0;
2902
2903 if (ni_pi->enable_cac) {
2904 if (enable) {
2905 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2906 if (ni_pi->support_cac_long_term_average) {
2907 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2908 if (smc_result != PPSMC_Result_OK)
2909 ni_pi->support_cac_long_term_average = false;
2910 }
2911
2912 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2913 if (smc_result != PPSMC_Result_OK) {
2914 ret = -EINVAL;
2915 ni_pi->cac_enabled = false;
2916 } else {
2917 ni_pi->cac_enabled = true;
2918 }
2919
2920 if (si_pi->enable_dte) {
2921 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2922 if (smc_result != PPSMC_Result_OK)
2923 ret = -EINVAL;
2924 }
2925 }
2926 } else if (ni_pi->cac_enabled) {
2927 if (si_pi->enable_dte)
2928 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2929
2930 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2931
2932 ni_pi->cac_enabled = false;
2933
2934 if (ni_pi->support_cac_long_term_average)
2935 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2936 }
2937 }
2938 return ret;
2939 }
2940
2941 static int si_init_smc_spll_table(struct amdgpu_device *adev)
2942 {
2943 struct ni_power_info *ni_pi = ni_get_pi(adev);
2944 struct si_power_info *si_pi = si_get_pi(adev);
2945 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2946 SISLANDS_SMC_SCLK_VALUE sclk_params;
2947 u32 fb_div, p_div;
2948 u32 clk_s, clk_v;
2949 u32 sclk = 0;
2950 int ret = 0;
2951 u32 tmp;
2952 int i;
2953
2954 if (si_pi->spll_table_start == 0)
2955 return -EINVAL;
2956
2957 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2958 if (spll_table == NULL)
2959 return -ENOMEM;
2960
2961 for (i = 0; i < 256; i++) {
2962 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2963 if (ret)
2964 break;
2965 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2966 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2967 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2968 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2969
2970 fb_div &= ~0x00001FFF;
2971 fb_div >>= 1;
2972 clk_v >>= 6;
2973
2974 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2975 ret = -EINVAL;
2976 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2977 ret = -EINVAL;
2978 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2979 ret = -EINVAL;
2980 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2981 ret = -EINVAL;
2982
2983 if (ret)
2984 break;
2985
2986 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2987 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2988 spll_table->freq[i] = cpu_to_be32(tmp);
2989
2990 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2991 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2992 spll_table->ss[i] = cpu_to_be32(tmp);
2993
2994 sclk += 512;
2995 }
2996
2997
2998 if (!ret)
2999 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
3000 (u8 *)spll_table,
3001 sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
3002 si_pi->sram_end);
3003
3004 if (ret)
3005 ni_pi->enable_power_containment = false;
3006
3007 kfree(spll_table);
3008
3009 return ret;
3010 }
3011
3012 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3013 u16 vce_voltage)
3014 {
3015 u16 highest_leakage = 0;
3016 struct si_power_info *si_pi = si_get_pi(adev);
3017 int i;
3018
3019 for (i = 0; i < si_pi->leakage_voltage.count; i++){
3020 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3021 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3022 }
3023
3024 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3025 return highest_leakage;
3026
3027 return vce_voltage;
3028 }
3029
3030 static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3031 u32 evclk, u32 ecclk, u16 *voltage)
3032 {
3033 u32 i;
3034 int ret = -EINVAL;
3035 struct amdgpu_vce_clock_voltage_dependency_table *table =
3036 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3037
3038 if (((evclk == 0) && (ecclk == 0)) ||
3039 (table && (table->count == 0))) {
3040 *voltage = 0;
3041 return 0;
3042 }
3043
3044 for (i = 0; i < table->count; i++) {
3045 if ((evclk <= table->entries[i].evclk) &&
3046 (ecclk <= table->entries[i].ecclk)) {
3047 *voltage = table->entries[i].v;
3048 ret = 0;
3049 break;
3050 }
3051 }
3052
3053 /* if no match return the highest voltage */
3054 if (ret)
3055 *voltage = table->entries[table->count - 1].v;
3056
3057 *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3058
3059 return ret;
3060 }
3061
3062 static bool si_dpm_vblank_too_short(struct amdgpu_device *adev)
3063 {
3064
3065 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3066 /* we never hit the non-gddr5 limit so disable it */
3067 u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3068
3069 if (vblank_time < switch_limit)
3070 return true;
3071 else
3072 return false;
3073
3074 }
3075
3076 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3077 u32 arb_freq_src, u32 arb_freq_dest)
3078 {
3079 u32 mc_arb_dram_timing;
3080 u32 mc_arb_dram_timing2;
3081 u32 burst_time;
3082 u32 mc_cg_config;
3083
3084 switch (arb_freq_src) {
3085 case MC_CG_ARB_FREQ_F0:
3086 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
3087 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3088 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3089 break;
3090 case MC_CG_ARB_FREQ_F1:
3091 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
3092 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3093 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3094 break;
3095 case MC_CG_ARB_FREQ_F2:
3096 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
3097 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3098 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3099 break;
3100 case MC_CG_ARB_FREQ_F3:
3101 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
3102 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3103 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3104 break;
3105 default:
3106 return -EINVAL;
3107 }
3108
3109 switch (arb_freq_dest) {
3110 case MC_CG_ARB_FREQ_F0:
3111 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3112 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3113 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3114 break;
3115 case MC_CG_ARB_FREQ_F1:
3116 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3117 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3118 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3119 break;
3120 case MC_CG_ARB_FREQ_F2:
3121 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3122 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3123 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3124 break;
3125 case MC_CG_ARB_FREQ_F3:
3126 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3127 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3128 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3129 break;
3130 default:
3131 return -EINVAL;
3132 }
3133
3134 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3135 WREG32(MC_CG_CONFIG, mc_cg_config);
3136 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3137
3138 return 0;
3139 }
3140
3141 static void ni_update_current_ps(struct amdgpu_device *adev,
3142 struct amdgpu_ps *rps)
3143 {
3144 struct si_ps *new_ps = si_get_ps(rps);
3145 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3146 struct ni_power_info *ni_pi = ni_get_pi(adev);
3147
3148 eg_pi->current_rps = *rps;
3149 ni_pi->current_ps = *new_ps;
3150 eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3151 adev->pm.dpm.current_ps = &eg_pi->current_rps;
3152 }
3153
3154 static void ni_update_requested_ps(struct amdgpu_device *adev,
3155 struct amdgpu_ps *rps)
3156 {
3157 struct si_ps *new_ps = si_get_ps(rps);
3158 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3159 struct ni_power_info *ni_pi = ni_get_pi(adev);
3160
3161 eg_pi->requested_rps = *rps;
3162 ni_pi->requested_ps = *new_ps;
3163 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3164 adev->pm.dpm.requested_ps = &eg_pi->requested_rps;
3165 }
3166
3167 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3168 struct amdgpu_ps *new_ps,
3169 struct amdgpu_ps *old_ps)
3170 {
3171 struct si_ps *new_state = si_get_ps(new_ps);
3172 struct si_ps *current_state = si_get_ps(old_ps);
3173
3174 if ((new_ps->vclk == old_ps->vclk) &&
3175 (new_ps->dclk == old_ps->dclk))
3176 return;
3177
3178 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3179 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3180 return;
3181
3182 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3183 }
3184
3185 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3186 struct amdgpu_ps *new_ps,
3187 struct amdgpu_ps *old_ps)
3188 {
3189 struct si_ps *new_state = si_get_ps(new_ps);
3190 struct si_ps *current_state = si_get_ps(old_ps);
3191
3192 if ((new_ps->vclk == old_ps->vclk) &&
3193 (new_ps->dclk == old_ps->dclk))
3194 return;
3195
3196 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3197 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3198 return;
3199
3200 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3201 }
3202
3203 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3204 {
3205 unsigned int i;
3206
3207 for (i = 0; i < table->count; i++)
3208 if (voltage <= table->entries[i].value)
3209 return table->entries[i].value;
3210
3211 return table->entries[table->count - 1].value;
3212 }
3213
3214 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
3215 u32 max_clock, u32 requested_clock)
3216 {
3217 unsigned int i;
3218
3219 if ((clocks == NULL) || (clocks->count == 0))
3220 return (requested_clock < max_clock) ? requested_clock : max_clock;
3221
3222 for (i = 0; i < clocks->count; i++) {
3223 if (clocks->values[i] >= requested_clock)
3224 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3225 }
3226
3227 return (clocks->values[clocks->count - 1] < max_clock) ?
3228 clocks->values[clocks->count - 1] : max_clock;
3229 }
3230
3231 static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
3232 u32 max_mclk, u32 requested_mclk)
3233 {
3234 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3235 max_mclk, requested_mclk);
3236 }
3237
3238 static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
3239 u32 max_sclk, u32 requested_sclk)
3240 {
3241 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3242 max_sclk, requested_sclk);
3243 }
3244
3245 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3246 u32 *max_clock)
3247 {
3248 u32 i, clock = 0;
3249
3250 if ((table == NULL) || (table->count == 0)) {
3251 *max_clock = clock;
3252 return;
3253 }
3254
3255 for (i = 0; i < table->count; i++) {
3256 if (clock < table->entries[i].clk)
3257 clock = table->entries[i].clk;
3258 }
3259 *max_clock = clock;
3260 }
3261
3262 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
3263 u32 clock, u16 max_voltage, u16 *voltage)
3264 {
3265 u32 i;
3266
3267 if ((table == NULL) || (table->count == 0))
3268 return;
3269
3270 for (i= 0; i < table->count; i++) {
3271 if (clock <= table->entries[i].clk) {
3272 if (*voltage < table->entries[i].v)
3273 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3274 table->entries[i].v : max_voltage);
3275 return;
3276 }
3277 }
3278
3279 *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
3280 }
3281
3282 static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
3283 const struct amdgpu_clock_and_voltage_limits *max_limits,
3284 struct rv7xx_pl *pl)
3285 {
3286
3287 if ((pl->mclk == 0) || (pl->sclk == 0))
3288 return;
3289
3290 if (pl->mclk == pl->sclk)
3291 return;
3292
3293 if (pl->mclk > pl->sclk) {
3294 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3295 pl->sclk = btc_get_valid_sclk(adev,
3296 max_limits->sclk,
3297 (pl->mclk +
3298 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3299 adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3300 } else {
3301 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3302 pl->mclk = btc_get_valid_mclk(adev,
3303 max_limits->mclk,
3304 pl->sclk -
3305 adev->pm.dpm.dyn_state.sclk_mclk_delta);
3306 }
3307 }
3308
3309 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3310 u16 max_vddc, u16 max_vddci,
3311 u16 *vddc, u16 *vddci)
3312 {
3313 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3314 u16 new_voltage;
3315
3316 if ((0 == *vddc) || (0 == *vddci))
3317 return;
3318
3319 if (*vddc > *vddci) {
3320 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3321 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3322 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3323 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3324 }
3325 } else {
3326 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3327 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3328 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3329 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3330 }
3331 }
3332 }
3333
3334 static enum amdgpu_pcie_gen r600_get_pcie_gen_support(struct amdgpu_device *adev,
3335 u32 sys_mask,
3336 enum amdgpu_pcie_gen asic_gen,
3337 enum amdgpu_pcie_gen default_gen)
3338 {
3339 switch (asic_gen) {
3340 case AMDGPU_PCIE_GEN1:
3341 return AMDGPU_PCIE_GEN1;
3342 case AMDGPU_PCIE_GEN2:
3343 return AMDGPU_PCIE_GEN2;
3344 case AMDGPU_PCIE_GEN3:
3345 return AMDGPU_PCIE_GEN3;
3346 default:
3347 if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
3348 return AMDGPU_PCIE_GEN3;
3349 else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
3350 return AMDGPU_PCIE_GEN2;
3351 else
3352 return AMDGPU_PCIE_GEN1;
3353 }
3354 return AMDGPU_PCIE_GEN1;
3355 }
3356
3357 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3358 u32 *p, u32 *u)
3359 {
3360 u32 b_c = 0;
3361 u32 i_c;
3362 u32 tmp;
3363
3364 i_c = (i * r_c) / 100;
3365 tmp = i_c >> p_b;
3366
3367 while (tmp) {
3368 b_c++;
3369 tmp >>= 1;
3370 }
3371
3372 *u = (b_c + 1) / 2;
3373 *p = i_c / (1 << (2 * (*u)));
3374 }
3375
3376 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3377 {
3378 u32 k, a, ah, al;
3379 u32 t1;
3380
3381 if ((fl == 0) || (fh == 0) || (fl > fh))
3382 return -EINVAL;
3383
3384 k = (100 * fh) / fl;
3385 t1 = (t * (k - 100));
3386 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3387 a = (a + 5) / 10;
3388 ah = ((a * t) + 5000) / 10000;
3389 al = a - ah;
3390
3391 *th = t - ah;
3392 *tl = t + al;
3393
3394 return 0;
3395 }
3396
3397 static bool r600_is_uvd_state(u32 class, u32 class2)
3398 {
3399 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3400 return true;
3401 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3402 return true;
3403 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3404 return true;
3405 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3406 return true;
3407 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3408 return true;
3409 return false;
3410 }
3411
3412 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3413 {
3414 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3415 }
3416
3417 static void rv770_get_max_vddc(struct amdgpu_device *adev)
3418 {
3419 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3420 u16 vddc;
3421
3422 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3423 pi->max_vddc = 0;
3424 else
3425 pi->max_vddc = vddc;
3426 }
3427
3428 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3429 {
3430 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3431 struct amdgpu_atom_ss ss;
3432
3433 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3434 ASIC_INTERNAL_ENGINE_SS, 0);
3435 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3436 ASIC_INTERNAL_MEMORY_SS, 0);
3437
3438 if (pi->sclk_ss || pi->mclk_ss)
3439 pi->dynamic_ss = true;
3440 else
3441 pi->dynamic_ss = false;
3442 }
3443
3444
3445 static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3446 struct amdgpu_ps *rps)
3447 {
3448 struct si_ps *ps = si_get_ps(rps);
3449 struct amdgpu_clock_and_voltage_limits *max_limits;
3450 bool disable_mclk_switching = false;
3451 bool disable_sclk_switching = false;
3452 u32 mclk, sclk;
3453 u16 vddc, vddci, min_vce_voltage = 0;
3454 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3455 u32 max_sclk = 0, max_mclk = 0;
3456 int i;
3457
3458 if (adev->asic_type == CHIP_HAINAN) {
3459 if ((adev->pdev->revision == 0x81) ||
3460 (adev->pdev->revision == 0x83) ||
3461 (adev->pdev->revision == 0xC3) ||
3462 (adev->pdev->device == 0x6664) ||
3463 (adev->pdev->device == 0x6665) ||
3464 (adev->pdev->device == 0x6667)) {
3465 max_sclk = 75000;
3466 }
3467 } else if (adev->asic_type == CHIP_OLAND) {
3468 if ((adev->pdev->revision == 0xC7) ||
3469 (adev->pdev->revision == 0x80) ||
3470 (adev->pdev->revision == 0x81) ||
3471 (adev->pdev->revision == 0x83) ||
3472 (adev->pdev->revision == 0x87) ||
3473 (adev->pdev->device == 0x6604) ||
3474 (adev->pdev->device == 0x6605)) {
3475 max_sclk = 75000;
3476 }
3477 }
3478
3479 if (rps->vce_active) {
3480 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3481 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3482 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3483 &min_vce_voltage);
3484 } else {
3485 rps->evclk = 0;
3486 rps->ecclk = 0;
3487 }
3488
3489 if ((adev->pm.dpm.new_active_crtc_count > 1) ||
3490 si_dpm_vblank_too_short(adev))
3491 disable_mclk_switching = true;
3492
3493 if (rps->vclk || rps->dclk) {
3494 disable_mclk_switching = true;
3495 disable_sclk_switching = true;
3496 }
3497
3498 if (adev->pm.dpm.ac_power)
3499 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3500 else
3501 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3502
3503 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3504 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3505 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3506 }
3507 if (adev->pm.dpm.ac_power == false) {
3508 for (i = 0; i < ps->performance_level_count; i++) {
3509 if (ps->performance_levels[i].mclk > max_limits->mclk)
3510 ps->performance_levels[i].mclk = max_limits->mclk;
3511 if (ps->performance_levels[i].sclk > max_limits->sclk)
3512 ps->performance_levels[i].sclk = max_limits->sclk;
3513 if (ps->performance_levels[i].vddc > max_limits->vddc)
3514 ps->performance_levels[i].vddc = max_limits->vddc;
3515 if (ps->performance_levels[i].vddci > max_limits->vddci)
3516 ps->performance_levels[i].vddci = max_limits->vddci;
3517 }
3518 }
3519
3520 /* limit clocks to max supported clocks based on voltage dependency tables */
3521 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3522 &max_sclk_vddc);
3523 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3524 &max_mclk_vddci);
3525 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3526 &max_mclk_vddc);
3527
3528 for (i = 0; i < ps->performance_level_count; i++) {
3529 if (max_sclk_vddc) {
3530 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3531 ps->performance_levels[i].sclk = max_sclk_vddc;
3532 }
3533 if (max_mclk_vddci) {
3534 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3535 ps->performance_levels[i].mclk = max_mclk_vddci;
3536 }
3537 if (max_mclk_vddc) {
3538 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3539 ps->performance_levels[i].mclk = max_mclk_vddc;
3540 }
3541 if (max_mclk) {
3542 if (ps->performance_levels[i].mclk > max_mclk)
3543 ps->performance_levels[i].mclk = max_mclk;
3544 }
3545 if (max_sclk) {
3546 if (ps->performance_levels[i].sclk > max_sclk)
3547 ps->performance_levels[i].sclk = max_sclk;
3548 }
3549 }
3550
3551 /* XXX validate the min clocks required for display */
3552
3553 if (disable_mclk_switching) {
3554 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3555 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3556 } else {
3557 mclk = ps->performance_levels[0].mclk;
3558 vddci = ps->performance_levels[0].vddci;
3559 }
3560
3561 if (disable_sclk_switching) {
3562 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3563 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3564 } else {
3565 sclk = ps->performance_levels[0].sclk;
3566 vddc = ps->performance_levels[0].vddc;
3567 }
3568
3569 if (rps->vce_active) {
3570 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3571 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3572 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3573 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3574 }
3575
3576 /* adjusted low state */
3577 ps->performance_levels[0].sclk = sclk;
3578 ps->performance_levels[0].mclk = mclk;
3579 ps->performance_levels[0].vddc = vddc;
3580 ps->performance_levels[0].vddci = vddci;
3581
3582 if (disable_sclk_switching) {
3583 sclk = ps->performance_levels[0].sclk;
3584 for (i = 1; i < ps->performance_level_count; i++) {
3585 if (sclk < ps->performance_levels[i].sclk)
3586 sclk = ps->performance_levels[i].sclk;
3587 }
3588 for (i = 0; i < ps->performance_level_count; i++) {
3589 ps->performance_levels[i].sclk = sclk;
3590 ps->performance_levels[i].vddc = vddc;
3591 }
3592 } else {
3593 for (i = 1; i < ps->performance_level_count; i++) {
3594 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3595 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3596 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3597 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3598 }
3599 }
3600
3601 if (disable_mclk_switching) {
3602 mclk = ps->performance_levels[0].mclk;
3603 for (i = 1; i < ps->performance_level_count; i++) {
3604 if (mclk < ps->performance_levels[i].mclk)
3605 mclk = ps->performance_levels[i].mclk;
3606 }
3607 for (i = 0; i < ps->performance_level_count; i++) {
3608 ps->performance_levels[i].mclk = mclk;
3609 ps->performance_levels[i].vddci = vddci;
3610 }
3611 } else {
3612 for (i = 1; i < ps->performance_level_count; i++) {
3613 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3614 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3615 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3616 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3617 }
3618 }
3619
3620 for (i = 0; i < ps->performance_level_count; i++)
3621 btc_adjust_clock_combinations(adev, max_limits,
3622 &ps->performance_levels[i]);
3623
3624 for (i = 0; i < ps->performance_level_count; i++) {
3625 if (ps->performance_levels[i].vddc < min_vce_voltage)
3626 ps->performance_levels[i].vddc = min_vce_voltage;
3627 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3628 ps->performance_levels[i].sclk,
3629 max_limits->vddc, &ps->performance_levels[i].vddc);
3630 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3631 ps->performance_levels[i].mclk,
3632 max_limits->vddci, &ps->performance_levels[i].vddci);
3633 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3634 ps->performance_levels[i].mclk,
3635 max_limits->vddc, &ps->performance_levels[i].vddc);
3636 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3637 adev->clock.current_dispclk,
3638 max_limits->vddc, &ps->performance_levels[i].vddc);
3639 }
3640
3641 for (i = 0; i < ps->performance_level_count; i++) {
3642 btc_apply_voltage_delta_rules(adev,
3643 max_limits->vddc, max_limits->vddci,
3644 &ps->performance_levels[i].vddc,
3645 &ps->performance_levels[i].vddci);
3646 }
3647
3648 ps->dc_compatible = true;
3649 for (i = 0; i < ps->performance_level_count; i++) {
3650 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3651 ps->dc_compatible = false;
3652 }
3653 }
3654
3655 #if 0
3656 static int si_read_smc_soft_register(struct amdgpu_device *adev,
3657 u16 reg_offset, u32 *value)
3658 {
3659 struct si_power_info *si_pi = si_get_pi(adev);
3660
3661 return amdgpu_si_read_smc_sram_dword(adev,
3662 si_pi->soft_regs_start + reg_offset, value,
3663 si_pi->sram_end);
3664 }
3665 #endif
3666
3667 static int si_write_smc_soft_register(struct amdgpu_device *adev,
3668 u16 reg_offset, u32 value)
3669 {
3670 struct si_power_info *si_pi = si_get_pi(adev);
3671
3672 return amdgpu_si_write_smc_sram_dword(adev,
3673 si_pi->soft_regs_start + reg_offset,
3674 value, si_pi->sram_end);
3675 }
3676
3677 static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3678 {
3679 bool ret = false;
3680 u32 tmp, width, row, column, bank, density;
3681 bool is_memory_gddr5, is_special;
3682
3683 tmp = RREG32(MC_SEQ_MISC0);
3684 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3685 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3686 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3687
3688 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3689 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3690
3691 tmp = RREG32(MC_ARB_RAMCFG);
3692 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3693 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3694 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3695
3696 density = (1 << (row + column - 20 + bank)) * width;
3697
3698 if ((adev->pdev->device == 0x6819) &&
3699 is_memory_gddr5 && is_special && (density == 0x400))
3700 ret = true;
3701
3702 return ret;
3703 }
3704
3705 static void si_get_leakage_vddc(struct amdgpu_device *adev)
3706 {
3707 struct si_power_info *si_pi = si_get_pi(adev);
3708 u16 vddc, count = 0;
3709 int i, ret;
3710
3711 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3712 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3713
3714 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3715 si_pi->leakage_voltage.entries[count].voltage = vddc;
3716 si_pi->leakage_voltage.entries[count].leakage_index =
3717 SISLANDS_LEAKAGE_INDEX0 + i;
3718 count++;
3719 }
3720 }
3721 si_pi->leakage_voltage.count = count;
3722 }
3723
3724 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3725 u32 index, u16 *leakage_voltage)
3726 {
3727 struct si_power_info *si_pi = si_get_pi(adev);
3728 int i;
3729
3730 if (leakage_voltage == NULL)
3731 return -EINVAL;
3732
3733 if ((index & 0xff00) != 0xff00)
3734 return -EINVAL;
3735
3736 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3737 return -EINVAL;
3738
3739 if (index < SISLANDS_LEAKAGE_INDEX0)
3740 return -EINVAL;
3741
3742 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3743 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3744 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3745 return 0;
3746 }
3747 }
3748 return -EAGAIN;
3749 }
3750
3751 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3752 {
3753 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3754 bool want_thermal_protection;
3755 enum amdgpu_dpm_event_src dpm_event_src;
3756
3757 switch (sources) {
3758 case 0:
3759 default:
3760 want_thermal_protection = false;
3761 break;
3762 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
3763 want_thermal_protection = true;
3764 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
3765 break;
3766 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3767 want_thermal_protection = true;
3768 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
3769 break;
3770 case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3771 (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3772 want_thermal_protection = true;
3773 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3774 break;
3775 }
3776
3777 if (want_thermal_protection) {
3778 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3779 if (pi->thermal_protection)
3780 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3781 } else {
3782 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3783 }
3784 }
3785
3786 static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3787 enum amdgpu_dpm_auto_throttle_src source,
3788 bool enable)
3789 {
3790 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3791
3792 if (enable) {
3793 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3794 pi->active_auto_throttle_sources |= 1 << source;
3795 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3796 }
3797 } else {
3798 if (pi->active_auto_throttle_sources & (1 << source)) {
3799 pi->active_auto_throttle_sources &= ~(1 << source);
3800 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3801 }
3802 }
3803 }
3804
3805 static void si_start_dpm(struct amdgpu_device *adev)
3806 {
3807 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3808 }
3809
3810 static void si_stop_dpm(struct amdgpu_device *adev)
3811 {
3812 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3813 }
3814
3815 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3816 {
3817 if (enable)
3818 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3819 else
3820 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3821
3822 }
3823
3824 #if 0
3825 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3826 u32 thermal_level)
3827 {
3828 PPSMC_Result ret;
3829
3830 if (thermal_level == 0) {
3831 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3832 if (ret == PPSMC_Result_OK)
3833 return 0;
3834 else
3835 return -EINVAL;
3836 }
3837 return 0;
3838 }
3839
3840 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3841 {
3842 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3843 }
3844 #endif
3845
3846 #if 0
3847 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3848 {
3849 if (ac_power)
3850 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3851 0 : -EINVAL;
3852
3853 return 0;
3854 }
3855 #endif
3856
3857 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3858 PPSMC_Msg msg, u32 parameter)
3859 {
3860 WREG32(SMC_SCRATCH0, parameter);
3861 return amdgpu_si_send_msg_to_smc(adev, msg);
3862 }
3863
3864 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3865 {
3866 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3867 return -EINVAL;
3868
3869 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3870 0 : -EINVAL;
3871 }
3872
3873 static int si_dpm_force_performance_level(struct amdgpu_device *adev,
3874 enum amd_dpm_forced_level level)
3875 {
3876 struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3877 struct si_ps *ps = si_get_ps(rps);
3878 u32 levels = ps->performance_level_count;
3879
3880 if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
3881 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3882 return -EINVAL;
3883
3884 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3885 return -EINVAL;
3886 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
3887 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3888 return -EINVAL;
3889
3890 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3891 return -EINVAL;
3892 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
3893 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3894 return -EINVAL;
3895
3896 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3897 return -EINVAL;
3898 }
3899
3900 adev->pm.dpm.forced_level = level;
3901
3902 return 0;
3903 }
3904
3905 #if 0
3906 static int si_set_boot_state(struct amdgpu_device *adev)
3907 {
3908 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3909 0 : -EINVAL;
3910 }
3911 #endif
3912
3913 static int si_set_sw_state(struct amdgpu_device *adev)
3914 {
3915 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3916 0 : -EINVAL;
3917 }
3918
3919 static int si_halt_smc(struct amdgpu_device *adev)
3920 {
3921 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3922 return -EINVAL;
3923
3924 return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3925 0 : -EINVAL;
3926 }
3927
3928 static int si_resume_smc(struct amdgpu_device *adev)
3929 {
3930 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3931 return -EINVAL;
3932
3933 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3934 0 : -EINVAL;
3935 }
3936
3937 static void si_dpm_start_smc(struct amdgpu_device *adev)
3938 {
3939 amdgpu_si_program_jump_on_start(adev);
3940 amdgpu_si_start_smc(adev);
3941 amdgpu_si_smc_clock(adev, true);
3942 }
3943
3944 static void si_dpm_stop_smc(struct amdgpu_device *adev)
3945 {
3946 amdgpu_si_reset_smc(adev);
3947 amdgpu_si_smc_clock(adev, false);
3948 }
3949
3950 static int si_process_firmware_header(struct amdgpu_device *adev)
3951 {
3952 struct si_power_info *si_pi = si_get_pi(adev);
3953 u32 tmp;
3954 int ret;
3955
3956 ret = amdgpu_si_read_smc_sram_dword(adev,
3957 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3958 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3959 &tmp, si_pi->sram_end);
3960 if (ret)
3961 return ret;
3962
3963 si_pi->state_table_start = tmp;
3964
3965 ret = amdgpu_si_read_smc_sram_dword(adev,
3966 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3967 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3968 &tmp, si_pi->sram_end);
3969 if (ret)
3970 return ret;
3971
3972 si_pi->soft_regs_start = tmp;
3973
3974 ret = amdgpu_si_read_smc_sram_dword(adev,
3975 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3976 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3977 &tmp, si_pi->sram_end);
3978 if (ret)
3979 return ret;
3980
3981 si_pi->mc_reg_table_start = tmp;
3982
3983 ret = amdgpu_si_read_smc_sram_dword(adev,
3984 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3985 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3986 &tmp, si_pi->sram_end);
3987 if (ret)
3988 return ret;
3989
3990 si_pi->fan_table_start = tmp;
3991
3992 ret = amdgpu_si_read_smc_sram_dword(adev,
3993 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3994 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3995 &tmp, si_pi->sram_end);
3996 if (ret)
3997 return ret;
3998
3999 si_pi->arb_table_start = tmp;
4000
4001 ret = amdgpu_si_read_smc_sram_dword(adev,
4002 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4003 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
4004 &tmp, si_pi->sram_end);
4005 if (ret)
4006 return ret;
4007
4008 si_pi->cac_table_start = tmp;
4009
4010 ret = amdgpu_si_read_smc_sram_dword(adev,
4011 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4012 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
4013 &tmp, si_pi->sram_end);
4014 if (ret)
4015 return ret;
4016
4017 si_pi->dte_table_start = tmp;
4018
4019 ret = amdgpu_si_read_smc_sram_dword(adev,
4020 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4021 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
4022 &tmp, si_pi->sram_end);
4023 if (ret)
4024 return ret;
4025
4026 si_pi->spll_table_start = tmp;
4027
4028 ret = amdgpu_si_read_smc_sram_dword(adev,
4029 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4030 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4031 &tmp, si_pi->sram_end);
4032 if (ret)
4033 return ret;
4034
4035 si_pi->papm_cfg_table_start = tmp;
4036
4037 return ret;
4038 }
4039
4040 static void si_read_clock_registers(struct amdgpu_device *adev)
4041 {
4042 struct si_power_info *si_pi = si_get_pi(adev);
4043
4044 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4045 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4046 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4047 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
4048 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
4049 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
4050 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4051 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4052 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4053 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4054 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4055 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4056 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4057 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4058 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4059 }
4060
4061 static void si_enable_thermal_protection(struct amdgpu_device *adev,
4062 bool enable)
4063 {
4064 if (enable)
4065 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
4066 else
4067 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
4068 }
4069
4070 static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4071 {
4072 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
4073 }
4074
4075 #if 0
4076 static int si_enter_ulp_state(struct amdgpu_device *adev)
4077 {
4078 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4079
4080 udelay(25000);
4081
4082 return 0;
4083 }
4084
4085 static int si_exit_ulp_state(struct amdgpu_device *adev)
4086 {
4087 int i;
4088
4089 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4090
4091 udelay(7000);
4092
4093 for (i = 0; i < adev->usec_timeout; i++) {
4094 if (RREG32(SMC_RESP_0) == 1)
4095 break;
4096 udelay(1000);
4097 }
4098
4099 return 0;
4100 }
4101 #endif
4102
4103 static int si_notify_smc_display_change(struct amdgpu_device *adev,
4104 bool has_display)
4105 {
4106 PPSMC_Msg msg = has_display ?
4107 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4108
4109 return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4110 0 : -EINVAL;
4111 }
4112
4113 static void si_program_response_times(struct amdgpu_device *adev)
4114 {
4115 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
4116 u32 vddc_dly, acpi_dly, vbi_dly;
4117 u32 reference_clock;
4118
4119 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4120
4121 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
4122 backbias_response_time = (u32)adev->pm.dpm.backbias_response_time;
4123
4124 if (voltage_response_time == 0)
4125 voltage_response_time = 1000;
4126
4127 acpi_delay_time = 15000;
4128 vbi_time_out = 100000;
4129
4130 reference_clock = amdgpu_asic_get_xclk(adev);
4131
4132 vddc_dly = (voltage_response_time * reference_clock) / 100;
4133 acpi_dly = (acpi_delay_time * reference_clock) / 100;
4134 vbi_dly = (vbi_time_out * reference_clock) / 100;
4135
4136 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
4137 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
4138 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4139 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4140 }
4141
4142 static void si_program_ds_registers(struct amdgpu_device *adev)
4143 {
4144 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4145 u32 tmp;
4146
4147 /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4148 if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4149 tmp = 0x10;
4150 else
4151 tmp = 0x1;
4152
4153 if (eg_pi->sclk_deep_sleep) {
4154 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
4155 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
4156 ~AUTOSCALE_ON_SS_CLEAR);
4157 }
4158 }
4159
4160 static void si_program_display_gap(struct amdgpu_device *adev)
4161 {
4162 u32 tmp, pipe;
4163 int i;
4164
4165 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4166 if (adev->pm.dpm.new_active_crtc_count > 0)
4167 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4168 else
4169 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4170
4171 if (adev->pm.dpm.new_active_crtc_count > 1)
4172 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4173 else
4174 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4175
4176 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4177
4178 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4179 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4180
4181 if ((adev->pm.dpm.new_active_crtc_count > 0) &&
4182 (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
4183 /* find the first active crtc */
4184 for (i = 0; i < adev->mode_info.num_crtc; i++) {
4185 if (adev->pm.dpm.new_active_crtcs & (1 << i))
4186 break;
4187 }
4188 if (i == adev->mode_info.num_crtc)
4189 pipe = 0;
4190 else
4191 pipe = i;
4192
4193 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4194 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4195 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4196 }
4197
4198 /* Setting this to false forces the performance state to low if the crtcs are disabled.
4199 * This can be a problem on PowerXpress systems or if you want to use the card
4200 * for offscreen rendering or compute if there are no crtcs enabled.
4201 */
4202 si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0);
4203 }
4204
4205 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4206 {
4207 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4208
4209 if (enable) {
4210 if (pi->sclk_ss)
4211 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
4212 } else {
4213 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
4214 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
4215 }
4216 }
4217
4218 static void si_setup_bsp(struct amdgpu_device *adev)
4219 {
4220 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4221 u32 xclk = amdgpu_asic_get_xclk(adev);
4222
4223 r600_calculate_u_and_p(pi->asi,
4224 xclk,
4225 16,
4226 &pi->bsp,
4227 &pi->bsu);
4228
4229 r600_calculate_u_and_p(pi->pasi,
4230 xclk,
4231 16,
4232 &pi->pbsp,
4233 &pi->pbsu);
4234
4235
4236 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
4237 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
4238
4239 WREG32(CG_BSP, pi->dsp);
4240 }
4241
4242 static void si_program_git(struct amdgpu_device *adev)
4243 {
4244 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
4245 }
4246
4247 static void si_program_tp(struct amdgpu_device *adev)
4248 {
4249 int i;
4250 enum r600_td td = R600_TD_DFLT;
4251
4252 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4253 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
4254
4255 if (td == R600_TD_AUTO)
4256 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4257 else
4258 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4259
4260 if (td == R600_TD_UP)
4261 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4262
4263 if (td == R600_TD_DOWN)
4264 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
4265 }
4266
4267 static void si_program_tpp(struct amdgpu_device *adev)
4268 {
4269 WREG32(CG_TPC, R600_TPC_DFLT);
4270 }
4271
4272 static void si_program_sstp(struct amdgpu_device *adev)
4273 {
4274 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
4275 }
4276
4277 static void si_enable_display_gap(struct amdgpu_device *adev)
4278 {
4279 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
4280
4281 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4282 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
4283 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
4284
4285 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
4286 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
4287 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
4288 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4289 }
4290
4291 static void si_program_vc(struct amdgpu_device *adev)
4292 {
4293 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4294
4295 WREG32(CG_FTV, pi->vrc);
4296 }
4297
4298 static void si_clear_vc(struct amdgpu_device *adev)
4299 {
4300 WREG32(CG_FTV, 0);
4301 }
4302
4303 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
4304 {
4305 u8 mc_para_index;
4306
4307 if (memory_clock < 10000)
4308 mc_para_index = 0;
4309 else if (memory_clock >= 80000)
4310 mc_para_index = 0x0f;
4311 else
4312 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4313 return mc_para_index;
4314 }
4315
4316 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
4317 {
4318 u8 mc_para_index;
4319
4320 if (strobe_mode) {
4321 if (memory_clock < 12500)
4322 mc_para_index = 0x00;
4323 else if (memory_clock > 47500)
4324 mc_para_index = 0x0f;
4325 else
4326 mc_para_index = (u8)((memory_clock - 10000) / 2500);
4327 } else {
4328 if (memory_clock < 65000)
4329 mc_para_index = 0x00;
4330 else if (memory_clock > 135000)
4331 mc_para_index = 0x0f;
4332 else
4333 mc_para_index = (u8)((memory_clock - 60000) / 5000);
4334 }
4335 return mc_para_index;
4336 }
4337
4338 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4339 {
4340 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4341 bool strobe_mode = false;
4342 u8 result = 0;
4343
4344 if (mclk <= pi->mclk_strobe_mode_threshold)
4345 strobe_mode = true;
4346
4347 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4348 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4349 else
4350 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4351
4352 if (strobe_mode)
4353 result |= SISLANDS_SMC_STROBE_ENABLE;
4354
4355 return result;
4356 }
4357
4358 static int si_upload_firmware(struct amdgpu_device *adev)
4359 {
4360 struct si_power_info *si_pi = si_get_pi(adev);
4361
4362 amdgpu_si_reset_smc(adev);
4363 amdgpu_si_smc_clock(adev, false);
4364
4365 return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
4366 }
4367
4368 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4369 const struct atom_voltage_table *table,
4370 const struct amdgpu_phase_shedding_limits_table *limits)
4371 {
4372 u32 data, num_bits, num_levels;
4373
4374 if ((table == NULL) || (limits == NULL))
4375 return false;
4376
4377 data = table->mask_low;
4378
4379 num_bits = hweight32(data);
4380
4381 if (num_bits == 0)
4382 return false;
4383
4384 num_levels = (1 << num_bits);
4385
4386 if (table->count != num_levels)
4387 return false;
4388
4389 if (limits->count != (num_levels - 1))
4390 return false;
4391
4392 return true;
4393 }
4394
4395 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4396 u32 max_voltage_steps,
4397 struct atom_voltage_table *voltage_table)
4398 {
4399 unsigned int i, diff;
4400
4401 if (voltage_table->count <= max_voltage_steps)
4402 return;
4403
4404 diff = voltage_table->count - max_voltage_steps;
4405
4406 for (i= 0; i < max_voltage_steps; i++)
4407 voltage_table->entries[i] = voltage_table->entries[i + diff];
4408
4409 voltage_table->count = max_voltage_steps;
4410 }
4411
4412 static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4413 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4414 struct atom_voltage_table *voltage_table)
4415 {
4416 u32 i;
4417
4418 if (voltage_dependency_table == NULL)
4419 return -EINVAL;
4420
4421 voltage_table->mask_low = 0;
4422 voltage_table->phase_delay = 0;
4423
4424 voltage_table->count = voltage_dependency_table->count;
4425 for (i = 0; i < voltage_table->count; i++) {
4426 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4427 voltage_table->entries[i].smio_low = 0;
4428 }
4429
4430 return 0;
4431 }
4432
4433 static int si_construct_voltage_tables(struct amdgpu_device *adev)
4434 {
4435 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4436 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4437 struct si_power_info *si_pi = si_get_pi(adev);
4438 int ret;
4439
4440 if (pi->voltage_control) {
4441 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4442 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4443 if (ret)
4444 return ret;
4445
4446 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4447 si_trim_voltage_table_to_fit_state_table(adev,
4448 SISLANDS_MAX_NO_VREG_STEPS,
4449 &eg_pi->vddc_voltage_table);
4450 } else if (si_pi->voltage_control_svi2) {
4451 ret = si_get_svi2_voltage_table(adev,
4452 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4453 &eg_pi->vddc_voltage_table);
4454 if (ret)
4455 return ret;
4456 } else {
4457 return -EINVAL;
4458 }
4459
4460 if (eg_pi->vddci_control) {
4461 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4462 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4463 if (ret)
4464 return ret;
4465
4466 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4467 si_trim_voltage_table_to_fit_state_table(adev,
4468 SISLANDS_MAX_NO_VREG_STEPS,
4469 &eg_pi->vddci_voltage_table);
4470 }
4471 if (si_pi->vddci_control_svi2) {
4472 ret = si_get_svi2_voltage_table(adev,
4473 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4474 &eg_pi->vddci_voltage_table);
4475 if (ret)
4476 return ret;
4477 }
4478
4479 if (pi->mvdd_control) {
4480 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4481 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4482
4483 if (ret) {
4484 pi->mvdd_control = false;
4485 return ret;
4486 }
4487
4488 if (si_pi->mvdd_voltage_table.count == 0) {
4489 pi->mvdd_control = false;
4490 return -EINVAL;
4491 }
4492
4493 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4494 si_trim_voltage_table_to_fit_state_table(adev,
4495 SISLANDS_MAX_NO_VREG_STEPS,
4496 &si_pi->mvdd_voltage_table);
4497 }
4498
4499 if (si_pi->vddc_phase_shed_control) {
4500 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4501 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4502 if (ret)
4503 si_pi->vddc_phase_shed_control = false;
4504
4505 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4506 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4507 si_pi->vddc_phase_shed_control = false;
4508 }
4509
4510 return 0;
4511 }
4512
4513 static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4514 const struct atom_voltage_table *voltage_table,
4515 SISLANDS_SMC_STATETABLE *table)
4516 {
4517 unsigned int i;
4518
4519 for (i = 0; i < voltage_table->count; i++)
4520 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4521 }
4522
4523 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4524 SISLANDS_SMC_STATETABLE *table)
4525 {
4526 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4527 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4528 struct si_power_info *si_pi = si_get_pi(adev);
4529 u8 i;
4530
4531 if (si_pi->voltage_control_svi2) {
4532 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4533 si_pi->svc_gpio_id);
4534 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4535 si_pi->svd_gpio_id);
4536 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4537 2);
4538 } else {
4539 if (eg_pi->vddc_voltage_table.count) {
4540 si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4541 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4542 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4543
4544 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4545 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4546 table->maxVDDCIndexInPPTable = i;
4547 break;
4548 }
4549 }
4550 }
4551
4552 if (eg_pi->vddci_voltage_table.count) {
4553 si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4554
4555 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4556 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4557 }
4558
4559
4560 if (si_pi->mvdd_voltage_table.count) {
4561 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4562
4563 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4564 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4565 }
4566
4567 if (si_pi->vddc_phase_shed_control) {
4568 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4569 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4570 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4571
4572 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4573 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4574
4575 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4576 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4577 } else {
4578 si_pi->vddc_phase_shed_control = false;
4579 }
4580 }
4581 }
4582
4583 return 0;
4584 }
4585
4586 static int si_populate_voltage_value(struct amdgpu_device *adev,
4587 const struct atom_voltage_table *table,
4588 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4589 {
4590 unsigned int i;
4591
4592 for (i = 0; i < table->count; i++) {
4593 if (value <= table->entries[i].value) {
4594 voltage->index = (u8)i;
4595 voltage->value = cpu_to_be16(table->entries[i].value);
4596 break;
4597 }
4598 }
4599
4600 if (i >= table->count)
4601 return -EINVAL;
4602
4603 return 0;
4604 }
4605
4606 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4607 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4608 {
4609 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4610 struct si_power_info *si_pi = si_get_pi(adev);
4611
4612 if (pi->mvdd_control) {
4613 if (mclk <= pi->mvdd_split_frequency)
4614 voltage->index = 0;
4615 else
4616 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4617
4618 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4619 }
4620 return 0;
4621 }
4622
4623 static int si_get_std_voltage_value(struct amdgpu_device *adev,
4624 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4625 u16 *std_voltage)
4626 {
4627 u16 v_index;
4628 bool voltage_found = false;
4629 *std_voltage = be16_to_cpu(voltage->value);
4630
4631 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4632 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4633 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4634 return -EINVAL;
4635
4636 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4637 if (be16_to_cpu(voltage->value) ==
4638 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4639 voltage_found = true;
4640 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4641 *std_voltage =
4642 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4643 else
4644 *std_voltage =
4645 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4646 break;
4647 }
4648 }
4649
4650 if (!voltage_found) {
4651 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4652 if (be16_to_cpu(voltage->value) <=
4653 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4654 voltage_found = true;
4655 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4656 *std_voltage =
4657 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4658 else
4659 *std_voltage =
4660 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4661 break;
4662 }
4663 }
4664 }
4665 } else {
4666 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4667 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4668 }
4669 }
4670
4671 return 0;
4672 }
4673
4674 static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4675 u16 value, u8 index,
4676 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4677 {
4678 voltage->index = index;
4679 voltage->value = cpu_to_be16(value);
4680
4681 return 0;
4682 }
4683
4684 static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4685 const struct amdgpu_phase_shedding_limits_table *limits,
4686 u16 voltage, u32 sclk, u32 mclk,
4687 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4688 {
4689 unsigned int i;
4690
4691 for (i = 0; i < limits->count; i++) {
4692 if ((voltage <= limits->entries[i].voltage) &&
4693 (sclk <= limits->entries[i].sclk) &&
4694 (mclk <= limits->entries[i].mclk))
4695 break;
4696 }
4697
4698 smc_voltage->phase_settings = (u8)i;
4699
4700 return 0;
4701 }
4702
4703 static int si_init_arb_table_index(struct amdgpu_device *adev)
4704 {
4705 struct si_power_info *si_pi = si_get_pi(adev);
4706 u32 tmp;
4707 int ret;
4708
4709 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4710 &tmp, si_pi->sram_end);
4711 if (ret)
4712 return ret;
4713
4714 tmp &= 0x00FFFFFF;
4715 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4716
4717 return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4718 tmp, si_pi->sram_end);
4719 }
4720
4721 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4722 {
4723 return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4724 }
4725
4726 static int si_reset_to_default(struct amdgpu_device *adev)
4727 {
4728 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4729 0 : -EINVAL;
4730 }
4731
4732 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4733 {
4734 struct si_power_info *si_pi = si_get_pi(adev);
4735 u32 tmp;
4736 int ret;
4737
4738 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4739 &tmp, si_pi->sram_end);
4740 if (ret)
4741 return ret;
4742
4743 tmp = (tmp >> 24) & 0xff;
4744
4745 if (tmp == MC_CG_ARB_FREQ_F0)
4746 return 0;
4747
4748 return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4749 }
4750
4751 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4752 u32 engine_clock)
4753 {
4754 u32 dram_rows;
4755 u32 dram_refresh_rate;
4756 u32 mc_arb_rfsh_rate;
4757 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4758
4759 if (tmp >= 4)
4760 dram_rows = 16384;
4761 else
4762 dram_rows = 1 << (tmp + 10);
4763
4764 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4765 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4766
4767 return mc_arb_rfsh_rate;
4768 }
4769
4770 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4771 struct rv7xx_pl *pl,
4772 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4773 {
4774 u32 dram_timing;
4775 u32 dram_timing2;
4776 u32 burst_time;
4777
4778 arb_regs->mc_arb_rfsh_rate =
4779 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4780
4781 amdgpu_atombios_set_engine_dram_timings(adev,
4782 pl->sclk,
4783 pl->mclk);
4784
4785 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4786 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4787 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4788
4789 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4790 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4791 arb_regs->mc_arb_burst_time = (u8)burst_time;
4792
4793 return 0;
4794 }
4795
4796 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4797 struct amdgpu_ps *amdgpu_state,
4798 unsigned int first_arb_set)
4799 {
4800 struct si_power_info *si_pi = si_get_pi(adev);
4801 struct si_ps *state = si_get_ps(amdgpu_state);
4802 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4803 int i, ret = 0;
4804
4805 for (i = 0; i < state->performance_level_count; i++) {
4806 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4807 if (ret)
4808 break;
4809 ret = amdgpu_si_copy_bytes_to_smc(adev,
4810 si_pi->arb_table_start +
4811 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4812 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4813 (u8 *)&arb_regs,
4814 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4815 si_pi->sram_end);
4816 if (ret)
4817 break;
4818 }
4819
4820 return ret;
4821 }
4822
4823 static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4824 struct amdgpu_ps *amdgpu_new_state)
4825 {
4826 return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4827 SISLANDS_DRIVER_STATE_ARB_INDEX);
4828 }
4829
4830 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4831 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4832 {
4833 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4834 struct si_power_info *si_pi = si_get_pi(adev);
4835
4836 if (pi->mvdd_control)
4837 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4838 si_pi->mvdd_bootup_value, voltage);
4839
4840 return 0;
4841 }
4842
4843 static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4844 struct amdgpu_ps *amdgpu_initial_state,
4845 SISLANDS_SMC_STATETABLE *table)
4846 {
4847 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4848 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4849 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4850 struct si_power_info *si_pi = si_get_pi(adev);
4851 u32 reg;
4852 int ret;
4853
4854 table->initialState.levels[0].mclk.vDLL_CNTL =
4855 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4856 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4857 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4858 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4859 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4860 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4861 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4862 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4863 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4864 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4865 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4866 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4867 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4868 table->initialState.levels[0].mclk.vMPLL_SS =
4869 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4870 table->initialState.levels[0].mclk.vMPLL_SS2 =
4871 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4872
4873 table->initialState.levels[0].mclk.mclk_value =
4874 cpu_to_be32(initial_state->performance_levels[0].mclk);
4875
4876 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4877 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4878 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4879 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4880 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4881 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4882 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4883 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4884 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4885 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4886 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4887 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4888
4889 table->initialState.levels[0].sclk.sclk_value =
4890 cpu_to_be32(initial_state->performance_levels[0].sclk);
4891
4892 table->initialState.levels[0].arbRefreshState =
4893 SISLANDS_INITIAL_STATE_ARB_INDEX;
4894
4895 table->initialState.levels[0].ACIndex = 0;
4896
4897 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4898 initial_state->performance_levels[0].vddc,
4899 &table->initialState.levels[0].vddc);
4900
4901 if (!ret) {
4902 u16 std_vddc;
4903
4904 ret = si_get_std_voltage_value(adev,
4905 &table->initialState.levels[0].vddc,
4906 &std_vddc);
4907 if (!ret)
4908 si_populate_std_voltage_value(adev, std_vddc,
4909 table->initialState.levels[0].vddc.index,
4910 &table->initialState.levels[0].std_vddc);
4911 }
4912
4913 if (eg_pi->vddci_control)
4914 si_populate_voltage_value(adev,
4915 &eg_pi->vddci_voltage_table,
4916 initial_state->performance_levels[0].vddci,
4917 &table->initialState.levels[0].vddci);
4918
4919 if (si_pi->vddc_phase_shed_control)
4920 si_populate_phase_shedding_value(adev,
4921 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4922 initial_state->performance_levels[0].vddc,
4923 initial_state->performance_levels[0].sclk,
4924 initial_state->performance_levels[0].mclk,
4925 &table->initialState.levels[0].vddc);
4926
4927 si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);
4928
4929 reg = CG_R(0xffff) | CG_L(0);
4930 table->initialState.levels[0].aT = cpu_to_be32(reg);
4931 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4932 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4933
4934 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4935 table->initialState.levels[0].strobeMode =
4936 si_get_strobe_mode_settings(adev,
4937 initial_state->performance_levels[0].mclk);
4938
4939 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4940 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4941 else
4942 table->initialState.levels[0].mcFlags = 0;
4943 }
4944
4945 table->initialState.levelCount = 1;
4946
4947 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4948
4949 table->initialState.levels[0].dpm2.MaxPS = 0;
4950 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4951 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4952 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4953 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4954
4955 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4956 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4957
4958 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4959 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4960
4961 return 0;
4962 }
4963
4964 static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
4965 SISLANDS_SMC_STATETABLE *table)
4966 {
4967 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4968 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4969 struct si_power_info *si_pi = si_get_pi(adev);
4970 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4971 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4972 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4973 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4974 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4975 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4976 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4977 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4978 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4979 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4980 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4981 u32 reg;
4982 int ret;
4983
4984 table->ACPIState = table->initialState;
4985
4986 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4987
4988 if (pi->acpi_vddc) {
4989 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4990 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4991 if (!ret) {
4992 u16 std_vddc;
4993
4994 ret = si_get_std_voltage_value(adev,
4995 &table->ACPIState.levels[0].vddc, &std_vddc);
4996 if (!ret)
4997 si_populate_std_voltage_value(adev, std_vddc,
4998 table->ACPIState.levels[0].vddc.index,
4999 &table->ACPIState.levels[0].std_vddc);
5000 }
5001 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
5002
5003 if (si_pi->vddc_phase_shed_control) {
5004 si_populate_phase_shedding_value(adev,
5005 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5006 pi->acpi_vddc,
5007 0,
5008 0,
5009 &table->ACPIState.levels[0].vddc);
5010 }
5011 } else {
5012 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5013 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
5014 if (!ret) {
5015 u16 std_vddc;
5016
5017 ret = si_get_std_voltage_value(adev,
5018 &table->ACPIState.levels[0].vddc, &std_vddc);
5019
5020 if (!ret)
5021 si_populate_std_voltage_value(adev, std_vddc,
5022 table->ACPIState.levels[0].vddc.index,
5023 &table->ACPIState.levels[0].std_vddc);
5024 }
5025 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(adev,
5026 si_pi->sys_pcie_mask,
5027 si_pi->boot_pcie_gen,
5028 AMDGPU_PCIE_GEN1);
5029
5030 if (si_pi->vddc_phase_shed_control)
5031 si_populate_phase_shedding_value(adev,
5032 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5033 pi->min_vddc_in_table,
5034 0,
5035 0,
5036 &table->ACPIState.levels[0].vddc);
5037 }
5038
5039 if (pi->acpi_vddc) {
5040 if (eg_pi->acpi_vddci)
5041 si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5042 eg_pi->acpi_vddci,
5043 &table->ACPIState.levels[0].vddci);
5044 }
5045
5046 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5047 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5048
5049 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5050
5051 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5052 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
5053
5054 table->ACPIState.levels[0].mclk.vDLL_CNTL =
5055 cpu_to_be32(dll_cntl);
5056 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
5057 cpu_to_be32(mclk_pwrmgt_cntl);
5058 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
5059 cpu_to_be32(mpll_ad_func_cntl);
5060 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
5061 cpu_to_be32(mpll_dq_func_cntl);
5062 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
5063 cpu_to_be32(mpll_func_cntl);
5064 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
5065 cpu_to_be32(mpll_func_cntl_1);
5066 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
5067 cpu_to_be32(mpll_func_cntl_2);
5068 table->ACPIState.levels[0].mclk.vMPLL_SS =
5069 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5070 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
5071 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5072
5073 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
5074 cpu_to_be32(spll_func_cntl);
5075 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
5076 cpu_to_be32(spll_func_cntl_2);
5077 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
5078 cpu_to_be32(spll_func_cntl_3);
5079 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
5080 cpu_to_be32(spll_func_cntl_4);
5081
5082 table->ACPIState.levels[0].mclk.mclk_value = 0;
5083 table->ACPIState.levels[0].sclk.sclk_value = 0;
5084
5085 si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);
5086
5087 if (eg_pi->dynamic_ac_timing)
5088 table->ACPIState.levels[0].ACIndex = 0;
5089
5090 table->ACPIState.levels[0].dpm2.MaxPS = 0;
5091 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
5092 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
5093 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
5094 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5095
5096 reg = MIN_POWER_MASK | MAX_POWER_MASK;
5097 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5098
5099 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5100 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5101
5102 return 0;
5103 }
5104
5105 static int si_populate_ulv_state(struct amdgpu_device *adev,
5106 SISLANDS_SMC_SWSTATE *state)
5107 {
5108 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5109 struct si_power_info *si_pi = si_get_pi(adev);
5110 struct si_ulv_param *ulv = &si_pi->ulv;
5111 u32 sclk_in_sr = 1350; /* ??? */
5112 int ret;
5113
5114 ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5115 &state->levels[0]);
5116 if (!ret) {
5117 if (eg_pi->sclk_deep_sleep) {
5118 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5119 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5120 else
5121 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5122 }
5123 if (ulv->one_pcie_lane_in_ulv)
5124 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5125 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5126 state->levels[0].ACIndex = 1;
5127 state->levels[0].std_vddc = state->levels[0].vddc;
5128 state->levelCount = 1;
5129
5130 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5131 }
5132
5133 return ret;
5134 }
5135
5136 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5137 {
5138 struct si_power_info *si_pi = si_get_pi(adev);
5139 struct si_ulv_param *ulv = &si_pi->ulv;
5140 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5141 int ret;
5142
5143 ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5144 &arb_regs);
5145 if (ret)
5146 return ret;
5147
5148 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5149 ulv->volt_change_delay);
5150
5151 ret = amdgpu_si_copy_bytes_to_smc(adev,
5152 si_pi->arb_table_start +
5153 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5154 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5155 (u8 *)&arb_regs,
5156 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5157 si_pi->sram_end);
5158
5159 return ret;
5160 }
5161
5162 static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5163 {
5164 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5165
5166 pi->mvdd_split_frequency = 30000;
5167 }
5168
5169 static int si_init_smc_table(struct amdgpu_device *adev)
5170 {
5171 struct si_power_info *si_pi = si_get_pi(adev);
5172 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5173 const struct si_ulv_param *ulv = &si_pi->ulv;
5174 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
5175 int ret;
5176 u32 lane_width;
5177 u32 vr_hot_gpio;
5178
5179 si_populate_smc_voltage_tables(adev, table);
5180
5181 switch (adev->pm.int_thermal_type) {
5182 case THERMAL_TYPE_SI:
5183 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5184 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5185 break;
5186 case THERMAL_TYPE_NONE:
5187 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5188 break;
5189 default:
5190 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5191 break;
5192 }
5193
5194 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5195 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5196
5197 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5198 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5199 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5200 }
5201
5202 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5203 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5204
5205 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5206 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5207
5208 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5209 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5210
5211 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5212 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5213 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5214 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5215 vr_hot_gpio);
5216 }
5217
5218 ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5219 if (ret)
5220 return ret;
5221
5222 ret = si_populate_smc_acpi_state(adev, table);
5223 if (ret)
5224 return ret;
5225
5226 table->driverState = table->initialState;
5227
5228 ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5229 SISLANDS_INITIAL_STATE_ARB_INDEX);
5230 if (ret)
5231 return ret;
5232
5233 if (ulv->supported && ulv->pl.vddc) {
5234 ret = si_populate_ulv_state(adev, &table->ULVState);
5235 if (ret)
5236 return ret;
5237
5238 ret = si_program_ulv_memory_timing_parameters(adev);
5239 if (ret)
5240 return ret;
5241
5242 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
5243 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5244
5245 lane_width = amdgpu_get_pcie_lanes(adev);
5246 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5247 } else {
5248 table->ULVState = table->initialState;
5249 }
5250
5251 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5252 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5253 si_pi->sram_end);
5254 }
5255
5256 static int si_calculate_sclk_params(struct amdgpu_device *adev,
5257 u32 engine_clock,
5258 SISLANDS_SMC_SCLK_VALUE *sclk)
5259 {
5260 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5261 struct si_power_info *si_pi = si_get_pi(adev);
5262 struct atom_clock_dividers dividers;
5263 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5264 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5265 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5266 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5267 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5268 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5269 u64 tmp;
5270 u32 reference_clock = adev->clock.spll.reference_freq;
5271 u32 reference_divider;
5272 u32 fbdiv;
5273 int ret;
5274
5275 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5276 engine_clock, false, &dividers);
5277 if (ret)
5278 return ret;
5279
5280 reference_divider = 1 + dividers.ref_div;
5281
5282 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5283 do_div(tmp, reference_clock);
5284 fbdiv = (u32) tmp;
5285
5286 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
5287 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
5288 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
5289
5290 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5291 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
5292
5293 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
5294 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
5295 spll_func_cntl_3 |= SPLL_DITHEN;
5296
5297 if (pi->sclk_ss) {
5298 struct amdgpu_atom_ss ss;
5299 u32 vco_freq = engine_clock * dividers.post_div;
5300
5301 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5302 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5303 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5304 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5305
5306 cg_spll_spread_spectrum &= ~CLK_S_MASK;
5307 cg_spll_spread_spectrum |= CLK_S(clk_s);
5308 cg_spll_spread_spectrum |= SSEN;
5309
5310 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
5311 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
5312 }
5313 }
5314
5315 sclk->sclk_value = engine_clock;
5316 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5317 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5318 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5319 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5320 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5321 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5322
5323 return 0;
5324 }
5325
5326 static int si_populate_sclk_value(struct amdgpu_device *adev,
5327 u32 engine_clock,
5328 SISLANDS_SMC_SCLK_VALUE *sclk)
5329 {
5330 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5331 int ret;
5332
5333 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5334 if (!ret) {
5335 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5336 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5337 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5338 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5339 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5340 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5341 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5342 }
5343
5344 return ret;
5345 }
5346
5347 static int si_populate_mclk_value(struct amdgpu_device *adev,
5348 u32 engine_clock,
5349 u32 memory_clock,
5350 SISLANDS_SMC_MCLK_VALUE *mclk,
5351 bool strobe_mode,
5352 bool dll_state_on)
5353 {
5354 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5355 struct si_power_info *si_pi = si_get_pi(adev);
5356 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5357 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5358 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5359 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5360 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5361 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5362 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5363 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5364 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5365 struct atom_mpll_param mpll_param;
5366 int ret;
5367
5368 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5369 if (ret)
5370 return ret;
5371
5372 mpll_func_cntl &= ~BWCTRL_MASK;
5373 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5374
5375 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5376 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5377 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5378
5379 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5380 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5381
5382 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5383 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5384 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5385 YCLK_POST_DIV(mpll_param.post_div);
5386 }
5387
5388 if (pi->mclk_ss) {
5389 struct amdgpu_atom_ss ss;
5390 u32 freq_nom;
5391 u32 tmp;
5392 u32 reference_clock = adev->clock.mpll.reference_freq;
5393
5394 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5395 freq_nom = memory_clock * 4;
5396 else
5397 freq_nom = memory_clock * 2;
5398
5399 tmp = freq_nom / reference_clock;
5400 tmp = tmp * tmp;
5401 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5402 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
5403 u32 clks = reference_clock * 5 / ss.rate;
5404 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5405
5406 mpll_ss1 &= ~CLKV_MASK;
5407 mpll_ss1 |= CLKV(clkv);
5408
5409 mpll_ss2 &= ~CLKS_MASK;
5410 mpll_ss2 |= CLKS(clks);
5411 }
5412 }
5413
5414 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5415 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5416
5417 if (dll_state_on)
5418 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5419 else
5420 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5421
5422 mclk->mclk_value = cpu_to_be32(memory_clock);
5423 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5424 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5425 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5426 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5427 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5428 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5429 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5430 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5431 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5432
5433 return 0;
5434 }
5435
5436 static void si_populate_smc_sp(struct amdgpu_device *adev,
5437 struct amdgpu_ps *amdgpu_state,
5438 SISLANDS_SMC_SWSTATE *smc_state)
5439 {
5440 struct si_ps *ps = si_get_ps(amdgpu_state);
5441 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5442 int i;
5443
5444 for (i = 0; i < ps->performance_level_count - 1; i++)
5445 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5446
5447 smc_state->levels[ps->performance_level_count - 1].bSP =
5448 cpu_to_be32(pi->psp);
5449 }
5450
5451 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5452 struct rv7xx_pl *pl,
5453 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5454 {
5455 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5456 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5457 struct si_power_info *si_pi = si_get_pi(adev);
5458 int ret;
5459 bool dll_state_on;
5460 u16 std_vddc;
5461 bool gmc_pg = false;
5462
5463 if (eg_pi->pcie_performance_request &&
5464 (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID))
5465 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5466 else
5467 level->gen2PCIE = (u8)pl->pcie_gen;
5468
5469 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5470 if (ret)
5471 return ret;
5472
5473 level->mcFlags = 0;
5474
5475 if (pi->mclk_stutter_mode_threshold &&
5476 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5477 !eg_pi->uvd_enabled &&
5478 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5479 (adev->pm.dpm.new_active_crtc_count <= 2)) {
5480 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5481
5482 if (gmc_pg)
5483 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5484 }
5485
5486 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5487 if (pl->mclk > pi->mclk_edc_enable_threshold)
5488 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5489
5490 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5491 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5492
5493 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5494
5495 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5496 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5497 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5498 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5499 else
5500 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5501 } else {
5502 dll_state_on = false;
5503 }
5504 } else {
5505 level->strobeMode = si_get_strobe_mode_settings(adev,
5506 pl->mclk);
5507
5508 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5509 }
5510
5511 ret = si_populate_mclk_value(adev,
5512 pl->sclk,
5513 pl->mclk,
5514 &level->mclk,
5515 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5516 if (ret)
5517 return ret;
5518
5519 ret = si_populate_voltage_value(adev,
5520 &eg_pi->vddc_voltage_table,
5521 pl->vddc, &level->vddc);
5522 if (ret)
5523 return ret;
5524
5525
5526 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5527 if (ret)
5528 return ret;
5529
5530 ret = si_populate_std_voltage_value(adev, std_vddc,
5531 level->vddc.index, &level->std_vddc);
5532 if (ret)
5533 return ret;
5534
5535 if (eg_pi->vddci_control) {
5536 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5537 pl->vddci, &level->vddci);
5538 if (ret)
5539 return ret;
5540 }
5541
5542 if (si_pi->vddc_phase_shed_control) {
5543 ret = si_populate_phase_shedding_value(adev,
5544 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5545 pl->vddc,
5546 pl->sclk,
5547 pl->mclk,
5548 &level->vddc);
5549 if (ret)
5550 return ret;
5551 }
5552
5553 level->MaxPoweredUpCU = si_pi->max_cu;
5554
5555 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5556
5557 return ret;
5558 }
5559
5560 static int si_populate_smc_t(struct amdgpu_device *adev,
5561 struct amdgpu_ps *amdgpu_state,
5562 SISLANDS_SMC_SWSTATE *smc_state)
5563 {
5564 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5565 struct si_ps *state = si_get_ps(amdgpu_state);
5566 u32 a_t;
5567 u32 t_l, t_h;
5568 u32 high_bsp;
5569 int i, ret;
5570
5571 if (state->performance_level_count >= 9)
5572 return -EINVAL;
5573
5574 if (state->performance_level_count < 2) {
5575 a_t = CG_R(0xffff) | CG_L(0);
5576 smc_state->levels[0].aT = cpu_to_be32(a_t);
5577 return 0;
5578 }
5579
5580 smc_state->levels[0].aT = cpu_to_be32(0);
5581
5582 for (i = 0; i <= state->performance_level_count - 2; i++) {
5583 ret = r600_calculate_at(
5584 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5585 100 * R600_AH_DFLT,
5586 state->performance_levels[i + 1].sclk,
5587 state->performance_levels[i].sclk,
5588 &t_l,
5589 &t_h);
5590
5591 if (ret) {
5592 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5593 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5594 }
5595
5596 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5597 a_t |= CG_R(t_l * pi->bsp / 20000);
5598 smc_state->levels[i].aT = cpu_to_be32(a_t);
5599
5600 high_bsp = (i == state->performance_level_count - 2) ?
5601 pi->pbsp : pi->bsp;
5602 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5603 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5604 }
5605
5606 return 0;
5607 }
5608
5609 static int si_disable_ulv(struct amdgpu_device *adev)
5610 {
5611 struct si_power_info *si_pi = si_get_pi(adev);
5612 struct si_ulv_param *ulv = &si_pi->ulv;
5613
5614 if (ulv->supported)
5615 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5616 0 : -EINVAL;
5617
5618 return 0;
5619 }
5620
5621 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5622 struct amdgpu_ps *amdgpu_state)
5623 {
5624 const struct si_power_info *si_pi = si_get_pi(adev);
5625 const struct si_ulv_param *ulv = &si_pi->ulv;
5626 const struct si_ps *state = si_get_ps(amdgpu_state);
5627 int i;
5628
5629 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5630 return false;
5631
5632 /* XXX validate against display requirements! */
5633
5634 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5635 if (adev->clock.current_dispclk <=
5636 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5637 if (ulv->pl.vddc <
5638 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5639 return false;
5640 }
5641 }
5642
5643 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5644 return false;
5645
5646 return true;
5647 }
5648
5649 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5650 struct amdgpu_ps *amdgpu_new_state)
5651 {
5652 const struct si_power_info *si_pi = si_get_pi(adev);
5653 const struct si_ulv_param *ulv = &si_pi->ulv;
5654
5655 if (ulv->supported) {
5656 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5657 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5658 0 : -EINVAL;
5659 }
5660 return 0;
5661 }
5662
5663 static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5664 struct amdgpu_ps *amdgpu_state,
5665 SISLANDS_SMC_SWSTATE *smc_state)
5666 {
5667 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5668 struct ni_power_info *ni_pi = ni_get_pi(adev);
5669 struct si_power_info *si_pi = si_get_pi(adev);
5670 struct si_ps *state = si_get_ps(amdgpu_state);
5671 int i, ret;
5672 u32 threshold;
5673 u32 sclk_in_sr = 1350; /* ??? */
5674
5675 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5676 return -EINVAL;
5677
5678 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5679
5680 if (amdgpu_state->vclk && amdgpu_state->dclk) {
5681 eg_pi->uvd_enabled = true;
5682 if (eg_pi->smu_uvd_hs)
5683 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5684 } else {
5685 eg_pi->uvd_enabled = false;
5686 }
5687
5688 if (state->dc_compatible)
5689 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5690
5691 smc_state->levelCount = 0;
5692 for (i = 0; i < state->performance_level_count; i++) {
5693 if (eg_pi->sclk_deep_sleep) {
5694 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5695 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5696 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5697 else
5698 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5699 }
5700 }
5701
5702 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5703 &smc_state->levels[i]);
5704 smc_state->levels[i].arbRefreshState =
5705 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5706
5707 if (ret)
5708 return ret;
5709
5710 if (ni_pi->enable_power_containment)
5711 smc_state->levels[i].displayWatermark =
5712 (state->performance_levels[i].sclk < threshold) ?
5713 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5714 else
5715 smc_state->levels[i].displayWatermark = (i < 2) ?
5716 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5717
5718 if (eg_pi->dynamic_ac_timing)
5719 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5720 else
5721 smc_state->levels[i].ACIndex = 0;
5722
5723 smc_state->levelCount++;
5724 }
5725
5726 si_write_smc_soft_register(adev,
5727 SI_SMC_SOFT_REGISTER_watermark_threshold,
5728 threshold / 512);
5729
5730 si_populate_smc_sp(adev, amdgpu_state, smc_state);
5731
5732 ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5733 if (ret)
5734 ni_pi->enable_power_containment = false;
5735
5736 ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
5737 if (ret)
5738 ni_pi->enable_sq_ramping = false;
5739
5740 return si_populate_smc_t(adev, amdgpu_state, smc_state);
5741 }
5742
5743 static int si_upload_sw_state(struct amdgpu_device *adev,
5744 struct amdgpu_ps *amdgpu_new_state)
5745 {
5746 struct si_power_info *si_pi = si_get_pi(adev);
5747 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
5748 int ret;
5749 u32 address = si_pi->state_table_start +
5750 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5751 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5752 ((new_state->performance_level_count - 1) *
5753 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5754 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5755
5756 memset(smc_state, 0, state_size);
5757
5758 ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5759 if (ret)
5760 return ret;
5761
5762 return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5763 state_size, si_pi->sram_end);
5764 }
5765
5766 static int si_upload_ulv_state(struct amdgpu_device *adev)
5767 {
5768 struct si_power_info *si_pi = si_get_pi(adev);
5769 struct si_ulv_param *ulv = &si_pi->ulv;
5770 int ret = 0;
5771
5772 if (ulv->supported && ulv->pl.vddc) {
5773 u32 address = si_pi->state_table_start +
5774 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5775 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5776 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5777
5778 memset(smc_state, 0, state_size);
5779
5780 ret = si_populate_ulv_state(adev, smc_state);
5781 if (!ret)
5782 ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5783 state_size, si_pi->sram_end);
5784 }
5785
5786 return ret;
5787 }
5788
5789 static int si_upload_smc_data(struct amdgpu_device *adev)
5790 {
5791 struct amdgpu_crtc *amdgpu_crtc = NULL;
5792 int i;
5793
5794 if (adev->pm.dpm.new_active_crtc_count == 0)
5795 return 0;
5796
5797 for (i = 0; i < adev->mode_info.num_crtc; i++) {
5798 if (adev->pm.dpm.new_active_crtcs & (1 << i)) {
5799 amdgpu_crtc = adev->mode_info.crtcs[i];
5800 break;
5801 }
5802 }
5803
5804 if (amdgpu_crtc == NULL)
5805 return 0;
5806
5807 if (amdgpu_crtc->line_time <= 0)
5808 return 0;
5809
5810 if (si_write_smc_soft_register(adev,
5811 SI_SMC_SOFT_REGISTER_crtc_index,
5812 amdgpu_crtc->crtc_id) != PPSMC_Result_OK)
5813 return 0;
5814
5815 if (si_write_smc_soft_register(adev,
5816 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5817 amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5818 return 0;
5819
5820 if (si_write_smc_soft_register(adev,
5821 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5822 amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5823 return 0;
5824
5825 return 0;
5826 }
5827
5828 static int si_set_mc_special_registers(struct amdgpu_device *adev,
5829 struct si_mc_reg_table *table)
5830 {
5831 u8 i, j, k;
5832 u32 temp_reg;
5833
5834 for (i = 0, j = table->last; i < table->last; i++) {
5835 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5836 return -EINVAL;
5837 switch (table->mc_reg_address[i].s1) {
5838 case MC_SEQ_MISC1:
5839 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5840 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5841 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5842 for (k = 0; k < table->num_entries; k++)
5843 table->mc_reg_table_entry[k].mc_data[j] =
5844 ((temp_reg & 0xffff0000)) |
5845 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5846 j++;
5847 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5848 return -EINVAL;
5849
5850 temp_reg = RREG32(MC_PMG_CMD_MRS);
5851 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5852 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5853 for (k = 0; k < table->num_entries; k++) {
5854 table->mc_reg_table_entry[k].mc_data[j] =
5855 (temp_reg & 0xffff0000) |
5856 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5857 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5858 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5859 }
5860 j++;
5861 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5862 return -EINVAL;
5863
5864 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5865 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5866 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5867 for (k = 0; k < table->num_entries; k++)
5868 table->mc_reg_table_entry[k].mc_data[j] =
5869 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5870 j++;
5871 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5872 return -EINVAL;
5873 }
5874 break;
5875 case MC_SEQ_RESERVE_M:
5876 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5877 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5878 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5879 for(k = 0; k < table->num_entries; k++)
5880 table->mc_reg_table_entry[k].mc_data[j] =
5881 (temp_reg & 0xffff0000) |
5882 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5883 j++;
5884 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5885 return -EINVAL;
5886 break;
5887 default:
5888 break;
5889 }
5890 }
5891
5892 table->last = j;
5893
5894 return 0;
5895 }
5896
5897 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5898 {
5899 bool result = true;
5900 switch (in_reg) {
5901 case MC_SEQ_RAS_TIMING:
5902 *out_reg = MC_SEQ_RAS_TIMING_LP;
5903 break;
5904 case MC_SEQ_CAS_TIMING:
5905 *out_reg = MC_SEQ_CAS_TIMING_LP;
5906 break;
5907 case MC_SEQ_MISC_TIMING:
5908 *out_reg = MC_SEQ_MISC_TIMING_LP;
5909 break;
5910 case MC_SEQ_MISC_TIMING2:
5911 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5912 break;
5913 case MC_SEQ_RD_CTL_D0:
5914 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5915 break;
5916 case MC_SEQ_RD_CTL_D1:
5917 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5918 break;
5919 case MC_SEQ_WR_CTL_D0:
5920 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5921 break;
5922 case MC_SEQ_WR_CTL_D1:
5923 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5924 break;
5925 case MC_PMG_CMD_EMRS:
5926 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5927 break;
5928 case MC_PMG_CMD_MRS:
5929 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5930 break;
5931 case MC_PMG_CMD_MRS1:
5932 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5933 break;
5934 case MC_SEQ_PMG_TIMING:
5935 *out_reg = MC_SEQ_PMG_TIMING_LP;
5936 break;
5937 case MC_PMG_CMD_MRS2:
5938 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5939 break;
5940 case MC_SEQ_WR_CTL_2:
5941 *out_reg = MC_SEQ_WR_CTL_2_LP;
5942 break;
5943 default:
5944 result = false;
5945 break;
5946 }
5947
5948 return result;
5949 }
5950
5951 static void si_set_valid_flag(struct si_mc_reg_table *table)
5952 {
5953 u8 i, j;
5954
5955 for (i = 0; i < table->last; i++) {
5956 for (j = 1; j < table->num_entries; j++) {
5957 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5958 table->valid_flag |= 1 << i;
5959 break;
5960 }
5961 }
5962 }
5963 }
5964
5965 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5966 {
5967 u32 i;
5968 u16 address;
5969
5970 for (i = 0; i < table->last; i++)
5971 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5972 address : table->mc_reg_address[i].s1;
5973
5974 }
5975
5976 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5977 struct si_mc_reg_table *si_table)
5978 {
5979 u8 i, j;
5980
5981 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5982 return -EINVAL;
5983 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5984 return -EINVAL;
5985
5986 for (i = 0; i < table->last; i++)
5987 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5988 si_table->last = table->last;
5989
5990 for (i = 0; i < table->num_entries; i++) {
5991 si_table->mc_reg_table_entry[i].mclk_max =
5992 table->mc_reg_table_entry[i].mclk_max;
5993 for (j = 0; j < table->last; j++) {
5994 si_table->mc_reg_table_entry[i].mc_data[j] =
5995 table->mc_reg_table_entry[i].mc_data[j];
5996 }
5997 }
5998 si_table->num_entries = table->num_entries;
5999
6000 return 0;
6001 }
6002
6003 static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
6004 {
6005 struct si_power_info *si_pi = si_get_pi(adev);
6006 struct atom_mc_reg_table *table;
6007 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
6008 u8 module_index = rv770_get_memory_module_index(adev);
6009 int ret;
6010
6011 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
6012 if (!table)
6013 return -ENOMEM;
6014
6015 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
6016 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
6017 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
6018 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
6019 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
6020 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
6021 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
6022 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
6023 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
6024 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
6025 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6026 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6027 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6028 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6029
6030 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6031 if (ret)
6032 goto init_mc_done;
6033
6034 ret = si_copy_vbios_mc_reg_table(table, si_table);
6035 if (ret)
6036 goto init_mc_done;
6037
6038 si_set_s0_mc_reg_index(si_table);
6039
6040 ret = si_set_mc_special_registers(adev, si_table);
6041 if (ret)
6042 goto init_mc_done;
6043
6044 si_set_valid_flag(si_table);
6045
6046 init_mc_done:
6047 kfree(table);
6048
6049 return ret;
6050
6051 }
6052
6053 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6054 SMC_SIslands_MCRegisters *mc_reg_table)
6055 {
6056 struct si_power_info *si_pi = si_get_pi(adev);
6057 u32 i, j;
6058
6059 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6060 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6061 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6062 break;
6063 mc_reg_table->address[i].s0 =
6064 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6065 mc_reg_table->address[i].s1 =
6066 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6067 i++;
6068 }
6069 }
6070 mc_reg_table->last = (u8)i;
6071 }
6072
6073 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6074 SMC_SIslands_MCRegisterSet *data,
6075 u32 num_entries, u32 valid_flag)
6076 {
6077 u32 i, j;
6078
6079 for(i = 0, j = 0; j < num_entries; j++) {
6080 if (valid_flag & (1 << j)) {
6081 data->value[i] = cpu_to_be32(entry->mc_data[j]);
6082 i++;
6083 }
6084 }
6085 }
6086
6087 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6088 struct rv7xx_pl *pl,
6089 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6090 {
6091 struct si_power_info *si_pi = si_get_pi(adev);
6092 u32 i = 0;
6093
6094 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6095 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6096 break;
6097 }
6098
6099 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6100 --i;
6101
6102 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6103 mc_reg_table_data, si_pi->mc_reg_table.last,
6104 si_pi->mc_reg_table.valid_flag);
6105 }
6106
6107 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6108 struct amdgpu_ps *amdgpu_state,
6109 SMC_SIslands_MCRegisters *mc_reg_table)
6110 {
6111 struct si_ps *state = si_get_ps(amdgpu_state);
6112 int i;
6113
6114 for (i = 0; i < state->performance_level_count; i++) {
6115 si_convert_mc_reg_table_entry_to_smc(adev,
6116 &state->performance_levels[i],
6117 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6118 }
6119 }
6120
6121 static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6122 struct amdgpu_ps *amdgpu_boot_state)
6123 {
6124 struct si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6125 struct si_power_info *si_pi = si_get_pi(adev);
6126 struct si_ulv_param *ulv = &si_pi->ulv;
6127 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6128
6129 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6130
6131 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6132
6133 si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6134
6135 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6136 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6137
6138 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6139 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6140 si_pi->mc_reg_table.last,
6141 si_pi->mc_reg_table.valid_flag);
6142
6143 if (ulv->supported && ulv->pl.vddc != 0)
6144 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6145 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6146 else
6147 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6148 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6149 si_pi->mc_reg_table.last,
6150 si_pi->mc_reg_table.valid_flag);
6151
6152 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6153
6154 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6155 (u8 *)smc_mc_reg_table,
6156 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6157 }
6158
6159 static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6160 struct amdgpu_ps *amdgpu_new_state)
6161 {
6162 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
6163 struct si_power_info *si_pi = si_get_pi(adev);
6164 u32 address = si_pi->mc_reg_table_start +
6165 offsetof(SMC_SIslands_MCRegisters,
6166 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6167 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6168
6169 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6170
6171 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6172
6173 return amdgpu_si_copy_bytes_to_smc(adev, address,
6174 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6175 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6176 si_pi->sram_end);
6177 }
6178
6179 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6180 {
6181 if (enable)
6182 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
6183 else
6184 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
6185 }
6186
6187 static enum amdgpu_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6188 struct amdgpu_ps *amdgpu_state)
6189 {
6190 struct si_ps *state = si_get_ps(amdgpu_state);
6191 int i;
6192 u16 pcie_speed, max_speed = 0;
6193
6194 for (i = 0; i < state->performance_level_count; i++) {
6195 pcie_speed = state->performance_levels[i].pcie_gen;
6196 if (max_speed < pcie_speed)
6197 max_speed = pcie_speed;
6198 }
6199 return max_speed;
6200 }
6201
6202 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6203 {
6204 u32 speed_cntl;
6205
6206 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
6207 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
6208
6209 return (u16)speed_cntl;
6210 }
6211
6212 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6213 struct amdgpu_ps *amdgpu_new_state,
6214 struct amdgpu_ps *amdgpu_current_state)
6215 {
6216 struct si_power_info *si_pi = si_get_pi(adev);
6217 enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6218 enum amdgpu_pcie_gen current_link_speed;
6219
6220 if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
6221 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6222 else
6223 current_link_speed = si_pi->force_pcie_gen;
6224
6225 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
6226 si_pi->pspp_notify_required = false;
6227 if (target_link_speed > current_link_speed) {
6228 switch (target_link_speed) {
6229 #if defined(CONFIG_ACPI)
6230 case AMDGPU_PCIE_GEN3:
6231 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6232 break;
6233 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
6234 if (current_link_speed == AMDGPU_PCIE_GEN2)
6235 break;
6236 case AMDGPU_PCIE_GEN2:
6237 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6238 break;
6239 #endif
6240 default:
6241 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6242 break;
6243 }
6244 } else {
6245 if (target_link_speed < current_link_speed)
6246 si_pi->pspp_notify_required = true;
6247 }
6248 }
6249
6250 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6251 struct amdgpu_ps *amdgpu_new_state,
6252 struct amdgpu_ps *amdgpu_current_state)
6253 {
6254 struct si_power_info *si_pi = si_get_pi(adev);
6255 enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6256 u8 request;
6257
6258 if (si_pi->pspp_notify_required) {
6259 if (target_link_speed == AMDGPU_PCIE_GEN3)
6260 request = PCIE_PERF_REQ_PECI_GEN3;
6261 else if (target_link_speed == AMDGPU_PCIE_GEN2)
6262 request = PCIE_PERF_REQ_PECI_GEN2;
6263 else
6264 request = PCIE_PERF_REQ_PECI_GEN1;
6265
6266 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6267 (si_get_current_pcie_speed(adev) > 0))
6268 return;
6269
6270 #if defined(CONFIG_ACPI)
6271 amdgpu_acpi_pcie_performance_request(adev, request, false);
6272 #endif
6273 }
6274 }
6275
6276 #if 0
6277 static int si_ds_request(struct amdgpu_device *adev,
6278 bool ds_status_on, u32 count_write)
6279 {
6280 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6281
6282 if (eg_pi->sclk_deep_sleep) {
6283 if (ds_status_on)
6284 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6285 PPSMC_Result_OK) ?
6286 0 : -EINVAL;
6287 else
6288 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6289 PPSMC_Result_OK) ? 0 : -EINVAL;
6290 }
6291 return 0;
6292 }
6293 #endif
6294
6295 static void si_set_max_cu_value(struct amdgpu_device *adev)
6296 {
6297 struct si_power_info *si_pi = si_get_pi(adev);
6298
6299 if (adev->asic_type == CHIP_VERDE) {
6300 switch (adev->pdev->device) {
6301 case 0x6820:
6302 case 0x6825:
6303 case 0x6821:
6304 case 0x6823:
6305 case 0x6827:
6306 si_pi->max_cu = 10;
6307 break;
6308 case 0x682D:
6309 case 0x6824:
6310 case 0x682F:
6311 case 0x6826:
6312 si_pi->max_cu = 8;
6313 break;
6314 case 0x6828:
6315 case 0x6830:
6316 case 0x6831:
6317 case 0x6838:
6318 case 0x6839:
6319 case 0x683D:
6320 si_pi->max_cu = 10;
6321 break;
6322 case 0x683B:
6323 case 0x683F:
6324 case 0x6829:
6325 si_pi->max_cu = 8;
6326 break;
6327 default:
6328 si_pi->max_cu = 0;
6329 break;
6330 }
6331 } else {
6332 si_pi->max_cu = 0;
6333 }
6334 }
6335
6336 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6337 struct amdgpu_clock_voltage_dependency_table *table)
6338 {
6339 u32 i;
6340 int j;
6341 u16 leakage_voltage;
6342
6343 if (table) {
6344 for (i = 0; i < table->count; i++) {
6345 switch (si_get_leakage_voltage_from_leakage_index(adev,
6346 table->entries[i].v,
6347 &leakage_voltage)) {
6348 case 0:
6349 table->entries[i].v = leakage_voltage;
6350 break;
6351 case -EAGAIN:
6352 return -EINVAL;
6353 case -EINVAL:
6354 default:
6355 break;
6356 }
6357 }
6358
6359 for (j = (table->count - 2); j >= 0; j--) {
6360 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6361 table->entries[j].v : table->entries[j + 1].v;
6362 }
6363 }
6364 return 0;
6365 }
6366
6367 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6368 {
6369 int ret = 0;
6370
6371 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6372 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
6373 if (ret)
6374 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
6375 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6376 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
6377 if (ret)
6378 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
6379 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6380 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
6381 if (ret)
6382 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
6383 return ret;
6384 }
6385
6386 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6387 struct amdgpu_ps *amdgpu_new_state,
6388 struct amdgpu_ps *amdgpu_current_state)
6389 {
6390 u32 lane_width;
6391 u32 new_lane_width =
6392 (amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6393 u32 current_lane_width =
6394 (amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6395
6396 if (new_lane_width != current_lane_width) {
6397 amdgpu_set_pcie_lanes(adev, new_lane_width);
6398 lane_width = amdgpu_get_pcie_lanes(adev);
6399 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6400 }
6401 }
6402
6403 static void si_dpm_setup_asic(struct amdgpu_device *adev)
6404 {
6405 si_read_clock_registers(adev);
6406 si_enable_acpi_power_management(adev);
6407 }
6408
6409 static int si_thermal_enable_alert(struct amdgpu_device *adev,
6410 bool enable)
6411 {
6412 u32 thermal_int = RREG32(CG_THERMAL_INT);
6413
6414 if (enable) {
6415 PPSMC_Result result;
6416
6417 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6418 WREG32(CG_THERMAL_INT, thermal_int);
6419 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6420 if (result != PPSMC_Result_OK) {
6421 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6422 return -EINVAL;
6423 }
6424 } else {
6425 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6426 WREG32(CG_THERMAL_INT, thermal_int);
6427 }
6428
6429 return 0;
6430 }
6431
6432 static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6433 int min_temp, int max_temp)
6434 {
6435 int low_temp = 0 * 1000;
6436 int high_temp = 255 * 1000;
6437
6438 if (low_temp < min_temp)
6439 low_temp = min_temp;
6440 if (high_temp > max_temp)
6441 high_temp = max_temp;
6442 if (high_temp < low_temp) {
6443 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6444 return -EINVAL;
6445 }
6446
6447 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6448 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6449 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6450
6451 adev->pm.dpm.thermal.min_temp = low_temp;
6452 adev->pm.dpm.thermal.max_temp = high_temp;
6453
6454 return 0;
6455 }
6456
6457 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6458 {
6459 struct si_power_info *si_pi = si_get_pi(adev);
6460 u32 tmp;
6461
6462 if (si_pi->fan_ctrl_is_in_default_mode) {
6463 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6464 si_pi->fan_ctrl_default_mode = tmp;
6465 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6466 si_pi->t_min = tmp;
6467 si_pi->fan_ctrl_is_in_default_mode = false;
6468 }
6469
6470 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6471 tmp |= TMIN(0);
6472 WREG32(CG_FDO_CTRL2, tmp);
6473
6474 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6475 tmp |= FDO_PWM_MODE(mode);
6476 WREG32(CG_FDO_CTRL2, tmp);
6477 }
6478
6479 static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6480 {
6481 struct si_power_info *si_pi = si_get_pi(adev);
6482 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6483 u32 duty100;
6484 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6485 u16 fdo_min, slope1, slope2;
6486 u32 reference_clock, tmp;
6487 int ret;
6488 u64 tmp64;
6489
6490 if (!si_pi->fan_table_start) {
6491 adev->pm.dpm.fan.ucode_fan_control = false;
6492 return 0;
6493 }
6494
6495 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6496
6497 if (duty100 == 0) {
6498 adev->pm.dpm.fan.ucode_fan_control = false;
6499 return 0;
6500 }
6501
6502 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6503 do_div(tmp64, 10000);
6504 fdo_min = (u16)tmp64;
6505
6506 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6507 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6508
6509 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6510 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6511
6512 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6513 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6514
6515 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6516 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6517 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
6518 fan_table.slope1 = cpu_to_be16(slope1);
6519 fan_table.slope2 = cpu_to_be16(slope2);
6520 fan_table.fdo_min = cpu_to_be16(fdo_min);
6521 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
6522 fan_table.hys_up = cpu_to_be16(1);
6523 fan_table.hys_slope = cpu_to_be16(1);
6524 fan_table.temp_resp_lim = cpu_to_be16(5);
6525 reference_clock = amdgpu_asic_get_xclk(adev);
6526
6527 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6528 reference_clock) / 1600);
6529 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6530
6531 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6532 fan_table.temp_src = (uint8_t)tmp;
6533
6534 ret = amdgpu_si_copy_bytes_to_smc(adev,
6535 si_pi->fan_table_start,
6536 (u8 *)(&fan_table),
6537 sizeof(fan_table),
6538 si_pi->sram_end);
6539
6540 if (ret) {
6541 DRM_ERROR("Failed to load fan table to the SMC.");
6542 adev->pm.dpm.fan.ucode_fan_control = false;
6543 }
6544
6545 return ret;
6546 }
6547
6548 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6549 {
6550 struct si_power_info *si_pi = si_get_pi(adev);
6551 PPSMC_Result ret;
6552
6553 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6554 if (ret == PPSMC_Result_OK) {
6555 si_pi->fan_is_controlled_by_smc = true;
6556 return 0;
6557 } else {
6558 return -EINVAL;
6559 }
6560 }
6561
6562 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6563 {
6564 struct si_power_info *si_pi = si_get_pi(adev);
6565 PPSMC_Result ret;
6566
6567 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6568
6569 if (ret == PPSMC_Result_OK) {
6570 si_pi->fan_is_controlled_by_smc = false;
6571 return 0;
6572 } else {
6573 return -EINVAL;
6574 }
6575 }
6576
6577 static int si_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
6578 u32 *speed)
6579 {
6580 u32 duty, duty100;
6581 u64 tmp64;
6582
6583 if (adev->pm.no_fan)
6584 return -ENOENT;
6585
6586 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6587 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6588
6589 if (duty100 == 0)
6590 return -EINVAL;
6591
6592 tmp64 = (u64)duty * 100;
6593 do_div(tmp64, duty100);
6594 *speed = (u32)tmp64;
6595
6596 if (*speed > 100)
6597 *speed = 100;
6598
6599 return 0;
6600 }
6601
6602 static int si_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
6603 u32 speed)
6604 {
6605 struct si_power_info *si_pi = si_get_pi(adev);
6606 u32 tmp;
6607 u32 duty, duty100;
6608 u64 tmp64;
6609
6610 if (adev->pm.no_fan)
6611 return -ENOENT;
6612
6613 if (si_pi->fan_is_controlled_by_smc)
6614 return -EINVAL;
6615
6616 if (speed > 100)
6617 return -EINVAL;
6618
6619 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6620
6621 if (duty100 == 0)
6622 return -EINVAL;
6623
6624 tmp64 = (u64)speed * duty100;
6625 do_div(tmp64, 100);
6626 duty = (u32)tmp64;
6627
6628 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6629 tmp |= FDO_STATIC_DUTY(duty);
6630 WREG32(CG_FDO_CTRL0, tmp);
6631
6632 return 0;
6633 }
6634
6635 static void si_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
6636 {
6637 if (mode) {
6638 /* stop auto-manage */
6639 if (adev->pm.dpm.fan.ucode_fan_control)
6640 si_fan_ctrl_stop_smc_fan_control(adev);
6641 si_fan_ctrl_set_static_mode(adev, mode);
6642 } else {
6643 /* restart auto-manage */
6644 if (adev->pm.dpm.fan.ucode_fan_control)
6645 si_thermal_start_smc_fan_control(adev);
6646 else
6647 si_fan_ctrl_set_default_mode(adev);
6648 }
6649 }
6650
6651 static u32 si_dpm_get_fan_control_mode(struct amdgpu_device *adev)
6652 {
6653 struct si_power_info *si_pi = si_get_pi(adev);
6654 u32 tmp;
6655
6656 if (si_pi->fan_is_controlled_by_smc)
6657 return 0;
6658
6659 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6660 return (tmp >> FDO_PWM_MODE_SHIFT);
6661 }
6662
6663 #if 0
6664 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6665 u32 *speed)
6666 {
6667 u32 tach_period;
6668 u32 xclk = amdgpu_asic_get_xclk(adev);
6669
6670 if (adev->pm.no_fan)
6671 return -ENOENT;
6672
6673 if (adev->pm.fan_pulses_per_revolution == 0)
6674 return -ENOENT;
6675
6676 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6677 if (tach_period == 0)
6678 return -ENOENT;
6679
6680 *speed = 60 * xclk * 10000 / tach_period;
6681
6682 return 0;
6683 }
6684
6685 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6686 u32 speed)
6687 {
6688 u32 tach_period, tmp;
6689 u32 xclk = amdgpu_asic_get_xclk(adev);
6690
6691 if (adev->pm.no_fan)
6692 return -ENOENT;
6693
6694 if (adev->pm.fan_pulses_per_revolution == 0)
6695 return -ENOENT;
6696
6697 if ((speed < adev->pm.fan_min_rpm) ||
6698 (speed > adev->pm.fan_max_rpm))
6699 return -EINVAL;
6700
6701 if (adev->pm.dpm.fan.ucode_fan_control)
6702 si_fan_ctrl_stop_smc_fan_control(adev);
6703
6704 tach_period = 60 * xclk * 10000 / (8 * speed);
6705 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6706 tmp |= TARGET_PERIOD(tach_period);
6707 WREG32(CG_TACH_CTRL, tmp);
6708
6709 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6710
6711 return 0;
6712 }
6713 #endif
6714
6715 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6716 {
6717 struct si_power_info *si_pi = si_get_pi(adev);
6718 u32 tmp;
6719
6720 if (!si_pi->fan_ctrl_is_in_default_mode) {
6721 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6722 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6723 WREG32(CG_FDO_CTRL2, tmp);
6724
6725 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6726 tmp |= TMIN(si_pi->t_min);
6727 WREG32(CG_FDO_CTRL2, tmp);
6728 si_pi->fan_ctrl_is_in_default_mode = true;
6729 }
6730 }
6731
6732 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6733 {
6734 if (adev->pm.dpm.fan.ucode_fan_control) {
6735 si_fan_ctrl_start_smc_fan_control(adev);
6736 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6737 }
6738 }
6739
6740 static void si_thermal_initialize(struct amdgpu_device *adev)
6741 {
6742 u32 tmp;
6743
6744 if (adev->pm.fan_pulses_per_revolution) {
6745 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6746 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1);
6747 WREG32(CG_TACH_CTRL, tmp);
6748 }
6749
6750 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6751 tmp |= TACH_PWM_RESP_RATE(0x28);
6752 WREG32(CG_FDO_CTRL2, tmp);
6753 }
6754
6755 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6756 {
6757 int ret;
6758
6759 si_thermal_initialize(adev);
6760 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6761 if (ret)
6762 return ret;
6763 ret = si_thermal_enable_alert(adev, true);
6764 if (ret)
6765 return ret;
6766 if (adev->pm.dpm.fan.ucode_fan_control) {
6767 ret = si_halt_smc(adev);
6768 if (ret)
6769 return ret;
6770 ret = si_thermal_setup_fan_table(adev);
6771 if (ret)
6772 return ret;
6773 ret = si_resume_smc(adev);
6774 if (ret)
6775 return ret;
6776 si_thermal_start_smc_fan_control(adev);
6777 }
6778
6779 return 0;
6780 }
6781
6782 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6783 {
6784 if (!adev->pm.no_fan) {
6785 si_fan_ctrl_set_default_mode(adev);
6786 si_fan_ctrl_stop_smc_fan_control(adev);
6787 }
6788 }
6789
6790 static int si_dpm_enable(struct amdgpu_device *adev)
6791 {
6792 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6793 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6794 struct si_power_info *si_pi = si_get_pi(adev);
6795 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6796 int ret;
6797
6798 if (amdgpu_si_is_smc_running(adev))
6799 return -EINVAL;
6800 if (pi->voltage_control || si_pi->voltage_control_svi2)
6801 si_enable_voltage_control(adev, true);
6802 if (pi->mvdd_control)
6803 si_get_mvdd_configuration(adev);
6804 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6805 ret = si_construct_voltage_tables(adev);
6806 if (ret) {
6807 DRM_ERROR("si_construct_voltage_tables failed\n");
6808 return ret;
6809 }
6810 }
6811 if (eg_pi->dynamic_ac_timing) {
6812 ret = si_initialize_mc_reg_table(adev);
6813 if (ret)
6814 eg_pi->dynamic_ac_timing = false;
6815 }
6816 if (pi->dynamic_ss)
6817 si_enable_spread_spectrum(adev, true);
6818 if (pi->thermal_protection)
6819 si_enable_thermal_protection(adev, true);
6820 si_setup_bsp(adev);
6821 si_program_git(adev);
6822 si_program_tp(adev);
6823 si_program_tpp(adev);
6824 si_program_sstp(adev);
6825 si_enable_display_gap(adev);
6826 si_program_vc(adev);
6827 ret = si_upload_firmware(adev);
6828 if (ret) {
6829 DRM_ERROR("si_upload_firmware failed\n");
6830 return ret;
6831 }
6832 ret = si_process_firmware_header(adev);
6833 if (ret) {
6834 DRM_ERROR("si_process_firmware_header failed\n");
6835 return ret;
6836 }
6837 ret = si_initial_switch_from_arb_f0_to_f1(adev);
6838 if (ret) {
6839 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6840 return ret;
6841 }
6842 ret = si_init_smc_table(adev);
6843 if (ret) {
6844 DRM_ERROR("si_init_smc_table failed\n");
6845 return ret;
6846 }
6847 ret = si_init_smc_spll_table(adev);
6848 if (ret) {
6849 DRM_ERROR("si_init_smc_spll_table failed\n");
6850 return ret;
6851 }
6852 ret = si_init_arb_table_index(adev);
6853 if (ret) {
6854 DRM_ERROR("si_init_arb_table_index failed\n");
6855 return ret;
6856 }
6857 if (eg_pi->dynamic_ac_timing) {
6858 ret = si_populate_mc_reg_table(adev, boot_ps);
6859 if (ret) {
6860 DRM_ERROR("si_populate_mc_reg_table failed\n");
6861 return ret;
6862 }
6863 }
6864 ret = si_initialize_smc_cac_tables(adev);
6865 if (ret) {
6866 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6867 return ret;
6868 }
6869 ret = si_initialize_hardware_cac_manager(adev);
6870 if (ret) {
6871 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6872 return ret;
6873 }
6874 ret = si_initialize_smc_dte_tables(adev);
6875 if (ret) {
6876 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6877 return ret;
6878 }
6879 ret = si_populate_smc_tdp_limits(adev, boot_ps);
6880 if (ret) {
6881 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6882 return ret;
6883 }
6884 ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6885 if (ret) {
6886 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6887 return ret;
6888 }
6889 si_program_response_times(adev);
6890 si_program_ds_registers(adev);
6891 si_dpm_start_smc(adev);
6892 ret = si_notify_smc_display_change(adev, false);
6893 if (ret) {
6894 DRM_ERROR("si_notify_smc_display_change failed\n");
6895 return ret;
6896 }
6897 si_enable_sclk_control(adev, true);
6898 si_start_dpm(adev);
6899
6900 si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6901 si_thermal_start_thermal_controller(adev);
6902 ni_update_current_ps(adev, boot_ps);
6903
6904 return 0;
6905 }
6906
6907 static int si_set_temperature_range(struct amdgpu_device *adev)
6908 {
6909 int ret;
6910
6911 ret = si_thermal_enable_alert(adev, false);
6912 if (ret)
6913 return ret;
6914 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6915 if (ret)
6916 return ret;
6917 ret = si_thermal_enable_alert(adev, true);
6918 if (ret)
6919 return ret;
6920
6921 return ret;
6922 }
6923
6924 static void si_dpm_disable(struct amdgpu_device *adev)
6925 {
6926 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6927 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6928
6929 if (!amdgpu_si_is_smc_running(adev))
6930 return;
6931 si_thermal_stop_thermal_controller(adev);
6932 si_disable_ulv(adev);
6933 si_clear_vc(adev);
6934 if (pi->thermal_protection)
6935 si_enable_thermal_protection(adev, false);
6936 si_enable_power_containment(adev, boot_ps, false);
6937 si_enable_smc_cac(adev, boot_ps, false);
6938 si_enable_spread_spectrum(adev, false);
6939 si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6940 si_stop_dpm(adev);
6941 si_reset_to_default(adev);
6942 si_dpm_stop_smc(adev);
6943 si_force_switch_to_arb_f0(adev);
6944
6945 ni_update_current_ps(adev, boot_ps);
6946 }
6947
6948 static int si_dpm_pre_set_power_state(struct amdgpu_device *adev)
6949 {
6950 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6951 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
6952 struct amdgpu_ps *new_ps = &requested_ps;
6953
6954 ni_update_requested_ps(adev, new_ps);
6955 si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
6956
6957 return 0;
6958 }
6959
6960 static int si_power_control_set_level(struct amdgpu_device *adev)
6961 {
6962 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
6963 int ret;
6964
6965 ret = si_restrict_performance_levels_before_switch(adev);
6966 if (ret)
6967 return ret;
6968 ret = si_halt_smc(adev);
6969 if (ret)
6970 return ret;
6971 ret = si_populate_smc_tdp_limits(adev, new_ps);
6972 if (ret)
6973 return ret;
6974 ret = si_populate_smc_tdp_limits_2(adev, new_ps);
6975 if (ret)
6976 return ret;
6977 ret = si_resume_smc(adev);
6978 if (ret)
6979 return ret;
6980 ret = si_set_sw_state(adev);
6981 if (ret)
6982 return ret;
6983 return 0;
6984 }
6985
6986 static int si_dpm_set_power_state(struct amdgpu_device *adev)
6987 {
6988 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6989 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
6990 struct amdgpu_ps *old_ps = &eg_pi->current_rps;
6991 int ret;
6992
6993 ret = si_disable_ulv(adev);
6994 if (ret) {
6995 DRM_ERROR("si_disable_ulv failed\n");
6996 return ret;
6997 }
6998 ret = si_restrict_performance_levels_before_switch(adev);
6999 if (ret) {
7000 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
7001 return ret;
7002 }
7003 if (eg_pi->pcie_performance_request)
7004 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
7005 ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
7006 ret = si_enable_power_containment(adev, new_ps, false);
7007 if (ret) {
7008 DRM_ERROR("si_enable_power_containment failed\n");
7009 return ret;
7010 }
7011 ret = si_enable_smc_cac(adev, new_ps, false);
7012 if (ret) {
7013 DRM_ERROR("si_enable_smc_cac failed\n");
7014 return ret;
7015 }
7016 ret = si_halt_smc(adev);
7017 if (ret) {
7018 DRM_ERROR("si_halt_smc failed\n");
7019 return ret;
7020 }
7021 ret = si_upload_sw_state(adev, new_ps);
7022 if (ret) {
7023 DRM_ERROR("si_upload_sw_state failed\n");
7024 return ret;
7025 }
7026 ret = si_upload_smc_data(adev);
7027 if (ret) {
7028 DRM_ERROR("si_upload_smc_data failed\n");
7029 return ret;
7030 }
7031 ret = si_upload_ulv_state(adev);
7032 if (ret) {
7033 DRM_ERROR("si_upload_ulv_state failed\n");
7034 return ret;
7035 }
7036 if (eg_pi->dynamic_ac_timing) {
7037 ret = si_upload_mc_reg_table(adev, new_ps);
7038 if (ret) {
7039 DRM_ERROR("si_upload_mc_reg_table failed\n");
7040 return ret;
7041 }
7042 }
7043 ret = si_program_memory_timing_parameters(adev, new_ps);
7044 if (ret) {
7045 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7046 return ret;
7047 }
7048 si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7049
7050 ret = si_resume_smc(adev);
7051 if (ret) {
7052 DRM_ERROR("si_resume_smc failed\n");
7053 return ret;
7054 }
7055 ret = si_set_sw_state(adev);
7056 if (ret) {
7057 DRM_ERROR("si_set_sw_state failed\n");
7058 return ret;
7059 }
7060 ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7061 if (eg_pi->pcie_performance_request)
7062 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7063 ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7064 if (ret) {
7065 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7066 return ret;
7067 }
7068 ret = si_enable_smc_cac(adev, new_ps, true);
7069 if (ret) {
7070 DRM_ERROR("si_enable_smc_cac failed\n");
7071 return ret;
7072 }
7073 ret = si_enable_power_containment(adev, new_ps, true);
7074 if (ret) {
7075 DRM_ERROR("si_enable_power_containment failed\n");
7076 return ret;
7077 }
7078
7079 ret = si_power_control_set_level(adev);
7080 if (ret) {
7081 DRM_ERROR("si_power_control_set_level failed\n");
7082 return ret;
7083 }
7084
7085 return 0;
7086 }
7087
7088 static void si_dpm_post_set_power_state(struct amdgpu_device *adev)
7089 {
7090 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7091 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7092
7093 ni_update_current_ps(adev, new_ps);
7094 }
7095
7096 #if 0
7097 void si_dpm_reset_asic(struct amdgpu_device *adev)
7098 {
7099 si_restrict_performance_levels_before_switch(adev);
7100 si_disable_ulv(adev);
7101 si_set_boot_state(adev);
7102 }
7103 #endif
7104
7105 static void si_dpm_display_configuration_changed(struct amdgpu_device *adev)
7106 {
7107 si_program_display_gap(adev);
7108 }
7109
7110
7111 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7112 struct amdgpu_ps *rps,
7113 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7114 u8 table_rev)
7115 {
7116 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7117 rps->class = le16_to_cpu(non_clock_info->usClassification);
7118 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7119
7120 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7121 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7122 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7123 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7124 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7125 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7126 } else {
7127 rps->vclk = 0;
7128 rps->dclk = 0;
7129 }
7130
7131 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7132 adev->pm.dpm.boot_ps = rps;
7133 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7134 adev->pm.dpm.uvd_ps = rps;
7135 }
7136
7137 static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7138 struct amdgpu_ps *rps, int index,
7139 union pplib_clock_info *clock_info)
7140 {
7141 struct rv7xx_power_info *pi = rv770_get_pi(adev);
7142 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7143 struct si_power_info *si_pi = si_get_pi(adev);
7144 struct si_ps *ps = si_get_ps(rps);
7145 u16 leakage_voltage;
7146 struct rv7xx_pl *pl = &ps->performance_levels[index];
7147 int ret;
7148
7149 ps->performance_level_count = index + 1;
7150
7151 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7152 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7153 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7154 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7155
7156 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7157 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7158 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7159 pl->pcie_gen = r600_get_pcie_gen_support(adev,
7160 si_pi->sys_pcie_mask,
7161 si_pi->boot_pcie_gen,
7162 clock_info->si.ucPCIEGen);
7163
7164 /* patch up vddc if necessary */
7165 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7166 &leakage_voltage);
7167 if (ret == 0)
7168 pl->vddc = leakage_voltage;
7169
7170 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7171 pi->acpi_vddc = pl->vddc;
7172 eg_pi->acpi_vddci = pl->vddci;
7173 si_pi->acpi_pcie_gen = pl->pcie_gen;
7174 }
7175
7176 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7177 index == 0) {
7178 /* XXX disable for A0 tahiti */
7179 si_pi->ulv.supported = false;
7180 si_pi->ulv.pl = *pl;
7181 si_pi->ulv.one_pcie_lane_in_ulv = false;
7182 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7183 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7184 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7185 }
7186
7187 if (pi->min_vddc_in_table > pl->vddc)
7188 pi->min_vddc_in_table = pl->vddc;
7189
7190 if (pi->max_vddc_in_table < pl->vddc)
7191 pi->max_vddc_in_table = pl->vddc;
7192
7193 /* patch up boot state */
7194 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7195 u16 vddc, vddci, mvdd;
7196 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7197 pl->mclk = adev->clock.default_mclk;
7198 pl->sclk = adev->clock.default_sclk;
7199 pl->vddc = vddc;
7200 pl->vddci = vddci;
7201 si_pi->mvdd_bootup_value = mvdd;
7202 }
7203
7204 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7205 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7206 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7207 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7208 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7209 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7210 }
7211 }
7212
7213 union pplib_power_state {
7214 struct _ATOM_PPLIB_STATE v1;
7215 struct _ATOM_PPLIB_STATE_V2 v2;
7216 };
7217
7218 static int si_parse_power_table(struct amdgpu_device *adev)
7219 {
7220 struct amdgpu_mode_info *mode_info = &adev->mode_info;
7221 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7222 union pplib_power_state *power_state;
7223 int i, j, k, non_clock_array_index, clock_array_index;
7224 union pplib_clock_info *clock_info;
7225 struct _StateArray *state_array;
7226 struct _ClockInfoArray *clock_info_array;
7227 struct _NonClockInfoArray *non_clock_info_array;
7228 union power_info *power_info;
7229 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
7230 u16 data_offset;
7231 u8 frev, crev;
7232 u8 *power_state_offset;
7233 struct si_ps *ps;
7234
7235 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7236 &frev, &crev, &data_offset))
7237 return -EINVAL;
7238 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7239
7240 amdgpu_add_thermal_controller(adev);
7241
7242 state_array = (struct _StateArray *)
7243 (mode_info->atom_context->bios + data_offset +
7244 le16_to_cpu(power_info->pplib.usStateArrayOffset));
7245 clock_info_array = (struct _ClockInfoArray *)
7246 (mode_info->atom_context->bios + data_offset +
7247 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7248 non_clock_info_array = (struct _NonClockInfoArray *)
7249 (mode_info->atom_context->bios + data_offset +
7250 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7251
7252 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
7253 state_array->ucNumEntries, GFP_KERNEL);
7254 if (!adev->pm.dpm.ps)
7255 return -ENOMEM;
7256 power_state_offset = (u8 *)state_array->states;
7257 for (i = 0; i < state_array->ucNumEntries; i++) {
7258 u8 *idx;
7259 power_state = (union pplib_power_state *)power_state_offset;
7260 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7261 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7262 &non_clock_info_array->nonClockInfo[non_clock_array_index];
7263 ps = kzalloc(sizeof(struct si_ps), GFP_KERNEL);
7264 if (ps == NULL) {
7265 kfree(adev->pm.dpm.ps);
7266 return -ENOMEM;
7267 }
7268 adev->pm.dpm.ps[i].ps_priv = ps;
7269 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7270 non_clock_info,
7271 non_clock_info_array->ucEntrySize);
7272 k = 0;
7273 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7274 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7275 clock_array_index = idx[j];
7276 if (clock_array_index >= clock_info_array->ucNumEntries)
7277 continue;
7278 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7279 break;
7280 clock_info = (union pplib_clock_info *)
7281 ((u8 *)&clock_info_array->clockInfo[0] +
7282 (clock_array_index * clock_info_array->ucEntrySize));
7283 si_parse_pplib_clock_info(adev,
7284 &adev->pm.dpm.ps[i], k,
7285 clock_info);
7286 k++;
7287 }
7288 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7289 }
7290 adev->pm.dpm.num_ps = state_array->ucNumEntries;
7291
7292 /* fill in the vce power states */
7293 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
7294 u32 sclk, mclk;
7295 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7296 clock_info = (union pplib_clock_info *)
7297 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7298 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7299 sclk |= clock_info->si.ucEngineClockHigh << 16;
7300 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7301 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7302 adev->pm.dpm.vce_states[i].sclk = sclk;
7303 adev->pm.dpm.vce_states[i].mclk = mclk;
7304 }
7305
7306 return 0;
7307 }
7308
7309 static int si_dpm_init(struct amdgpu_device *adev)
7310 {
7311 struct rv7xx_power_info *pi;
7312 struct evergreen_power_info *eg_pi;
7313 struct ni_power_info *ni_pi;
7314 struct si_power_info *si_pi;
7315 struct atom_clock_dividers dividers;
7316 int ret;
7317 u32 mask;
7318
7319 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7320 if (si_pi == NULL)
7321 return -ENOMEM;
7322 adev->pm.dpm.priv = si_pi;
7323 ni_pi = &si_pi->ni;
7324 eg_pi = &ni_pi->eg;
7325 pi = &eg_pi->rv7xx;
7326
7327 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
7328 if (ret)
7329 si_pi->sys_pcie_mask = 0;
7330 else
7331 si_pi->sys_pcie_mask = mask;
7332 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7333 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7334
7335 si_set_max_cu_value(adev);
7336
7337 rv770_get_max_vddc(adev);
7338 si_get_leakage_vddc(adev);
7339 si_patch_dependency_tables_based_on_leakage(adev);
7340
7341 pi->acpi_vddc = 0;
7342 eg_pi->acpi_vddci = 0;
7343 pi->min_vddc_in_table = 0;
7344 pi->max_vddc_in_table = 0;
7345
7346 ret = amdgpu_get_platform_caps(adev);
7347 if (ret)
7348 return ret;
7349
7350 ret = amdgpu_parse_extended_power_table(adev);
7351 if (ret)
7352 return ret;
7353
7354 ret = si_parse_power_table(adev);
7355 if (ret)
7356 return ret;
7357
7358 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7359 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
7360 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7361 amdgpu_free_extended_power_table(adev);
7362 return -ENOMEM;
7363 }
7364 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7365 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7366 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7367 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7368 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7369 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7370 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7371 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7372 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7373
7374 if (adev->pm.dpm.voltage_response_time == 0)
7375 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7376 if (adev->pm.dpm.backbias_response_time == 0)
7377 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7378
7379 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7380 0, false, &dividers);
7381 if (ret)
7382 pi->ref_div = dividers.ref_div + 1;
7383 else
7384 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7385
7386 eg_pi->smu_uvd_hs = false;
7387
7388 pi->mclk_strobe_mode_threshold = 40000;
7389 if (si_is_special_1gb_platform(adev))
7390 pi->mclk_stutter_mode_threshold = 0;
7391 else
7392 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7393 pi->mclk_edc_enable_threshold = 40000;
7394 eg_pi->mclk_edc_wr_enable_threshold = 40000;
7395
7396 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7397
7398 pi->voltage_control =
7399 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7400 VOLTAGE_OBJ_GPIO_LUT);
7401 if (!pi->voltage_control) {
7402 si_pi->voltage_control_svi2 =
7403 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7404 VOLTAGE_OBJ_SVID2);
7405 if (si_pi->voltage_control_svi2)
7406 amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7407 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7408 }
7409
7410 pi->mvdd_control =
7411 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7412 VOLTAGE_OBJ_GPIO_LUT);
7413
7414 eg_pi->vddci_control =
7415 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7416 VOLTAGE_OBJ_GPIO_LUT);
7417 if (!eg_pi->vddci_control)
7418 si_pi->vddci_control_svi2 =
7419 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7420 VOLTAGE_OBJ_SVID2);
7421
7422 si_pi->vddc_phase_shed_control =
7423 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7424 VOLTAGE_OBJ_PHASE_LUT);
7425
7426 rv770_get_engine_memory_ss(adev);
7427
7428 pi->asi = RV770_ASI_DFLT;
7429 pi->pasi = CYPRESS_HASI_DFLT;
7430 pi->vrc = SISLANDS_VRC_DFLT;
7431
7432 pi->gfx_clock_gating = true;
7433
7434 eg_pi->sclk_deep_sleep = true;
7435 si_pi->sclk_deep_sleep_above_low = false;
7436
7437 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7438 pi->thermal_protection = true;
7439 else
7440 pi->thermal_protection = false;
7441
7442 eg_pi->dynamic_ac_timing = true;
7443
7444 eg_pi->light_sleep = true;
7445 #if defined(CONFIG_ACPI)
7446 eg_pi->pcie_performance_request =
7447 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7448 #else
7449 eg_pi->pcie_performance_request = false;
7450 #endif
7451
7452 si_pi->sram_end = SMC_RAM_END;
7453
7454 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7455 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7456 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7457 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7458 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7459 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7460 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7461
7462 si_initialize_powertune_defaults(adev);
7463
7464 /* make sure dc limits are valid */
7465 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7466 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7467 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7468 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7469
7470 si_pi->fan_ctrl_is_in_default_mode = true;
7471
7472 return 0;
7473 }
7474
7475 static void si_dpm_fini(struct amdgpu_device *adev)
7476 {
7477 int i;
7478
7479 if (adev->pm.dpm.ps)
7480 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7481 kfree(adev->pm.dpm.ps[i].ps_priv);
7482 kfree(adev->pm.dpm.ps);
7483 kfree(adev->pm.dpm.priv);
7484 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7485 amdgpu_free_extended_power_table(adev);
7486 }
7487
7488 static void si_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
7489 struct seq_file *m)
7490 {
7491 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7492 struct amdgpu_ps *rps = &eg_pi->current_rps;
7493 struct si_ps *ps = si_get_ps(rps);
7494 struct rv7xx_pl *pl;
7495 u32 current_index =
7496 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7497 CURRENT_STATE_INDEX_SHIFT;
7498
7499 if (current_index >= ps->performance_level_count) {
7500 seq_printf(m, "invalid dpm profile %d\n", current_index);
7501 } else {
7502 pl = &ps->performance_levels[current_index];
7503 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7504 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7505 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7506 }
7507 }
7508
7509 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7510 struct amdgpu_irq_src *source,
7511 unsigned type,
7512 enum amdgpu_interrupt_state state)
7513 {
7514 u32 cg_thermal_int;
7515
7516 switch (type) {
7517 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7518 switch (state) {
7519 case AMDGPU_IRQ_STATE_DISABLE:
7520 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7521 cg_thermal_int |= THERM_INT_MASK_HIGH;
7522 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7523 break;
7524 case AMDGPU_IRQ_STATE_ENABLE:
7525 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7526 cg_thermal_int &= ~THERM_INT_MASK_HIGH;
7527 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7528 break;
7529 default:
7530 break;
7531 }
7532 break;
7533
7534 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7535 switch (state) {
7536 case AMDGPU_IRQ_STATE_DISABLE:
7537 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7538 cg_thermal_int |= THERM_INT_MASK_LOW;
7539 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7540 break;
7541 case AMDGPU_IRQ_STATE_ENABLE:
7542 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7543 cg_thermal_int &= ~THERM_INT_MASK_LOW;
7544 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7545 break;
7546 default:
7547 break;
7548 }
7549 break;
7550
7551 default:
7552 break;
7553 }
7554 return 0;
7555 }
7556
7557 static int si_dpm_process_interrupt(struct amdgpu_device *adev,
7558 struct amdgpu_irq_src *source,
7559 struct amdgpu_iv_entry *entry)
7560 {
7561 bool queue_thermal = false;
7562
7563 if (entry == NULL)
7564 return -EINVAL;
7565
7566 switch (entry->src_id) {
7567 case 230: /* thermal low to high */
7568 DRM_DEBUG("IH: thermal low to high\n");
7569 adev->pm.dpm.thermal.high_to_low = false;
7570 queue_thermal = true;
7571 break;
7572 case 231: /* thermal high to low */
7573 DRM_DEBUG("IH: thermal high to low\n");
7574 adev->pm.dpm.thermal.high_to_low = true;
7575 queue_thermal = true;
7576 break;
7577 default:
7578 break;
7579 }
7580
7581 if (queue_thermal)
7582 schedule_work(&adev->pm.dpm.thermal.work);
7583
7584 return 0;
7585 }
7586
7587 static int si_dpm_late_init(void *handle)
7588 {
7589 int ret;
7590 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7591
7592 if (!amdgpu_dpm)
7593 return 0;
7594
7595 /* init the sysfs and debugfs files late */
7596 ret = amdgpu_pm_sysfs_init(adev);
7597 if (ret)
7598 return ret;
7599
7600 ret = si_set_temperature_range(adev);
7601 if (ret)
7602 return ret;
7603 #if 0 //TODO ?
7604 si_dpm_powergate_uvd(adev, true);
7605 #endif
7606 return 0;
7607 }
7608
7609 /**
7610 * si_dpm_init_microcode - load ucode images from disk
7611 *
7612 * @adev: amdgpu_device pointer
7613 *
7614 * Use the firmware interface to load the ucode images into
7615 * the driver (not loaded into hw).
7616 * Returns 0 on success, error on failure.
7617 */
7618 static int si_dpm_init_microcode(struct amdgpu_device *adev)
7619 {
7620 const char *chip_name;
7621 char fw_name[30];
7622 int err;
7623
7624 DRM_DEBUG("\n");
7625 switch (adev->asic_type) {
7626 case CHIP_TAHITI:
7627 chip_name = "tahiti";
7628 break;
7629 case CHIP_PITCAIRN:
7630 if ((adev->pdev->revision == 0x81) &&
7631 ((adev->pdev->device == 0x6810) ||
7632 (adev->pdev->device == 0x6811)))
7633 chip_name = "pitcairn_k";
7634 else
7635 chip_name = "pitcairn";
7636 break;
7637 case CHIP_VERDE:
7638 if (((adev->pdev->device == 0x6820) &&
7639 ((adev->pdev->revision == 0x81) ||
7640 (adev->pdev->revision == 0x83))) ||
7641 ((adev->pdev->device == 0x6821) &&
7642 ((adev->pdev->revision == 0x83) ||
7643 (adev->pdev->revision == 0x87))) ||
7644 ((adev->pdev->revision == 0x87) &&
7645 ((adev->pdev->device == 0x6823) ||
7646 (adev->pdev->device == 0x682b))))
7647 chip_name = "verde_k";
7648 else
7649 chip_name = "verde";
7650 break;
7651 case CHIP_OLAND:
7652 if (((adev->pdev->revision == 0x81) &&
7653 ((adev->pdev->device == 0x6600) ||
7654 (adev->pdev->device == 0x6604) ||
7655 (adev->pdev->device == 0x6605) ||
7656 (adev->pdev->device == 0x6610))) ||
7657 ((adev->pdev->revision == 0x83) &&
7658 (adev->pdev->device == 0x6610)))
7659 chip_name = "oland_k";
7660 else
7661 chip_name = "oland";
7662 break;
7663 case CHIP_HAINAN:
7664 if (((adev->pdev->revision == 0x81) &&
7665 (adev->pdev->device == 0x6660)) ||
7666 ((adev->pdev->revision == 0x83) &&
7667 ((adev->pdev->device == 0x6660) ||
7668 (adev->pdev->device == 0x6663) ||
7669 (adev->pdev->device == 0x6665) ||
7670 (adev->pdev->device == 0x6667))))
7671 chip_name = "hainan_k";
7672 else if ((adev->pdev->revision == 0xc3) &&
7673 (adev->pdev->device == 0x6665))
7674 chip_name = "banks_k_2";
7675 else
7676 chip_name = "hainan";
7677 break;
7678 default: BUG();
7679 }
7680
7681 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
7682 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
7683 if (err)
7684 goto out;
7685 err = amdgpu_ucode_validate(adev->pm.fw);
7686
7687 out:
7688 if (err) {
7689 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
7690 err, fw_name);
7691 release_firmware(adev->pm.fw);
7692 adev->pm.fw = NULL;
7693 }
7694 return err;
7695
7696 }
7697
7698 static int si_dpm_sw_init(void *handle)
7699 {
7700 int ret;
7701 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7702
7703 ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq);
7704 if (ret)
7705 return ret;
7706
7707 ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq);
7708 if (ret)
7709 return ret;
7710
7711 /* default to balanced state */
7712 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7713 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7714 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
7715 adev->pm.default_sclk = adev->clock.default_sclk;
7716 adev->pm.default_mclk = adev->clock.default_mclk;
7717 adev->pm.current_sclk = adev->clock.default_sclk;
7718 adev->pm.current_mclk = adev->clock.default_mclk;
7719 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7720
7721 if (amdgpu_dpm == 0)
7722 return 0;
7723
7724 ret = si_dpm_init_microcode(adev);
7725 if (ret)
7726 return ret;
7727
7728 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7729 mutex_lock(&adev->pm.mutex);
7730 ret = si_dpm_init(adev);
7731 if (ret)
7732 goto dpm_failed;
7733 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7734 if (amdgpu_dpm == 1)
7735 amdgpu_pm_print_power_states(adev);
7736 mutex_unlock(&adev->pm.mutex);
7737 DRM_INFO("amdgpu: dpm initialized\n");
7738
7739 return 0;
7740
7741 dpm_failed:
7742 si_dpm_fini(adev);
7743 mutex_unlock(&adev->pm.mutex);
7744 DRM_ERROR("amdgpu: dpm initialization failed\n");
7745 return ret;
7746 }
7747
7748 static int si_dpm_sw_fini(void *handle)
7749 {
7750 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7751
7752 flush_work(&adev->pm.dpm.thermal.work);
7753
7754 mutex_lock(&adev->pm.mutex);
7755 amdgpu_pm_sysfs_fini(adev);
7756 si_dpm_fini(adev);
7757 mutex_unlock(&adev->pm.mutex);
7758
7759 return 0;
7760 }
7761
7762 static int si_dpm_hw_init(void *handle)
7763 {
7764 int ret;
7765
7766 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7767
7768 if (!amdgpu_dpm)
7769 return 0;
7770
7771 mutex_lock(&adev->pm.mutex);
7772 si_dpm_setup_asic(adev);
7773 ret = si_dpm_enable(adev);
7774 if (ret)
7775 adev->pm.dpm_enabled = false;
7776 else
7777 adev->pm.dpm_enabled = true;
7778 mutex_unlock(&adev->pm.mutex);
7779
7780 return ret;
7781 }
7782
7783 static int si_dpm_hw_fini(void *handle)
7784 {
7785 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7786
7787 if (adev->pm.dpm_enabled) {
7788 mutex_lock(&adev->pm.mutex);
7789 si_dpm_disable(adev);
7790 mutex_unlock(&adev->pm.mutex);
7791 }
7792
7793 return 0;
7794 }
7795
7796 static int si_dpm_suspend(void *handle)
7797 {
7798 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7799
7800 if (adev->pm.dpm_enabled) {
7801 mutex_lock(&adev->pm.mutex);
7802 /* disable dpm */
7803 si_dpm_disable(adev);
7804 /* reset the power state */
7805 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7806 mutex_unlock(&adev->pm.mutex);
7807 }
7808 return 0;
7809 }
7810
7811 static int si_dpm_resume(void *handle)
7812 {
7813 int ret;
7814 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7815
7816 if (adev->pm.dpm_enabled) {
7817 /* asic init will reset to the boot state */
7818 mutex_lock(&adev->pm.mutex);
7819 si_dpm_setup_asic(adev);
7820 ret = si_dpm_enable(adev);
7821 if (ret)
7822 adev->pm.dpm_enabled = false;
7823 else
7824 adev->pm.dpm_enabled = true;
7825 mutex_unlock(&adev->pm.mutex);
7826 if (adev->pm.dpm_enabled)
7827 amdgpu_pm_compute_clocks(adev);
7828 }
7829 return 0;
7830 }
7831
7832 static bool si_dpm_is_idle(void *handle)
7833 {
7834 /* XXX */
7835 return true;
7836 }
7837
7838 static int si_dpm_wait_for_idle(void *handle)
7839 {
7840 /* XXX */
7841 return 0;
7842 }
7843
7844 static int si_dpm_soft_reset(void *handle)
7845 {
7846 return 0;
7847 }
7848
7849 static int si_dpm_set_clockgating_state(void *handle,
7850 enum amd_clockgating_state state)
7851 {
7852 return 0;
7853 }
7854
7855 static int si_dpm_set_powergating_state(void *handle,
7856 enum amd_powergating_state state)
7857 {
7858 return 0;
7859 }
7860
7861 /* get temperature in millidegrees */
7862 static int si_dpm_get_temp(struct amdgpu_device *adev)
7863 {
7864 u32 temp;
7865 int actual_temp = 0;
7866
7867 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
7868 CTF_TEMP_SHIFT;
7869
7870 if (temp & 0x200)
7871 actual_temp = 255;
7872 else
7873 actual_temp = temp & 0x1ff;
7874
7875 actual_temp = (actual_temp * 1000);
7876
7877 return actual_temp;
7878 }
7879
7880 static u32 si_dpm_get_sclk(struct amdgpu_device *adev, bool low)
7881 {
7882 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7883 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7884
7885 if (low)
7886 return requested_state->performance_levels[0].sclk;
7887 else
7888 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
7889 }
7890
7891 static u32 si_dpm_get_mclk(struct amdgpu_device *adev, bool low)
7892 {
7893 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7894 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7895
7896 if (low)
7897 return requested_state->performance_levels[0].mclk;
7898 else
7899 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
7900 }
7901
7902 static void si_dpm_print_power_state(struct amdgpu_device *adev,
7903 struct amdgpu_ps *rps)
7904 {
7905 struct si_ps *ps = si_get_ps(rps);
7906 struct rv7xx_pl *pl;
7907 int i;
7908
7909 amdgpu_dpm_print_class_info(rps->class, rps->class2);
7910 amdgpu_dpm_print_cap_info(rps->caps);
7911 DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7912 for (i = 0; i < ps->performance_level_count; i++) {
7913 pl = &ps->performance_levels[i];
7914 if (adev->asic_type >= CHIP_TAHITI)
7915 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7916 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7917 else
7918 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u\n",
7919 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
7920 }
7921 amdgpu_dpm_print_ps_status(adev, rps);
7922 }
7923
7924 static int si_dpm_early_init(void *handle)
7925 {
7926
7927 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7928
7929 si_dpm_set_dpm_funcs(adev);
7930 si_dpm_set_irq_funcs(adev);
7931 return 0;
7932 }
7933
7934 static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1,
7935 const struct rv7xx_pl *si_cpl2)
7936 {
7937 return ((si_cpl1->mclk == si_cpl2->mclk) &&
7938 (si_cpl1->sclk == si_cpl2->sclk) &&
7939 (si_cpl1->pcie_gen == si_cpl2->pcie_gen) &&
7940 (si_cpl1->vddc == si_cpl2->vddc) &&
7941 (si_cpl1->vddci == si_cpl2->vddci));
7942 }
7943
7944 static int si_check_state_equal(struct amdgpu_device *adev,
7945 struct amdgpu_ps *cps,
7946 struct amdgpu_ps *rps,
7947 bool *equal)
7948 {
7949 struct si_ps *si_cps;
7950 struct si_ps *si_rps;
7951 int i;
7952
7953 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
7954 return -EINVAL;
7955
7956 si_cps = si_get_ps(cps);
7957 si_rps = si_get_ps(rps);
7958
7959 if (si_cps == NULL) {
7960 printk("si_cps is NULL\n");
7961 *equal = false;
7962 return 0;
7963 }
7964
7965 if (si_cps->performance_level_count != si_rps->performance_level_count) {
7966 *equal = false;
7967 return 0;
7968 }
7969
7970 for (i = 0; i < si_cps->performance_level_count; i++) {
7971 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]),
7972 &(si_rps->performance_levels[i]))) {
7973 *equal = false;
7974 return 0;
7975 }
7976 }
7977
7978 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
7979 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
7980 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
7981
7982 return 0;
7983 }
7984
7985 static int si_dpm_read_sensor(struct amdgpu_device *adev, int idx,
7986 void *value, int *size)
7987 {
7988 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7989 struct amdgpu_ps *rps = &eg_pi->current_rps;
7990 struct si_ps *ps = si_get_ps(rps);
7991 uint32_t sclk, mclk;
7992 u32 pl_index =
7993 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7994 CURRENT_STATE_INDEX_SHIFT;
7995
7996 /* size must be at least 4 bytes for all sensors */
7997 if (*size < 4)
7998 return -EINVAL;
7999
8000 switch (idx) {
8001 case AMDGPU_PP_SENSOR_GFX_SCLK:
8002 if (pl_index < ps->performance_level_count) {
8003 sclk = ps->performance_levels[pl_index].sclk;
8004 *((uint32_t *)value) = sclk;
8005 *size = 4;
8006 return 0;
8007 }
8008 return -EINVAL;
8009 case AMDGPU_PP_SENSOR_GFX_MCLK:
8010 if (pl_index < ps->performance_level_count) {
8011 mclk = ps->performance_levels[pl_index].mclk;
8012 *((uint32_t *)value) = mclk;
8013 *size = 4;
8014 return 0;
8015 }
8016 return -EINVAL;
8017 case AMDGPU_PP_SENSOR_GPU_TEMP:
8018 *((uint32_t *)value) = si_dpm_get_temp(adev);
8019 *size = 4;
8020 return 0;
8021 default:
8022 return -EINVAL;
8023 }
8024 }
8025
8026 const struct amd_ip_funcs si_dpm_ip_funcs = {
8027 .name = "si_dpm",
8028 .early_init = si_dpm_early_init,
8029 .late_init = si_dpm_late_init,
8030 .sw_init = si_dpm_sw_init,
8031 .sw_fini = si_dpm_sw_fini,
8032 .hw_init = si_dpm_hw_init,
8033 .hw_fini = si_dpm_hw_fini,
8034 .suspend = si_dpm_suspend,
8035 .resume = si_dpm_resume,
8036 .is_idle = si_dpm_is_idle,
8037 .wait_for_idle = si_dpm_wait_for_idle,
8038 .soft_reset = si_dpm_soft_reset,
8039 .set_clockgating_state = si_dpm_set_clockgating_state,
8040 .set_powergating_state = si_dpm_set_powergating_state,
8041 };
8042
8043 static const struct amdgpu_dpm_funcs si_dpm_funcs = {
8044 .get_temperature = &si_dpm_get_temp,
8045 .pre_set_power_state = &si_dpm_pre_set_power_state,
8046 .set_power_state = &si_dpm_set_power_state,
8047 .post_set_power_state = &si_dpm_post_set_power_state,
8048 .display_configuration_changed = &si_dpm_display_configuration_changed,
8049 .get_sclk = &si_dpm_get_sclk,
8050 .get_mclk = &si_dpm_get_mclk,
8051 .print_power_state = &si_dpm_print_power_state,
8052 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8053 .force_performance_level = &si_dpm_force_performance_level,
8054 .vblank_too_short = &si_dpm_vblank_too_short,
8055 .set_fan_control_mode = &si_dpm_set_fan_control_mode,
8056 .get_fan_control_mode = &si_dpm_get_fan_control_mode,
8057 .set_fan_speed_percent = &si_dpm_set_fan_speed_percent,
8058 .get_fan_speed_percent = &si_dpm_get_fan_speed_percent,
8059 .check_state_equal = &si_check_state_equal,
8060 .get_vce_clock_state = amdgpu_get_vce_clock_state,
8061 .read_sensor = &si_dpm_read_sensor,
8062 };
8063
8064 static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev)
8065 {
8066 if (adev->pm.funcs == NULL)
8067 adev->pm.funcs = &si_dpm_funcs;
8068 }
8069
8070 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8071 .set = si_dpm_set_interrupt_state,
8072 .process = si_dpm_process_interrupt,
8073 };
8074
8075 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8076 {
8077 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8078 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
8079 }
8080
CRIS linux kernel tree