drivers/gpu/drm/amd/amdgpu/vega10_ih.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "drmP.h"
  24 #include "amdgpu.h"
  25 #include "amdgpu_ih.h"
  26 #include "soc15.h"
  27
  28
  29 #include "vega10/soc15ip.h"
  30 #include "vega10/OSSSYS/osssys_4_0_offset.h"
  31 #include "vega10/OSSSYS/osssys_4_0_sh_mask.h"
  32
  33 #include "soc15_common.h"
  34 #include "vega10_ih.h"
  35
  36
  37
  38 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
  39
  40 /**
  41  * vega10_ih_enable_interrupts - Enable the interrupt ring buffer
  42  *
  43  * @adev: amdgpu_device pointer
  44  *
  45  * Enable the interrupt ring buffer (VEGA10).
  46  */
  47 static void vega10_ih_enable_interrupts(struct amdgpu_device *adev)
  48 {
  49         u32 ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
  50
  51         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
  52         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
  53         WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl);
  54         adev->irq.ih.enabled = true;
  55 }
  56
  57 /**
  58  * vega10_ih_disable_interrupts - Disable the interrupt ring buffer
  59  *
  60  * @adev: amdgpu_device pointer
  61  *
  62  * Disable the interrupt ring buffer (VEGA10).
  63  */
  64 static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
  65 {
  66         u32 ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
  67
  68         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
  69         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
  70         WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl);
  71         /* set rptr, wptr to 0 */
  72         WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), 0);
  73         WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR), 0);
  74         adev->irq.ih.enabled = false;
  75         adev->irq.ih.rptr = 0;
  76 }
  77
  78 /**
  79  * vega10_ih_irq_init - init and enable the interrupt ring
  80  *
  81  * @adev: amdgpu_device pointer
  82  *
  83  * Allocate a ring buffer for the interrupt controller,
  84  * enable the RLC, disable interrupts, enable the IH
  85  * ring buffer and enable it (VI).
  86  * Called at device load and reume.
  87  * Returns 0 for success, errors for failure.
  88  */
  89 static int vega10_ih_irq_init(struct amdgpu_device *adev)
  90 {
  91         int ret = 0;
  92         int rb_bufsz;
  93         u32 ih_rb_cntl, ih_doorbell_rtpr;
  94         u32 tmp;
  95         u64 wptr_off;
  96
  97         /* disable irqs */
  98         vega10_ih_disable_interrupts(adev);
  99
 100         nbio_v6_1_ih_control(adev);
 101
 102         ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
 103         /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
 104         if (adev->irq.ih.use_bus_addr) {
 105                 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.rb_dma_addr >> 8);
 106                 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff);
 107                 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1);
 108         } else {
 109                 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.gpu_addr >> 8);
 110                 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), (adev->irq.ih.gpu_addr >> 40) & 0xff);
 111                 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 4);
 112         }
 113         rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
 114         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
 115         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
 116         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
 117         /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
 118         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
 119         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
 120         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
 121         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
 122
 123         if (adev->irq.msi_enabled)
 124                 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);
 125
 126         WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl);
 127
 128         /* set the writeback address whether it's enabled or not */
 129         if (adev->irq.ih.use_bus_addr)
 130                 wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4);
 131         else
 132                 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
 133         WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO), lower_32_bits(wptr_off));
 134         WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI), upper_32_bits(wptr_off) & 0xFF);
 135
 136         /* set rptr, wptr to 0 */
 137         WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), 0);
 138         WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR), 0);
 139
 140         ih_doorbell_rtpr = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR));
 141         if (adev->irq.ih.use_doorbell) {
 142                 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
 143                                                  OFFSET, adev->irq.ih.doorbell_index);
 144                 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
 145                                                  ENABLE, 1);
 146         } else {
 147                 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
 148                                                  ENABLE, 0);
 149         }
 150         WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR), ih_doorbell_rtpr);
 151         nbio_v6_1_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index);
 152
 153         tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL));
 154         tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
 155                             CLIENT18_IS_STORM_CLIENT, 1);
 156         WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL), tmp);
 157
 158         tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_INT_FLOOD_CNTL));
 159         tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
 160         WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_INT_FLOOD_CNTL), tmp);
 161
 162         pci_set_master(adev->pdev);
 163
 164         /* enable interrupts */
 165         vega10_ih_enable_interrupts(adev);
 166
 167         return ret;
 168 }
 169
 170 /**
 171  * vega10_ih_irq_disable - disable interrupts
 172  *
 173  * @adev: amdgpu_device pointer
 174  *
 175  * Disable interrupts on the hw (VEGA10).
 176  */
 177 static void vega10_ih_irq_disable(struct amdgpu_device *adev)
 178 {
 179         vega10_ih_disable_interrupts(adev);
 180
 181         /* Wait and acknowledge irq */
 182         mdelay(1);
 183 }
 184
 185 /**
 186  * vega10_ih_get_wptr - get the IH ring buffer wptr
 187  *
 188  * @adev: amdgpu_device pointer
 189  *
 190  * Get the IH ring buffer wptr from either the register
 191  * or the writeback memory buffer (VEGA10).  Also check for
 192  * ring buffer overflow and deal with it.
 193  * Returns the value of the wptr.
 194  */
 195 static u32 vega10_ih_get_wptr(struct amdgpu_device *adev)
 196 {
 197         u32 wptr, tmp;
 198
 199         if (adev->irq.ih.use_bus_addr)
 200                 wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]);
 201         else
 202                 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
 203
 204         if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
 205                 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
 206
 207                 /* When a ring buffer overflow happen start parsing interrupt
 208                  * from the last not overwritten vector (wptr + 32). Hopefully
 209                  * this should allow us to catchup.
 210                  */
 211                 tmp = (wptr + 32) & adev->irq.ih.ptr_mask;
 212                 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
 213                         wptr, adev->irq.ih.rptr, tmp);
 214                 adev->irq.ih.rptr = tmp;
 215
 216                 tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
 217                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
 218                 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp);
 219         }
 220         return (wptr & adev->irq.ih.ptr_mask);
 221 }
 222
 223 /**
 224  * vega10_ih_decode_iv - decode an interrupt vector
 225  *
 226  * @adev: amdgpu_device pointer
 227  *
 228  * Decodes the interrupt vector at the current rptr
 229  * position and also advance the position.
 230  */
 231 static void vega10_ih_decode_iv(struct amdgpu_device *adev,
 232                                  struct amdgpu_iv_entry *entry)
 233 {
 234         /* wptr/rptr are in bytes! */
 235         u32 ring_index = adev->irq.ih.rptr >> 2;
 236         uint32_t dw[8];
 237
 238         dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
 239         dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
 240         dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
 241         dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
 242         dw[4] = le32_to_cpu(adev->irq.ih.ring[ring_index + 4]);
 243         dw[5] = le32_to_cpu(adev->irq.ih.ring[ring_index + 5]);
 244         dw[6] = le32_to_cpu(adev->irq.ih.ring[ring_index + 6]);
 245         dw[7] = le32_to_cpu(adev->irq.ih.ring[ring_index + 7]);
 246
 247         entry->client_id = dw[0] & 0xff;
 248         entry->src_id = (dw[0] >> 8) & 0xff;
 249         entry->ring_id = (dw[0] >> 16) & 0xff;
 250         entry->vm_id = (dw[0] >> 24) & 0xf;
 251         entry->vm_id_src = (dw[0] >> 31);
 252         entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32);
 253         entry->timestamp_src = dw[2] >> 31;
 254         entry->pas_id = dw[3] & 0xffff;
 255         entry->pasid_src = dw[3] >> 31;
 256         entry->src_data[0] = dw[4];
 257         entry->src_data[1] = dw[5];
 258         entry->src_data[2] = dw[6];
 259         entry->src_data[3] = dw[7];
 260
 261
 262         /* wptr/rptr are in bytes! */
 263         adev->irq.ih.rptr += 32;
 264 }
 265
 266 /**
 267  * vega10_ih_set_rptr - set the IH ring buffer rptr
 268  *
 269  * @adev: amdgpu_device pointer
 270  *
 271  * Set the IH ring buffer rptr.
 272  */
 273 static void vega10_ih_set_rptr(struct amdgpu_device *adev)
 274 {
 275         if (adev->irq.ih.use_doorbell) {
 276                 /* XXX check if swapping is necessary on BE */
 277                 if (adev->irq.ih.use_bus_addr)
 278                         adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
 279                 else
 280                         adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
 281                 WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);
 282         } else {
 283                 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), adev->irq.ih.rptr);
 284         }
 285 }
 286
 287 static int vega10_ih_early_init(void *handle)
 288 {
 289         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 290
 291         vega10_ih_set_interrupt_funcs(adev);
 292         return 0;
 293 }
 294
 295 static int vega10_ih_sw_init(void *handle)
 296 {
 297         int r;
 298         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 299
 300         r = amdgpu_ih_ring_init(adev, 256 * 1024, true);
 301         if (r)
 302                 return r;
 303
 304         adev->irq.ih.use_doorbell = true;
 305         adev->irq.ih.doorbell_index = AMDGPU_DOORBELL64_IH << 1;
 306
 307         r = amdgpu_irq_init(adev);
 308
 309         return r;
 310 }
 311
 312 static int vega10_ih_sw_fini(void *handle)
 313 {
 314         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 315
 316         amdgpu_irq_fini(adev);
 317         amdgpu_ih_ring_fini(adev);
 318
 319         return 0;
 320 }
 321
 322 static int vega10_ih_hw_init(void *handle)
 323 {
 324         int r;
 325         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 326
 327         r = vega10_ih_irq_init(adev);
 328         if (r)
 329                 return r;
 330
 331         return 0;
 332 }
 333
 334 static int vega10_ih_hw_fini(void *handle)
 335 {
 336         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 337
 338         vega10_ih_irq_disable(adev);
 339
 340         return 0;
 341 }
 342
 343 static int vega10_ih_suspend(void *handle)
 344 {
 345         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 346
 347         return vega10_ih_hw_fini(adev);
 348 }
 349
 350 static int vega10_ih_resume(void *handle)
 351 {
 352         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 353
 354         return vega10_ih_hw_init(adev);
 355 }
 356
 357 static bool vega10_ih_is_idle(void *handle)
 358 {
 359         /* todo */
 360         return true;
 361 }
 362
 363 static int vega10_ih_wait_for_idle(void *handle)
 364 {
 365         /* todo */
 366         return -ETIMEDOUT;
 367 }
 368
 369 static int vega10_ih_soft_reset(void *handle)
 370 {
 371         /* todo */
 372
 373         return 0;
 374 }
 375
 376 static int vega10_ih_set_clockgating_state(void *handle,
 377                                           enum amd_clockgating_state state)
 378 {
 379         return 0;
 380 }
 381
 382 static int vega10_ih_set_powergating_state(void *handle,
 383                                           enum amd_powergating_state state)
 384 {
 385         return 0;
 386 }
 387
 388 const struct amd_ip_funcs vega10_ih_ip_funcs = {
 389         .name = "vega10_ih",
 390         .early_init = vega10_ih_early_init,
 391         .late_init = NULL,
 392         .sw_init = vega10_ih_sw_init,
 393         .sw_fini = vega10_ih_sw_fini,
 394         .hw_init = vega10_ih_hw_init,
 395         .hw_fini = vega10_ih_hw_fini,
 396         .suspend = vega10_ih_suspend,
 397         .resume = vega10_ih_resume,
 398         .is_idle = vega10_ih_is_idle,
 399         .wait_for_idle = vega10_ih_wait_for_idle,
 400         .soft_reset = vega10_ih_soft_reset,
 401         .set_clockgating_state = vega10_ih_set_clockgating_state,
 402         .set_powergating_state = vega10_ih_set_powergating_state,
 403 };
 404
 405 static const struct amdgpu_ih_funcs vega10_ih_funcs = {
 406         .get_wptr = vega10_ih_get_wptr,
 407         .decode_iv = vega10_ih_decode_iv,
 408         .set_rptr = vega10_ih_set_rptr
 409 };
 410
 411 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev)
 412 {
 413         if (adev->irq.ih_funcs == NULL)
 414                 adev->irq.ih_funcs = &vega10_ih_funcs;
 415 }
 416
 417 const struct amdgpu_ip_block_version vega10_ih_ip_block =
 418 {
 419         .type = AMD_IP_BLOCK_TYPE_IH,
 420         .major = 4,
 421         .minor = 0,
 422         .rev = 0,
 423         .funcs = &vega10_ih_ip_funcs,
 424 };