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proc: Fix proc_sys_prune_dcache to hold a sb reference
[cris-mirror.git] / drivers / gpu / drm / exynos / exynos5433_drm_decon.c
blobc0e8d3302292c9c9329ca4795b4d9ffb3465a178
1 /* drivers/gpu/drm/exynos5433_drm_decon.c
2 *
3 * Copyright (C) 2015 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Hyungwon Hwang <human.hwang@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundationr
11 */
12
13 #include <linux/platform_device.h>
14 #include <linux/clk.h>
15 #include <linux/component.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/of_device.h>
18 #include <linux/of_gpio.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regmap.h>
21
22 #include <video/exynos5433_decon.h>
23
24 #include "exynos_drm_drv.h"
25 #include "exynos_drm_crtc.h"
26 #include "exynos_drm_fb.h"
27 #include "exynos_drm_plane.h"
28 #include "exynos_drm_iommu.h"
29
30 #define DSD_CFG_MUX 0x1004
31 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
32
33 #define WINDOWS_NR 3
34 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
35
36 #define IFTYPE_I80 (1 << 0)
37 #define I80_HW_TRG (1 << 1)
38 #define IFTYPE_HDMI (1 << 2)
39
40 static const char * const decon_clks_name[] = {
41 "pclk",
42 "aclk_decon",
43 "aclk_smmu_decon0x",
44 "aclk_xiu_decon0x",
45 "pclk_smmu_decon0x",
46 "sclk_decon_vclk",
47 "sclk_decon_eclk",
48 };
49
50 enum decon_flag_bits {
51 BIT_CLKS_ENABLED,
52 BIT_IRQS_ENABLED,
53 BIT_WIN_UPDATED,
54 BIT_SUSPENDED,
55 BIT_REQUEST_UPDATE
56 };
57
58 struct decon_context {
59 struct device *dev;
60 struct drm_device *drm_dev;
61 struct exynos_drm_crtc *crtc;
62 struct exynos_drm_plane planes[WINDOWS_NR];
63 struct exynos_drm_plane_config configs[WINDOWS_NR];
64 void __iomem *addr;
65 struct regmap *sysreg;
66 struct clk *clks[ARRAY_SIZE(decon_clks_name)];
67 int pipe;
68 unsigned long flags;
69 unsigned long out_type;
70 int first_win;
71 spinlock_t vblank_lock;
72 u32 frame_id;
73 };
74
75 static const uint32_t decon_formats[] = {
76 DRM_FORMAT_XRGB1555,
77 DRM_FORMAT_RGB565,
78 DRM_FORMAT_XRGB8888,
79 DRM_FORMAT_ARGB8888,
80 };
81
82 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
83 DRM_PLANE_TYPE_PRIMARY,
84 DRM_PLANE_TYPE_OVERLAY,
85 DRM_PLANE_TYPE_CURSOR,
86 };
87
88 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
89 u32 val)
90 {
91 val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
92 writel(val, ctx->addr + reg);
93 }
94
95 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
96 {
97 struct decon_context *ctx = crtc->ctx;
98 u32 val;
99
100 if (test_bit(BIT_SUSPENDED, &ctx->flags))
101 return -EPERM;
102
103 if (!test_and_set_bit(BIT_IRQS_ENABLED, &ctx->flags)) {
104 val = VIDINTCON0_INTEN;
105 if (ctx->out_type & IFTYPE_I80)
106 val |= VIDINTCON0_FRAMEDONE;
107 else
108 val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP;
109
110 writel(val, ctx->addr + DECON_VIDINTCON0);
111 }
112
113 return 0;
114 }
115
116 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
117 {
118 struct decon_context *ctx = crtc->ctx;
119
120 if (test_bit(BIT_SUSPENDED, &ctx->flags))
121 return;
122
123 if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
124 writel(0, ctx->addr + DECON_VIDINTCON0);
125 }
126
127 /* return number of starts/ends of frame transmissions since reset */
128 static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
129 {
130 u32 frm, pfrm, status, cnt = 2;
131
132 /* To get consistent result repeat read until frame id is stable.
133 * Usually the loop will be executed once, in rare cases when the loop
134 * is executed at frame change time 2nd pass will be needed.
135 */
136 frm = readl(ctx->addr + DECON_CRFMID);
137 do {
138 status = readl(ctx->addr + DECON_VIDCON1);
139 pfrm = frm;
140 frm = readl(ctx->addr + DECON_CRFMID);
141 } while (frm != pfrm && --cnt);
142
143 /* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case
144 * of RGB, it should be taken into account.
145 */
146 if (!frm)
147 return 0;
148
149 switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) {
150 case VIDCON1_VSTATUS_VS:
151 if (!(ctx->out_type & IFTYPE_I80))
152 --frm;
153 break;
154 case VIDCON1_VSTATUS_BP:
155 --frm;
156 break;
157 case VIDCON1_I80_ACTIVE:
158 case VIDCON1_VSTATUS_AC:
159 if (end)
160 --frm;
161 break;
162 default:
163 break;
164 }
165
166 return frm;
167 }
168
169 static void decon_setup_trigger(struct decon_context *ctx)
170 {
171 if (!(ctx->out_type & (IFTYPE_I80 | I80_HW_TRG)))
172 return;
173
174 if (!(ctx->out_type & I80_HW_TRG)) {
175 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
176 TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
177 ctx->addr + DECON_TRIGCON);
178 return;
179 }
180
181 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
182 | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
183
184 if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
185 DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
186 DRM_ERROR("Cannot update sysreg.\n");
187 }
188
189 static void decon_commit(struct exynos_drm_crtc *crtc)
190 {
191 struct decon_context *ctx = crtc->ctx;
192 struct drm_display_mode *m = &crtc->base.mode;
193 bool interlaced = false;
194 u32 val;
195
196 if (test_bit(BIT_SUSPENDED, &ctx->flags))
197 return;
198
199 if (ctx->out_type & IFTYPE_HDMI) {
200 m->crtc_hsync_start = m->crtc_hdisplay + 10;
201 m->crtc_hsync_end = m->crtc_htotal - 92;
202 m->crtc_vsync_start = m->crtc_vdisplay + 1;
203 m->crtc_vsync_end = m->crtc_vsync_start + 1;
204 if (m->flags & DRM_MODE_FLAG_INTERLACE)
205 interlaced = true;
206 }
207
208 decon_setup_trigger(ctx);
209
210 /* lcd on and use command if */
211 val = VIDOUT_LCD_ON;
212 if (interlaced)
213 val |= VIDOUT_INTERLACE_EN_F;
214 if (ctx->out_type & IFTYPE_I80) {
215 val |= VIDOUT_COMMAND_IF;
216 } else {
217 val |= VIDOUT_RGB_IF;
218 }
219
220 writel(val, ctx->addr + DECON_VIDOUTCON0);
221
222 if (interlaced)
223 val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) |
224 VIDTCON2_HOZVAL(m->hdisplay - 1);
225 else
226 val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
227 VIDTCON2_HOZVAL(m->hdisplay - 1);
228 writel(val, ctx->addr + DECON_VIDTCON2);
229
230 if (!(ctx->out_type & IFTYPE_I80)) {
231 int vbp = m->crtc_vtotal - m->crtc_vsync_end;
232 int vfp = m->crtc_vsync_start - m->crtc_vdisplay;
233
234 if (interlaced)
235 vbp = vbp / 2 - 1;
236 val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1);
237 writel(val, ctx->addr + DECON_VIDTCON00);
238
239 val = VIDTCON01_VSPW_F(
240 m->crtc_vsync_end - m->crtc_vsync_start - 1);
241 writel(val, ctx->addr + DECON_VIDTCON01);
242
243 val = VIDTCON10_HBPD_F(
244 m->crtc_htotal - m->crtc_hsync_end - 1) |
245 VIDTCON10_HFPD_F(
246 m->crtc_hsync_start - m->crtc_hdisplay - 1);
247 writel(val, ctx->addr + DECON_VIDTCON10);
248
249 val = VIDTCON11_HSPW_F(
250 m->crtc_hsync_end - m->crtc_hsync_start - 1);
251 writel(val, ctx->addr + DECON_VIDTCON11);
252 }
253
254 /* enable output and display signal */
255 decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
256
257 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
258 }
259
260 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
261 struct drm_framebuffer *fb)
262 {
263 unsigned long val;
264
265 val = readl(ctx->addr + DECON_WINCONx(win));
266 val &= ~WINCONx_BPPMODE_MASK;
267
268 switch (fb->format->format) {
269 case DRM_FORMAT_XRGB1555:
270 val |= WINCONx_BPPMODE_16BPP_I1555;
271 val |= WINCONx_HAWSWP_F;
272 val |= WINCONx_BURSTLEN_16WORD;
273 break;
274 case DRM_FORMAT_RGB565:
275 val |= WINCONx_BPPMODE_16BPP_565;
276 val |= WINCONx_HAWSWP_F;
277 val |= WINCONx_BURSTLEN_16WORD;
278 break;
279 case DRM_FORMAT_XRGB8888:
280 val |= WINCONx_BPPMODE_24BPP_888;
281 val |= WINCONx_WSWP_F;
282 val |= WINCONx_BURSTLEN_16WORD;
283 break;
284 case DRM_FORMAT_ARGB8888:
285 val |= WINCONx_BPPMODE_32BPP_A8888;
286 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
287 val |= WINCONx_BURSTLEN_16WORD;
288 break;
289 default:
290 DRM_ERROR("Proper pixel format is not set\n");
291 return;
292 }
293
294 DRM_DEBUG_KMS("bpp = %u\n", fb->format->cpp[0] * 8);
295
296 /*
297 * In case of exynos, setting dma-burst to 16Word causes permanent
298 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
299 * switching which is based on plane size is not recommended as
300 * plane size varies a lot towards the end of the screen and rapid
301 * movement causes unstable DMA which results into iommu crash/tear.
302 */
303
304 if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
305 val &= ~WINCONx_BURSTLEN_MASK;
306 val |= WINCONx_BURSTLEN_8WORD;
307 }
308
309 writel(val, ctx->addr + DECON_WINCONx(win));
310 }
311
312 static void decon_shadow_protect_win(struct decon_context *ctx, int win,
313 bool protect)
314 {
315 decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_Wx_PROTECT(win),
316 protect ? ~0 : 0);
317 }
318
319 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
320 {
321 struct decon_context *ctx = crtc->ctx;
322 int i;
323
324 if (test_bit(BIT_SUSPENDED, &ctx->flags))
325 return;
326
327 for (i = ctx->first_win; i < WINDOWS_NR; i++)
328 decon_shadow_protect_win(ctx, i, true);
329 }
330
331 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
332 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
333 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
334
335 static void decon_update_plane(struct exynos_drm_crtc *crtc,
336 struct exynos_drm_plane *plane)
337 {
338 struct exynos_drm_plane_state *state =
339 to_exynos_plane_state(plane->base.state);
340 struct decon_context *ctx = crtc->ctx;
341 struct drm_framebuffer *fb = state->base.fb;
342 unsigned int win = plane->index;
343 unsigned int bpp = fb->format->cpp[0];
344 unsigned int pitch = fb->pitches[0];
345 dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
346 u32 val;
347
348 if (test_bit(BIT_SUSPENDED, &ctx->flags))
349 return;
350
351 if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) {
352 val = COORDINATE_X(state->crtc.x) |
353 COORDINATE_Y(state->crtc.y / 2);
354 writel(val, ctx->addr + DECON_VIDOSDxA(win));
355
356 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
357 COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1);
358 writel(val, ctx->addr + DECON_VIDOSDxB(win));
359 } else {
360 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
361 writel(val, ctx->addr + DECON_VIDOSDxA(win));
362
363 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
364 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
365 writel(val, ctx->addr + DECON_VIDOSDxB(win));
366 }
367
368 val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
369 VIDOSD_Wx_ALPHA_B_F(0x0);
370 writel(val, ctx->addr + DECON_VIDOSDxC(win));
371
372 val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
373 VIDOSD_Wx_ALPHA_B_F(0x0);
374 writel(val, ctx->addr + DECON_VIDOSDxD(win));
375
376 writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
377
378 val = dma_addr + pitch * state->src.h;
379 writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
380
381 if (!(ctx->out_type & IFTYPE_HDMI))
382 val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14)
383 | BIT_VAL(state->crtc.w * bpp, 13, 0);
384 else
385 val = BIT_VAL(pitch - state->crtc.w * bpp, 29, 15)
386 | BIT_VAL(state->crtc.w * bpp, 14, 0);
387 writel(val, ctx->addr + DECON_VIDW0xADD2(win));
388
389 decon_win_set_pixfmt(ctx, win, fb);
390
391 /* window enable */
392 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
393 set_bit(BIT_REQUEST_UPDATE, &ctx->flags);
394 }
395
396 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
397 struct exynos_drm_plane *plane)
398 {
399 struct decon_context *ctx = crtc->ctx;
400 unsigned int win = plane->index;
401
402 if (test_bit(BIT_SUSPENDED, &ctx->flags))
403 return;
404
405 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
406 set_bit(BIT_REQUEST_UPDATE, &ctx->flags);
407 }
408
409 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
410 {
411 struct decon_context *ctx = crtc->ctx;
412 unsigned long flags;
413 int i;
414
415 if (test_bit(BIT_SUSPENDED, &ctx->flags))
416 return;
417
418 spin_lock_irqsave(&ctx->vblank_lock, flags);
419
420 for (i = ctx->first_win; i < WINDOWS_NR; i++)
421 decon_shadow_protect_win(ctx, i, false);
422
423 if (test_and_clear_bit(BIT_REQUEST_UPDATE, &ctx->flags))
424 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
425
426 if (ctx->out_type & IFTYPE_I80)
427 set_bit(BIT_WIN_UPDATED, &ctx->flags);
428
429 ctx->frame_id = decon_get_frame_count(ctx, true);
430
431 exynos_crtc_handle_event(crtc);
432
433 spin_unlock_irqrestore(&ctx->vblank_lock, flags);
434 }
435
436 static void decon_swreset(struct decon_context *ctx)
437 {
438 unsigned int tries;
439 unsigned long flags;
440
441 writel(0, ctx->addr + DECON_VIDCON0);
442 for (tries = 2000; tries; --tries) {
443 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS)
444 break;
445 udelay(10);
446 }
447
448 writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
449 for (tries = 2000; tries; --tries) {
450 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
451 break;
452 udelay(10);
453 }
454
455 WARN(tries == 0, "failed to software reset DECON\n");
456
457 spin_lock_irqsave(&ctx->vblank_lock, flags);
458 ctx->frame_id = 0;
459 spin_unlock_irqrestore(&ctx->vblank_lock, flags);
460
461 if (!(ctx->out_type & IFTYPE_HDMI))
462 return;
463
464 writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
465 decon_set_bits(ctx, DECON_CMU,
466 CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
467 writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
468 writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
469 ctx->addr + DECON_CRCCTRL);
470 }
471
472 static void decon_enable(struct exynos_drm_crtc *crtc)
473 {
474 struct decon_context *ctx = crtc->ctx;
475
476 if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags))
477 return;
478
479 pm_runtime_get_sync(ctx->dev);
480
481 exynos_drm_pipe_clk_enable(crtc, true);
482
483 set_bit(BIT_CLKS_ENABLED, &ctx->flags);
484
485 decon_swreset(ctx);
486
487 /* if vblank was enabled status, enable it again. */
488 if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
489 decon_enable_vblank(ctx->crtc);
490
491 decon_commit(ctx->crtc);
492 }
493
494 static void decon_disable(struct exynos_drm_crtc *crtc)
495 {
496 struct decon_context *ctx = crtc->ctx;
497 int i;
498
499 if (test_bit(BIT_SUSPENDED, &ctx->flags))
500 return;
501
502 /*
503 * We need to make sure that all windows are disabled before we
504 * suspend that connector. Otherwise we might try to scan from
505 * a destroyed buffer later.
506 */
507 for (i = ctx->first_win; i < WINDOWS_NR; i++)
508 decon_disable_plane(crtc, &ctx->planes[i]);
509
510 decon_swreset(ctx);
511
512 clear_bit(BIT_CLKS_ENABLED, &ctx->flags);
513
514 exynos_drm_pipe_clk_enable(crtc, false);
515
516 pm_runtime_put_sync(ctx->dev);
517
518 set_bit(BIT_SUSPENDED, &ctx->flags);
519 }
520
521 static void decon_te_irq_handler(struct exynos_drm_crtc *crtc)
522 {
523 struct decon_context *ctx = crtc->ctx;
524
525 if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags) ||
526 (ctx->out_type & I80_HW_TRG))
527 return;
528
529 if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags))
530 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
531 }
532
533 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
534 {
535 struct decon_context *ctx = crtc->ctx;
536 int win, i, ret;
537
538 DRM_DEBUG_KMS("%s\n", __FILE__);
539
540 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
541 ret = clk_prepare_enable(ctx->clks[i]);
542 if (ret < 0)
543 goto err;
544 }
545
546 for (win = 0; win < WINDOWS_NR; win++) {
547 decon_shadow_protect_win(ctx, win, true);
548 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
549 decon_shadow_protect_win(ctx, win, false);
550 }
551
552 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
553
554 /* TODO: wait for possible vsync */
555 msleep(50);
556
557 err:
558 while (--i >= 0)
559 clk_disable_unprepare(ctx->clks[i]);
560 }
561
562 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
563 .enable = decon_enable,
564 .disable = decon_disable,
565 .enable_vblank = decon_enable_vblank,
566 .disable_vblank = decon_disable_vblank,
567 .atomic_begin = decon_atomic_begin,
568 .update_plane = decon_update_plane,
569 .disable_plane = decon_disable_plane,
570 .atomic_flush = decon_atomic_flush,
571 .te_handler = decon_te_irq_handler,
572 };
573
574 static int decon_bind(struct device *dev, struct device *master, void *data)
575 {
576 struct decon_context *ctx = dev_get_drvdata(dev);
577 struct drm_device *drm_dev = data;
578 struct exynos_drm_private *priv = drm_dev->dev_private;
579 struct exynos_drm_plane *exynos_plane;
580 enum exynos_drm_output_type out_type;
581 unsigned int win;
582 int ret;
583
584 ctx->drm_dev = drm_dev;
585 ctx->pipe = priv->pipe++;
586
587 for (win = ctx->first_win; win < WINDOWS_NR; win++) {
588 int tmp = (win == ctx->first_win) ? 0 : win;
589
590 ctx->configs[win].pixel_formats = decon_formats;
591 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
592 ctx->configs[win].zpos = win;
593 ctx->configs[win].type = decon_win_types[tmp];
594
595 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
596 1 << ctx->pipe, &ctx->configs[win]);
597 if (ret)
598 return ret;
599 }
600
601 exynos_plane = &ctx->planes[ctx->first_win];
602 out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
603 : EXYNOS_DISPLAY_TYPE_LCD;
604 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
605 ctx->pipe, out_type,
606 &decon_crtc_ops, ctx);
607 if (IS_ERR(ctx->crtc)) {
608 ret = PTR_ERR(ctx->crtc);
609 goto err;
610 }
611
612 decon_clear_channels(ctx->crtc);
613
614 ret = drm_iommu_attach_device(drm_dev, dev);
615 if (ret)
616 goto err;
617
618 return ret;
619 err:
620 priv->pipe--;
621 return ret;
622 }
623
624 static void decon_unbind(struct device *dev, struct device *master, void *data)
625 {
626 struct decon_context *ctx = dev_get_drvdata(dev);
627
628 decon_disable(ctx->crtc);
629
630 /* detach this sub driver from iommu mapping if supported. */
631 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
632 }
633
634 static const struct component_ops decon_component_ops = {
635 .bind = decon_bind,
636 .unbind = decon_unbind,
637 };
638
639 static void decon_handle_vblank(struct decon_context *ctx)
640 {
641 u32 frm;
642
643 spin_lock(&ctx->vblank_lock);
644
645 frm = decon_get_frame_count(ctx, true);
646
647 if (frm != ctx->frame_id) {
648 /* handle only if incremented, take care of wrap-around */
649 if ((s32)(frm - ctx->frame_id) > 0)
650 drm_crtc_handle_vblank(&ctx->crtc->base);
651 ctx->frame_id = frm;
652 }
653
654 spin_unlock(&ctx->vblank_lock);
655 }
656
657 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
658 {
659 struct decon_context *ctx = dev_id;
660 u32 val;
661
662 if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
663 goto out;
664
665 val = readl(ctx->addr + DECON_VIDINTCON1);
666 val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
667
668 if (val) {
669 writel(val, ctx->addr + DECON_VIDINTCON1);
670 if (ctx->out_type & IFTYPE_HDMI) {
671 val = readl(ctx->addr + DECON_VIDOUTCON0);
672 val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
673 if (val ==
674 (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
675 return IRQ_HANDLED;
676 }
677 decon_handle_vblank(ctx);
678 }
679
680 out:
681 return IRQ_HANDLED;
682 }
683
684 #ifdef CONFIG_PM
685 static int exynos5433_decon_suspend(struct device *dev)
686 {
687 struct decon_context *ctx = dev_get_drvdata(dev);
688 int i = ARRAY_SIZE(decon_clks_name);
689
690 while (--i >= 0)
691 clk_disable_unprepare(ctx->clks[i]);
692
693 return 0;
694 }
695
696 static int exynos5433_decon_resume(struct device *dev)
697 {
698 struct decon_context *ctx = dev_get_drvdata(dev);
699 int i, ret;
700
701 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
702 ret = clk_prepare_enable(ctx->clks[i]);
703 if (ret < 0)
704 goto err;
705 }
706
707 return 0;
708
709 err:
710 while (--i >= 0)
711 clk_disable_unprepare(ctx->clks[i]);
712
713 return ret;
714 }
715 #endif
716
717 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
718 SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
719 NULL)
720 };
721
722 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
723 {
724 .compatible = "samsung,exynos5433-decon",
725 .data = (void *)I80_HW_TRG
726 },
727 {
728 .compatible = "samsung,exynos5433-decon-tv",
729 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
730 },
731 {},
732 };
733 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
734
735 static int exynos5433_decon_probe(struct platform_device *pdev)
736 {
737 struct device *dev = &pdev->dev;
738 struct decon_context *ctx;
739 struct resource *res;
740 int ret;
741 int i;
742
743 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
744 if (!ctx)
745 return -ENOMEM;
746
747 __set_bit(BIT_SUSPENDED, &ctx->flags);
748 ctx->dev = dev;
749 ctx->out_type = (unsigned long)of_device_get_match_data(dev);
750 spin_lock_init(&ctx->vblank_lock);
751
752 if (ctx->out_type & IFTYPE_HDMI) {
753 ctx->first_win = 1;
754 } else if (of_get_child_by_name(dev->of_node, "i80-if-timings")) {
755 ctx->out_type |= IFTYPE_I80;
756 }
757
758 if (ctx->out_type & I80_HW_TRG) {
759 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
760 "samsung,disp-sysreg");
761 if (IS_ERR(ctx->sysreg)) {
762 dev_err(dev, "failed to get system register\n");
763 return PTR_ERR(ctx->sysreg);
764 }
765 }
766
767 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
768 struct clk *clk;
769
770 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
771 if (IS_ERR(clk))
772 return PTR_ERR(clk);
773
774 ctx->clks[i] = clk;
775 }
776
777 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
778 if (!res) {
779 dev_err(dev, "cannot find IO resource\n");
780 return -ENXIO;
781 }
782
783 ctx->addr = devm_ioremap_resource(dev, res);
784 if (IS_ERR(ctx->addr)) {
785 dev_err(dev, "ioremap failed\n");
786 return PTR_ERR(ctx->addr);
787 }
788
789 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
790 (ctx->out_type & IFTYPE_I80) ? "lcd_sys" : "vsync");
791 if (!res) {
792 dev_err(dev, "cannot find IRQ resource\n");
793 return -ENXIO;
794 }
795
796 ret = devm_request_irq(dev, res->start, decon_irq_handler, 0,
797 "drm_decon", ctx);
798 if (ret < 0) {
799 dev_err(dev, "lcd_sys irq request failed\n");
800 return ret;
801 }
802
803 platform_set_drvdata(pdev, ctx);
804
805 pm_runtime_enable(dev);
806
807 ret = component_add(dev, &decon_component_ops);
808 if (ret)
809 goto err_disable_pm_runtime;
810
811 return 0;
812
813 err_disable_pm_runtime:
814 pm_runtime_disable(dev);
815
816 return ret;
817 }
818
819 static int exynos5433_decon_remove(struct platform_device *pdev)
820 {
821 pm_runtime_disable(&pdev->dev);
822
823 component_del(&pdev->dev, &decon_component_ops);
824
825 return 0;
826 }
827
828 struct platform_driver exynos5433_decon_driver = {
829 .probe = exynos5433_decon_probe,
830 .remove = exynos5433_decon_remove,
831 .driver = {
832 .name = "exynos5433-decon",
833 .pm = &exynos5433_decon_pm_ops,
834 .of_match_table = exynos5433_decon_driver_dt_match,
835 },
836 };
CRIS linux kernel tree