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proc: Fix proc_sys_prune_dcache to hold a sb reference
[cris-mirror.git] / drivers / gpu / drm / rockchip / rockchip_drm_vop.c
blob3f7a82d1e0956e6a37e1478412210955db38aa19
1 /*
2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <drm/drm.h>
16 #include <drm/drmP.h>
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_flip_work.h>
21 #include <drm/drm_plane_helper.h>
22 #ifdef CONFIG_DRM_ANALOGIX_DP
23 #include <drm/bridge/analogix_dp.h>
24 #endif
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/clk.h>
30 #include <linux/iopoll.h>
31 #include <linux/of.h>
32 #include <linux/of_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/component.h>
35
36 #include <linux/reset.h>
37 #include <linux/delay.h>
38
39 #include "rockchip_drm_drv.h"
40 #include "rockchip_drm_gem.h"
41 #include "rockchip_drm_fb.h"
42 #include "rockchip_drm_psr.h"
43 #include "rockchip_drm_vop.h"
44
45 #define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
46 vop_mask_write(x, off, mask, shift, v, write_mask, true)
47
48 #define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
49 vop_mask_write(x, off, mask, shift, v, write_mask, false)
50
51 #define REG_SET(x, base, reg, v, mode) \
52 __REG_SET_##mode(x, base + reg.offset, \
53 reg.mask, reg.shift, v, reg.write_mask)
54 #define REG_SET_MASK(x, base, reg, mask, v, mode) \
55 __REG_SET_##mode(x, base + reg.offset, \
56 mask, reg.shift, v, reg.write_mask)
57
58 #define VOP_WIN_SET(x, win, name, v) \
59 REG_SET(x, win->base, win->phy->name, v, RELAXED)
60 #define VOP_SCL_SET(x, win, name, v) \
61 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
62 #define VOP_SCL_SET_EXT(x, win, name, v) \
63 REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
64 #define VOP_CTRL_SET(x, name, v) \
65 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
66
67 #define VOP_INTR_GET(vop, name) \
68 vop_read_reg(vop, 0, &vop->data->ctrl->name)
69
70 #define VOP_INTR_SET(vop, name, mask, v) \
71 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
72 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
73 do { \
74 int i, reg = 0, mask = 0; \
75 for (i = 0; i < vop->data->intr->nintrs; i++) { \
76 if (vop->data->intr->intrs[i] & type) { \
77 reg |= (v) << i; \
78 mask |= 1 << i; \
79 } \
80 } \
81 VOP_INTR_SET(vop, name, mask, reg); \
82 } while (0)
83 #define VOP_INTR_GET_TYPE(vop, name, type) \
84 vop_get_intr_type(vop, &vop->data->intr->name, type)
85
86 #define VOP_WIN_GET(x, win, name) \
87 vop_read_reg(x, win->base, &win->phy->name)
88
89 #define VOP_WIN_GET_YRGBADDR(vop, win) \
90 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
91
92 #define to_vop(x) container_of(x, struct vop, crtc)
93 #define to_vop_win(x) container_of(x, struct vop_win, base)
94
95 enum vop_pending {
96 VOP_PENDING_FB_UNREF,
97 };
98
99 struct vop_win {
100 struct drm_plane base;
101 const struct vop_win_data *data;
102 struct vop *vop;
103 };
104
105 struct vop {
106 struct drm_crtc crtc;
107 struct device *dev;
108 struct drm_device *drm_dev;
109 bool is_enabled;
110
111 /* mutex vsync_ work */
112 struct mutex vsync_mutex;
113 bool vsync_work_pending;
114 struct completion dsp_hold_completion;
115
116 /* protected by dev->event_lock */
117 struct drm_pending_vblank_event *event;
118
119 struct drm_flip_work fb_unref_work;
120 unsigned long pending;
121
122 struct completion line_flag_completion;
123
124 const struct vop_data *data;
125
126 uint32_t *regsbak;
127 void __iomem *regs;
128
129 /* physical map length of vop register */
130 uint32_t len;
131
132 /* one time only one process allowed to config the register */
133 spinlock_t reg_lock;
134 /* lock vop irq reg */
135 spinlock_t irq_lock;
136
137 unsigned int irq;
138
139 /* vop AHP clk */
140 struct clk *hclk;
141 /* vop dclk */
142 struct clk *dclk;
143 /* vop share memory frequency */
144 struct clk *aclk;
145
146 /* vop dclk reset */
147 struct reset_control *dclk_rst;
148
149 struct vop_win win[];
150 };
151
152 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
153 {
154 writel(v, vop->regs + offset);
155 vop->regsbak[offset >> 2] = v;
156 }
157
158 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
159 {
160 return readl(vop->regs + offset);
161 }
162
163 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
164 const struct vop_reg *reg)
165 {
166 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
167 }
168
169 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
170 uint32_t mask, uint32_t shift, uint32_t v,
171 bool write_mask, bool relaxed)
172 {
173 if (!mask)
174 return;
175
176 if (write_mask) {
177 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
178 } else {
179 uint32_t cached_val = vop->regsbak[offset >> 2];
180
181 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
182 vop->regsbak[offset >> 2] = v;
183 }
184
185 if (relaxed)
186 writel_relaxed(v, vop->regs + offset);
187 else
188 writel(v, vop->regs + offset);
189 }
190
191 static inline uint32_t vop_get_intr_type(struct vop *vop,
192 const struct vop_reg *reg, int type)
193 {
194 uint32_t i, ret = 0;
195 uint32_t regs = vop_read_reg(vop, 0, reg);
196
197 for (i = 0; i < vop->data->intr->nintrs; i++) {
198 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
199 ret |= vop->data->intr->intrs[i];
200 }
201
202 return ret;
203 }
204
205 static inline void vop_cfg_done(struct vop *vop)
206 {
207 VOP_CTRL_SET(vop, cfg_done, 1);
208 }
209
210 static bool has_rb_swapped(uint32_t format)
211 {
212 switch (format) {
213 case DRM_FORMAT_XBGR8888:
214 case DRM_FORMAT_ABGR8888:
215 case DRM_FORMAT_BGR888:
216 case DRM_FORMAT_BGR565:
217 return true;
218 default:
219 return false;
220 }
221 }
222
223 static enum vop_data_format vop_convert_format(uint32_t format)
224 {
225 switch (format) {
226 case DRM_FORMAT_XRGB8888:
227 case DRM_FORMAT_ARGB8888:
228 case DRM_FORMAT_XBGR8888:
229 case DRM_FORMAT_ABGR8888:
230 return VOP_FMT_ARGB8888;
231 case DRM_FORMAT_RGB888:
232 case DRM_FORMAT_BGR888:
233 return VOP_FMT_RGB888;
234 case DRM_FORMAT_RGB565:
235 case DRM_FORMAT_BGR565:
236 return VOP_FMT_RGB565;
237 case DRM_FORMAT_NV12:
238 return VOP_FMT_YUV420SP;
239 case DRM_FORMAT_NV16:
240 return VOP_FMT_YUV422SP;
241 case DRM_FORMAT_NV24:
242 return VOP_FMT_YUV444SP;
243 default:
244 DRM_ERROR("unsupported format[%08x]\n", format);
245 return -EINVAL;
246 }
247 }
248
249 static bool is_yuv_support(uint32_t format)
250 {
251 switch (format) {
252 case DRM_FORMAT_NV12:
253 case DRM_FORMAT_NV16:
254 case DRM_FORMAT_NV24:
255 return true;
256 default:
257 return false;
258 }
259 }
260
261 static bool is_alpha_support(uint32_t format)
262 {
263 switch (format) {
264 case DRM_FORMAT_ARGB8888:
265 case DRM_FORMAT_ABGR8888:
266 return true;
267 default:
268 return false;
269 }
270 }
271
272 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
273 uint32_t dst, bool is_horizontal,
274 int vsu_mode, int *vskiplines)
275 {
276 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
277
278 if (is_horizontal) {
279 if (mode == SCALE_UP)
280 val = GET_SCL_FT_BIC(src, dst);
281 else if (mode == SCALE_DOWN)
282 val = GET_SCL_FT_BILI_DN(src, dst);
283 } else {
284 if (mode == SCALE_UP) {
285 if (vsu_mode == SCALE_UP_BIL)
286 val = GET_SCL_FT_BILI_UP(src, dst);
287 else
288 val = GET_SCL_FT_BIC(src, dst);
289 } else if (mode == SCALE_DOWN) {
290 if (vskiplines) {
291 *vskiplines = scl_get_vskiplines(src, dst);
292 val = scl_get_bili_dn_vskip(src, dst,
293 *vskiplines);
294 } else {
295 val = GET_SCL_FT_BILI_DN(src, dst);
296 }
297 }
298 }
299
300 return val;
301 }
302
303 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
304 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
305 uint32_t dst_h, uint32_t pixel_format)
306 {
307 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
308 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
309 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
310 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
311 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
312 bool is_yuv = is_yuv_support(pixel_format);
313 uint16_t cbcr_src_w = src_w / hsub;
314 uint16_t cbcr_src_h = src_h / vsub;
315 uint16_t vsu_mode;
316 uint16_t lb_mode;
317 uint32_t val;
318 int vskiplines = 0;
319
320 if (dst_w > 3840) {
321 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
322 return;
323 }
324
325 if (!win->phy->scl->ext) {
326 VOP_SCL_SET(vop, win, scale_yrgb_x,
327 scl_cal_scale2(src_w, dst_w));
328 VOP_SCL_SET(vop, win, scale_yrgb_y,
329 scl_cal_scale2(src_h, dst_h));
330 if (is_yuv) {
331 VOP_SCL_SET(vop, win, scale_cbcr_x,
332 scl_cal_scale2(cbcr_src_w, dst_w));
333 VOP_SCL_SET(vop, win, scale_cbcr_y,
334 scl_cal_scale2(cbcr_src_h, dst_h));
335 }
336 return;
337 }
338
339 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
340 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
341
342 if (is_yuv) {
343 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
344 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
345 if (cbcr_hor_scl_mode == SCALE_DOWN)
346 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
347 else
348 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
349 } else {
350 if (yrgb_hor_scl_mode == SCALE_DOWN)
351 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
352 else
353 lb_mode = scl_vop_cal_lb_mode(src_w, false);
354 }
355
356 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
357 if (lb_mode == LB_RGB_3840X2) {
358 if (yrgb_ver_scl_mode != SCALE_NONE) {
359 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
360 return;
361 }
362 if (cbcr_ver_scl_mode != SCALE_NONE) {
363 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
364 return;
365 }
366 vsu_mode = SCALE_UP_BIL;
367 } else if (lb_mode == LB_RGB_2560X4) {
368 vsu_mode = SCALE_UP_BIL;
369 } else {
370 vsu_mode = SCALE_UP_BIC;
371 }
372
373 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
374 true, 0, NULL);
375 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
376 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
377 false, vsu_mode, &vskiplines);
378 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
379
380 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
381 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
382
383 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
384 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
385 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
386 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
387 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
388 if (is_yuv) {
389 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
390 dst_w, true, 0, NULL);
391 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
392 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
393 dst_h, false, vsu_mode, &vskiplines);
394 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
395
396 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
397 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
398 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
399 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
400 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
401 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
402 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
403 }
404 }
405
406 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
407 {
408 unsigned long flags;
409
410 if (WARN_ON(!vop->is_enabled))
411 return;
412
413 spin_lock_irqsave(&vop->irq_lock, flags);
414
415 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
416 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
417
418 spin_unlock_irqrestore(&vop->irq_lock, flags);
419 }
420
421 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
422 {
423 unsigned long flags;
424
425 if (WARN_ON(!vop->is_enabled))
426 return;
427
428 spin_lock_irqsave(&vop->irq_lock, flags);
429
430 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
431
432 spin_unlock_irqrestore(&vop->irq_lock, flags);
433 }
434
435 /*
436 * (1) each frame starts at the start of the Vsync pulse which is signaled by
437 * the "FRAME_SYNC" interrupt.
438 * (2) the active data region of each frame ends at dsp_vact_end
439 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
440 * to get "LINE_FLAG" interrupt at the end of the active on screen data.
441 *
442 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
443 * Interrupts
444 * LINE_FLAG -------------------------------+
445 * FRAME_SYNC ----+ |
446 * | |
447 * v v
448 * | Vsync | Vbp | Vactive | Vfp |
449 * ^ ^ ^ ^
450 * | | | |
451 * | | | |
452 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
453 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
454 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
455 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
456 */
457 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
458 {
459 uint32_t line_flag_irq;
460 unsigned long flags;
461
462 spin_lock_irqsave(&vop->irq_lock, flags);
463
464 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
465
466 spin_unlock_irqrestore(&vop->irq_lock, flags);
467
468 return !!line_flag_irq;
469 }
470
471 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
472 {
473 unsigned long flags;
474
475 if (WARN_ON(!vop->is_enabled))
476 return;
477
478 spin_lock_irqsave(&vop->irq_lock, flags);
479
480 VOP_CTRL_SET(vop, line_flag_num[0], line_num);
481 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
482 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
483
484 spin_unlock_irqrestore(&vop->irq_lock, flags);
485 }
486
487 static void vop_line_flag_irq_disable(struct vop *vop)
488 {
489 unsigned long flags;
490
491 if (WARN_ON(!vop->is_enabled))
492 return;
493
494 spin_lock_irqsave(&vop->irq_lock, flags);
495
496 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
497
498 spin_unlock_irqrestore(&vop->irq_lock, flags);
499 }
500
501 static int vop_enable(struct drm_crtc *crtc)
502 {
503 struct vop *vop = to_vop(crtc);
504 int ret;
505
506 ret = pm_runtime_get_sync(vop->dev);
507 if (ret < 0) {
508 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
509 return ret;
510 }
511
512 ret = clk_enable(vop->hclk);
513 if (WARN_ON(ret < 0))
514 goto err_put_pm_runtime;
515
516 ret = clk_enable(vop->dclk);
517 if (WARN_ON(ret < 0))
518 goto err_disable_hclk;
519
520 ret = clk_enable(vop->aclk);
521 if (WARN_ON(ret < 0))
522 goto err_disable_dclk;
523
524 /*
525 * Slave iommu shares power, irq and clock with vop. It was associated
526 * automatically with this master device via common driver code.
527 * Now that we have enabled the clock we attach it to the shared drm
528 * mapping.
529 */
530 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
531 if (ret) {
532 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
533 goto err_disable_aclk;
534 }
535
536 memcpy(vop->regs, vop->regsbak, vop->len);
537 vop_cfg_done(vop);
538
539 /*
540 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
541 */
542 vop->is_enabled = true;
543
544 spin_lock(&vop->reg_lock);
545
546 VOP_CTRL_SET(vop, standby, 0);
547
548 spin_unlock(&vop->reg_lock);
549
550 enable_irq(vop->irq);
551
552 drm_crtc_vblank_on(crtc);
553
554 return 0;
555
556 err_disable_aclk:
557 clk_disable(vop->aclk);
558 err_disable_dclk:
559 clk_disable(vop->dclk);
560 err_disable_hclk:
561 clk_disable(vop->hclk);
562 err_put_pm_runtime:
563 pm_runtime_put_sync(vop->dev);
564 return ret;
565 }
566
567 static void vop_crtc_disable(struct drm_crtc *crtc)
568 {
569 struct vop *vop = to_vop(crtc);
570 int i;
571
572 WARN_ON(vop->event);
573
574 rockchip_drm_psr_deactivate(&vop->crtc);
575
576 /*
577 * We need to make sure that all windows are disabled before we
578 * disable that crtc. Otherwise we might try to scan from a destroyed
579 * buffer later.
580 */
581 for (i = 0; i < vop->data->win_size; i++) {
582 struct vop_win *vop_win = &vop->win[i];
583 const struct vop_win_data *win = vop_win->data;
584
585 spin_lock(&vop->reg_lock);
586 VOP_WIN_SET(vop, win, enable, 0);
587 spin_unlock(&vop->reg_lock);
588 }
589
590 vop_cfg_done(vop);
591
592 drm_crtc_vblank_off(crtc);
593
594 /*
595 * Vop standby will take effect at end of current frame,
596 * if dsp hold valid irq happen, it means standby complete.
597 *
598 * we must wait standby complete when we want to disable aclk,
599 * if not, memory bus maybe dead.
600 */
601 reinit_completion(&vop->dsp_hold_completion);
602 vop_dsp_hold_valid_irq_enable(vop);
603
604 spin_lock(&vop->reg_lock);
605
606 VOP_CTRL_SET(vop, standby, 1);
607
608 spin_unlock(&vop->reg_lock);
609
610 wait_for_completion(&vop->dsp_hold_completion);
611
612 vop_dsp_hold_valid_irq_disable(vop);
613
614 disable_irq(vop->irq);
615
616 vop->is_enabled = false;
617
618 /*
619 * vop standby complete, so iommu detach is safe.
620 */
621 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
622
623 clk_disable(vop->dclk);
624 clk_disable(vop->aclk);
625 clk_disable(vop->hclk);
626 pm_runtime_put(vop->dev);
627
628 if (crtc->state->event && !crtc->state->active) {
629 spin_lock_irq(&crtc->dev->event_lock);
630 drm_crtc_send_vblank_event(crtc, crtc->state->event);
631 spin_unlock_irq(&crtc->dev->event_lock);
632
633 crtc->state->event = NULL;
634 }
635 }
636
637 static void vop_plane_destroy(struct drm_plane *plane)
638 {
639 drm_plane_cleanup(plane);
640 }
641
642 static int vop_plane_atomic_check(struct drm_plane *plane,
643 struct drm_plane_state *state)
644 {
645 struct drm_crtc *crtc = state->crtc;
646 struct drm_crtc_state *crtc_state;
647 struct drm_framebuffer *fb = state->fb;
648 struct vop_win *vop_win = to_vop_win(plane);
649 const struct vop_win_data *win = vop_win->data;
650 int ret;
651 struct drm_rect clip;
652 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
653 DRM_PLANE_HELPER_NO_SCALING;
654 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
655 DRM_PLANE_HELPER_NO_SCALING;
656
657 if (!crtc || !fb)
658 return 0;
659
660 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
661 if (WARN_ON(!crtc_state))
662 return -EINVAL;
663
664 clip.x1 = 0;
665 clip.y1 = 0;
666 clip.x2 = crtc_state->adjusted_mode.hdisplay;
667 clip.y2 = crtc_state->adjusted_mode.vdisplay;
668
669 ret = drm_plane_helper_check_state(state, &clip,
670 min_scale, max_scale,
671 true, true);
672 if (ret)
673 return ret;
674
675 if (!state->visible)
676 return 0;
677
678 ret = vop_convert_format(fb->format->format);
679 if (ret < 0)
680 return ret;
681
682 /*
683 * Src.x1 can be odd when do clip, but yuv plane start point
684 * need align with 2 pixel.
685 */
686 if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2))
687 return -EINVAL;
688
689 return 0;
690 }
691
692 static void vop_plane_atomic_disable(struct drm_plane *plane,
693 struct drm_plane_state *old_state)
694 {
695 struct vop_win *vop_win = to_vop_win(plane);
696 const struct vop_win_data *win = vop_win->data;
697 struct vop *vop = to_vop(old_state->crtc);
698
699 if (!old_state->crtc)
700 return;
701
702 spin_lock(&vop->reg_lock);
703
704 VOP_WIN_SET(vop, win, enable, 0);
705
706 spin_unlock(&vop->reg_lock);
707 }
708
709 static void vop_plane_atomic_update(struct drm_plane *plane,
710 struct drm_plane_state *old_state)
711 {
712 struct drm_plane_state *state = plane->state;
713 struct drm_crtc *crtc = state->crtc;
714 struct vop_win *vop_win = to_vop_win(plane);
715 const struct vop_win_data *win = vop_win->data;
716 struct vop *vop = to_vop(state->crtc);
717 struct drm_framebuffer *fb = state->fb;
718 unsigned int actual_w, actual_h;
719 unsigned int dsp_stx, dsp_sty;
720 uint32_t act_info, dsp_info, dsp_st;
721 struct drm_rect *src = &state->src;
722 struct drm_rect *dest = &state->dst;
723 struct drm_gem_object *obj, *uv_obj;
724 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
725 unsigned long offset;
726 dma_addr_t dma_addr;
727 uint32_t val;
728 bool rb_swap;
729 int format;
730
731 /*
732 * can't update plane when vop is disabled.
733 */
734 if (WARN_ON(!crtc))
735 return;
736
737 if (WARN_ON(!vop->is_enabled))
738 return;
739
740 if (!state->visible) {
741 vop_plane_atomic_disable(plane, old_state);
742 return;
743 }
744
745 obj = rockchip_fb_get_gem_obj(fb, 0);
746 rk_obj = to_rockchip_obj(obj);
747
748 actual_w = drm_rect_width(src) >> 16;
749 actual_h = drm_rect_height(src) >> 16;
750 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
751
752 dsp_info = (drm_rect_height(dest) - 1) << 16;
753 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
754
755 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
756 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
757 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
758
759 offset = (src->x1 >> 16) * fb->format->cpp[0];
760 offset += (src->y1 >> 16) * fb->pitches[0];
761 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
762
763 format = vop_convert_format(fb->format->format);
764
765 spin_lock(&vop->reg_lock);
766
767 VOP_WIN_SET(vop, win, format, format);
768 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
769 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
770 if (is_yuv_support(fb->format->format)) {
771 int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
772 int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
773 int bpp = fb->format->cpp[1];
774
775 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
776 rk_uv_obj = to_rockchip_obj(uv_obj);
777
778 offset = (src->x1 >> 16) * bpp / hsub;
779 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
780
781 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
782 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
783 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
784 }
785
786 if (win->phy->scl)
787 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
788 drm_rect_width(dest), drm_rect_height(dest),
789 fb->format->format);
790
791 VOP_WIN_SET(vop, win, act_info, act_info);
792 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
793 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
794
795 rb_swap = has_rb_swapped(fb->format->format);
796 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
797
798 if (is_alpha_support(fb->format->format)) {
799 VOP_WIN_SET(vop, win, dst_alpha_ctl,
800 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
801 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
802 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
803 SRC_BLEND_M0(ALPHA_PER_PIX) |
804 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
805 SRC_FACTOR_M0(ALPHA_ONE);
806 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
807 } else {
808 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
809 }
810
811 VOP_WIN_SET(vop, win, enable, 1);
812 spin_unlock(&vop->reg_lock);
813 }
814
815 static const struct drm_plane_helper_funcs plane_helper_funcs = {
816 .atomic_check = vop_plane_atomic_check,
817 .atomic_update = vop_plane_atomic_update,
818 .atomic_disable = vop_plane_atomic_disable,
819 };
820
821 static const struct drm_plane_funcs vop_plane_funcs = {
822 .update_plane = drm_atomic_helper_update_plane,
823 .disable_plane = drm_atomic_helper_disable_plane,
824 .destroy = vop_plane_destroy,
825 .reset = drm_atomic_helper_plane_reset,
826 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
827 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
828 };
829
830 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
831 {
832 struct vop *vop = to_vop(crtc);
833 unsigned long flags;
834
835 if (WARN_ON(!vop->is_enabled))
836 return -EPERM;
837
838 spin_lock_irqsave(&vop->irq_lock, flags);
839
840 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
841 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
842
843 spin_unlock_irqrestore(&vop->irq_lock, flags);
844
845 return 0;
846 }
847
848 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
849 {
850 struct vop *vop = to_vop(crtc);
851 unsigned long flags;
852
853 if (WARN_ON(!vop->is_enabled))
854 return;
855
856 spin_lock_irqsave(&vop->irq_lock, flags);
857
858 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
859
860 spin_unlock_irqrestore(&vop->irq_lock, flags);
861 }
862
863 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
864 const struct drm_display_mode *mode,
865 struct drm_display_mode *adjusted_mode)
866 {
867 struct vop *vop = to_vop(crtc);
868
869 adjusted_mode->clock =
870 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
871
872 return true;
873 }
874
875 static void vop_crtc_enable(struct drm_crtc *crtc)
876 {
877 struct vop *vop = to_vop(crtc);
878 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
879 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
880 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
881 u16 hdisplay = adjusted_mode->hdisplay;
882 u16 htotal = adjusted_mode->htotal;
883 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
884 u16 hact_end = hact_st + hdisplay;
885 u16 vdisplay = adjusted_mode->vdisplay;
886 u16 vtotal = adjusted_mode->vtotal;
887 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
888 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
889 u16 vact_end = vact_st + vdisplay;
890 uint32_t pin_pol, val;
891 int ret;
892
893 WARN_ON(vop->event);
894
895 ret = vop_enable(crtc);
896 if (ret) {
897 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
898 return;
899 }
900
901 /*
902 * If dclk rate is zero, mean that scanout is stop,
903 * we don't need wait any more.
904 */
905 if (clk_get_rate(vop->dclk)) {
906 /*
907 * Rk3288 vop timing register is immediately, when configure
908 * display timing on display time, may cause tearing.
909 *
910 * Vop standby will take effect at end of current frame,
911 * if dsp hold valid irq happen, it means standby complete.
912 *
913 * mode set:
914 * standby and wait complete --> |----
915 * | display time
916 * |----
917 * |---> dsp hold irq
918 * configure display timing --> |
919 * standby exit |
920 * | new frame start.
921 */
922
923 reinit_completion(&vop->dsp_hold_completion);
924 vop_dsp_hold_valid_irq_enable(vop);
925
926 spin_lock(&vop->reg_lock);
927
928 VOP_CTRL_SET(vop, standby, 1);
929
930 spin_unlock(&vop->reg_lock);
931
932 wait_for_completion(&vop->dsp_hold_completion);
933
934 vop_dsp_hold_valid_irq_disable(vop);
935 }
936
937 pin_pol = BIT(DCLK_INVERT);
938 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
939 BIT(HSYNC_POSITIVE) : 0;
940 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
941 BIT(VSYNC_POSITIVE) : 0;
942 VOP_CTRL_SET(vop, pin_pol, pin_pol);
943
944 switch (s->output_type) {
945 case DRM_MODE_CONNECTOR_LVDS:
946 VOP_CTRL_SET(vop, rgb_en, 1);
947 VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol);
948 break;
949 case DRM_MODE_CONNECTOR_eDP:
950 VOP_CTRL_SET(vop, edp_pin_pol, pin_pol);
951 VOP_CTRL_SET(vop, edp_en, 1);
952 break;
953 case DRM_MODE_CONNECTOR_HDMIA:
954 VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol);
955 VOP_CTRL_SET(vop, hdmi_en, 1);
956 break;
957 case DRM_MODE_CONNECTOR_DSI:
958 VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol);
959 VOP_CTRL_SET(vop, mipi_en, 1);
960 break;
961 case DRM_MODE_CONNECTOR_DisplayPort:
962 pin_pol &= ~BIT(DCLK_INVERT);
963 VOP_CTRL_SET(vop, dp_pin_pol, pin_pol);
964 VOP_CTRL_SET(vop, dp_en, 1);
965 break;
966 default:
967 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
968 s->output_type);
969 }
970 VOP_CTRL_SET(vop, out_mode, s->output_mode);
971
972 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
973 val = hact_st << 16;
974 val |= hact_end;
975 VOP_CTRL_SET(vop, hact_st_end, val);
976 VOP_CTRL_SET(vop, hpost_st_end, val);
977
978 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
979 val = vact_st << 16;
980 val |= vact_end;
981 VOP_CTRL_SET(vop, vact_st_end, val);
982 VOP_CTRL_SET(vop, vpost_st_end, val);
983
984 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
985
986 VOP_CTRL_SET(vop, standby, 0);
987
988 rockchip_drm_psr_activate(&vop->crtc);
989 }
990
991 static bool vop_fs_irq_is_pending(struct vop *vop)
992 {
993 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
994 }
995
996 static void vop_wait_for_irq_handler(struct vop *vop)
997 {
998 bool pending;
999 int ret;
1000
1001 /*
1002 * Spin until frame start interrupt status bit goes low, which means
1003 * that interrupt handler was invoked and cleared it. The timeout of
1004 * 10 msecs is really too long, but it is just a safety measure if
1005 * something goes really wrong. The wait will only happen in the very
1006 * unlikely case of a vblank happening exactly at the same time and
1007 * shouldn't exceed microseconds range.
1008 */
1009 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1010 !pending, 0, 10 * 1000);
1011 if (ret)
1012 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1013
1014 synchronize_irq(vop->irq);
1015 }
1016
1017 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1018 struct drm_crtc_state *old_crtc_state)
1019 {
1020 struct drm_atomic_state *old_state = old_crtc_state->state;
1021 struct drm_plane_state *old_plane_state;
1022 struct vop *vop = to_vop(crtc);
1023 struct drm_plane *plane;
1024 int i;
1025
1026 if (WARN_ON(!vop->is_enabled))
1027 return;
1028
1029 spin_lock(&vop->reg_lock);
1030
1031 vop_cfg_done(vop);
1032
1033 spin_unlock(&vop->reg_lock);
1034
1035 /*
1036 * There is a (rather unlikely) possiblity that a vblank interrupt
1037 * fired before we set the cfg_done bit. To avoid spuriously
1038 * signalling flip completion we need to wait for it to finish.
1039 */
1040 vop_wait_for_irq_handler(vop);
1041
1042 spin_lock_irq(&crtc->dev->event_lock);
1043 if (crtc->state->event) {
1044 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1045 WARN_ON(vop->event);
1046
1047 vop->event = crtc->state->event;
1048 crtc->state->event = NULL;
1049 }
1050 spin_unlock_irq(&crtc->dev->event_lock);
1051
1052 for_each_plane_in_state(old_state, plane, old_plane_state, i) {
1053 if (!old_plane_state->fb)
1054 continue;
1055
1056 if (old_plane_state->fb == plane->state->fb)
1057 continue;
1058
1059 drm_framebuffer_reference(old_plane_state->fb);
1060 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1061 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1062 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1063 }
1064 }
1065
1066 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1067 struct drm_crtc_state *old_crtc_state)
1068 {
1069 rockchip_drm_psr_flush(crtc);
1070 }
1071
1072 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1073 .enable = vop_crtc_enable,
1074 .disable = vop_crtc_disable,
1075 .mode_fixup = vop_crtc_mode_fixup,
1076 .atomic_flush = vop_crtc_atomic_flush,
1077 .atomic_begin = vop_crtc_atomic_begin,
1078 };
1079
1080 static void vop_crtc_destroy(struct drm_crtc *crtc)
1081 {
1082 drm_crtc_cleanup(crtc);
1083 }
1084
1085 static void vop_crtc_reset(struct drm_crtc *crtc)
1086 {
1087 if (crtc->state)
1088 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1089 kfree(crtc->state);
1090
1091 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1092 if (crtc->state)
1093 crtc->state->crtc = crtc;
1094 }
1095
1096 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1097 {
1098 struct rockchip_crtc_state *rockchip_state;
1099
1100 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1101 if (!rockchip_state)
1102 return NULL;
1103
1104 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1105 return &rockchip_state->base;
1106 }
1107
1108 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1109 struct drm_crtc_state *state)
1110 {
1111 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1112
1113 __drm_atomic_helper_crtc_destroy_state(&s->base);
1114 kfree(s);
1115 }
1116
1117 #ifdef CONFIG_DRM_ANALOGIX_DP
1118 static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1119 {
1120 struct drm_crtc *crtc = &vop->crtc;
1121 struct drm_connector *connector;
1122
1123 mutex_lock(&crtc->dev->mode_config.mutex);
1124 drm_for_each_connector(connector, crtc->dev)
1125 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1126 mutex_unlock(&crtc->dev->mode_config.mutex);
1127 return connector;
1128 }
1129 mutex_unlock(&crtc->dev->mode_config.mutex);
1130
1131 return NULL;
1132 }
1133
1134 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1135 const char *source_name, size_t *values_cnt)
1136 {
1137 struct vop *vop = to_vop(crtc);
1138 struct drm_connector *connector;
1139 int ret;
1140
1141 connector = vop_get_edp_connector(vop);
1142 if (!connector)
1143 return -EINVAL;
1144
1145 *values_cnt = 3;
1146
1147 if (source_name && strcmp(source_name, "auto") == 0)
1148 ret = analogix_dp_start_crc(connector);
1149 else if (!source_name)
1150 ret = analogix_dp_stop_crc(connector);
1151 else
1152 ret = -EINVAL;
1153
1154 return ret;
1155 }
1156 #else
1157 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1158 const char *source_name, size_t *values_cnt)
1159 {
1160 return -ENODEV;
1161 }
1162 #endif
1163
1164 static const struct drm_crtc_funcs vop_crtc_funcs = {
1165 .set_config = drm_atomic_helper_set_config,
1166 .page_flip = drm_atomic_helper_page_flip,
1167 .destroy = vop_crtc_destroy,
1168 .reset = vop_crtc_reset,
1169 .atomic_duplicate_state = vop_crtc_duplicate_state,
1170 .atomic_destroy_state = vop_crtc_destroy_state,
1171 .enable_vblank = vop_crtc_enable_vblank,
1172 .disable_vblank = vop_crtc_disable_vblank,
1173 .set_crc_source = vop_crtc_set_crc_source,
1174 };
1175
1176 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1177 {
1178 struct vop *vop = container_of(work, struct vop, fb_unref_work);
1179 struct drm_framebuffer *fb = val;
1180
1181 drm_crtc_vblank_put(&vop->crtc);
1182 drm_framebuffer_unreference(fb);
1183 }
1184
1185 static void vop_handle_vblank(struct vop *vop)
1186 {
1187 struct drm_device *drm = vop->drm_dev;
1188 struct drm_crtc *crtc = &vop->crtc;
1189 unsigned long flags;
1190
1191 spin_lock_irqsave(&drm->event_lock, flags);
1192 if (vop->event) {
1193 drm_crtc_send_vblank_event(crtc, vop->event);
1194 drm_crtc_vblank_put(crtc);
1195 vop->event = NULL;
1196 }
1197 spin_unlock_irqrestore(&drm->event_lock, flags);
1198
1199 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1200 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1201 }
1202
1203 static irqreturn_t vop_isr(int irq, void *data)
1204 {
1205 struct vop *vop = data;
1206 struct drm_crtc *crtc = &vop->crtc;
1207 uint32_t active_irqs;
1208 unsigned long flags;
1209 int ret = IRQ_NONE;
1210
1211 /*
1212 * interrupt register has interrupt status, enable and clear bits, we
1213 * must hold irq_lock to avoid a race with enable/disable_vblank().
1214 */
1215 spin_lock_irqsave(&vop->irq_lock, flags);
1216
1217 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1218 /* Clear all active interrupt sources */
1219 if (active_irqs)
1220 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1221
1222 spin_unlock_irqrestore(&vop->irq_lock, flags);
1223
1224 /* This is expected for vop iommu irqs, since the irq is shared */
1225 if (!active_irqs)
1226 return IRQ_NONE;
1227
1228 if (active_irqs & DSP_HOLD_VALID_INTR) {
1229 complete(&vop->dsp_hold_completion);
1230 active_irqs &= ~DSP_HOLD_VALID_INTR;
1231 ret = IRQ_HANDLED;
1232 }
1233
1234 if (active_irqs & LINE_FLAG_INTR) {
1235 complete(&vop->line_flag_completion);
1236 active_irqs &= ~LINE_FLAG_INTR;
1237 ret = IRQ_HANDLED;
1238 }
1239
1240 if (active_irqs & FS_INTR) {
1241 drm_crtc_handle_vblank(crtc);
1242 vop_handle_vblank(vop);
1243 active_irqs &= ~FS_INTR;
1244 ret = IRQ_HANDLED;
1245 }
1246
1247 /* Unhandled irqs are spurious. */
1248 if (active_irqs)
1249 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1250 active_irqs);
1251
1252 return ret;
1253 }
1254
1255 static int vop_create_crtc(struct vop *vop)
1256 {
1257 const struct vop_data *vop_data = vop->data;
1258 struct device *dev = vop->dev;
1259 struct drm_device *drm_dev = vop->drm_dev;
1260 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1261 struct drm_crtc *crtc = &vop->crtc;
1262 struct device_node *port;
1263 int ret;
1264 int i;
1265
1266 /*
1267 * Create drm_plane for primary and cursor planes first, since we need
1268 * to pass them to drm_crtc_init_with_planes, which sets the
1269 * "possible_crtcs" to the newly initialized crtc.
1270 */
1271 for (i = 0; i < vop_data->win_size; i++) {
1272 struct vop_win *vop_win = &vop->win[i];
1273 const struct vop_win_data *win_data = vop_win->data;
1274
1275 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1276 win_data->type != DRM_PLANE_TYPE_CURSOR)
1277 continue;
1278
1279 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1280 0, &vop_plane_funcs,
1281 win_data->phy->data_formats,
1282 win_data->phy->nformats,
1283 win_data->type, NULL);
1284 if (ret) {
1285 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1286 ret);
1287 goto err_cleanup_planes;
1288 }
1289
1290 plane = &vop_win->base;
1291 drm_plane_helper_add(plane, &plane_helper_funcs);
1292 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1293 primary = plane;
1294 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1295 cursor = plane;
1296 }
1297
1298 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1299 &vop_crtc_funcs, NULL);
1300 if (ret)
1301 goto err_cleanup_planes;
1302
1303 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1304
1305 /*
1306 * Create drm_planes for overlay windows with possible_crtcs restricted
1307 * to the newly created crtc.
1308 */
1309 for (i = 0; i < vop_data->win_size; i++) {
1310 struct vop_win *vop_win = &vop->win[i];
1311 const struct vop_win_data *win_data = vop_win->data;
1312 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1313
1314 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1315 continue;
1316
1317 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1318 possible_crtcs,
1319 &vop_plane_funcs,
1320 win_data->phy->data_formats,
1321 win_data->phy->nformats,
1322 win_data->type, NULL);
1323 if (ret) {
1324 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1325 ret);
1326 goto err_cleanup_crtc;
1327 }
1328 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1329 }
1330
1331 port = of_get_child_by_name(dev->of_node, "port");
1332 if (!port) {
1333 DRM_DEV_ERROR(vop->dev, "no port node found in %s\n",
1334 dev->of_node->full_name);
1335 ret = -ENOENT;
1336 goto err_cleanup_crtc;
1337 }
1338
1339 drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1340 vop_fb_unref_worker);
1341
1342 init_completion(&vop->dsp_hold_completion);
1343 init_completion(&vop->line_flag_completion);
1344 crtc->port = port;
1345
1346 return 0;
1347
1348 err_cleanup_crtc:
1349 drm_crtc_cleanup(crtc);
1350 err_cleanup_planes:
1351 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1352 head)
1353 drm_plane_cleanup(plane);
1354 return ret;
1355 }
1356
1357 static void vop_destroy_crtc(struct vop *vop)
1358 {
1359 struct drm_crtc *crtc = &vop->crtc;
1360 struct drm_device *drm_dev = vop->drm_dev;
1361 struct drm_plane *plane, *tmp;
1362
1363 of_node_put(crtc->port);
1364
1365 /*
1366 * We need to cleanup the planes now. Why?
1367 *
1368 * The planes are "&vop->win[i].base". That means the memory is
1369 * all part of the big "struct vop" chunk of memory. That memory
1370 * was devm allocated and associated with this component. We need to
1371 * free it ourselves before vop_unbind() finishes.
1372 */
1373 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1374 head)
1375 vop_plane_destroy(plane);
1376
1377 /*
1378 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1379 * references the CRTC.
1380 */
1381 drm_crtc_cleanup(crtc);
1382 drm_flip_work_cleanup(&vop->fb_unref_work);
1383 }
1384
1385 static int vop_initial(struct vop *vop)
1386 {
1387 const struct vop_data *vop_data = vop->data;
1388 const struct vop_reg_data *init_table = vop_data->init_table;
1389 struct reset_control *ahb_rst;
1390 int i, ret;
1391
1392 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1393 if (IS_ERR(vop->hclk)) {
1394 dev_err(vop->dev, "failed to get hclk source\n");
1395 return PTR_ERR(vop->hclk);
1396 }
1397 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1398 if (IS_ERR(vop->aclk)) {
1399 dev_err(vop->dev, "failed to get aclk source\n");
1400 return PTR_ERR(vop->aclk);
1401 }
1402 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1403 if (IS_ERR(vop->dclk)) {
1404 dev_err(vop->dev, "failed to get dclk source\n");
1405 return PTR_ERR(vop->dclk);
1406 }
1407
1408 ret = pm_runtime_get_sync(vop->dev);
1409 if (ret < 0) {
1410 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
1411 return ret;
1412 }
1413
1414 ret = clk_prepare(vop->dclk);
1415 if (ret < 0) {
1416 dev_err(vop->dev, "failed to prepare dclk\n");
1417 goto err_put_pm_runtime;
1418 }
1419
1420 /* Enable both the hclk and aclk to setup the vop */
1421 ret = clk_prepare_enable(vop->hclk);
1422 if (ret < 0) {
1423 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1424 goto err_unprepare_dclk;
1425 }
1426
1427 ret = clk_prepare_enable(vop->aclk);
1428 if (ret < 0) {
1429 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1430 goto err_disable_hclk;
1431 }
1432
1433 /*
1434 * do hclk_reset, reset all vop registers.
1435 */
1436 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1437 if (IS_ERR(ahb_rst)) {
1438 dev_err(vop->dev, "failed to get ahb reset\n");
1439 ret = PTR_ERR(ahb_rst);
1440 goto err_disable_aclk;
1441 }
1442 reset_control_assert(ahb_rst);
1443 usleep_range(10, 20);
1444 reset_control_deassert(ahb_rst);
1445
1446 memcpy(vop->regsbak, vop->regs, vop->len);
1447
1448 for (i = 0; i < vop_data->table_size; i++)
1449 vop_writel(vop, init_table[i].offset, init_table[i].value);
1450
1451 for (i = 0; i < vop_data->win_size; i++) {
1452 const struct vop_win_data *win = &vop_data->win[i];
1453
1454 VOP_WIN_SET(vop, win, enable, 0);
1455 }
1456
1457 vop_cfg_done(vop);
1458
1459 /*
1460 * do dclk_reset, let all config take affect.
1461 */
1462 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1463 if (IS_ERR(vop->dclk_rst)) {
1464 dev_err(vop->dev, "failed to get dclk reset\n");
1465 ret = PTR_ERR(vop->dclk_rst);
1466 goto err_disable_aclk;
1467 }
1468 reset_control_assert(vop->dclk_rst);
1469 usleep_range(10, 20);
1470 reset_control_deassert(vop->dclk_rst);
1471
1472 clk_disable(vop->hclk);
1473 clk_disable(vop->aclk);
1474
1475 vop->is_enabled = false;
1476
1477 pm_runtime_put_sync(vop->dev);
1478
1479 return 0;
1480
1481 err_disable_aclk:
1482 clk_disable_unprepare(vop->aclk);
1483 err_disable_hclk:
1484 clk_disable_unprepare(vop->hclk);
1485 err_unprepare_dclk:
1486 clk_unprepare(vop->dclk);
1487 err_put_pm_runtime:
1488 pm_runtime_put_sync(vop->dev);
1489 return ret;
1490 }
1491
1492 /*
1493 * Initialize the vop->win array elements.
1494 */
1495 static void vop_win_init(struct vop *vop)
1496 {
1497 const struct vop_data *vop_data = vop->data;
1498 unsigned int i;
1499
1500 for (i = 0; i < vop_data->win_size; i++) {
1501 struct vop_win *vop_win = &vop->win[i];
1502 const struct vop_win_data *win_data = &vop_data->win[i];
1503
1504 vop_win->data = win_data;
1505 vop_win->vop = vop;
1506 }
1507 }
1508
1509 /**
1510 * rockchip_drm_wait_line_flag - acqiure the give line flag event
1511 * @crtc: CRTC to enable line flag
1512 * @line_num: interested line number
1513 * @mstimeout: millisecond for timeout
1514 *
1515 * Driver would hold here until the interested line flag interrupt have
1516 * happened or timeout to wait.
1517 *
1518 * Returns:
1519 * Zero on success, negative errno on failure.
1520 */
1521 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
1522 unsigned int mstimeout)
1523 {
1524 struct vop *vop = to_vop(crtc);
1525 unsigned long jiffies_left;
1526
1527 if (!crtc || !vop->is_enabled)
1528 return -ENODEV;
1529
1530 if (line_num > crtc->mode.vtotal || mstimeout <= 0)
1531 return -EINVAL;
1532
1533 if (vop_line_flag_irq_is_enabled(vop))
1534 return -EBUSY;
1535
1536 reinit_completion(&vop->line_flag_completion);
1537 vop_line_flag_irq_enable(vop, line_num);
1538
1539 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
1540 msecs_to_jiffies(mstimeout));
1541 vop_line_flag_irq_disable(vop);
1542
1543 if (jiffies_left == 0) {
1544 dev_err(vop->dev, "Timeout waiting for IRQ\n");
1545 return -ETIMEDOUT;
1546 }
1547
1548 return 0;
1549 }
1550 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
1551
1552 static int vop_bind(struct device *dev, struct device *master, void *data)
1553 {
1554 struct platform_device *pdev = to_platform_device(dev);
1555 const struct vop_data *vop_data;
1556 struct drm_device *drm_dev = data;
1557 struct vop *vop;
1558 struct resource *res;
1559 size_t alloc_size;
1560 int ret, irq;
1561
1562 vop_data = of_device_get_match_data(dev);
1563 if (!vop_data)
1564 return -ENODEV;
1565
1566 /* Allocate vop struct and its vop_win array */
1567 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1568 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1569 if (!vop)
1570 return -ENOMEM;
1571
1572 vop->dev = dev;
1573 vop->data = vop_data;
1574 vop->drm_dev = drm_dev;
1575 dev_set_drvdata(dev, vop);
1576
1577 vop_win_init(vop);
1578
1579 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1580 vop->len = resource_size(res);
1581 vop->regs = devm_ioremap_resource(dev, res);
1582 if (IS_ERR(vop->regs))
1583 return PTR_ERR(vop->regs);
1584
1585 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1586 if (!vop->regsbak)
1587 return -ENOMEM;
1588
1589 irq = platform_get_irq(pdev, 0);
1590 if (irq < 0) {
1591 dev_err(dev, "cannot find irq for vop\n");
1592 return irq;
1593 }
1594 vop->irq = (unsigned int)irq;
1595
1596 spin_lock_init(&vop->reg_lock);
1597 spin_lock_init(&vop->irq_lock);
1598
1599 mutex_init(&vop->vsync_mutex);
1600
1601 ret = devm_request_irq(dev, vop->irq, vop_isr,
1602 IRQF_SHARED, dev_name(dev), vop);
1603 if (ret)
1604 return ret;
1605
1606 /* IRQ is initially disabled; it gets enabled in power_on */
1607 disable_irq(vop->irq);
1608
1609 ret = vop_create_crtc(vop);
1610 if (ret)
1611 goto err_enable_irq;
1612
1613 pm_runtime_enable(&pdev->dev);
1614
1615 ret = vop_initial(vop);
1616 if (ret < 0) {
1617 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1618 goto err_disable_pm_runtime;
1619 }
1620
1621 return 0;
1622
1623 err_disable_pm_runtime:
1624 pm_runtime_disable(&pdev->dev);
1625 vop_destroy_crtc(vop);
1626 err_enable_irq:
1627 enable_irq(vop->irq); /* To balance out the disable_irq above */
1628 return ret;
1629 }
1630
1631 static void vop_unbind(struct device *dev, struct device *master, void *data)
1632 {
1633 struct vop *vop = dev_get_drvdata(dev);
1634
1635 pm_runtime_disable(dev);
1636 vop_destroy_crtc(vop);
1637
1638 clk_unprepare(vop->aclk);
1639 clk_unprepare(vop->hclk);
1640 clk_unprepare(vop->dclk);
1641 }
1642
1643 const struct component_ops vop_component_ops = {
1644 .bind = vop_bind,
1645 .unbind = vop_unbind,
1646 };
1647 EXPORT_SYMBOL_GPL(vop_component_ops);
CRIS linux kernel tree