drivers/pinctrl/sh-pfc/pfc-r8a7794.c

   1 /*
   2  * r8a7794/r8a7745 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2014-2015 Renesas Electronics Corporation
   5  * Copyright (C) 2015 Renesas Solutions Corp.
   6  * Copyright (C) 2015-2017 Cogent Embedded, Inc. <source@cogentembedded.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2
  10  * as published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14
  15 #include "core.h"
  16 #include "sh_pfc.h"
  17
  18 #define CPU_ALL_PORT(fn, sfx)                                           \
  19         PORT_GP_32(0, fn, sfx),                                         \
  20         PORT_GP_26(1, fn, sfx),                                         \
  21         PORT_GP_32(2, fn, sfx),                                         \
  22         PORT_GP_32(3, fn, sfx),                                         \
  23         PORT_GP_32(4, fn, sfx),                                         \
  24         PORT_GP_28(5, fn, sfx),                                         \
  25         PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),          \
  26         PORT_GP_1(6, 24, fn, sfx),                                      \
  27         PORT_GP_1(6, 25, fn, sfx)
  28
  29 enum {
  30         PINMUX_RESERVED = 0,
  31
  32         PINMUX_DATA_BEGIN,
  33         GP_ALL(DATA),
  34         PINMUX_DATA_END,
  35
  36         PINMUX_FUNCTION_BEGIN,
  37         GP_ALL(FN),
  38
  39         /* GPSR0 */
  40         FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
  41         FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
  42         FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
  43         FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
  44         FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
  45         FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
  46         FN_IP2_17_16,
  47
  48         /* GPSR1 */
  49         FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
  50         FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
  51         FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
  52         FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
  53         FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
  54
  55         /* GPSR2 */
  56         FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
  57         FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
  58         FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
  59         FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
  60         FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
  61         FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
  62         FN_IP6_5_4, FN_IP6_7_6,
  63
  64         /* GPSR3 */
  65         FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
  66         FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
  67         FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
  68         FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
  69         FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
  70         FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
  71         FN_IP8_22_20,
  72
  73         /* GPSR4 */
  74         FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
  75         FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
  76         FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
  77         FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
  78         FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
  79         FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
  80         FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
  81
  82         /* GPSR5 */
  83         FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
  84         FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
  85         FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
  86         FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
  87         FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
  88         FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
  89
  90         /* GPSR6 */
  91         FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
  92         FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
  93         FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
  94         FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
  95         FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
  96
  97         /* IPSR0 */
  98         FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
  99         FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
 100         FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
 101         FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
 102         FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
 103         FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
 104         FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
 105         FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
 106
 107         /* IPSR1 */
 108         FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D,
 109         FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
 110         FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B,
 111         FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B,
 112         FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
 113         FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
 114         FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
 115         FN_D13, FN_SCIFA1_SCK, FN_PWM2_C, FN_TCLK2_B,
 116         FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B,
 117         FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B,
 118         FN_A0, FN_SCIFB1_SCK, FN_PWM3_B,
 119         FN_A1, FN_SCIFB1_TXD,
 120         FN_A3, FN_SCIFB0_SCK,
 121         FN_A4, FN_SCIFB0_TXD,
 122         FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
 123         FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
 124
 125         /* IPSR2 */
 126         FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B,
 127         FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B,
 128         FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B,
 129         FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B,
 130         FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B,
 131         FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B,
 132         FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B,
 133         FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
 134         FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
 135         FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_CAN_CLK_C,
 136         FN_TPUTO2_B,
 137         FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
 138         FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
 139         FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
 140         FN_A20, FN_SPCLK,
 141
 142         /* IPSR3 */
 143         FN_A21, FN_MOSI_IO0,
 144         FN_A22, FN_MISO_IO1, FN_ATADIR1_N,
 145         FN_A23, FN_IO2, FN_ATAWR1_N,
 146         FN_A24, FN_IO3, FN_EX_WAIT2,
 147         FN_A25, FN_SSL, FN_ATARD1_N,
 148         FN_CS0_N, FN_VI1_DATA8,
 149         FN_CS1_N_A26, FN_VI1_DATA9,
 150         FN_EX_CS0_N, FN_VI1_DATA10,
 151         FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
 152         FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_TPUTO3,
 153         FN_SCIFB2_TXD,
 154         FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, FN_BPFCLK,
 155         FN_SCIFB2_SCK,
 156         FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_FMCLK,
 157         FN_SCIFB2_CTS_N,
 158         FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, FN_FMIN,
 159         FN_SCIFB2_RTS_N,
 160         FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
 161         FN_RD_N, FN_ATACS11_N,
 162         FN_RD_WR_N, FN_ATAG1_N,
 163
 164         /* IPSR4 */
 165         FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK,
 166         FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
 167         FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
 168         FN_DU0_DR2, FN_LCDOUT18,
 169         FN_DU0_DR3, FN_LCDOUT19,
 170         FN_DU0_DR4, FN_LCDOUT20,
 171         FN_DU0_DR5, FN_LCDOUT21,
 172         FN_DU0_DR6, FN_LCDOUT22,
 173         FN_DU0_DR7, FN_LCDOUT23,
 174         FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
 175         FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
 176         FN_DU0_DG2, FN_LCDOUT10,
 177         FN_DU0_DG3, FN_LCDOUT11,
 178         FN_DU0_DG4, FN_LCDOUT12,
 179
 180         /* IPSR5 */
 181         FN_DU0_DG5, FN_LCDOUT13,
 182         FN_DU0_DG6, FN_LCDOUT14,
 183         FN_DU0_DG7, FN_LCDOUT15,
 184         FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
 185         FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, FN_CAN0_TX_C,
 186         FN_DU0_DB2, FN_LCDOUT2,
 187         FN_DU0_DB3, FN_LCDOUT3,
 188         FN_DU0_DB4, FN_LCDOUT4,
 189         FN_DU0_DB5, FN_LCDOUT5,
 190         FN_DU0_DB6, FN_LCDOUT6,
 191         FN_DU0_DB7, FN_LCDOUT7,
 192         FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
 193         FN_DU0_DOTCLKOUT0, FN_QCLK,
 194         FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
 195         FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
 196
 197         /* IPSR6 */
 198         FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
 199         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE,
 200         FN_DU0_DISP, FN_QPOLA,
 201         FN_DU0_CDE, FN_QPOLB,
 202         FN_VI0_CLK, FN_AVB_RX_CLK,
 203         FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
 204         FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
 205         FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
 206         FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
 207         FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
 208         FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
 209         FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
 210         FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
 211         FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7,
 212         FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER,
 213         FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL,
 214         FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B,
 215         FN_AVB_TX_EN,
 216         FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK,
 217         FN_ADIDATA,
 218
 219         /* IPSR7 */
 220         FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, FN_AVB_TXD0,
 221         FN_ADICS_SAMP,
 222         FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, FN_AVB_TXD1,
 223         FN_ADICLK,
 224         FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2,
 225         FN_ADICHS0,
 226         FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
 227         FN_ADICHS1,
 228         FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, FN_AVB_TXD4,
 229         FN_ADICHS2,
 230         FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, FN_SSI_SCK5_B,
 231         FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, FN_AVB_TXD6,
 232         FN_SSI_WS5_B,
 233         FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D, FN_AVB_TXD7,
 234         FN_SSI_SDATA5_B,
 235         FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
 236         FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
 237         FN_SSI_WS6_B,
 238         FN_DREQ0_N, FN_SCIFB1_RXD,
 239
 240         /* IPSR8 */
 241         FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
 242         FN_SSI_SDATA6_B,
 243         FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, FN_AVB_MDIO,
 244         FN_SSI_SCK78_B,
 245         FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK,
 246         FN_SSI_WS78_B,
 247         FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
 248         FN_AVB_MAGIC, FN_SSI_SDATA7_B,
 249         FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
 250         FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
 251         FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
 252         FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
 253         FN_CAN1_RX_D, FN_TPUTO0_B,
 254         FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, FN_DVC_MUTE,
 255         FN_CAN1_TX_D,
 256         FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, FN_TS_SDATA_D,
 257         FN_TPUTO1_B,
 258         FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_TS_SCK_D,
 259         FN_BPFCLK_C,
 260         FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, FN_TS_SDEN_D,
 261         FN_FMCLK_C,
 262
 263         /* IPSR9 */
 264         FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_TS_SPSYNC_D,
 265         FN_FMIN_C,
 266         FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, FN_TPUTO1_C,
 267         FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_BPFCLK_B,
 268         FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_FMCLK_B,
 269         FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, FN_FMIN_B,
 270         FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
 271         FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
 272         FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
 273         FN_SPEEDIN_B,
 274         FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, FN_SSI_SCK1_B,
 275         FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
 276         FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B,
 277
 278         /* IPSR10 */
 279         FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
 280         FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
 281         FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
 282         FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
 283         FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
 284         FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, FN_SSI_SDATA9_B,
 285         FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
 286         FN_SSI_SCK4_B,
 287         FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C,
 288         FN_SSI_WS4_B,
 289         FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
 290         FN_SSI_SDATA4_B,
 291         FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
 292         FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN,
 293
 294         /* IPSR11 */
 295         FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
 296         FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
 297         FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
 298         FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
 299         FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
 300         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
 301         FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
 302         FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
 303         FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
 304         FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
 305         FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
 306         FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
 307
 308         /* IPSR12 */
 309         FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
 310         FN_DREQ1_N_B,
 311         FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
 312         FN_CAN1_RX_C, FN_DACK1_B,
 313         FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
 314         FN_CAN1_TX_C, FN_DREQ2_N,
 315         FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B,
 316         FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B,
 317         FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, FN_REMOCON,
 318         FN_DACK2, FN_ETH_MDIO_B,
 319         FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
 320         FN_ETH_CRS_DV_B,
 321         FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D,
 322         FN_ETH_RX_ER_B,
 323         FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_ATAWR0_N,
 324         FN_ETH_RXD0_B,
 325         FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_ATAG0_N, FN_ETH_RXD1_B,
 326
 327         /* IPSR13 */
 328         FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
 329         FN_ATACS00_N, FN_ETH_LINK_B,
 330         FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, FN_VI1_DATA4,
 331         FN_ATACS10_N, FN_ETH_REFCLK_B,
 332         FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_EX_WAIT1,
 333         FN_ETH_TXD1_B,
 334         FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, FN_ATARD0_N,
 335         FN_ETH_TX_EN_B,
 336         FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
 337         FN_ATADIR0_N, FN_ETH_MAGIC_B,
 338         FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
 339         FN_TS_SDATA_C, FN_ETH_TXD0_B,
 340         FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
 341         FN_TS_SCK_C, FN_BPFCLK_E, FN_ETH_MDC_B,
 342         FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
 343         FN_TS_SDEN_C, FN_FMCLK_E,
 344         FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
 345         FN_TS_SPSYNC_C, FN_FMIN_E,
 346
 347         /* MOD_SEL */
 348         FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
 349         FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
 350         FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
 351         FN_SEL_DARC_4,
 352         FN_SEL_ETH_0, FN_SEL_ETH_1,
 353         FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
 354         FN_SEL_I2C00_4,
 355         FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
 356         FN_SEL_I2C01_4,
 357         FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
 358         FN_SEL_I2C02_4,
 359         FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
 360         FN_SEL_I2C03_4,
 361         FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
 362         FN_SEL_I2C04_4,
 363         FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
 364
 365         /* MOD_SEL2 */
 366         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
 367         FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
 368         FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1,
 369         FN_SEL_MSI2_0, FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1,
 370         FN_SEL_RCN_0, FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1,
 371         FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3,
 372         FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
 373         FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
 374         FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3,
 375         FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3,
 376         FN_SEL_TMU_0, FN_SEL_TMU_1,
 377         FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
 378         FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
 379         FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
 380         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
 381
 382         /* MOD_SEL3 */
 383         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 384         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
 385         FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
 386         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
 387         FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
 388         FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
 389         FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
 390         FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
 391         FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
 392         FN_SEL_SSI9_1,
 393         PINMUX_FUNCTION_END,
 394
 395         PINMUX_MARK_BEGIN,
 396         A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
 397
 398         USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
 399
 400         SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
 401         SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
 402
 403         SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
 404         SD1_DATA2_MARK, SD1_DATA3_MARK,
 405
 406         /* IPSR0 */
 407         SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
 408         MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
 409         SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
 410         SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
 411         MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
 412         CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
 413         CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
 414         SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
 415         SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
 416         SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
 417
 418         /* IPSR1 */
 419         D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK,
 420         D7_MARK, IRQ3_MARK, TCLK1_MARK, PWM6_B_MARK,
 421         D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK,
 422         D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK,
 423         D10_MARK, HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
 424         D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
 425         D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
 426         D13_MARK, SCIFA1_SCK_MARK, PWM2_C_MARK, TCLK2_B_MARK,
 427         D14_MARK, SCIFA1_RXD_MARK, I2C5_SCL_B_MARK,
 428         D15_MARK, SCIFA1_TXD_MARK, I2C5_SDA_B_MARK,
 429         A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK,
 430         A1_MARK, SCIFB1_TXD_MARK,
 431         A3_MARK, SCIFB0_SCK_MARK,
 432         A4_MARK, SCIFB0_TXD_MARK,
 433         A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK,
 434         A6_MARK, SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
 435
 436         /* IPSR2 */
 437         A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK,
 438         A8_MARK, MSIOF1_RXD_MARK, SCIFA0_RXD_B_MARK,
 439         A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
 440         A10_MARK, MSIOF1_SCK_MARK, IIC0_SCL_B_MARK,
 441         A11_MARK, MSIOF1_SYNC_MARK, IIC0_SDA_B_MARK,
 442         A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
 443         A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK,
 444         A14_MARK, MSIOF2_RXD_MARK, HSCIF0_HRX_B_MARK, DREQ1_N_MARK,
 445         A15_MARK, MSIOF2_TXD_MARK, HSCIF0_HTX_B_MARK, DACK1_MARK,
 446         A16_MARK, MSIOF2_SCK_MARK, HSCIF0_HSCK_B_MARK, SPEEDIN_MARK,
 447         CAN_CLK_C_MARK, TPUTO2_B_MARK,
 448         A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, CAN1_RX_B_MARK,
 449         A18_MARK, MSIOF2_SS1_MARK, SCIF4_TXD_E_MARK, CAN1_TX_B_MARK,
 450         A19_MARK, MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK,
 451         A20_MARK, SPCLK_MARK,
 452
 453         /* IPSR3 */
 454         A21_MARK, MOSI_IO0_MARK,
 455         A22_MARK, MISO_IO1_MARK, ATADIR1_N_MARK,
 456         A23_MARK, IO2_MARK, ATAWR1_N_MARK,
 457         A24_MARK, IO3_MARK, EX_WAIT2_MARK,
 458         A25_MARK, SSL_MARK, ATARD1_N_MARK,
 459         CS0_N_MARK, VI1_DATA8_MARK,
 460         CS1_N_A26_MARK, VI1_DATA9_MARK,
 461         EX_CS0_N_MARK, VI1_DATA10_MARK,
 462         EX_CS1_N_MARK, TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK,
 463         EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK,
 464         TPUTO3_MARK, SCIFB2_TXD_MARK,
 465         EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK,
 466         BPFCLK_MARK, SCIFB2_SCK_MARK,
 467         EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK,
 468         FMCLK_MARK, SCIFB2_CTS_N_MARK,
 469         EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK,
 470         FMIN_MARK, SCIFB2_RTS_N_MARK,
 471         BS_N_MARK, DRACK0_MARK, PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK,
 472         RD_N_MARK, ATACS11_N_MARK,
 473         RD_WR_N_MARK, ATAG1_N_MARK,
 474
 475         /* IPSR4 */
 476         EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK,
 477         DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
 478         DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, I2C2_SDA_D_MARK,
 479         DU0_DR2_MARK, LCDOUT18_MARK,
 480         DU0_DR3_MARK, LCDOUT19_MARK,
 481         DU0_DR4_MARK, LCDOUT20_MARK,
 482         DU0_DR5_MARK, LCDOUT21_MARK,
 483         DU0_DR6_MARK, LCDOUT22_MARK,
 484         DU0_DR7_MARK, LCDOUT23_MARK,
 485         DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
 486         DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, I2C3_SDA_D_MARK,
 487         DU0_DG2_MARK, LCDOUT10_MARK,
 488         DU0_DG3_MARK, LCDOUT11_MARK,
 489         DU0_DG4_MARK, LCDOUT12_MARK,
 490
 491         /* IPSR5 */
 492         DU0_DG5_MARK, LCDOUT13_MARK,
 493         DU0_DG6_MARK, LCDOUT14_MARK,
 494         DU0_DG7_MARK, LCDOUT15_MARK,
 495         DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, I2C4_SCL_D_MARK,
 496         CAN0_RX_C_MARK,
 497         DU0_DB1_MARK, LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK,
 498         CAN0_TX_C_MARK,
 499         DU0_DB2_MARK, LCDOUT2_MARK,
 500         DU0_DB3_MARK, LCDOUT3_MARK,
 501         DU0_DB4_MARK, LCDOUT4_MARK,
 502         DU0_DB5_MARK, LCDOUT5_MARK,
 503         DU0_DB6_MARK, LCDOUT6_MARK,
 504         DU0_DB7_MARK, LCDOUT7_MARK,
 505         DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
 506         DU0_DOTCLKOUT0_MARK, QCLK_MARK,
 507         DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
 508         DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
 509
 510         /* IPSR6 */
 511         DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
 512         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
 513         DU0_DISP_MARK, QPOLA_MARK, DU0_CDE_MARK, QPOLB_MARK,
 514         VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, AVB_RX_DV_MARK,
 515         VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
 516         VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK,
 517         VI0_DATA3_VI0_B3_MARK, AVB_RXD2_MARK,
 518         VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
 519         VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK,
 520         VI0_DATA6_VI0_B6_MARK, AVB_RXD5_MARK,
 521         VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK,
 522         VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK,
 523         AVB_RXD7_MARK,
 524         VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
 525         AVB_RX_ER_MARK,
 526         VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, IERX_C_MARK,
 527         AVB_COL_MARK,
 528         VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, I2C0_SDA_C_MARK,
 529         AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK,
 530         ETH_MDIO_MARK, VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK,
 531         AVB_TX_CLK_MARK, ADIDATA_MARK,
 532
 533         /* IPSR7 */
 534         ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, I2C5_SDA_D_MARK,
 535         AVB_TXD0_MARK, ADICS_SAMP_MARK,
 536         ETH_RX_ER_MARK, VI0_G2_MARK, MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK,
 537         AVB_TXD1_MARK, ADICLK_MARK,
 538         ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, CAN0_TX_B_MARK,
 539         AVB_TXD2_MARK, ADICHS0_MARK,
 540         ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
 541         AVB_TXD3_MARK, ADICHS1_MARK,
 542         ETH_LINK_MARK, VI0_G5_MARK, MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK,
 543         AVB_TXD4_MARK, ADICHS2_MARK,
 544         ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
 545         SSI_SCK5_B_MARK,
 546         ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, IIC0_SCL_D_MARK,
 547         AVB_TXD6_MARK, SSI_WS5_B_MARK,
 548         ETH_TX_EN_MARK, VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC0_SDA_D_MARK,
 549         AVB_TXD7_MARK, SSI_SDATA5_B_MARK,
 550         ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, AVB_TX_ER_MARK,
 551         SSI_SCK6_B_MARK,
 552         ETH_TXD0_MARK, VI0_R2_MARK, SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK,
 553         AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
 554         DREQ0_N_MARK, SCIFB1_RXD_MARK,
 555
 556         /* IPSR8 */
 557         ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
 558         AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
 559         I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
 560         HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
 561         AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
 562         SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
 563         HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
 564         AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
 565         HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
 566         I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
 567         AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
 568         SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
 569         CAN1_TX_D_MARK,
 570         I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, DU1_DR0_MARK,
 571         TS_SDATA_D_MARK, TPUTO1_B_MARK,
 572         I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, TS_SCK_D_MARK,
 573         BPFCLK_C_MARK,
 574         MSIOF0_RXD_MARK, SCIF5_RXD_MARK, I2C2_SCL_C_MARK, DU1_DR2_MARK,
 575         TS_SDEN_D_MARK, FMCLK_C_MARK,
 576
 577         /* IPSR9 */
 578         MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
 579         TS_SPSYNC_D_MARK, FMIN_C_MARK,
 580         MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, TPUTO1_C_MARK,
 581         MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, BPFCLK_B_MARK,
 582         MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK, DU1_DR6_MARK,
 583         FMCLK_B_MARK,
 584         MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
 585         FMIN_B_MARK,
 586         HSCIF1_HRX_MARK, I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK,
 587         HSCIF1_HTX_MARK, I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK,
 588         HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
 589         SPEEDIN_B_MARK,
 590         HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, DU1_DG3_MARK,
 591         SSI_SCK1_B_MARK,
 592         HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, DU1_DG4_MARK,
 593         SSI_WS1_B_MARK,
 594         SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
 595         CAN_TXCLK_MARK,
 596
 597         /* IPSR10 */
 598         SCIF1_RXD_MARK, I2C5_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
 599         SCIF1_TXD_MARK, I2C5_SDA_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
 600         SCIF2_RXD_MARK, IIC0_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
 601         SCIF2_TXD_MARK, IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK,
 602         SCIF2_SCK_MARK, IRQ1_MARK, DU1_DB2_MARK, SSI_WS9_B_MARK,
 603         SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, DU1_DB3_MARK,
 604         SSI_SDATA9_B_MARK,
 605         SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, DU1_DB4_MARK,
 606         AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK,
 607         SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, DU1_DB5_MARK,
 608         AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
 609         I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK,
 610         SSI_SDATA4_B_MARK,
 611         I2C2_SDA_MARK, SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
 612         SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK,
 613
 614         /* IPSR11 */
 615         SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
 616         SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, DU1_DOTCLKOUT1_MARK,
 617         SSI_SCK6_MARK, SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
 618         SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
 619         DU1_EXVSYNC_DU1_VSYNC_MARK,
 620         SSI_SDATA6_MARK, SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK,
 621         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
 622         SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, I2C5_SDA_C_MARK, DU1_DISP_MARK,
 623         SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK, DU1_CDE_MARK,
 624         SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK,
 625         CAN_CLK_D_MARK,
 626         SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK,
 627         SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, ADICS_SAMP_B_MARK,
 628         SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK, ADICLK_B_MARK,
 629
 630         /* IPSR12 */
 631         SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
 632         DREQ1_N_B_MARK,
 633         SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK, ADICHS1_B_MARK,
 634         CAN1_RX_C_MARK, DACK1_B_MARK,
 635         SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
 636         CAN1_TX_C_MARK, DREQ2_N_MARK,
 637         SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
 638         SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK,
 639         SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK,
 640         SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
 641         DACK2_MARK, ETH_MDIO_B_MARK,
 642         SSI_SCK1_MARK, SCIF1_RXD_B_MARK, IIC0_SCL_C_MARK, VI1_CLK_MARK,
 643         CAN0_RX_D_MARK, ETH_CRS_DV_B_MARK,
 644         SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK, VI1_DATA0_MARK,
 645         CAN0_TX_D_MARK, ETH_RX_ER_B_MARK,
 646         SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, ATAWR0_N_MARK,
 647         ETH_RXD0_B_MARK,
 648         SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, VI1_DATA2_MARK, ATAG0_N_MARK,
 649         ETH_RXD1_B_MARK,
 650
 651         /* IPSR13 */
 652         SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
 653         ATACS00_N_MARK, ETH_LINK_B_MARK,
 654         SSI_SDATA2_MARK, HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK,
 655         VI1_DATA4_MARK, ATACS10_N_MARK, ETH_REFCLK_B_MARK,
 656         SSI_SCK9_MARK, SCIF2_SCK_B_MARK, PWM2_B_MARK, VI1_DATA5_MARK,
 657         EX_WAIT1_MARK, ETH_TXD1_B_MARK,
 658         SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, VI1_DATA6_MARK,
 659         ATARD0_N_MARK, ETH_TX_EN_B_MARK,
 660         SSI_SDATA9_MARK, SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK,
 661         ATADIR0_N_MARK, ETH_MAGIC_B_MARK,
 662         AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, VI1_CLKENB_MARK,
 663         TS_SDATA_C_MARK, ETH_TXD0_B_MARK,
 664         AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
 665         TS_SCK_C_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
 666         AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
 667         TS_SDEN_C_MARK, FMCLK_E_MARK,
 668         AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
 669         TS_SPSYNC_C_MARK, FMIN_E_MARK,
 670         PINMUX_MARK_END,
 671 };
 672
 673 static const u16 pinmux_data[] = {
 674         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 675
 676         PINMUX_SINGLE(A2),
 677         PINMUX_SINGLE(WE0_N),
 678         PINMUX_SINGLE(WE1_N),
 679         PINMUX_SINGLE(DACK0),
 680         PINMUX_SINGLE(USB0_PWEN),
 681         PINMUX_SINGLE(USB0_OVC),
 682         PINMUX_SINGLE(USB1_PWEN),
 683         PINMUX_SINGLE(USB1_OVC),
 684         PINMUX_SINGLE(SD0_CLK),
 685         PINMUX_SINGLE(SD0_CMD),
 686         PINMUX_SINGLE(SD0_DATA0),
 687         PINMUX_SINGLE(SD0_DATA1),
 688         PINMUX_SINGLE(SD0_DATA2),
 689         PINMUX_SINGLE(SD0_DATA3),
 690         PINMUX_SINGLE(SD0_CD),
 691         PINMUX_SINGLE(SD0_WP),
 692         PINMUX_SINGLE(SD1_CLK),
 693         PINMUX_SINGLE(SD1_CMD),
 694         PINMUX_SINGLE(SD1_DATA0),
 695         PINMUX_SINGLE(SD1_DATA1),
 696         PINMUX_SINGLE(SD1_DATA2),
 697         PINMUX_SINGLE(SD1_DATA3),
 698
 699         /* IPSR0 */
 700         PINMUX_IPSR_GPSR(IP0_0, SD1_CD),
 701         PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0),
 702         PINMUX_IPSR_GPSR(IP0_9_8, SD1_WP),
 703         PINMUX_IPSR_GPSR(IP0_9_8, IRQ7),
 704         PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0),
 705         PINMUX_IPSR_GPSR(IP0_10, MMC_CLK),
 706         PINMUX_IPSR_GPSR(IP0_10, SD2_CLK),
 707         PINMUX_IPSR_GPSR(IP0_11, MMC_CMD),
 708         PINMUX_IPSR_GPSR(IP0_11, SD2_CMD),
 709         PINMUX_IPSR_GPSR(IP0_12, MMC_D0),
 710         PINMUX_IPSR_GPSR(IP0_12, SD2_DATA0),
 711         PINMUX_IPSR_GPSR(IP0_13, MMC_D1),
 712         PINMUX_IPSR_GPSR(IP0_13, SD2_DATA1),
 713         PINMUX_IPSR_GPSR(IP0_14, MMC_D2),
 714         PINMUX_IPSR_GPSR(IP0_14, SD2_DATA2),
 715         PINMUX_IPSR_GPSR(IP0_15, MMC_D3),
 716         PINMUX_IPSR_GPSR(IP0_15, SD2_DATA3),
 717         PINMUX_IPSR_GPSR(IP0_16, MMC_D4),
 718         PINMUX_IPSR_GPSR(IP0_16, SD2_CD),
 719         PINMUX_IPSR_GPSR(IP0_17, MMC_D5),
 720         PINMUX_IPSR_GPSR(IP0_17, SD2_WP),
 721         PINMUX_IPSR_GPSR(IP0_19_18, MMC_D6),
 722         PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
 723         PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
 724         PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0),
 725         PINMUX_IPSR_GPSR(IP0_21_20, MMC_D7),
 726         PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
 727         PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
 728         PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0),
 729         PINMUX_IPSR_GPSR(IP0_23_22, D0),
 730         PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
 731         PINMUX_IPSR_GPSR(IP0_23_22, IRQ4),
 732         PINMUX_IPSR_GPSR(IP0_24, D1),
 733         PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
 734         PINMUX_IPSR_GPSR(IP0_25, D2),
 735         PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
 736         PINMUX_IPSR_GPSR(IP0_27_26, D3),
 737         PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
 738         PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
 739         PINMUX_IPSR_GPSR(IP0_29_28, D4),
 740         PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
 741         PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
 742         PINMUX_IPSR_GPSR(IP0_31_30, D5),
 743         PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
 744         PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
 745
 746         /* IPSR1 */
 747         PINMUX_IPSR_GPSR(IP1_1_0, D6),
 748         PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1),
 749         PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3),
 750         PINMUX_IPSR_GPSR(IP1_3_2, D7),
 751         PINMUX_IPSR_GPSR(IP1_3_2, IRQ3),
 752         PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0),
 753         PINMUX_IPSR_GPSR(IP1_3_2, PWM6_B),
 754         PINMUX_IPSR_GPSR(IP1_5_4, D8),
 755         PINMUX_IPSR_GPSR(IP1_5_4, HSCIF2_HRX),
 756         PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1),
 757         PINMUX_IPSR_GPSR(IP1_7_6, D9),
 758         PINMUX_IPSR_GPSR(IP1_7_6, HSCIF2_HTX),
 759         PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1),
 760         PINMUX_IPSR_GPSR(IP1_10_8, D10),
 761         PINMUX_IPSR_GPSR(IP1_10_8, HSCIF2_HSCK),
 762         PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2),
 763         PINMUX_IPSR_GPSR(IP1_10_8, IRQ6),
 764         PINMUX_IPSR_GPSR(IP1_10_8, PWM5_C),
 765         PINMUX_IPSR_GPSR(IP1_12_11, D11),
 766         PINMUX_IPSR_GPSR(IP1_12_11, HSCIF2_HCTS_N),
 767         PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2),
 768         PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3),
 769         PINMUX_IPSR_GPSR(IP1_14_13, D12),
 770         PINMUX_IPSR_GPSR(IP1_14_13, HSCIF2_HRTS_N),
 771         PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2),
 772         PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
 773         PINMUX_IPSR_GPSR(IP1_17_15, D13),
 774         PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
 775         PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C),
 776         PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
 777         PINMUX_IPSR_GPSR(IP1_19_18, D14),
 778         PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
 779         PINMUX_IPSR_MSEL(IP1_19_18, I2C5_SCL_B, SEL_I2C05_1),
 780         PINMUX_IPSR_GPSR(IP1_21_20, D15),
 781         PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
 782         PINMUX_IPSR_MSEL(IP1_21_20, I2C5_SDA_B, SEL_I2C05_1),
 783         PINMUX_IPSR_GPSR(IP1_23_22, A0),
 784         PINMUX_IPSR_GPSR(IP1_23_22, SCIFB1_SCK),
 785         PINMUX_IPSR_GPSR(IP1_23_22, PWM3_B),
 786         PINMUX_IPSR_GPSR(IP1_24, A1),
 787         PINMUX_IPSR_GPSR(IP1_24, SCIFB1_TXD),
 788         PINMUX_IPSR_GPSR(IP1_26, A3),
 789         PINMUX_IPSR_GPSR(IP1_26, SCIFB0_SCK),
 790         PINMUX_IPSR_GPSR(IP1_27, A4),
 791         PINMUX_IPSR_GPSR(IP1_27, SCIFB0_TXD),
 792         PINMUX_IPSR_GPSR(IP1_29_28, A5),
 793         PINMUX_IPSR_GPSR(IP1_29_28, SCIFB0_RXD),
 794         PINMUX_IPSR_GPSR(IP1_29_28, PWM4_B),
 795         PINMUX_IPSR_GPSR(IP1_29_28, TPUTO3_C),
 796         PINMUX_IPSR_GPSR(IP1_31_30, A6),
 797         PINMUX_IPSR_GPSR(IP1_31_30, SCIFB0_CTS_N),
 798         PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1),
 799         PINMUX_IPSR_GPSR(IP1_31_30, TPUTO2_C),
 800
 801         /* IPSR2 */
 802         PINMUX_IPSR_GPSR(IP2_1_0, A7),
 803         PINMUX_IPSR_GPSR(IP2_1_0, SCIFB0_RTS_N),
 804         PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1),
 805         PINMUX_IPSR_GPSR(IP2_3_2, A8),
 806         PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0),
 807         PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1),
 808         PINMUX_IPSR_GPSR(IP2_5_4, A9),
 809         PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0),
 810         PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
 811         PINMUX_IPSR_GPSR(IP2_7_6, A10),
 812         PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
 813         PINMUX_IPSR_MSEL(IP2_7_6, IIC0_SCL_B, SEL_IIC0_1),
 814         PINMUX_IPSR_GPSR(IP2_9_8, A11),
 815         PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
 816         PINMUX_IPSR_MSEL(IP2_9_8, IIC0_SDA_B, SEL_IIC0_1),
 817         PINMUX_IPSR_GPSR(IP2_11_10, A12),
 818         PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
 819         PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
 820         PINMUX_IPSR_GPSR(IP2_13_12, A13),
 821         PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0),
 822         PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1),
 823         PINMUX_IPSR_GPSR(IP2_15_14, A14),
 824         PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0),
 825         PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1),
 826         PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0),
 827         PINMUX_IPSR_GPSR(IP2_17_16, A15),
 828         PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0),
 829         PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1),
 830         PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0),
 831         PINMUX_IPSR_GPSR(IP2_20_18, A16),
 832         PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
 833         PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
 834         PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
 835         PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
 836         PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
 837         PINMUX_IPSR_GPSR(IP2_23_21, A17),
 838         PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
 839         PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
 840         PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
 841         PINMUX_IPSR_GPSR(IP2_26_24, A18),
 842         PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
 843         PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
 844         PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
 845         PINMUX_IPSR_GPSR(IP2_29_27, A19),
 846         PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
 847         PINMUX_IPSR_GPSR(IP2_29_27, PWM4),
 848         PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2),
 849         PINMUX_IPSR_GPSR(IP2_31_30, A20),
 850         PINMUX_IPSR_GPSR(IP2_31_30, SPCLK),
 851
 852         /* IPSR3 */
 853         PINMUX_IPSR_GPSR(IP3_1_0, A21),
 854         PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0),
 855         PINMUX_IPSR_GPSR(IP3_3_2, A22),
 856         PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1),
 857         PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N),
 858         PINMUX_IPSR_GPSR(IP3_5_4, A23),
 859         PINMUX_IPSR_GPSR(IP3_5_4, IO2),
 860         PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N),
 861         PINMUX_IPSR_GPSR(IP3_7_6, A24),
 862         PINMUX_IPSR_GPSR(IP3_7_6, IO3),
 863         PINMUX_IPSR_GPSR(IP3_7_6, EX_WAIT2),
 864         PINMUX_IPSR_GPSR(IP3_9_8, A25),
 865         PINMUX_IPSR_GPSR(IP3_9_8, SSL),
 866         PINMUX_IPSR_GPSR(IP3_9_8, ATARD1_N),
 867         PINMUX_IPSR_GPSR(IP3_10, CS0_N),
 868         PINMUX_IPSR_GPSR(IP3_10, VI1_DATA8),
 869         PINMUX_IPSR_GPSR(IP3_11, CS1_N_A26),
 870         PINMUX_IPSR_GPSR(IP3_11, VI1_DATA9),
 871         PINMUX_IPSR_GPSR(IP3_12, EX_CS0_N),
 872         PINMUX_IPSR_GPSR(IP3_12, VI1_DATA10),
 873         PINMUX_IPSR_GPSR(IP3_14_13, EX_CS1_N),
 874         PINMUX_IPSR_GPSR(IP3_14_13, TPUTO3_B),
 875         PINMUX_IPSR_GPSR(IP3_14_13, SCIFB2_RXD),
 876         PINMUX_IPSR_GPSR(IP3_14_13, VI1_DATA11),
 877         PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N),
 878         PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
 879         PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
 880         PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
 881         PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
 882         PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
 883         PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
 884         PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
 885         PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
 886         PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
 887         PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
 888         PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
 889         PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
 890         PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
 891         PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
 892         PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
 893         PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
 894         PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
 895         PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
 896         PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
 897         PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
 898         PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
 899         PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
 900         PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
 901         PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
 902         PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
 903         PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C),
 904         PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C),
 905         PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N),
 906         PINMUX_IPSR_GPSR(IP3_30, RD_N),
 907         PINMUX_IPSR_GPSR(IP3_30, ATACS11_N),
 908         PINMUX_IPSR_GPSR(IP3_31, RD_WR_N),
 909         PINMUX_IPSR_GPSR(IP3_31, ATAG1_N),
 910
 911         /* IPSR4 */
 912         PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0),
 913         PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
 914         PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
 915         PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
 916         PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
 917         PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
 918         PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
 919         PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
 920         PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
 921         PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
 922         PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
 923         PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
 924         PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
 925         PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
 926         PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
 927         PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
 928         PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
 929         PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
 930         PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
 931         PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
 932         PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
 933         PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
 934         PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
 935         PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
 936         PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
 937         PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
 938         PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
 939         PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
 940         PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
 941         PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
 942         PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
 943         PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
 944         PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
 945         PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
 946         PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
 947         PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
 948         PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
 949
 950         /* IPSR5 */
 951         PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
 952         PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
 953         PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
 954         PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
 955         PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
 956         PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
 957         PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
 958         PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
 959         PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
 960         PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
 961         PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
 962         PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
 963         PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
 964         PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
 965         PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
 966         PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
 967         PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
 968         PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
 969         PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
 970         PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
 971         PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
 972         PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
 973         PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
 974         PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
 975         PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
 976         PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
 977         PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
 978         PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
 979         PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
 980         PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
 981         PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
 982         PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
 983         PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
 984         PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
 985         PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
 986         PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
 987
 988         /* IPSR6 */
 989         PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
 990         PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
 991         PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
 992         PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
 993         PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
 994         PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
 995         PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
 996         PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
 997         PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
 998         PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
 999         PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
1000         PINMUX_IPSR_GPSR(IP6_9, AVB_RX_DV),
1001         PINMUX_IPSR_GPSR(IP6_10, VI0_DATA1_VI0_B1),
1002         PINMUX_IPSR_GPSR(IP6_10, AVB_RXD0),
1003         PINMUX_IPSR_GPSR(IP6_11, VI0_DATA2_VI0_B2),
1004         PINMUX_IPSR_GPSR(IP6_11, AVB_RXD1),
1005         PINMUX_IPSR_GPSR(IP6_12, VI0_DATA3_VI0_B3),
1006         PINMUX_IPSR_GPSR(IP6_12, AVB_RXD2),
1007         PINMUX_IPSR_GPSR(IP6_13, VI0_DATA4_VI0_B4),
1008         PINMUX_IPSR_GPSR(IP6_13, AVB_RXD3),
1009         PINMUX_IPSR_GPSR(IP6_14, VI0_DATA5_VI0_B5),
1010         PINMUX_IPSR_GPSR(IP6_14, AVB_RXD4),
1011         PINMUX_IPSR_GPSR(IP6_15, VI0_DATA6_VI0_B6),
1012         PINMUX_IPSR_GPSR(IP6_15, AVB_RXD5),
1013         PINMUX_IPSR_GPSR(IP6_16, VI0_DATA7_VI0_B7),
1014         PINMUX_IPSR_GPSR(IP6_16, AVB_RXD6),
1015         PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB),
1016         PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
1017         PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
1018         PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
1019         PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7),
1020         PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD),
1021         PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
1022         PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
1023         PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
1024         PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER),
1025         PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N),
1026         PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
1027         PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
1028         PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
1029         PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL),
1030         PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N),
1031         PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
1032         PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
1033         PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
1034         PINMUX_IPSR_GPSR(IP6_28_26, AVB_TX_EN),
1035         PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0),
1036         PINMUX_IPSR_GPSR(IP6_31_29, VI0_G0),
1037         PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
1038         PINMUX_IPSR_MSEL(IP6_31_29, I2C5_SCL_D, SEL_I2C05_3),
1039         PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
1040         PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
1041
1042         /* IPSR7 */
1043         PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
1044         PINMUX_IPSR_GPSR(IP7_2_0, VI0_G1),
1045         PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
1046         PINMUX_IPSR_MSEL(IP7_2_0, I2C5_SDA_D, SEL_I2C05_3),
1047         PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
1048         PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
1049         PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
1050         PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
1051         PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
1052         PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
1053         PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1),
1054         PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
1055         PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
1056         PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3),
1057         PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
1058         PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
1059         PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
1060         PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
1061         PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
1062         PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
1063         PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
1064         PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
1065         PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3),
1066         PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
1067         PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
1068         PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5),
1069         PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
1070         PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
1071         PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4),
1072         PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
1073         PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
1074         PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6),
1075         PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
1076         PINMUX_IPSR_GPSR(IP7_17_15, AVB_TXD5),
1077         PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
1078         PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0),
1079         PINMUX_IPSR_GPSR(IP7_20_18, VI0_G7),
1080         PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
1081         PINMUX_IPSR_MSEL(IP7_20_18, IIC0_SCL_D, SEL_IIC0_3),
1082         PINMUX_IPSR_GPSR(IP7_20_18, AVB_TXD6),
1083         PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
1084         PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
1085         PINMUX_IPSR_GPSR(IP7_23_21, VI0_R0),
1086         PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
1087         PINMUX_IPSR_MSEL(IP7_23_21, IIC0_SDA_D, SEL_IIC0_3),
1088         PINMUX_IPSR_GPSR(IP7_23_21, AVB_TXD7),
1089         PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
1090         PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
1091         PINMUX_IPSR_GPSR(IP7_26_24, VI0_R1),
1092         PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
1093         PINMUX_IPSR_GPSR(IP7_26_24, AVB_TX_ER),
1094         PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
1095         PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0),
1096         PINMUX_IPSR_GPSR(IP7_29_27, VI0_R2),
1097         PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
1098         PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
1099         PINMUX_IPSR_GPSR(IP7_29_27, AVB_GTX_CLK),
1100         PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
1101         PINMUX_IPSR_GPSR(IP7_31, DREQ0_N),
1102         PINMUX_IPSR_GPSR(IP7_31, SCIFB1_RXD),
1103
1104         /* IPSR8 */
1105         PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0),
1106         PINMUX_IPSR_GPSR(IP8_2_0, VI0_R3),
1107         PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
1108         PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
1109         PINMUX_IPSR_GPSR(IP8_2_0, AVB_MDC),
1110         PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
1111         PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
1112         PINMUX_IPSR_GPSR(IP8_5_3, VI0_R4),
1113         PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
1114         PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
1115         PINMUX_IPSR_GPSR(IP8_5_3, AVB_MDIO),
1116         PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
1117         PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
1118         PINMUX_IPSR_GPSR(IP8_8_6, VI0_R5),
1119         PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
1120         PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1121         PINMUX_IPSR_GPSR(IP8_5_3, AVB_LINK),
1122         PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
1123         PINMUX_IPSR_GPSR(IP8_11_9, HSCIF0_HCTS_N),
1124         PINMUX_IPSR_GPSR(IP8_11_9, VI0_R6),
1125         PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
1126         PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
1127         PINMUX_IPSR_GPSR(IP8_11_9, AVB_MAGIC),
1128         PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
1129         PINMUX_IPSR_GPSR(IP8_14_12, HSCIF0_HRTS_N),
1130         PINMUX_IPSR_GPSR(IP8_14_12, VI0_R7),
1131         PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
1132         PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
1133         PINMUX_IPSR_GPSR(IP8_14_12, AVB_PHY_INT),
1134         PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
1135         PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
1136         PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
1137         PINMUX_IPSR_GPSR(IP8_16_15, AVB_CRS),
1138         PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
1139         PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
1140         PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
1141         PINMUX_IPSR_GPSR(IP8_19_17, PWM5),
1142         PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1),
1143         PINMUX_IPSR_GPSR(IP8_19_17, AVB_GTXREFCLK),
1144         PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
1145         PINMUX_IPSR_GPSR(IP8_19_17, TPUTO0_B),
1146         PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
1147         PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
1148         PINMUX_IPSR_GPSR(IP8_22_20, TPUTO0),
1149         PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0),
1150         PINMUX_IPSR_GPSR(IP8_22_20, DVC_MUTE),
1151         PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
1152         PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
1153         PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
1154         PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
1155         PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
1156         PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
1157         PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
1158         PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
1159         PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
1160         PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
1161         PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
1162         PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
1163         PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
1164         PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
1165         PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
1166         PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
1167         PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
1168         PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
1169         PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
1170
1171         /* IPSR9 */
1172         PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
1173         PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
1174         PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
1175         PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
1176         PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
1177         PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
1178         PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
1179         PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
1180         PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
1181         PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
1182         PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
1183         PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
1184         PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
1185         PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
1186         PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
1187         PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
1188         PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
1189         PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
1190         PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
1191         PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
1192         PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
1193         PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
1194         PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
1195         PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
1196         PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
1197         PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
1198         PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
1199         PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
1200         PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
1201         PINMUX_IPSR_GPSR(IP9_16_15, DU1_DG0),
1202         PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0),
1203         PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0),
1204         PINMUX_IPSR_GPSR(IP9_18_17, TPUTO1),
1205         PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1),
1206         PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK),
1207         PINMUX_IPSR_GPSR(IP9_21_19, PWM2),
1208         PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
1209         PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
1210         PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
1211         PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
1212         PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
1213         PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
1214         PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
1215         PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
1216         PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
1217         PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
1218         PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
1219         PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
1220         PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
1221         PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
1222         PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
1223         PINMUX_IPSR_GPSR(IP9_30_28, PWM3),
1224         PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
1225         PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5),
1226         PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
1227
1228         /* IPSR10 */
1229         PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
1230         PINMUX_IPSR_MSEL(IP10_2_0, I2C5_SCL, SEL_I2C05_0),
1231         PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
1232         PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
1233         PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
1234         PINMUX_IPSR_MSEL(IP10_5_3, I2C5_SDA, SEL_I2C05_0),
1235         PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
1236         PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
1237         PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
1238         PINMUX_IPSR_MSEL(IP10_8_6, IIC0_SCL, SEL_IIC0_0),
1239         PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
1240         PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
1241         PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
1242         PINMUX_IPSR_MSEL(IP10_11_9, IIC0_SDA, SEL_IIC0_0),
1243         PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
1244         PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
1245         PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
1246         PINMUX_IPSR_GPSR(IP10_14_12, IRQ1),
1247         PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2),
1248         PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
1249         PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
1250         PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
1251         PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
1252         PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
1253         PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
1254         PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
1255         PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
1256         PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
1257         PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
1258         PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
1259         PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
1260         PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
1261         PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
1262         PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
1263         PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
1264         PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
1265         PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
1266         PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
1267         PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
1268         PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6),
1269         PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
1270         PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
1271         PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
1272         PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
1273         PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7),
1274         PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
1275         PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
1276         PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
1277         PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN),
1278
1279         /* IPSR11 */
1280         PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
1281         PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1282         PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
1283         PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0),
1284         PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
1285         PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
1286         PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
1287         PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1),
1288         PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
1289         PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
1290         PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
1291         PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
1292         PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
1293         PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
1294         PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
1295         PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
1296         PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
1297         PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
1298         PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1299         PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
1300         PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
1301         PINMUX_IPSR_MSEL(IP11_15_14, I2C5_SDA_C, SEL_I2C05_2),
1302         PINMUX_IPSR_GPSR(IP11_15_14, DU1_DISP),
1303         PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0),
1304         PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
1305         PINMUX_IPSR_MSEL(IP11_17_16, I2C5_SCL_C, SEL_I2C05_2),
1306         PINMUX_IPSR_GPSR(IP11_17_16, DU1_CDE),
1307         PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
1308         PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
1309         PINMUX_IPSR_GPSR(IP11_20_18, IRQ8),
1310         PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
1311         PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
1312         PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
1313         PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
1314         PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
1315         PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
1316         PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
1317         PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
1318         PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
1319         PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
1320         PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
1321         PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
1322         PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
1323         PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
1324
1325         /* IPSR12 */
1326         PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
1327         PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
1328         PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
1329         PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
1330         PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
1331         PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
1332         PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
1333         PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
1334         PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
1335         PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
1336         PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
1337         PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3),
1338         PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
1339         PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
1340         PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
1341         PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
1342         PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N),
1343         PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
1344         PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
1345         PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
1346         PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
1347         PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
1348         PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
1349         PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
1350         PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
1351         PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
1352         PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
1353         PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
1354         PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
1355         PINMUX_IPSR_GPSR(IP12_17_15, IRQ9),
1356         PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
1357         PINMUX_IPSR_GPSR(IP12_17_15, DACK2),
1358         PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
1359         PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
1360         PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
1361         PINMUX_IPSR_MSEL(IP12_20_18, IIC0_SCL_C, SEL_IIC0_2),
1362         PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
1363         PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
1364         PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
1365         PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
1366         PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
1367         PINMUX_IPSR_MSEL(IP12_23_21, IIC0_SDA_C, SEL_IIC0_2),
1368         PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
1369         PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
1370         PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
1371         PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
1372         PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
1373         PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
1374         PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N),
1375         PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
1376         PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
1377         PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
1378         PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
1379         PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N),
1380         PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
1381
1382         /* IPSR13 */
1383         PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0),
1384         PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
1385         PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
1386         PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3),
1387         PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N),
1388         PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
1389         PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
1390         PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
1391         PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
1392         PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4),
1393         PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N),
1394         PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
1395         PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
1396         PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
1397         PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B),
1398         PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5),
1399         PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1),
1400         PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
1401         PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
1402         PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1),
1403         PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4),
1404         PINMUX_IPSR_GPSR(IP13_11_9, VI1_DATA6),
1405         PINMUX_IPSR_GPSR(IP13_11_9, ATARD0_N),
1406         PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1),
1407         PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0),
1408         PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1),
1409         PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4),
1410         PINMUX_IPSR_GPSR(IP13_14_12, VI1_DATA7),
1411         PINMUX_IPSR_GPSR(IP13_14_12, ATADIR0_N),
1412         PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1),
1413         PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0),
1414         PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
1415         PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
1416         PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
1417         PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
1418         PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
1419         PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
1420         PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
1421         PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
1422         PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
1423         PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
1424         PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
1425         PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
1426         PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
1427         PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
1428         PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
1429         PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
1430         PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
1431         PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
1432         PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
1433         PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
1434         PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
1435         PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
1436         PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
1437         PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
1438 };
1439
1440 static const struct sh_pfc_pin pinmux_pins[] = {
1441         PINMUX_GPIO_GP_ALL(),
1442 };
1443
1444 /* - Audio Clock ------------------------------------------------------------ */
1445 static const unsigned int audio_clka_pins[] = {
1446         /* CLKA */
1447         RCAR_GP_PIN(5, 20),
1448 };
1449 static const unsigned int audio_clka_mux[] = {
1450         AUDIO_CLKA_MARK,
1451 };
1452 static const unsigned int audio_clka_b_pins[] = {
1453         /* CLKA */
1454         RCAR_GP_PIN(3, 25),
1455 };
1456 static const unsigned int audio_clka_b_mux[] = {
1457         AUDIO_CLKA_B_MARK,
1458 };
1459 static const unsigned int audio_clka_c_pins[] = {
1460         /* CLKA */
1461         RCAR_GP_PIN(4, 20),
1462 };
1463 static const unsigned int audio_clka_c_mux[] = {
1464         AUDIO_CLKA_C_MARK,
1465 };
1466 static const unsigned int audio_clka_d_pins[] = {
1467         /* CLKA */
1468         RCAR_GP_PIN(5, 0),
1469 };
1470 static const unsigned int audio_clka_d_mux[] = {
1471         AUDIO_CLKA_D_MARK,
1472 };
1473 static const unsigned int audio_clkb_pins[] = {
1474         /* CLKB */
1475         RCAR_GP_PIN(5, 21),
1476 };
1477 static const unsigned int audio_clkb_mux[] = {
1478         AUDIO_CLKB_MARK,
1479 };
1480 static const unsigned int audio_clkb_b_pins[] = {
1481         /* CLKB */
1482         RCAR_GP_PIN(3, 26),
1483 };
1484 static const unsigned int audio_clkb_b_mux[] = {
1485         AUDIO_CLKB_B_MARK,
1486 };
1487 static const unsigned int audio_clkb_c_pins[] = {
1488         /* CLKB */
1489         RCAR_GP_PIN(4, 21),
1490 };
1491 static const unsigned int audio_clkb_c_mux[] = {
1492         AUDIO_CLKB_C_MARK,
1493 };
1494 static const unsigned int audio_clkc_pins[] = {
1495         /* CLKC */
1496         RCAR_GP_PIN(5, 22),
1497 };
1498 static const unsigned int audio_clkc_mux[] = {
1499         AUDIO_CLKC_MARK,
1500 };
1501 static const unsigned int audio_clkc_b_pins[] = {
1502         /* CLKC */
1503         RCAR_GP_PIN(3, 29),
1504 };
1505 static const unsigned int audio_clkc_b_mux[] = {
1506         AUDIO_CLKC_B_MARK,
1507 };
1508 static const unsigned int audio_clkc_c_pins[] = {
1509         /* CLKC */
1510         RCAR_GP_PIN(4, 22),
1511 };
1512 static const unsigned int audio_clkc_c_mux[] = {
1513         AUDIO_CLKC_C_MARK,
1514 };
1515 static const unsigned int audio_clkout_pins[] = {
1516         /* CLKOUT */
1517         RCAR_GP_PIN(5, 23),
1518 };
1519 static const unsigned int audio_clkout_mux[] = {
1520         AUDIO_CLKOUT_MARK,
1521 };
1522 static const unsigned int audio_clkout_b_pins[] = {
1523         /* CLKOUT */
1524         RCAR_GP_PIN(3, 12),
1525 };
1526 static const unsigned int audio_clkout_b_mux[] = {
1527         AUDIO_CLKOUT_B_MARK,
1528 };
1529 static const unsigned int audio_clkout_c_pins[] = {
1530         /* CLKOUT */
1531         RCAR_GP_PIN(4, 23),
1532 };
1533 static const unsigned int audio_clkout_c_mux[] = {
1534         AUDIO_CLKOUT_C_MARK,
1535 };
1536 /* - AVB -------------------------------------------------------------------- */
1537 static const unsigned int avb_link_pins[] = {
1538         RCAR_GP_PIN(3, 26),
1539 };
1540 static const unsigned int avb_link_mux[] = {
1541         AVB_LINK_MARK,
1542 };
1543 static const unsigned int avb_magic_pins[] = {
1544         RCAR_GP_PIN(3, 27),
1545 };
1546 static const unsigned int avb_magic_mux[] = {
1547         AVB_MAGIC_MARK,
1548 };
1549 static const unsigned int avb_phy_int_pins[] = {
1550         RCAR_GP_PIN(3, 28),
1551 };
1552 static const unsigned int avb_phy_int_mux[] = {
1553         AVB_PHY_INT_MARK,
1554 };
1555 static const unsigned int avb_mdio_pins[] = {
1556         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
1557 };
1558 static const unsigned int avb_mdio_mux[] = {
1559         AVB_MDC_MARK, AVB_MDIO_MARK,
1560 };
1561 static const unsigned int avb_mii_pins[] = {
1562         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1563         RCAR_GP_PIN(3, 17),
1564
1565         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1566         RCAR_GP_PIN(3, 5),
1567
1568         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
1569         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22),
1570         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 11),
1571 };
1572 static const unsigned int avb_mii_mux[] = {
1573         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1574         AVB_TXD3_MARK,
1575
1576         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1577         AVB_RXD3_MARK,
1578
1579         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1580         AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1581         AVB_TX_CLK_MARK, AVB_COL_MARK,
1582 };
1583 static const unsigned int avb_gmii_pins[] = {
1584         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1585         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
1586         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
1587
1588         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1589         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1590         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1591
1592         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
1593         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 30),
1594         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 13),
1595         RCAR_GP_PIN(3, 11),
1596 };
1597 static const unsigned int avb_gmii_mux[] = {
1598         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1599         AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1600         AVB_TXD6_MARK, AVB_TXD7_MARK,
1601
1602         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1603         AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1604         AVB_RXD6_MARK, AVB_RXD7_MARK,
1605
1606         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1607         AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1608         AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1609         AVB_COL_MARK,
1610 };
1611 /* - DU --------------------------------------------------------------------- */
1612 static const unsigned int du0_rgb666_pins[] = {
1613         /* R[7:2], G[7:2], B[7:2] */
1614         RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 5),
1615         RCAR_GP_PIN(2, 4),  RCAR_GP_PIN(2, 3),  RCAR_GP_PIN(2, 2),
1616         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1617         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1618         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1619         RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
1620 };
1621 static const unsigned int du0_rgb666_mux[] = {
1622         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1623         DU0_DR3_MARK, DU0_DR2_MARK,
1624         DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1625         DU0_DG3_MARK, DU0_DG2_MARK,
1626         DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1627         DU0_DB3_MARK, DU0_DB2_MARK,
1628 };
1629 static const unsigned int du0_rgb888_pins[] = {
1630         /* R[7:0], G[7:0], B[7:0] */
1631         RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 5),
1632         RCAR_GP_PIN(2, 4),  RCAR_GP_PIN(2, 3),  RCAR_GP_PIN(2, 2),
1633         RCAR_GP_PIN(2, 1),  RCAR_GP_PIN(2, 0),
1634         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1635         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1636         RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 8),
1637         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1638         RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
1639         RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
1640 };
1641 static const unsigned int du0_rgb888_mux[] = {
1642         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1643         DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
1644         DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1645         DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
1646         DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1647         DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
1648 };
1649 static const unsigned int du0_clk0_out_pins[] = {
1650         /* DOTCLKOUT0 */
1651         RCAR_GP_PIN(2, 25),
1652 };
1653 static const unsigned int du0_clk0_out_mux[] = {
1654         DU0_DOTCLKOUT0_MARK
1655 };
1656 static const unsigned int du0_clk1_out_pins[] = {
1657         /* DOTCLKOUT1 */
1658         RCAR_GP_PIN(2, 26),
1659 };
1660 static const unsigned int du0_clk1_out_mux[] = {
1661         DU0_DOTCLKOUT1_MARK
1662 };
1663 static const unsigned int du0_clk_in_pins[] = {
1664         /* CLKIN */
1665         RCAR_GP_PIN(2, 24),
1666 };
1667 static const unsigned int du0_clk_in_mux[] = {
1668         DU0_DOTCLKIN_MARK
1669 };
1670 static const unsigned int du0_sync_pins[] = {
1671         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1672         RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27),
1673 };
1674 static const unsigned int du0_sync_mux[] = {
1675         DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK
1676 };
1677 static const unsigned int du0_oddf_pins[] = {
1678         /* EXODDF/ODDF/DISP/CDE */
1679         RCAR_GP_PIN(2, 29),
1680 };
1681 static const unsigned int du0_oddf_mux[] = {
1682         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
1683 };
1684 static const unsigned int du0_cde_pins[] = {
1685         /* CDE */
1686         RCAR_GP_PIN(2, 31),
1687 };
1688 static const unsigned int du0_cde_mux[] = {
1689         DU0_CDE_MARK,
1690 };
1691 static const unsigned int du0_disp_pins[] = {
1692         /* DISP */
1693         RCAR_GP_PIN(2, 30),
1694 };
1695 static const unsigned int du0_disp_mux[] = {
1696         DU0_DISP_MARK
1697 };
1698 static const unsigned int du1_rgb666_pins[] = {
1699         /* R[7:2], G[7:2], B[7:2] */
1700         RCAR_GP_PIN(4, 7),  RCAR_GP_PIN(4, 6),  RCAR_GP_PIN(4, 5),
1701         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 3),  RCAR_GP_PIN(4, 2),
1702         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
1703         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1704         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
1705         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1706 };
1707 static const unsigned int du1_rgb666_mux[] = {
1708         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1709         DU1_DR3_MARK, DU1_DR2_MARK,
1710         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1711         DU1_DG3_MARK, DU1_DG2_MARK,
1712         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1713         DU1_DB3_MARK, DU1_DB2_MARK,
1714 };
1715 static const unsigned int du1_rgb888_pins[] = {
1716         /* R[7:0], G[7:0], B[7:0] */
1717         RCAR_GP_PIN(4, 7),  RCAR_GP_PIN(4, 6),  RCAR_GP_PIN(4, 5),
1718         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 3),  RCAR_GP_PIN(4, 2),
1719         RCAR_GP_PIN(4, 1),  RCAR_GP_PIN(4, 0),
1720         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
1721         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1722         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 8),
1723         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
1724         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1725         RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1726 };
1727 static const unsigned int du1_rgb888_mux[] = {
1728         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1729         DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1730         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1731         DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1732         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1733         DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1734 };
1735 static const unsigned int du1_clk0_out_pins[] = {
1736         /* DOTCLKOUT0 */
1737         RCAR_GP_PIN(4, 25),
1738 };
1739 static const unsigned int du1_clk0_out_mux[] = {
1740         DU1_DOTCLKOUT0_MARK
1741 };
1742 static const unsigned int du1_clk1_out_pins[] = {
1743         /* DOTCLKOUT1 */
1744         RCAR_GP_PIN(4, 26),
1745 };
1746 static const unsigned int du1_clk1_out_mux[] = {
1747         DU1_DOTCLKOUT1_MARK
1748 };
1749 static const unsigned int du1_clk_in_pins[] = {
1750         /* DOTCLKIN */
1751         RCAR_GP_PIN(4, 24),
1752 };
1753 static const unsigned int du1_clk_in_mux[] = {
1754         DU1_DOTCLKIN_MARK
1755 };
1756 static const unsigned int du1_sync_pins[] = {
1757         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1758         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
1759 };
1760 static const unsigned int du1_sync_mux[] = {
1761         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1762 };
1763 static const unsigned int du1_oddf_pins[] = {
1764         /* EXODDF/ODDF/DISP/CDE */
1765         RCAR_GP_PIN(4, 29),
1766 };
1767 static const unsigned int du1_oddf_mux[] = {
1768         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1769 };
1770 static const unsigned int du1_cde_pins[] = {
1771         /* CDE */
1772         RCAR_GP_PIN(4, 31),
1773 };
1774 static const unsigned int du1_cde_mux[] = {
1775         DU1_CDE_MARK
1776 };
1777 static const unsigned int du1_disp_pins[] = {
1778         /* DISP */
1779         RCAR_GP_PIN(4, 30),
1780 };
1781 static const unsigned int du1_disp_mux[] = {
1782         DU1_DISP_MARK
1783 };
1784 /* - ETH -------------------------------------------------------------------- */
1785 static const unsigned int eth_link_pins[] = {
1786         /* LINK */
1787         RCAR_GP_PIN(3, 18),
1788 };
1789 static const unsigned int eth_link_mux[] = {
1790         ETH_LINK_MARK,
1791 };
1792 static const unsigned int eth_magic_pins[] = {
1793         /* MAGIC */
1794         RCAR_GP_PIN(3, 22),
1795 };
1796 static const unsigned int eth_magic_mux[] = {
1797         ETH_MAGIC_MARK,
1798 };
1799 static const unsigned int eth_mdio_pins[] = {
1800         /* MDC, MDIO */
1801         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13),
1802 };
1803 static const unsigned int eth_mdio_mux[] = {
1804         ETH_MDC_MARK, ETH_MDIO_MARK,
1805 };
1806 static const unsigned int eth_rmii_pins[] = {
1807         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1808         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15),
1809         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20),
1810         RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19),
1811 };
1812 static const unsigned int eth_rmii_mux[] = {
1813         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1814         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1815 };
1816 static const unsigned int eth_link_b_pins[] = {
1817         /* LINK */
1818         RCAR_GP_PIN(5, 15),
1819 };
1820 static const unsigned int eth_link_b_mux[] = {
1821         ETH_LINK_B_MARK,
1822 };
1823 static const unsigned int eth_magic_b_pins[] = {
1824         /* MAGIC */
1825         RCAR_GP_PIN(5, 19),
1826 };
1827 static const unsigned int eth_magic_b_mux[] = {
1828         ETH_MAGIC_B_MARK,
1829 };
1830 static const unsigned int eth_mdio_b_pins[] = {
1831         /* MDC, MDIO */
1832         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10),
1833 };
1834 static const unsigned int eth_mdio_b_mux[] = {
1835         ETH_MDC_B_MARK, ETH_MDIO_B_MARK,
1836 };
1837 static const unsigned int eth_rmii_b_pins[] = {
1838         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1839         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12),
1840         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17),
1841         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16),
1842 };
1843 static const unsigned int eth_rmii_b_mux[] = {
1844         ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK,
1845         ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK,
1846 };
1847 /* - HSCIF0 ----------------------------------------------------------------- */
1848 static const unsigned int hscif0_data_pins[] = {
1849         /* RX, TX */
1850         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1851 };
1852 static const unsigned int hscif0_data_mux[] = {
1853         HSCIF0_HRX_MARK, HSCIF0_HTX_MARK,
1854 };
1855 static const unsigned int hscif0_clk_pins[] = {
1856         /* SCK */
1857         RCAR_GP_PIN(3, 29),
1858 };
1859 static const unsigned int hscif0_clk_mux[] = {
1860         HSCIF0_HSCK_MARK,
1861 };
1862 static const unsigned int hscif0_ctrl_pins[] = {
1863         /* RTS, CTS */
1864         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1865 };
1866 static const unsigned int hscif0_ctrl_mux[] = {
1867         HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK,
1868 };
1869 static const unsigned int hscif0_data_b_pins[] = {
1870         /* RX, TX */
1871         RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31),
1872 };
1873 static const unsigned int hscif0_data_b_mux[] = {
1874         HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK,
1875 };
1876 static const unsigned int hscif0_clk_b_pins[] = {
1877         /* SCK */
1878         RCAR_GP_PIN(1, 0),
1879 };
1880 static const unsigned int hscif0_clk_b_mux[] = {
1881         HSCIF0_HSCK_B_MARK,
1882 };
1883 /* - HSCIF1 ----------------------------------------------------------------- */
1884 static const unsigned int hscif1_data_pins[] = {
1885         /* RX, TX */
1886         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1887 };
1888 static const unsigned int hscif1_data_mux[] = {
1889         HSCIF1_HRX_MARK, HSCIF1_HTX_MARK,
1890 };
1891 static const unsigned int hscif1_clk_pins[] = {
1892         /* SCK */
1893         RCAR_GP_PIN(4, 10),
1894 };
1895 static const unsigned int hscif1_clk_mux[] = {
1896         HSCIF1_HSCK_MARK,
1897 };
1898 static const unsigned int hscif1_ctrl_pins[] = {
1899         /* RTS, CTS */
1900         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
1901 };
1902 static const unsigned int hscif1_ctrl_mux[] = {
1903         HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK,
1904 };
1905 static const unsigned int hscif1_data_b_pins[] = {
1906         /* RX, TX */
1907         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1908 };
1909 static const unsigned int hscif1_data_b_mux[] = {
1910         HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK,
1911 };
1912 static const unsigned int hscif1_ctrl_b_pins[] = {
1913         /* RTS, CTS */
1914         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
1915 };
1916 static const unsigned int hscif1_ctrl_b_mux[] = {
1917         HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK,
1918 };
1919 /* - HSCIF2 ----------------------------------------------------------------- */
1920 static const unsigned int hscif2_data_pins[] = {
1921         /* RX, TX */
1922         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1923 };
1924 static const unsigned int hscif2_data_mux[] = {
1925         HSCIF2_HRX_MARK, HSCIF2_HTX_MARK,
1926 };
1927 static const unsigned int hscif2_clk_pins[] = {
1928         /* SCK */
1929         RCAR_GP_PIN(0, 10),
1930 };
1931 static const unsigned int hscif2_clk_mux[] = {
1932         HSCIF2_HSCK_MARK,
1933 };
1934 static const unsigned int hscif2_ctrl_pins[] = {
1935         /* RTS, CTS */
1936         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
1937 };
1938 static const unsigned int hscif2_ctrl_mux[] = {
1939         HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK,
1940 };
1941 /* - I2C0 ------------------------------------------------------------------- */
1942 static const unsigned int i2c0_pins[] = {
1943         /* SCL, SDA */
1944         RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
1945 };
1946 static const unsigned int i2c0_mux[] = {
1947         I2C0_SCL_MARK, I2C0_SDA_MARK,
1948 };
1949 static const unsigned int i2c0_b_pins[] = {
1950         /* SCL, SDA */
1951         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
1952 };
1953 static const unsigned int i2c0_b_mux[] = {
1954         I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
1955 };
1956 static const unsigned int i2c0_c_pins[] = {
1957         /* SCL, SDA */
1958         RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1959 };
1960 static const unsigned int i2c0_c_mux[] = {
1961         I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
1962 };
1963 static const unsigned int i2c0_d_pins[] = {
1964         /* SCL, SDA */
1965         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1966 };
1967 static const unsigned int i2c0_d_mux[] = {
1968         I2C0_SCL_D_MARK, I2C0_SDA_D_MARK,
1969 };
1970 static const unsigned int i2c0_e_pins[] = {
1971         /* SCL, SDA */
1972         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
1973 };
1974 static const unsigned int i2c0_e_mux[] = {
1975         I2C0_SCL_E_MARK, I2C0_SDA_E_MARK,
1976 };
1977 /* - I2C1 ------------------------------------------------------------------- */
1978 static const unsigned int i2c1_pins[] = {
1979         /* SCL, SDA */
1980         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1981 };
1982 static const unsigned int i2c1_mux[] = {
1983         I2C1_SCL_MARK, I2C1_SDA_MARK,
1984 };
1985 static const unsigned int i2c1_b_pins[] = {
1986         /* SCL, SDA */
1987         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1988 };
1989 static const unsigned int i2c1_b_mux[] = {
1990         I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
1991 };
1992 static const unsigned int i2c1_c_pins[] = {
1993         /* SCL, SDA */
1994         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1995 };
1996 static const unsigned int i2c1_c_mux[] = {
1997         I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
1998 };
1999 static const unsigned int i2c1_d_pins[] = {
2000         /* SCL, SDA */
2001         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2002 };
2003 static const unsigned int i2c1_d_mux[] = {
2004         I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
2005 };
2006 static const unsigned int i2c1_e_pins[] = {
2007         /* SCL, SDA */
2008         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
2009 };
2010 static const unsigned int i2c1_e_mux[] = {
2011         I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
2012 };
2013 /* - I2C2 ------------------------------------------------------------------- */
2014 static const unsigned int i2c2_pins[] = {
2015         /* SCL, SDA */
2016         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
2017 };
2018 static const unsigned int i2c2_mux[] = {
2019         I2C2_SCL_MARK, I2C2_SDA_MARK,
2020 };
2021 static const unsigned int i2c2_b_pins[] = {
2022         /* SCL, SDA */
2023         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2024 };
2025 static const unsigned int i2c2_b_mux[] = {
2026         I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2027 };
2028 static const unsigned int i2c2_c_pins[] = {
2029         /* SCL, SDA */
2030         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2031 };
2032 static const unsigned int i2c2_c_mux[] = {
2033         I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2034 };
2035 static const unsigned int i2c2_d_pins[] = {
2036         /* SCL, SDA */
2037         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2038 };
2039 static const unsigned int i2c2_d_mux[] = {
2040         I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2041 };
2042 static const unsigned int i2c2_e_pins[] = {
2043         /* SCL, SDA */
2044         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2045 };
2046 static const unsigned int i2c2_e_mux[] = {
2047         I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2048 };
2049 /* - I2C3 ------------------------------------------------------------------- */
2050 static const unsigned int i2c3_pins[] = {
2051         /* SCL, SDA */
2052         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
2053 };
2054 static const unsigned int i2c3_mux[] = {
2055         I2C3_SCL_MARK, I2C3_SDA_MARK,
2056 };
2057 static const unsigned int i2c3_b_pins[] = {
2058         /* SCL, SDA */
2059         RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2060 };
2061 static const unsigned int i2c3_b_mux[] = {
2062         I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
2063 };
2064 static const unsigned int i2c3_c_pins[] = {
2065         /* SCL, SDA */
2066         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2067 };
2068 static const unsigned int i2c3_c_mux[] = {
2069         I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
2070 };
2071 static const unsigned int i2c3_d_pins[] = {
2072         /* SCL, SDA */
2073         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2074 };
2075 static const unsigned int i2c3_d_mux[] = {
2076         I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
2077 };
2078 static const unsigned int i2c3_e_pins[] = {
2079         /* SCL, SDA */
2080         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2081 };
2082 static const unsigned int i2c3_e_mux[] = {
2083         I2C3_SCL_E_MARK, I2C3_SDA_E_MARK,
2084 };
2085 /* - I2C4 ------------------------------------------------------------------- */
2086 static const unsigned int i2c4_pins[] = {
2087         /* SCL, SDA */
2088         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
2089 };
2090 static const unsigned int i2c4_mux[] = {
2091         I2C4_SCL_MARK, I2C4_SDA_MARK,
2092 };
2093 static const unsigned int i2c4_b_pins[] = {
2094         /* SCL, SDA */
2095         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2096 };
2097 static const unsigned int i2c4_b_mux[] = {
2098         I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
2099 };
2100 static const unsigned int i2c4_c_pins[] = {
2101         /* SCL, SDA */
2102         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2103 };
2104 static const unsigned int i2c4_c_mux[] = {
2105         I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
2106 };
2107 static const unsigned int i2c4_d_pins[] = {
2108         /* SCL, SDA */
2109         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
2110 };
2111 static const unsigned int i2c4_d_mux[] = {
2112         I2C4_SCL_D_MARK, I2C4_SDA_D_MARK,
2113 };
2114 static const unsigned int i2c4_e_pins[] = {
2115         /* SCL, SDA */
2116         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2117 };
2118 static const unsigned int i2c4_e_mux[] = {
2119         I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
2120 };
2121 /* - INTC ------------------------------------------------------------------- */
2122 static const unsigned int intc_irq0_pins[] = {
2123         /* IRQ0 */
2124         RCAR_GP_PIN(4, 4),
2125 };
2126 static const unsigned int intc_irq0_mux[] = {
2127         IRQ0_MARK,
2128 };
2129 static const unsigned int intc_irq1_pins[] = {
2130         /* IRQ1 */
2131         RCAR_GP_PIN(4, 18),
2132 };
2133 static const unsigned int intc_irq1_mux[] = {
2134         IRQ1_MARK,
2135 };
2136 static const unsigned int intc_irq2_pins[] = {
2137         /* IRQ2 */
2138         RCAR_GP_PIN(4, 19),
2139 };
2140 static const unsigned int intc_irq2_mux[] = {
2141         IRQ2_MARK,
2142 };
2143 static const unsigned int intc_irq3_pins[] = {
2144         /* IRQ3 */
2145         RCAR_GP_PIN(0, 7),
2146 };
2147 static const unsigned int intc_irq3_mux[] = {
2148         IRQ3_MARK,
2149 };
2150 static const unsigned int intc_irq4_pins[] = {
2151         /* IRQ4 */
2152         RCAR_GP_PIN(0, 0),
2153 };
2154 static const unsigned int intc_irq4_mux[] = {
2155         IRQ4_MARK,
2156 };
2157 static const unsigned int intc_irq5_pins[] = {
2158         /* IRQ5 */
2159         RCAR_GP_PIN(4, 1),
2160 };
2161 static const unsigned int intc_irq5_mux[] = {
2162         IRQ5_MARK,
2163 };
2164 static const unsigned int intc_irq6_pins[] = {
2165         /* IRQ6 */
2166         RCAR_GP_PIN(0, 10),
2167 };
2168 static const unsigned int intc_irq6_mux[] = {
2169         IRQ6_MARK,
2170 };
2171 static const unsigned int intc_irq7_pins[] = {
2172         /* IRQ7 */
2173         RCAR_GP_PIN(6, 15),
2174 };
2175 static const unsigned int intc_irq7_mux[] = {
2176         IRQ7_MARK,
2177 };
2178 static const unsigned int intc_irq8_pins[] = {
2179         /* IRQ8 */
2180         RCAR_GP_PIN(5, 0),
2181 };
2182 static const unsigned int intc_irq8_mux[] = {
2183         IRQ8_MARK,
2184 };
2185 static const unsigned int intc_irq9_pins[] = {
2186         /* IRQ9 */
2187         RCAR_GP_PIN(5, 10),
2188 };
2189 static const unsigned int intc_irq9_mux[] = {
2190         IRQ9_MARK,
2191 };
2192 /* - MMCIF ------------------------------------------------------------------ */
2193 static const unsigned int mmc_data1_pins[] = {
2194         /* D[0] */
2195         RCAR_GP_PIN(6, 18),
2196 };
2197 static const unsigned int mmc_data1_mux[] = {
2198         MMC_D0_MARK,
2199 };
2200 static const unsigned int mmc_data4_pins[] = {
2201         /* D[0:3] */
2202         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2203         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2204 };
2205 static const unsigned int mmc_data4_mux[] = {
2206         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2207 };
2208 static const unsigned int mmc_data8_pins[] = {
2209         /* D[0:7] */
2210         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2211         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2212         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2213         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2214 };
2215 static const unsigned int mmc_data8_mux[] = {
2216         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2217         MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2218 };
2219 static const unsigned int mmc_ctrl_pins[] = {
2220         /* CLK, CMD */
2221         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2222 };
2223 static const unsigned int mmc_ctrl_mux[] = {
2224         MMC_CLK_MARK, MMC_CMD_MARK,
2225 };
2226 /* - MSIOF0 ----------------------------------------------------------------- */
2227 static const unsigned int msiof0_clk_pins[] = {
2228         /* SCK */
2229         RCAR_GP_PIN(4, 4),
2230 };
2231 static const unsigned int msiof0_clk_mux[] = {
2232         MSIOF0_SCK_MARK,
2233 };
2234 static const unsigned int msiof0_sync_pins[] = {
2235         /* SYNC */
2236         RCAR_GP_PIN(4, 5),
2237 };
2238 static const unsigned int msiof0_sync_mux[] = {
2239         MSIOF0_SYNC_MARK,
2240 };
2241 static const unsigned int msiof0_ss1_pins[] = {
2242         /* SS1 */
2243         RCAR_GP_PIN(4, 6),
2244 };
2245 static const unsigned int msiof0_ss1_mux[] = {
2246         MSIOF0_SS1_MARK,
2247 };
2248 static const unsigned int msiof0_ss2_pins[] = {
2249         /* SS2 */
2250         RCAR_GP_PIN(4, 7),
2251 };
2252 static const unsigned int msiof0_ss2_mux[] = {
2253         MSIOF0_SS2_MARK,
2254 };
2255 static const unsigned int msiof0_rx_pins[] = {
2256         /* RXD */
2257         RCAR_GP_PIN(4, 2),
2258 };
2259 static const unsigned int msiof0_rx_mux[] = {
2260         MSIOF0_RXD_MARK,
2261 };
2262 static const unsigned int msiof0_tx_pins[] = {
2263         /* TXD */
2264         RCAR_GP_PIN(4, 3),
2265 };
2266 static const unsigned int msiof0_tx_mux[] = {
2267         MSIOF0_TXD_MARK,
2268 };
2269 /* - MSIOF1 ----------------------------------------------------------------- */
2270 static const unsigned int msiof1_clk_pins[] = {
2271         /* SCK */
2272         RCAR_GP_PIN(0, 26),
2273 };
2274 static const unsigned int msiof1_clk_mux[] = {
2275         MSIOF1_SCK_MARK,
2276 };
2277 static const unsigned int msiof1_sync_pins[] = {
2278         /* SYNC */
2279         RCAR_GP_PIN(0, 27),
2280 };
2281 static const unsigned int msiof1_sync_mux[] = {
2282         MSIOF1_SYNC_MARK,
2283 };
2284 static const unsigned int msiof1_ss1_pins[] = {
2285         /* SS1 */
2286         RCAR_GP_PIN(0, 28),
2287 };
2288 static const unsigned int msiof1_ss1_mux[] = {
2289         MSIOF1_SS1_MARK,
2290 };
2291 static const unsigned int msiof1_ss2_pins[] = {
2292         /* SS2 */
2293         RCAR_GP_PIN(0, 29),
2294 };
2295 static const unsigned int msiof1_ss2_mux[] = {
2296         MSIOF1_SS2_MARK,
2297 };
2298 static const unsigned int msiof1_rx_pins[] = {
2299         /* RXD */
2300         RCAR_GP_PIN(0, 24),
2301 };
2302 static const unsigned int msiof1_rx_mux[] = {
2303         MSIOF1_RXD_MARK,
2304 };
2305 static const unsigned int msiof1_tx_pins[] = {
2306         /* TXD */
2307         RCAR_GP_PIN(0, 25),
2308 };
2309 static const unsigned int msiof1_tx_mux[] = {
2310         MSIOF1_TXD_MARK,
2311 };
2312 static const unsigned int msiof1_clk_b_pins[] = {
2313         /* SCK */
2314         RCAR_GP_PIN(5, 3),
2315 };
2316 static const unsigned int msiof1_clk_b_mux[] = {
2317         MSIOF1_SCK_B_MARK,
2318 };
2319 static const unsigned int msiof1_sync_b_pins[] = {
2320         /* SYNC */
2321         RCAR_GP_PIN(5, 4),
2322 };
2323 static const unsigned int msiof1_sync_b_mux[] = {
2324         MSIOF1_SYNC_B_MARK,
2325 };
2326 static const unsigned int msiof1_ss1_b_pins[] = {
2327         /* SS1 */
2328         RCAR_GP_PIN(5, 5),
2329 };
2330 static const unsigned int msiof1_ss1_b_mux[] = {
2331         MSIOF1_SS1_B_MARK,
2332 };
2333 static const unsigned int msiof1_ss2_b_pins[] = {
2334         /* SS2 */
2335         RCAR_GP_PIN(5, 6),
2336 };
2337 static const unsigned int msiof1_ss2_b_mux[] = {
2338         MSIOF1_SS2_B_MARK,
2339 };
2340 static const unsigned int msiof1_rx_b_pins[] = {
2341         /* RXD */
2342         RCAR_GP_PIN(5, 1),
2343 };
2344 static const unsigned int msiof1_rx_b_mux[] = {
2345         MSIOF1_RXD_B_MARK,
2346 };
2347 static const unsigned int msiof1_tx_b_pins[] = {
2348         /* TXD */
2349         RCAR_GP_PIN(5, 2),
2350 };
2351 static const unsigned int msiof1_tx_b_mux[] = {
2352         MSIOF1_TXD_B_MARK,
2353 };
2354 /* - MSIOF2 ----------------------------------------------------------------- */
2355 static const unsigned int msiof2_clk_pins[] = {
2356         /* SCK */
2357         RCAR_GP_PIN(1, 0),
2358 };
2359 static const unsigned int msiof2_clk_mux[] = {
2360         MSIOF2_SCK_MARK,
2361 };
2362 static const unsigned int msiof2_sync_pins[] = {
2363         /* SYNC */
2364         RCAR_GP_PIN(1, 1),
2365 };
2366 static const unsigned int msiof2_sync_mux[] = {
2367         MSIOF2_SYNC_MARK,
2368 };
2369 static const unsigned int msiof2_ss1_pins[] = {
2370         /* SS1 */
2371         RCAR_GP_PIN(1, 2),
2372 };
2373 static const unsigned int msiof2_ss1_mux[] = {
2374         MSIOF2_SS1_MARK,
2375 };
2376 static const unsigned int msiof2_ss2_pins[] = {
2377         /* SS2 */
2378         RCAR_GP_PIN(1, 3),
2379 };
2380 static const unsigned int msiof2_ss2_mux[] = {
2381         MSIOF2_SS2_MARK,
2382 };
2383 static const unsigned int msiof2_rx_pins[] = {
2384         /* RXD */
2385         RCAR_GP_PIN(0, 30),
2386 };
2387 static const unsigned int msiof2_rx_mux[] = {
2388         MSIOF2_RXD_MARK,
2389 };
2390 static const unsigned int msiof2_tx_pins[] = {
2391         /* TXD */
2392         RCAR_GP_PIN(0, 31),
2393 };
2394 static const unsigned int msiof2_tx_mux[] = {
2395         MSIOF2_TXD_MARK,
2396 };
2397 static const unsigned int msiof2_clk_b_pins[] = {
2398         /* SCK */
2399         RCAR_GP_PIN(3, 15),
2400 };
2401 static const unsigned int msiof2_clk_b_mux[] = {
2402         MSIOF2_SCK_B_MARK,
2403 };
2404 static const unsigned int msiof2_sync_b_pins[] = {
2405         /* SYNC */
2406         RCAR_GP_PIN(3, 16),
2407 };
2408 static const unsigned int msiof2_sync_b_mux[] = {
2409         MSIOF2_SYNC_B_MARK,
2410 };
2411 static const unsigned int msiof2_ss1_b_pins[] = {
2412         /* SS1 */
2413         RCAR_GP_PIN(3, 17),
2414 };
2415 static const unsigned int msiof2_ss1_b_mux[] = {
2416         MSIOF2_SS1_B_MARK,
2417 };
2418 static const unsigned int msiof2_ss2_b_pins[] = {
2419         /* SS2 */
2420         RCAR_GP_PIN(3, 18),
2421 };
2422 static const unsigned int msiof2_ss2_b_mux[] = {
2423         MSIOF2_SS2_B_MARK,
2424 };
2425 static const unsigned int msiof2_rx_b_pins[] = {
2426         /* RXD */
2427         RCAR_GP_PIN(3, 13),
2428 };
2429 static const unsigned int msiof2_rx_b_mux[] = {
2430         MSIOF2_RXD_B_MARK,
2431 };
2432 static const unsigned int msiof2_tx_b_pins[] = {
2433         /* TXD */
2434         RCAR_GP_PIN(3, 14),
2435 };
2436 static const unsigned int msiof2_tx_b_mux[] = {
2437         MSIOF2_TXD_B_MARK,
2438 };
2439 /* - QSPI ------------------------------------------------------------------- */
2440 static const unsigned int qspi_ctrl_pins[] = {
2441         /* SPCLK, SSL */
2442         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2443 };
2444 static const unsigned int qspi_ctrl_mux[] = {
2445         SPCLK_MARK, SSL_MARK,
2446 };
2447 static const unsigned int qspi_data2_pins[] = {
2448         /* MOSI_IO0, MISO_IO1 */
2449         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2450 };
2451 static const unsigned int qspi_data2_mux[] = {
2452         MOSI_IO0_MARK, MISO_IO1_MARK,
2453 };
2454 static const unsigned int qspi_data4_pins[] = {
2455         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2456         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2457         RCAR_GP_PIN(1, 8),
2458 };
2459 static const unsigned int qspi_data4_mux[] = {
2460         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2461 };
2462 /* - SCIF0 ------------------------------------------------------------------ */
2463 static const unsigned int scif0_data_pins[] = {
2464         /* RX, TX */
2465         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2466 };
2467 static const unsigned int scif0_data_mux[] = {
2468         SCIF0_RXD_MARK, SCIF0_TXD_MARK,
2469 };
2470 static const unsigned int scif0_data_b_pins[] = {
2471         /* RX, TX */
2472         RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
2473 };
2474 static const unsigned int scif0_data_b_mux[] = {
2475         SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK,
2476 };
2477 static const unsigned int scif0_data_c_pins[] = {
2478         /* RX, TX */
2479         RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2480 };
2481 static const unsigned int scif0_data_c_mux[] = {
2482         SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK,
2483 };
2484 static const unsigned int scif0_data_d_pins[] = {
2485         /* RX, TX */
2486         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2487 };
2488 static const unsigned int scif0_data_d_mux[] = {
2489         SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK,
2490 };
2491 /* - SCIF1 ------------------------------------------------------------------ */
2492 static const unsigned int scif1_data_pins[] = {
2493         /* RX, TX */
2494         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2495 };
2496 static const unsigned int scif1_data_mux[] = {
2497         SCIF1_RXD_MARK, SCIF1_TXD_MARK,
2498 };
2499 static const unsigned int scif1_clk_pins[] = {
2500         /* SCK */
2501         RCAR_GP_PIN(4, 13),
2502 };
2503 static const unsigned int scif1_clk_mux[] = {
2504         SCIF1_SCK_MARK,
2505 };
2506 static const unsigned int scif1_data_b_pins[] = {
2507         /* RX, TX */
2508         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
2509 };
2510 static const unsigned int scif1_data_b_mux[] = {
2511         SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK,
2512 };
2513 static const unsigned int scif1_clk_b_pins[] = {
2514         /* SCK */
2515         RCAR_GP_PIN(5, 10),
2516 };
2517 static const unsigned int scif1_clk_b_mux[] = {
2518         SCIF1_SCK_B_MARK,
2519 };
2520 static const unsigned int scif1_data_c_pins[] = {
2521         /* RX, TX */
2522         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2523 };
2524 static const unsigned int scif1_data_c_mux[] = {
2525         SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK,
2526 };
2527 static const unsigned int scif1_clk_c_pins[] = {
2528         /* SCK */
2529         RCAR_GP_PIN(0, 10),
2530 };
2531 static const unsigned int scif1_clk_c_mux[] = {
2532         SCIF1_SCK_C_MARK,
2533 };
2534 /* - SCIF2 ------------------------------------------------------------------ */
2535 static const unsigned int scif2_data_pins[] = {
2536         /* RX, TX */
2537         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2538 };
2539 static const unsigned int scif2_data_mux[] = {
2540         SCIF2_RXD_MARK, SCIF2_TXD_MARK,
2541 };
2542 static const unsigned int scif2_clk_pins[] = {
2543         /* SCK */
2544         RCAR_GP_PIN(4, 18),
2545 };
2546 static const unsigned int scif2_clk_mux[] = {
2547         SCIF2_SCK_MARK,
2548 };
2549 static const unsigned int scif2_data_b_pins[] = {
2550         /* RX, TX */
2551         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2552 };
2553 static const unsigned int scif2_data_b_mux[] = {
2554         SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK,
2555 };
2556 static const unsigned int scif2_clk_b_pins[] = {
2557         /* SCK */
2558         RCAR_GP_PIN(5, 17),
2559 };
2560 static const unsigned int scif2_clk_b_mux[] = {
2561         SCIF2_SCK_B_MARK,
2562 };
2563 static const unsigned int scif2_data_c_pins[] = {
2564         /* RX, TX */
2565         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2566 };
2567 static const unsigned int scif2_data_c_mux[] = {
2568         SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK,
2569 };
2570 static const unsigned int scif2_clk_c_pins[] = {
2571         /* SCK */
2572         RCAR_GP_PIN(3, 19),
2573 };
2574 static const unsigned int scif2_clk_c_mux[] = {
2575         SCIF2_SCK_C_MARK,
2576 };
2577 /* - SCIF3 ------------------------------------------------------------------ */
2578 static const unsigned int scif3_data_pins[] = {
2579         /* RX, TX */
2580         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
2581 };
2582 static const unsigned int scif3_data_mux[] = {
2583         SCIF3_RXD_MARK, SCIF3_TXD_MARK,
2584 };
2585 static const unsigned int scif3_clk_pins[] = {
2586         /* SCK */
2587         RCAR_GP_PIN(4, 19),
2588 };
2589 static const unsigned int scif3_clk_mux[] = {
2590         SCIF3_SCK_MARK,
2591 };
2592 static const unsigned int scif3_data_b_pins[] = {
2593         /* RX, TX */
2594         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2595 };
2596 static const unsigned int scif3_data_b_mux[] = {
2597         SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK,
2598 };
2599 static const unsigned int scif3_clk_b_pins[] = {
2600         /* SCK */
2601         RCAR_GP_PIN(3, 22),
2602 };
2603 static const unsigned int scif3_clk_b_mux[] = {
2604         SCIF3_SCK_B_MARK,
2605 };
2606 /* - SCIF4 ------------------------------------------------------------------ */
2607 static const unsigned int scif4_data_pins[] = {
2608         /* RX, TX */
2609         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2610 };
2611 static const unsigned int scif4_data_mux[] = {
2612         SCIF4_RXD_MARK, SCIF4_TXD_MARK,
2613 };
2614 static const unsigned int scif4_data_b_pins[] = {
2615         /* RX, TX */
2616         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2617 };
2618 static const unsigned int scif4_data_b_mux[] = {
2619         SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK,
2620 };
2621 static const unsigned int scif4_data_c_pins[] = {
2622         /* RX, TX */
2623         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
2624 };
2625 static const unsigned int scif4_data_c_mux[] = {
2626         SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK,
2627 };
2628 static const unsigned int scif4_data_d_pins[] = {
2629         /* RX, TX */
2630         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
2631 };
2632 static const unsigned int scif4_data_d_mux[] = {
2633         SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK,
2634 };
2635 static const unsigned int scif4_data_e_pins[] = {
2636         /* RX, TX */
2637         RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
2638 };
2639 static const unsigned int scif4_data_e_mux[] = {
2640         SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK,
2641 };
2642 /* - SCIF5 ------------------------------------------------------------------ */
2643 static const unsigned int scif5_data_pins[] = {
2644         /* RX, TX */
2645         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2646 };
2647 static const unsigned int scif5_data_mux[] = {
2648         SCIF5_RXD_MARK, SCIF5_TXD_MARK,
2649 };
2650 static const unsigned int scif5_data_b_pins[] = {
2651         /* RX, TX */
2652         RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2653 };
2654 static const unsigned int scif5_data_b_mux[] = {
2655         SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK,
2656 };
2657 static const unsigned int scif5_data_c_pins[] = {
2658         /* RX, TX */
2659         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11),
2660 };
2661 static const unsigned int scif5_data_c_mux[] = {
2662         SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK,
2663 };
2664 static const unsigned int scif5_data_d_pins[] = {
2665         /* RX, TX */
2666         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2667 };
2668 static const unsigned int scif5_data_d_mux[] = {
2669         SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK,
2670 };
2671 /* - SCIFA0 ----------------------------------------------------------------- */
2672 static const unsigned int scifa0_data_pins[] = {
2673         /* RXD, TXD */
2674         RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
2675 };
2676 static const unsigned int scifa0_data_mux[] = {
2677         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2678 };
2679 static const unsigned int scifa0_data_b_pins[] = {
2680         /* RXD, TXD */
2681         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2682 };
2683 static const unsigned int scifa0_data_b_mux[] = {
2684         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2685 };
2686 static const unsigned int scifa0_data_c_pins[] = {
2687         /* RXD, TXD */
2688         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2689 };
2690 static const unsigned int scifa0_data_c_mux[] = {
2691         SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK
2692 };
2693 static const unsigned int scifa0_data_d_pins[] = {
2694         /* RXD, TXD */
2695         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2696 };
2697 static const unsigned int scifa0_data_d_mux[] = {
2698         SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK
2699 };
2700 /* - SCIFA1 ----------------------------------------------------------------- */
2701 static const unsigned int scifa1_data_pins[] = {
2702         /* RXD, TXD */
2703         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2704 };
2705 static const unsigned int scifa1_data_mux[] = {
2706         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2707 };
2708 static const unsigned int scifa1_clk_pins[] = {
2709         /* SCK */
2710         RCAR_GP_PIN(0, 13),
2711 };
2712 static const unsigned int scifa1_clk_mux[] = {
2713         SCIFA1_SCK_MARK,
2714 };
2715 static const unsigned int scifa1_data_b_pins[] = {
2716         /* RXD, TXD */
2717         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2718 };
2719 static const unsigned int scifa1_data_b_mux[] = {
2720         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2721 };
2722 static const unsigned int scifa1_clk_b_pins[] = {
2723         /* SCK */
2724         RCAR_GP_PIN(4, 27),
2725 };
2726 static const unsigned int scifa1_clk_b_mux[] = {
2727         SCIFA1_SCK_B_MARK,
2728 };
2729 static const unsigned int scifa1_data_c_pins[] = {
2730         /* RXD, TXD */
2731         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2732 };
2733 static const unsigned int scifa1_data_c_mux[] = {
2734         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2735 };
2736 static const unsigned int scifa1_clk_c_pins[] = {
2737         /* SCK */
2738         RCAR_GP_PIN(5, 4),
2739 };
2740 static const unsigned int scifa1_clk_c_mux[] = {
2741         SCIFA1_SCK_C_MARK,
2742 };
2743 /* - SCIFA2 ----------------------------------------------------------------- */
2744 static const unsigned int scifa2_data_pins[] = {
2745         /* RXD, TXD */
2746         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2747 };
2748 static const unsigned int scifa2_data_mux[] = {
2749         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2750 };
2751 static const unsigned int scifa2_clk_pins[] = {
2752         /* SCK */
2753         RCAR_GP_PIN(1, 15),
2754 };
2755 static const unsigned int scifa2_clk_mux[] = {
2756         SCIFA2_SCK_MARK,
2757 };
2758 static const unsigned int scifa2_data_b_pins[] = {
2759         /* RXD, TXD */
2760         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0),
2761 };
2762 static const unsigned int scifa2_data_b_mux[] = {
2763         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2764 };
2765 static const unsigned int scifa2_clk_b_pins[] = {
2766         /* SCK */
2767         RCAR_GP_PIN(4, 30),
2768 };
2769 static const unsigned int scifa2_clk_b_mux[] = {
2770         SCIFA2_SCK_B_MARK,
2771 };
2772 /* - SCIFA3 ----------------------------------------------------------------- */
2773 static const unsigned int scifa3_data_pins[] = {
2774         /* RXD, TXD */
2775         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2776 };
2777 static const unsigned int scifa3_data_mux[] = {
2778         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2779 };
2780 static const unsigned int scifa3_clk_pins[] = {
2781         /* SCK */
2782         RCAR_GP_PIN(4, 24),
2783 };
2784 static const unsigned int scifa3_clk_mux[] = {
2785         SCIFA3_SCK_MARK,
2786 };
2787 static const unsigned int scifa3_data_b_pins[] = {
2788         /* RXD, TXD */
2789         RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
2790 };
2791 static const unsigned int scifa3_data_b_mux[] = {
2792         SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
2793 };
2794 static const unsigned int scifa3_clk_b_pins[] = {
2795         /* SCK */
2796         RCAR_GP_PIN(0, 0),
2797 };
2798 static const unsigned int scifa3_clk_b_mux[] = {
2799         SCIFA3_SCK_B_MARK,
2800 };
2801 /* - SCIFA4 ----------------------------------------------------------------- */
2802 static const unsigned int scifa4_data_pins[] = {
2803         /* RXD, TXD */
2804         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12),
2805 };
2806 static const unsigned int scifa4_data_mux[] = {
2807         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2808 };
2809 static const unsigned int scifa4_data_b_pins[] = {
2810         /* RXD, TXD */
2811         RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23),
2812 };
2813 static const unsigned int scifa4_data_b_mux[] = {
2814         SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
2815 };
2816 static const unsigned int scifa4_data_c_pins[] = {
2817         /* RXD, TXD */
2818         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
2819 };
2820 static const unsigned int scifa4_data_c_mux[] = {
2821         SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
2822 };
2823 static const unsigned int scifa4_data_d_pins[] = {
2824         /* RXD, TXD */
2825         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
2826 };
2827 static const unsigned int scifa4_data_d_mux[] = {
2828         SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK,
2829 };
2830 /* - SCIFA5 ----------------------------------------------------------------- */
2831 static const unsigned int scifa5_data_pins[] = {
2832         /* RXD, TXD */
2833         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
2834 };
2835 static const unsigned int scifa5_data_mux[] = {
2836         SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
2837 };
2838 static const unsigned int scifa5_data_b_pins[] = {
2839         /* RXD, TXD */
2840         RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29),
2841 };
2842 static const unsigned int scifa5_data_b_mux[] = {
2843         SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
2844 };
2845 static const unsigned int scifa5_data_c_pins[] = {
2846         /* RXD, TXD */
2847         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
2848 };
2849 static const unsigned int scifa5_data_c_mux[] = {
2850         SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
2851 };
2852 static const unsigned int scifa5_data_d_pins[] = {
2853         /* RXD, TXD */
2854         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2855 };
2856 static const unsigned int scifa5_data_d_mux[] = {
2857         SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK,
2858 };
2859 /* - SCIFB0 ----------------------------------------------------------------- */
2860 static const unsigned int scifb0_data_pins[] = {
2861         /* RXD, TXD */
2862         RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20),
2863 };
2864 static const unsigned int scifb0_data_mux[] = {
2865         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2866 };
2867 static const unsigned int scifb0_clk_pins[] = {
2868         /* SCK */
2869         RCAR_GP_PIN(0, 19),
2870 };
2871 static const unsigned int scifb0_clk_mux[] = {
2872         SCIFB0_SCK_MARK,
2873 };
2874 static const unsigned int scifb0_ctrl_pins[] = {
2875         /* RTS, CTS */
2876         RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22),
2877 };
2878 static const unsigned int scifb0_ctrl_mux[] = {
2879         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2880 };
2881 /* - SCIFB1 ----------------------------------------------------------------- */
2882 static const unsigned int scifb1_data_pins[] = {
2883         /* RXD, TXD */
2884         RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17),
2885 };
2886 static const unsigned int scifb1_data_mux[] = {
2887         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
2888 };
2889 static const unsigned int scifb1_clk_pins[] = {
2890         /* SCK */
2891         RCAR_GP_PIN(0, 16),
2892 };
2893 static const unsigned int scifb1_clk_mux[] = {
2894         SCIFB1_SCK_MARK,
2895 };
2896 /* - SCIFB2 ----------------------------------------------------------------- */
2897 static const unsigned int scifb2_data_pins[] = {
2898         /* RXD, TXD */
2899         RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
2900 };
2901 static const unsigned int scifb2_data_mux[] = {
2902         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
2903 };
2904 static const unsigned int scifb2_clk_pins[] = {
2905         /* SCK */
2906         RCAR_GP_PIN(1, 15),
2907 };
2908 static const unsigned int scifb2_clk_mux[] = {
2909         SCIFB2_SCK_MARK,
2910 };
2911 static const unsigned int scifb2_ctrl_pins[] = {
2912         /* RTS, CTS */
2913         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2914 };
2915 static const unsigned int scifb2_ctrl_mux[] = {
2916         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
2917 };
2918 /* - SCIF Clock ------------------------------------------------------------- */
2919 static const unsigned int scif_clk_pins[] = {
2920         /* SCIF_CLK */
2921         RCAR_GP_PIN(1, 23),
2922 };
2923 static const unsigned int scif_clk_mux[] = {
2924         SCIF_CLK_MARK,
2925 };
2926 static const unsigned int scif_clk_b_pins[] = {
2927         /* SCIF_CLK */
2928         RCAR_GP_PIN(3, 29),
2929 };
2930 static const unsigned int scif_clk_b_mux[] = {
2931         SCIF_CLK_B_MARK,
2932 };
2933 /* - SDHI0 ------------------------------------------------------------------ */
2934 static const unsigned int sdhi0_data1_pins[] = {
2935         /* D0 */
2936         RCAR_GP_PIN(6, 2),
2937 };
2938 static const unsigned int sdhi0_data1_mux[] = {
2939         SD0_DATA0_MARK,
2940 };
2941 static const unsigned int sdhi0_data4_pins[] = {
2942         /* D[0:3] */
2943         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
2944         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
2945 };
2946 static const unsigned int sdhi0_data4_mux[] = {
2947         SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
2948 };
2949 static const unsigned int sdhi0_ctrl_pins[] = {
2950         /* CLK, CMD */
2951         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
2952 };
2953 static const unsigned int sdhi0_ctrl_mux[] = {
2954         SD0_CLK_MARK, SD0_CMD_MARK,
2955 };
2956 static const unsigned int sdhi0_cd_pins[] = {
2957         /* CD */
2958         RCAR_GP_PIN(6, 6),
2959 };
2960 static const unsigned int sdhi0_cd_mux[] = {
2961         SD0_CD_MARK,
2962 };
2963 static const unsigned int sdhi0_wp_pins[] = {
2964         /* WP */
2965         RCAR_GP_PIN(6, 7),
2966 };
2967 static const unsigned int sdhi0_wp_mux[] = {
2968         SD0_WP_MARK,
2969 };
2970 /* - SDHI1 ------------------------------------------------------------------ */
2971 static const unsigned int sdhi1_data1_pins[] = {
2972         /* D0 */
2973         RCAR_GP_PIN(6, 10),
2974 };
2975 static const unsigned int sdhi1_data1_mux[] = {
2976         SD1_DATA0_MARK,
2977 };
2978 static const unsigned int sdhi1_data4_pins[] = {
2979         /* D[0:3] */
2980         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
2981         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
2982 };
2983 static const unsigned int sdhi1_data4_mux[] = {
2984         SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
2985 };
2986 static const unsigned int sdhi1_ctrl_pins[] = {
2987         /* CLK, CMD */
2988         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2989 };
2990 static const unsigned int sdhi1_ctrl_mux[] = {
2991         SD1_CLK_MARK, SD1_CMD_MARK,
2992 };
2993 static const unsigned int sdhi1_cd_pins[] = {
2994         /* CD */
2995         RCAR_GP_PIN(6, 14),
2996 };
2997 static const unsigned int sdhi1_cd_mux[] = {
2998         SD1_CD_MARK,
2999 };
3000 static const unsigned int sdhi1_wp_pins[] = {
3001         /* WP */
3002         RCAR_GP_PIN(6, 15),
3003 };
3004 static const unsigned int sdhi1_wp_mux[] = {
3005         SD1_WP_MARK,
3006 };
3007 /* - SDHI2 ------------------------------------------------------------------ */
3008 static const unsigned int sdhi2_data1_pins[] = {
3009         /* D0 */
3010         RCAR_GP_PIN(6, 18),
3011 };
3012 static const unsigned int sdhi2_data1_mux[] = {
3013         SD2_DATA0_MARK,
3014 };
3015 static const unsigned int sdhi2_data4_pins[] = {
3016         /* D[0:3] */
3017         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3018         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3019 };
3020 static const unsigned int sdhi2_data4_mux[] = {
3021         SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3022 };
3023 static const unsigned int sdhi2_ctrl_pins[] = {
3024         /* CLK, CMD */
3025         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3026 };
3027 static const unsigned int sdhi2_ctrl_mux[] = {
3028         SD2_CLK_MARK, SD2_CMD_MARK,
3029 };
3030 static const unsigned int sdhi2_cd_pins[] = {
3031         /* CD */
3032         RCAR_GP_PIN(6, 22),
3033 };
3034 static const unsigned int sdhi2_cd_mux[] = {
3035         SD2_CD_MARK,
3036 };
3037 static const unsigned int sdhi2_wp_pins[] = {
3038         /* WP */
3039         RCAR_GP_PIN(6, 23),
3040 };
3041 static const unsigned int sdhi2_wp_mux[] = {
3042         SD2_WP_MARK,
3043 };
3044 /* - SSI -------------------------------------------------------------------- */
3045 static const unsigned int ssi0_data_pins[] = {
3046         /* SDATA0 */
3047         RCAR_GP_PIN(5, 3),
3048 };
3049 static const unsigned int ssi0_data_mux[] = {
3050         SSI_SDATA0_MARK,
3051 };
3052 static const unsigned int ssi0129_ctrl_pins[] = {
3053         /* SCK0129, WS0129 */
3054         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3055 };
3056 static const unsigned int ssi0129_ctrl_mux[] = {
3057         SSI_SCK0129_MARK, SSI_WS0129_MARK,
3058 };
3059 static const unsigned int ssi1_data_pins[] = {
3060         /* SDATA1 */
3061         RCAR_GP_PIN(5, 13),
3062 };
3063 static const unsigned int ssi1_data_mux[] = {
3064         SSI_SDATA1_MARK,
3065 };
3066 static const unsigned int ssi1_ctrl_pins[] = {
3067         /* SCK1, WS1 */
3068         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
3069 };
3070 static const unsigned int ssi1_ctrl_mux[] = {
3071         SSI_SCK1_MARK, SSI_WS1_MARK,
3072 };
3073 static const unsigned int ssi1_data_b_pins[] = {
3074         /* SDATA1 */
3075         RCAR_GP_PIN(4, 13),
3076 };
3077 static const unsigned int ssi1_data_b_mux[] = {
3078         SSI_SDATA1_B_MARK,
3079 };
3080 static const unsigned int ssi1_ctrl_b_pins[] = {
3081         /* SCK1, WS1 */
3082         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3083 };
3084 static const unsigned int ssi1_ctrl_b_mux[] = {
3085         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3086 };
3087 static const unsigned int ssi2_data_pins[] = {
3088         /* SDATA2 */
3089         RCAR_GP_PIN(5, 16),
3090 };
3091 static const unsigned int ssi2_data_mux[] = {
3092         SSI_SDATA2_MARK,
3093 };
3094 static const unsigned int ssi2_ctrl_pins[] = {
3095         /* SCK2, WS2 */
3096         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3097 };
3098 static const unsigned int ssi2_ctrl_mux[] = {
3099         SSI_SCK2_MARK, SSI_WS2_MARK,
3100 };
3101 static const unsigned int ssi2_data_b_pins[] = {
3102         /* SDATA2 */
3103         RCAR_GP_PIN(4, 16),
3104 };
3105 static const unsigned int ssi2_data_b_mux[] = {
3106         SSI_SDATA2_B_MARK,
3107 };
3108 static const unsigned int ssi2_ctrl_b_pins[] = {
3109         /* SCK2, WS2 */
3110         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3111 };
3112 static const unsigned int ssi2_ctrl_b_mux[] = {
3113         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3114 };
3115 static const unsigned int ssi3_data_pins[] = {
3116         /* SDATA3 */
3117         RCAR_GP_PIN(5, 6),
3118 };
3119 static const unsigned int ssi3_data_mux[] = {
3120         SSI_SDATA3_MARK
3121 };
3122 static const unsigned int ssi34_ctrl_pins[] = {
3123         /* SCK34, WS34 */
3124         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
3125 };
3126 static const unsigned int ssi34_ctrl_mux[] = {
3127         SSI_SCK34_MARK, SSI_WS34_MARK,
3128 };
3129 static const unsigned int ssi4_data_pins[] = {
3130         /* SDATA4 */
3131         RCAR_GP_PIN(5, 9),
3132 };
3133 static const unsigned int ssi4_data_mux[] = {
3134         SSI_SDATA4_MARK,
3135 };
3136 static const unsigned int ssi4_ctrl_pins[] = {
3137         /* SCK4, WS4 */
3138         RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
3139 };
3140 static const unsigned int ssi4_ctrl_mux[] = {
3141         SSI_SCK4_MARK, SSI_WS4_MARK,
3142 };
3143 static const unsigned int ssi4_data_b_pins[] = {
3144         /* SDATA4 */
3145         RCAR_GP_PIN(4, 22),
3146 };
3147 static const unsigned int ssi4_data_b_mux[] = {
3148         SSI_SDATA4_B_MARK,
3149 };
3150 static const unsigned int ssi4_ctrl_b_pins[] = {
3151         /* SCK4, WS4 */
3152         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3153 };
3154 static const unsigned int ssi4_ctrl_b_mux[] = {
3155         SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
3156 };
3157 static const unsigned int ssi5_data_pins[] = {
3158         /* SDATA5 */
3159         RCAR_GP_PIN(4, 26),
3160 };
3161 static const unsigned int ssi5_data_mux[] = {
3162         SSI_SDATA5_MARK,
3163 };
3164 static const unsigned int ssi5_ctrl_pins[] = {
3165         /* SCK5, WS5 */
3166         RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
3167 };
3168 static const unsigned int ssi5_ctrl_mux[] = {
3169         SSI_SCK5_MARK, SSI_WS5_MARK,
3170 };
3171 static const unsigned int ssi5_data_b_pins[] = {
3172         /* SDATA5 */
3173         RCAR_GP_PIN(3, 21),
3174 };
3175 static const unsigned int ssi5_data_b_mux[] = {
3176         SSI_SDATA5_B_MARK,
3177 };
3178 static const unsigned int ssi5_ctrl_b_pins[] = {
3179         /* SCK5, WS5 */
3180         RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3181 };
3182 static const unsigned int ssi5_ctrl_b_mux[] = {
3183         SSI_SCK5_B_MARK, SSI_WS5_B_MARK,
3184 };
3185 static const unsigned int ssi6_data_pins[] = {
3186         /* SDATA6 */
3187         RCAR_GP_PIN(4, 29),
3188 };
3189 static const unsigned int ssi6_data_mux[] = {
3190         SSI_SDATA6_MARK,
3191 };
3192 static const unsigned int ssi6_ctrl_pins[] = {
3193         /* SCK6, WS6 */
3194         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
3195 };
3196 static const unsigned int ssi6_ctrl_mux[] = {
3197         SSI_SCK6_MARK, SSI_WS6_MARK,
3198 };
3199 static const unsigned int ssi6_data_b_pins[] = {
3200         /* SDATA6 */
3201         RCAR_GP_PIN(3, 24),
3202 };
3203 static const unsigned int ssi6_data_b_mux[] = {
3204         SSI_SDATA6_B_MARK,
3205 };
3206 static const unsigned int ssi6_ctrl_b_pins[] = {
3207         /* SCK6, WS6 */
3208         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
3209 };
3210 static const unsigned int ssi6_ctrl_b_mux[] = {
3211         SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3212 };
3213 static const unsigned int ssi7_data_pins[] = {
3214         /* SDATA7 */
3215         RCAR_GP_PIN(5, 0),
3216 };
3217 static const unsigned int ssi7_data_mux[] = {
3218         SSI_SDATA7_MARK,
3219 };
3220 static const unsigned int ssi78_ctrl_pins[] = {
3221         /* SCK78, WS78 */
3222         RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 31),
3223 };
3224 static const unsigned int ssi78_ctrl_mux[] = {
3225         SSI_SCK78_MARK, SSI_WS78_MARK,
3226 };
3227 static const unsigned int ssi7_data_b_pins[] = {
3228         /* SDATA7 */
3229         RCAR_GP_PIN(3, 27),
3230 };
3231 static const unsigned int ssi7_data_b_mux[] = {
3232         SSI_SDATA7_B_MARK,
3233 };
3234 static const unsigned int ssi78_ctrl_b_pins[] = {
3235         /* SCK78, WS78 */
3236         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3237 };
3238 static const unsigned int ssi78_ctrl_b_mux[] = {
3239         SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3240 };
3241 static const unsigned int ssi8_data_pins[] = {
3242         /* SDATA8 */
3243         RCAR_GP_PIN(5, 10),
3244 };
3245 static const unsigned int ssi8_data_mux[] = {
3246         SSI_SDATA8_MARK,
3247 };
3248 static const unsigned int ssi8_data_b_pins[] = {
3249         /* SDATA8 */
3250         RCAR_GP_PIN(3, 28),
3251 };
3252 static const unsigned int ssi8_data_b_mux[] = {
3253         SSI_SDATA8_B_MARK,
3254 };
3255 static const unsigned int ssi9_data_pins[] = {
3256         /* SDATA9 */
3257         RCAR_GP_PIN(5, 19),
3258 };
3259 static const unsigned int ssi9_data_mux[] = {
3260         SSI_SDATA9_MARK,
3261 };
3262 static const unsigned int ssi9_ctrl_pins[] = {
3263         /* SCK9, WS9 */
3264         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
3265 };
3266 static const unsigned int ssi9_ctrl_mux[] = {
3267         SSI_SCK9_MARK, SSI_WS9_MARK,
3268 };
3269 static const unsigned int ssi9_data_b_pins[] = {
3270         /* SDATA9 */
3271         RCAR_GP_PIN(4, 19),
3272 };
3273 static const unsigned int ssi9_data_b_mux[] = {
3274         SSI_SDATA9_B_MARK,
3275 };
3276 static const unsigned int ssi9_ctrl_b_pins[] = {
3277         /* SCK9, WS9 */
3278         RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3279 };
3280 static const unsigned int ssi9_ctrl_b_mux[] = {
3281         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3282 };
3283 /* - USB0 ------------------------------------------------------------------- */
3284 static const unsigned int usb0_pins[] = {
3285         RCAR_GP_PIN(5, 24), /* PWEN */
3286         RCAR_GP_PIN(5, 25), /* OVC */
3287 };
3288 static const unsigned int usb0_mux[] = {
3289         USB0_PWEN_MARK,
3290         USB0_OVC_MARK,
3291 };
3292 /* - USB1 ------------------------------------------------------------------- */
3293 static const unsigned int usb1_pins[] = {
3294         RCAR_GP_PIN(5, 26), /* PWEN */
3295         RCAR_GP_PIN(5, 27), /* OVC */
3296 };
3297 static const unsigned int usb1_mux[] = {
3298         USB1_PWEN_MARK,
3299         USB1_OVC_MARK,
3300 };
3301 /* - VIN0 ------------------------------------------------------------------- */
3302 static const union vin_data vin0_data_pins = {
3303         .data24 = {
3304                 /* B */
3305                 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
3306                 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
3307                 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3308                 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
3309                 /* G */
3310                 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
3311                 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
3312                 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
3313                 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3314                 /* R */
3315                 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
3316                 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
3317                 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3318                 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
3319         },
3320 };
3321 static const union vin_data vin0_data_mux = {
3322         .data24 = {
3323                 /* B */
3324                 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3325                 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3326                 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3327                 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3328                 /* G */
3329                 VI0_G0_MARK, VI0_G1_MARK,
3330                 VI0_G2_MARK, VI0_G3_MARK,
3331                 VI0_G4_MARK, VI0_G5_MARK,
3332                 VI0_G6_MARK, VI0_G7_MARK,
3333                 /* R */
3334                 VI0_R0_MARK, VI0_R1_MARK,
3335                 VI0_R2_MARK, VI0_R3_MARK,
3336                 VI0_R4_MARK, VI0_R5_MARK,
3337                 VI0_R6_MARK, VI0_R7_MARK,
3338         },
3339 };
3340 static const unsigned int vin0_data18_pins[] = {
3341         /* B */
3342         RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
3343         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3344         RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
3345         /* G */
3346         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
3347         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
3348         RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3349         /* R */
3350         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
3351         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3352         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
3353 };
3354 static const unsigned int vin0_data18_mux[] = {
3355         /* B */
3356         VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3357         VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3358         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3359         /* G */
3360         VI0_G2_MARK, VI0_G3_MARK,
3361         VI0_G4_MARK, VI0_G5_MARK,
3362         VI0_G6_MARK, VI0_G7_MARK,
3363         /* R */
3364         VI0_R2_MARK, VI0_R3_MARK,
3365         VI0_R4_MARK, VI0_R5_MARK,
3366         VI0_R6_MARK, VI0_R7_MARK,
3367 };
3368 static const unsigned int vin0_sync_pins[] = {
3369         RCAR_GP_PIN(3, 11), /* HSYNC */
3370         RCAR_GP_PIN(3, 12), /* VSYNC */
3371 };
3372 static const unsigned int vin0_sync_mux[] = {
3373         VI0_HSYNC_N_MARK,
3374         VI0_VSYNC_N_MARK,
3375 };
3376 static const unsigned int vin0_field_pins[] = {
3377         RCAR_GP_PIN(3, 10),
3378 };
3379 static const unsigned int vin0_field_mux[] = {
3380         VI0_FIELD_MARK,
3381 };
3382 static const unsigned int vin0_clkenb_pins[] = {
3383         RCAR_GP_PIN(3, 9),
3384 };
3385 static const unsigned int vin0_clkenb_mux[] = {
3386         VI0_CLKENB_MARK,
3387 };
3388 static const unsigned int vin0_clk_pins[] = {
3389         RCAR_GP_PIN(3, 0),
3390 };
3391 static const unsigned int vin0_clk_mux[] = {
3392         VI0_CLK_MARK,
3393 };
3394 /* - VIN1 ------------------------------------------------------------------- */
3395 static const union vin_data vin1_data_pins = {
3396         .data12 = {
3397                 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
3398                 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3399                 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
3400                 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3401                 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
3402                 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3403         },
3404 };
3405 static const union vin_data vin1_data_mux = {
3406         .data12 = {
3407                 VI1_DATA0_MARK, VI1_DATA1_MARK,
3408                 VI1_DATA2_MARK, VI1_DATA3_MARK,
3409                 VI1_DATA4_MARK, VI1_DATA5_MARK,
3410                 VI1_DATA6_MARK, VI1_DATA7_MARK,
3411                 VI1_DATA8_MARK, VI1_DATA9_MARK,
3412                 VI1_DATA10_MARK, VI1_DATA11_MARK,
3413         },
3414 };
3415 static const unsigned int vin1_sync_pins[] = {
3416         RCAR_GP_PIN(5, 22), /* HSYNC */
3417         RCAR_GP_PIN(5, 23), /* VSYNC */
3418 };
3419 static const unsigned int vin1_sync_mux[] = {
3420         VI1_HSYNC_N_MARK,
3421         VI1_VSYNC_N_MARK,
3422 };
3423 static const unsigned int vin1_field_pins[] = {
3424         RCAR_GP_PIN(5, 21),
3425 };
3426 static const unsigned int vin1_field_mux[] = {
3427         VI1_FIELD_MARK,
3428 };
3429 static const unsigned int vin1_clkenb_pins[] = {
3430         RCAR_GP_PIN(5, 20),
3431 };
3432 static const unsigned int vin1_clkenb_mux[] = {
3433         VI1_CLKENB_MARK,
3434 };
3435 static const unsigned int vin1_clk_pins[] = {
3436         RCAR_GP_PIN(5, 11),
3437 };
3438 static const unsigned int vin1_clk_mux[] = {
3439         VI1_CLK_MARK,
3440 };
3441
3442 static const struct sh_pfc_pin_group pinmux_groups[] = {
3443         SH_PFC_PIN_GROUP(audio_clka),
3444         SH_PFC_PIN_GROUP(audio_clka_b),
3445         SH_PFC_PIN_GROUP(audio_clka_c),
3446         SH_PFC_PIN_GROUP(audio_clka_d),
3447         SH_PFC_PIN_GROUP(audio_clkb),
3448         SH_PFC_PIN_GROUP(audio_clkb_b),
3449         SH_PFC_PIN_GROUP(audio_clkb_c),
3450         SH_PFC_PIN_GROUP(audio_clkc),
3451         SH_PFC_PIN_GROUP(audio_clkc_b),
3452         SH_PFC_PIN_GROUP(audio_clkc_c),
3453         SH_PFC_PIN_GROUP(audio_clkout),
3454         SH_PFC_PIN_GROUP(audio_clkout_b),
3455         SH_PFC_PIN_GROUP(audio_clkout_c),
3456         SH_PFC_PIN_GROUP(avb_link),
3457         SH_PFC_PIN_GROUP(avb_magic),
3458         SH_PFC_PIN_GROUP(avb_phy_int),
3459         SH_PFC_PIN_GROUP(avb_mdio),
3460         SH_PFC_PIN_GROUP(avb_mii),
3461         SH_PFC_PIN_GROUP(avb_gmii),
3462         SH_PFC_PIN_GROUP(du0_rgb666),
3463         SH_PFC_PIN_GROUP(du0_rgb888),
3464         SH_PFC_PIN_GROUP(du0_clk0_out),
3465         SH_PFC_PIN_GROUP(du0_clk1_out),
3466         SH_PFC_PIN_GROUP(du0_clk_in),
3467         SH_PFC_PIN_GROUP(du0_sync),
3468         SH_PFC_PIN_GROUP(du0_oddf),
3469         SH_PFC_PIN_GROUP(du0_cde),
3470         SH_PFC_PIN_GROUP(du0_disp),
3471         SH_PFC_PIN_GROUP(du1_rgb666),
3472         SH_PFC_PIN_GROUP(du1_rgb888),
3473         SH_PFC_PIN_GROUP(du1_clk0_out),
3474         SH_PFC_PIN_GROUP(du1_clk1_out),
3475         SH_PFC_PIN_GROUP(du1_clk_in),
3476         SH_PFC_PIN_GROUP(du1_sync),
3477         SH_PFC_PIN_GROUP(du1_oddf),
3478         SH_PFC_PIN_GROUP(du1_cde),
3479         SH_PFC_PIN_GROUP(du1_disp),
3480         SH_PFC_PIN_GROUP(eth_link),
3481         SH_PFC_PIN_GROUP(eth_magic),
3482         SH_PFC_PIN_GROUP(eth_mdio),
3483         SH_PFC_PIN_GROUP(eth_rmii),
3484         SH_PFC_PIN_GROUP(eth_link_b),
3485         SH_PFC_PIN_GROUP(eth_magic_b),
3486         SH_PFC_PIN_GROUP(eth_mdio_b),
3487         SH_PFC_PIN_GROUP(eth_rmii_b),
3488         SH_PFC_PIN_GROUP(hscif0_data),
3489         SH_PFC_PIN_GROUP(hscif0_clk),
3490         SH_PFC_PIN_GROUP(hscif0_ctrl),
3491         SH_PFC_PIN_GROUP(hscif0_data_b),
3492         SH_PFC_PIN_GROUP(hscif0_clk_b),
3493         SH_PFC_PIN_GROUP(hscif1_data),
3494         SH_PFC_PIN_GROUP(hscif1_clk),
3495         SH_PFC_PIN_GROUP(hscif1_ctrl),
3496         SH_PFC_PIN_GROUP(hscif1_data_b),
3497         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3498         SH_PFC_PIN_GROUP(hscif2_data),
3499         SH_PFC_PIN_GROUP(hscif2_clk),
3500         SH_PFC_PIN_GROUP(hscif2_ctrl),
3501         SH_PFC_PIN_GROUP(i2c0),
3502         SH_PFC_PIN_GROUP(i2c0_b),
3503         SH_PFC_PIN_GROUP(i2c0_c),
3504         SH_PFC_PIN_GROUP(i2c0_d),
3505         SH_PFC_PIN_GROUP(i2c0_e),
3506         SH_PFC_PIN_GROUP(i2c1),
3507         SH_PFC_PIN_GROUP(i2c1_b),
3508         SH_PFC_PIN_GROUP(i2c1_c),
3509         SH_PFC_PIN_GROUP(i2c1_d),
3510         SH_PFC_PIN_GROUP(i2c1_e),
3511         SH_PFC_PIN_GROUP(i2c2),
3512         SH_PFC_PIN_GROUP(i2c2_b),
3513         SH_PFC_PIN_GROUP(i2c2_c),
3514         SH_PFC_PIN_GROUP(i2c2_d),
3515         SH_PFC_PIN_GROUP(i2c2_e),
3516         SH_PFC_PIN_GROUP(i2c3),
3517         SH_PFC_PIN_GROUP(i2c3_b),
3518         SH_PFC_PIN_GROUP(i2c3_c),
3519         SH_PFC_PIN_GROUP(i2c3_d),
3520         SH_PFC_PIN_GROUP(i2c3_e),
3521         SH_PFC_PIN_GROUP(i2c4),
3522         SH_PFC_PIN_GROUP(i2c4_b),
3523         SH_PFC_PIN_GROUP(i2c4_c),
3524         SH_PFC_PIN_GROUP(i2c4_d),
3525         SH_PFC_PIN_GROUP(i2c4_e),
3526         SH_PFC_PIN_GROUP(intc_irq0),
3527         SH_PFC_PIN_GROUP(intc_irq1),
3528         SH_PFC_PIN_GROUP(intc_irq2),
3529         SH_PFC_PIN_GROUP(intc_irq3),
3530         SH_PFC_PIN_GROUP(intc_irq4),
3531         SH_PFC_PIN_GROUP(intc_irq5),
3532         SH_PFC_PIN_GROUP(intc_irq6),
3533         SH_PFC_PIN_GROUP(intc_irq7),
3534         SH_PFC_PIN_GROUP(intc_irq8),
3535         SH_PFC_PIN_GROUP(intc_irq9),
3536         SH_PFC_PIN_GROUP(mmc_data1),
3537         SH_PFC_PIN_GROUP(mmc_data4),
3538         SH_PFC_PIN_GROUP(mmc_data8),
3539         SH_PFC_PIN_GROUP(mmc_ctrl),
3540         SH_PFC_PIN_GROUP(msiof0_clk),
3541         SH_PFC_PIN_GROUP(msiof0_sync),
3542         SH_PFC_PIN_GROUP(msiof0_ss1),
3543         SH_PFC_PIN_GROUP(msiof0_ss2),
3544         SH_PFC_PIN_GROUP(msiof0_rx),
3545         SH_PFC_PIN_GROUP(msiof0_tx),
3546         SH_PFC_PIN_GROUP(msiof1_clk),
3547         SH_PFC_PIN_GROUP(msiof1_sync),
3548         SH_PFC_PIN_GROUP(msiof1_ss1),
3549         SH_PFC_PIN_GROUP(msiof1_ss2),
3550         SH_PFC_PIN_GROUP(msiof1_rx),
3551         SH_PFC_PIN_GROUP(msiof1_tx),
3552         SH_PFC_PIN_GROUP(msiof1_clk_b),
3553         SH_PFC_PIN_GROUP(msiof1_sync_b),
3554         SH_PFC_PIN_GROUP(msiof1_ss1_b),
3555         SH_PFC_PIN_GROUP(msiof1_ss2_b),
3556         SH_PFC_PIN_GROUP(msiof1_rx_b),
3557         SH_PFC_PIN_GROUP(msiof1_tx_b),
3558         SH_PFC_PIN_GROUP(msiof2_clk),
3559         SH_PFC_PIN_GROUP(msiof2_sync),
3560         SH_PFC_PIN_GROUP(msiof2_ss1),
3561         SH_PFC_PIN_GROUP(msiof2_ss2),
3562         SH_PFC_PIN_GROUP(msiof2_rx),
3563         SH_PFC_PIN_GROUP(msiof2_tx),
3564         SH_PFC_PIN_GROUP(msiof2_clk_b),
3565         SH_PFC_PIN_GROUP(msiof2_sync_b),
3566         SH_PFC_PIN_GROUP(msiof2_ss1_b),
3567         SH_PFC_PIN_GROUP(msiof2_ss2_b),
3568         SH_PFC_PIN_GROUP(msiof2_rx_b),
3569         SH_PFC_PIN_GROUP(msiof2_tx_b),
3570         SH_PFC_PIN_GROUP(qspi_ctrl),
3571         SH_PFC_PIN_GROUP(qspi_data2),
3572         SH_PFC_PIN_GROUP(qspi_data4),
3573         SH_PFC_PIN_GROUP(scif0_data),
3574         SH_PFC_PIN_GROUP(scif0_data_b),
3575         SH_PFC_PIN_GROUP(scif0_data_c),
3576         SH_PFC_PIN_GROUP(scif0_data_d),
3577         SH_PFC_PIN_GROUP(scif1_data),
3578         SH_PFC_PIN_GROUP(scif1_clk),
3579         SH_PFC_PIN_GROUP(scif1_data_b),
3580         SH_PFC_PIN_GROUP(scif1_clk_b),
3581         SH_PFC_PIN_GROUP(scif1_data_c),
3582         SH_PFC_PIN_GROUP(scif1_clk_c),
3583         SH_PFC_PIN_GROUP(scif2_data),
3584         SH_PFC_PIN_GROUP(scif2_clk),
3585         SH_PFC_PIN_GROUP(scif2_data_b),
3586         SH_PFC_PIN_GROUP(scif2_clk_b),
3587         SH_PFC_PIN_GROUP(scif2_data_c),
3588         SH_PFC_PIN_GROUP(scif2_clk_c),
3589         SH_PFC_PIN_GROUP(scif3_data),
3590         SH_PFC_PIN_GROUP(scif3_clk),
3591         SH_PFC_PIN_GROUP(scif3_data_b),
3592         SH_PFC_PIN_GROUP(scif3_clk_b),
3593         SH_PFC_PIN_GROUP(scif4_data),
3594         SH_PFC_PIN_GROUP(scif4_data_b),
3595         SH_PFC_PIN_GROUP(scif4_data_c),
3596         SH_PFC_PIN_GROUP(scif4_data_d),
3597         SH_PFC_PIN_GROUP(scif4_data_e),
3598         SH_PFC_PIN_GROUP(scif5_data),
3599         SH_PFC_PIN_GROUP(scif5_data_b),
3600         SH_PFC_PIN_GROUP(scif5_data_c),
3601         SH_PFC_PIN_GROUP(scif5_data_d),
3602         SH_PFC_PIN_GROUP(scifa0_data),
3603         SH_PFC_PIN_GROUP(scifa0_data_b),
3604         SH_PFC_PIN_GROUP(scifa0_data_c),
3605         SH_PFC_PIN_GROUP(scifa0_data_d),
3606         SH_PFC_PIN_GROUP(scifa1_data),
3607         SH_PFC_PIN_GROUP(scifa1_clk),
3608         SH_PFC_PIN_GROUP(scifa1_data_b),
3609         SH_PFC_PIN_GROUP(scifa1_clk_b),
3610         SH_PFC_PIN_GROUP(scifa1_data_c),
3611         SH_PFC_PIN_GROUP(scifa1_clk_c),
3612         SH_PFC_PIN_GROUP(scifa2_data),
3613         SH_PFC_PIN_GROUP(scifa2_clk),
3614         SH_PFC_PIN_GROUP(scifa2_data_b),
3615         SH_PFC_PIN_GROUP(scifa2_clk_b),
3616         SH_PFC_PIN_GROUP(scifa3_data),
3617         SH_PFC_PIN_GROUP(scifa3_clk),
3618         SH_PFC_PIN_GROUP(scifa3_data_b),
3619         SH_PFC_PIN_GROUP(scifa3_clk_b),
3620         SH_PFC_PIN_GROUP(scifa4_data),
3621         SH_PFC_PIN_GROUP(scifa4_data_b),
3622         SH_PFC_PIN_GROUP(scifa4_data_c),
3623         SH_PFC_PIN_GROUP(scifa4_data_d),
3624         SH_PFC_PIN_GROUP(scifa5_data),
3625         SH_PFC_PIN_GROUP(scifa5_data_b),
3626         SH_PFC_PIN_GROUP(scifa5_data_c),
3627         SH_PFC_PIN_GROUP(scifa5_data_d),
3628         SH_PFC_PIN_GROUP(scifb0_data),
3629         SH_PFC_PIN_GROUP(scifb0_clk),
3630         SH_PFC_PIN_GROUP(scifb0_ctrl),
3631         SH_PFC_PIN_GROUP(scifb1_data),
3632         SH_PFC_PIN_GROUP(scifb1_clk),
3633         SH_PFC_PIN_GROUP(scifb2_data),
3634         SH_PFC_PIN_GROUP(scifb2_clk),
3635         SH_PFC_PIN_GROUP(scifb2_ctrl),
3636         SH_PFC_PIN_GROUP(scif_clk),
3637         SH_PFC_PIN_GROUP(scif_clk_b),
3638         SH_PFC_PIN_GROUP(sdhi0_data1),
3639         SH_PFC_PIN_GROUP(sdhi0_data4),
3640         SH_PFC_PIN_GROUP(sdhi0_ctrl),
3641         SH_PFC_PIN_GROUP(sdhi0_cd),
3642         SH_PFC_PIN_GROUP(sdhi0_wp),
3643         SH_PFC_PIN_GROUP(sdhi1_data1),
3644         SH_PFC_PIN_GROUP(sdhi1_data4),
3645         SH_PFC_PIN_GROUP(sdhi1_ctrl),
3646         SH_PFC_PIN_GROUP(sdhi1_cd),
3647         SH_PFC_PIN_GROUP(sdhi1_wp),
3648         SH_PFC_PIN_GROUP(sdhi2_data1),
3649         SH_PFC_PIN_GROUP(sdhi2_data4),
3650         SH_PFC_PIN_GROUP(sdhi2_ctrl),
3651         SH_PFC_PIN_GROUP(sdhi2_cd),
3652         SH_PFC_PIN_GROUP(sdhi2_wp),
3653         SH_PFC_PIN_GROUP(ssi0_data),
3654         SH_PFC_PIN_GROUP(ssi0129_ctrl),
3655         SH_PFC_PIN_GROUP(ssi1_data),
3656         SH_PFC_PIN_GROUP(ssi1_ctrl),
3657         SH_PFC_PIN_GROUP(ssi1_data_b),
3658         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
3659         SH_PFC_PIN_GROUP(ssi2_data),
3660         SH_PFC_PIN_GROUP(ssi2_ctrl),
3661         SH_PFC_PIN_GROUP(ssi2_data_b),
3662         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
3663         SH_PFC_PIN_GROUP(ssi3_data),
3664         SH_PFC_PIN_GROUP(ssi34_ctrl),
3665         SH_PFC_PIN_GROUP(ssi4_data),
3666         SH_PFC_PIN_GROUP(ssi4_ctrl),
3667         SH_PFC_PIN_GROUP(ssi4_data_b),
3668         SH_PFC_PIN_GROUP(ssi4_ctrl_b),
3669         SH_PFC_PIN_GROUP(ssi5_data),
3670         SH_PFC_PIN_GROUP(ssi5_ctrl),
3671         SH_PFC_PIN_GROUP(ssi5_data_b),
3672         SH_PFC_PIN_GROUP(ssi5_ctrl_b),
3673         SH_PFC_PIN_GROUP(ssi6_data),
3674         SH_PFC_PIN_GROUP(ssi6_ctrl),
3675         SH_PFC_PIN_GROUP(ssi6_data_b),
3676         SH_PFC_PIN_GROUP(ssi6_ctrl_b),
3677         SH_PFC_PIN_GROUP(ssi7_data),
3678         SH_PFC_PIN_GROUP(ssi78_ctrl),
3679         SH_PFC_PIN_GROUP(ssi7_data_b),
3680         SH_PFC_PIN_GROUP(ssi78_ctrl_b),
3681         SH_PFC_PIN_GROUP(ssi8_data),
3682         SH_PFC_PIN_GROUP(ssi8_data_b),
3683         SH_PFC_PIN_GROUP(ssi9_data),
3684         SH_PFC_PIN_GROUP(ssi9_ctrl),
3685         SH_PFC_PIN_GROUP(ssi9_data_b),
3686         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
3687         SH_PFC_PIN_GROUP(usb0),
3688         SH_PFC_PIN_GROUP(usb1),
3689         VIN_DATA_PIN_GROUP(vin0_data, 24),
3690         VIN_DATA_PIN_GROUP(vin0_data, 20),
3691         SH_PFC_PIN_GROUP(vin0_data18),
3692         VIN_DATA_PIN_GROUP(vin0_data, 16),
3693         VIN_DATA_PIN_GROUP(vin0_data, 12),
3694         VIN_DATA_PIN_GROUP(vin0_data, 10),
3695         VIN_DATA_PIN_GROUP(vin0_data, 8),
3696         SH_PFC_PIN_GROUP(vin0_sync),
3697         SH_PFC_PIN_GROUP(vin0_field),
3698         SH_PFC_PIN_GROUP(vin0_clkenb),
3699         SH_PFC_PIN_GROUP(vin0_clk),
3700         VIN_DATA_PIN_GROUP(vin1_data, 12),
3701         VIN_DATA_PIN_GROUP(vin1_data, 10),
3702         VIN_DATA_PIN_GROUP(vin1_data, 8),
3703         SH_PFC_PIN_GROUP(vin1_sync),
3704         SH_PFC_PIN_GROUP(vin1_field),
3705         SH_PFC_PIN_GROUP(vin1_clkenb),
3706         SH_PFC_PIN_GROUP(vin1_clk),
3707 };
3708
3709 static const char * const audio_clk_groups[] = {
3710         "audio_clka",
3711         "audio_clka_b",
3712         "audio_clka_c",
3713         "audio_clka_d",
3714         "audio_clkb",
3715         "audio_clkb_b",
3716         "audio_clkb_c",
3717         "audio_clkc",
3718         "audio_clkc_b",
3719         "audio_clkc_c",
3720         "audio_clkout",
3721         "audio_clkout_b",
3722         "audio_clkout_c",
3723 };
3724
3725 static const char * const avb_groups[] = {
3726         "avb_link",
3727         "avb_magic",
3728         "avb_phy_int",
3729         "avb_mdio",
3730         "avb_mii",
3731         "avb_gmii",
3732 };
3733
3734 static const char * const du0_groups[] = {
3735         "du0_rgb666",
3736         "du0_rgb888",
3737         "du0_clk0_out",
3738         "du0_clk1_out",
3739         "du0_clk_in",
3740         "du0_sync",
3741         "du0_oddf",
3742         "du0_cde",
3743         "du0_disp",
3744 };
3745
3746 static const char * const du1_groups[] = {
3747         "du1_rgb666",
3748         "du1_rgb888",
3749         "du1_clk0_out",
3750         "du1_clk1_out",
3751         "du1_clk_in",
3752         "du1_sync",
3753         "du1_oddf",
3754         "du1_cde",
3755         "du1_disp",
3756 };
3757
3758 static const char * const eth_groups[] = {
3759         "eth_link",
3760         "eth_magic",
3761         "eth_mdio",
3762         "eth_rmii",
3763         "eth_link_b",
3764         "eth_magic_b",
3765         "eth_mdio_b",
3766         "eth_rmii_b",
3767 };
3768
3769 static const char * const hscif0_groups[] = {
3770         "hscif0_data",
3771         "hscif0_clk",
3772         "hscif0_ctrl",
3773         "hscif0_data_b",
3774         "hscif0_clk_b",
3775 };
3776
3777 static const char * const hscif1_groups[] = {
3778         "hscif1_data",
3779         "hscif1_clk",
3780         "hscif1_ctrl",
3781         "hscif1_data_b",
3782         "hscif1_ctrl_b",
3783 };
3784
3785 static const char * const hscif2_groups[] = {
3786         "hscif2_data",
3787         "hscif2_clk",
3788         "hscif2_ctrl",
3789 };
3790
3791 static const char * const i2c0_groups[] = {
3792         "i2c0",
3793         "i2c0_b",
3794         "i2c0_c",
3795         "i2c0_d",
3796         "i2c0_e",
3797 };
3798
3799 static const char * const i2c1_groups[] = {
3800         "i2c1",
3801         "i2c1_b",
3802         "i2c1_c",
3803         "i2c1_d",
3804         "i2c1_e",
3805 };
3806
3807 static const char * const i2c2_groups[] = {
3808         "i2c2",
3809         "i2c2_b",
3810         "i2c2_c",
3811         "i2c2_d",
3812         "i2c2_e",
3813 };
3814
3815 static const char * const i2c3_groups[] = {
3816         "i2c3",
3817         "i2c3_b",
3818         "i2c3_c",
3819         "i2c3_d",
3820         "i2c3_e",
3821 };
3822
3823 static const char * const i2c4_groups[] = {
3824         "i2c4",
3825         "i2c4_b",
3826         "i2c4_c",
3827         "i2c4_d",
3828         "i2c4_e",
3829 };
3830
3831 static const char * const intc_groups[] = {
3832         "intc_irq0",
3833         "intc_irq1",
3834         "intc_irq2",
3835         "intc_irq3",
3836         "intc_irq4",
3837         "intc_irq5",
3838         "intc_irq6",
3839         "intc_irq7",
3840         "intc_irq8",
3841         "intc_irq9",
3842 };
3843
3844 static const char * const mmc_groups[] = {
3845         "mmc_data1",
3846         "mmc_data4",
3847         "mmc_data8",
3848         "mmc_ctrl",
3849 };
3850
3851 static const char * const msiof0_groups[] = {
3852         "msiof0_clk",
3853         "msiof0_sync",
3854         "msiof0_ss1",
3855         "msiof0_ss2",
3856         "msiof0_rx",
3857         "msiof0_tx",
3858 };
3859
3860 static const char * const msiof1_groups[] = {
3861         "msiof1_clk",
3862         "msiof1_sync",
3863         "msiof1_ss1",
3864         "msiof1_ss2",
3865         "msiof1_rx",
3866         "msiof1_tx",
3867         "msiof1_clk_b",
3868         "msiof1_sync_b",
3869         "msiof1_ss1_b",
3870         "msiof1_ss2_b",
3871         "msiof1_rx_b",
3872         "msiof1_tx_b",
3873 };
3874
3875 static const char * const msiof2_groups[] = {
3876         "msiof2_clk",
3877         "msiof2_sync",
3878         "msiof2_ss1",
3879         "msiof2_ss2",
3880         "msiof2_rx",
3881         "msiof2_tx",
3882         "msiof2_clk_b",
3883         "msiof2_sync_b",
3884         "msiof2_ss1_b",
3885         "msiof2_ss2_b",
3886         "msiof2_rx_b",
3887         "msiof2_tx_b",
3888 };
3889
3890 static const char * const qspi_groups[] = {
3891         "qspi_ctrl",
3892         "qspi_data2",
3893         "qspi_data4",
3894 };
3895
3896 static const char * const scif0_groups[] = {
3897         "scif0_data",
3898         "scif0_data_b",
3899         "scif0_data_c",
3900         "scif0_data_d",
3901 };
3902
3903 static const char * const scif1_groups[] = {
3904         "scif1_data",
3905         "scif1_clk",
3906         "scif1_data_b",
3907         "scif1_clk_b",
3908         "scif1_data_c",
3909         "scif1_clk_c",
3910 };
3911
3912 static const char * const scif2_groups[] = {
3913         "scif2_data",
3914         "scif2_clk",
3915         "scif2_data_b",
3916         "scif2_clk_b",
3917         "scif2_data_c",
3918         "scif2_clk_c",
3919 };
3920
3921 static const char * const scif3_groups[] = {
3922         "scif3_data",
3923         "scif3_clk",
3924         "scif3_data_b",
3925         "scif3_clk_b",
3926 };
3927
3928 static const char * const scif4_groups[] = {
3929         "scif4_data",
3930         "scif4_data_b",
3931         "scif4_data_c",
3932         "scif4_data_d",
3933         "scif4_data_e",
3934 };
3935
3936 static const char * const scif5_groups[] = {
3937         "scif5_data",
3938         "scif5_data_b",
3939         "scif5_data_c",
3940         "scif5_data_d",
3941 };
3942
3943 static const char * const scifa0_groups[] = {
3944         "scifa0_data",
3945         "scifa0_data_b",
3946         "scifa0_data_c",
3947         "scifa0_data_d",
3948 };
3949
3950 static const char * const scifa1_groups[] = {
3951         "scifa1_data",
3952         "scifa1_clk",
3953         "scifa1_data_b",
3954         "scifa1_clk_b",
3955         "scifa1_data_c",
3956         "scifa1_clk_c",
3957 };
3958
3959 static const char * const scifa2_groups[] = {
3960         "scifa2_data",
3961         "scifa2_clk",
3962         "scifa2_data_b",
3963         "scifa2_clk_b",
3964 };
3965
3966 static const char * const scifa3_groups[] = {
3967         "scifa3_data",
3968         "scifa3_clk",
3969         "scifa3_data_b",
3970         "scifa3_clk_b",
3971 };
3972
3973 static const char * const scifa4_groups[] = {
3974         "scifa4_data",
3975         "scifa4_data_b",
3976         "scifa4_data_c",
3977         "scifa4_data_d",
3978 };
3979
3980 static const char * const scifa5_groups[] = {
3981         "scifa5_data",
3982         "scifa5_data_b",
3983         "scifa5_data_c",
3984         "scifa5_data_d",
3985 };
3986
3987 static const char * const scifb0_groups[] = {
3988         "scifb0_data",
3989         "scifb0_clk",
3990         "scifb0_ctrl",
3991 };
3992
3993 static const char * const scifb1_groups[] = {
3994         "scifb1_data",
3995         "scifb1_clk",
3996 };
3997
3998 static const char * const scifb2_groups[] = {
3999         "scifb2_data",
4000         "scifb2_clk",
4001         "scifb2_ctrl",
4002 };
4003
4004 static const char * const scif_clk_groups[] = {
4005         "scif_clk",
4006         "scif_clk_b",
4007 };
4008
4009 static const char * const sdhi0_groups[] = {
4010         "sdhi0_data1",
4011         "sdhi0_data4",
4012         "sdhi0_ctrl",
4013         "sdhi0_cd",
4014         "sdhi0_wp",
4015 };
4016
4017 static const char * const sdhi1_groups[] = {
4018         "sdhi1_data1",
4019         "sdhi1_data4",
4020         "sdhi1_ctrl",
4021         "sdhi1_cd",
4022         "sdhi1_wp",
4023 };
4024
4025 static const char * const sdhi2_groups[] = {
4026         "sdhi2_data1",
4027         "sdhi2_data4",
4028         "sdhi2_ctrl",
4029         "sdhi2_cd",
4030         "sdhi2_wp",
4031 };
4032
4033 static const char * const ssi_groups[] = {
4034         "ssi0_data",
4035         "ssi0129_ctrl",
4036         "ssi1_data",
4037         "ssi1_ctrl",
4038         "ssi1_data_b",
4039         "ssi1_ctrl_b",
4040         "ssi2_data",
4041         "ssi2_ctrl",
4042         "ssi2_data_b",
4043         "ssi2_ctrl_b",
4044         "ssi3_data",
4045         "ssi34_ctrl",
4046         "ssi4_data",
4047         "ssi4_ctrl",
4048         "ssi4_data_b",
4049         "ssi4_ctrl_b",
4050         "ssi5_data",
4051         "ssi5_ctrl",
4052         "ssi5_data_b",
4053         "ssi5_ctrl_b",
4054         "ssi6_data",
4055         "ssi6_ctrl",
4056         "ssi6_data_b",
4057         "ssi6_ctrl_b",
4058         "ssi7_data",
4059         "ssi78_ctrl",
4060         "ssi7_data_b",
4061         "ssi78_ctrl_b",
4062         "ssi8_data",
4063         "ssi8_data_b",
4064         "ssi9_data",
4065         "ssi9_ctrl",
4066         "ssi9_data_b",
4067         "ssi9_ctrl_b",
4068 };
4069
4070 static const char * const usb0_groups[] = {
4071         "usb0",
4072 };
4073
4074 static const char * const usb1_groups[] = {
4075         "usb1",
4076 };
4077
4078 static const char * const vin0_groups[] = {
4079         "vin0_data24",
4080         "vin0_data20",
4081         "vin0_data18",
4082         "vin0_data16",
4083         "vin0_data12",
4084         "vin0_data10",
4085         "vin0_data8",
4086         "vin0_sync",
4087         "vin0_field",
4088         "vin0_clkenb",
4089         "vin0_clk",
4090 };
4091
4092 static const char * const vin1_groups[] = {
4093         "vin1_data12",
4094         "vin1_data10",
4095         "vin1_data8",
4096         "vin1_sync",
4097         "vin1_field",
4098         "vin1_clkenb",
4099         "vin1_clk",
4100 };
4101
4102 static const struct sh_pfc_function pinmux_functions[] = {
4103         SH_PFC_FUNCTION(audio_clk),
4104         SH_PFC_FUNCTION(avb),
4105         SH_PFC_FUNCTION(du0),
4106         SH_PFC_FUNCTION(du1),
4107         SH_PFC_FUNCTION(eth),
4108         SH_PFC_FUNCTION(hscif0),
4109         SH_PFC_FUNCTION(hscif1),
4110         SH_PFC_FUNCTION(hscif2),
4111         SH_PFC_FUNCTION(i2c0),
4112         SH_PFC_FUNCTION(i2c1),
4113         SH_PFC_FUNCTION(i2c2),
4114         SH_PFC_FUNCTION(i2c3),
4115         SH_PFC_FUNCTION(i2c4),
4116         SH_PFC_FUNCTION(intc),
4117         SH_PFC_FUNCTION(mmc),
4118         SH_PFC_FUNCTION(msiof0),
4119         SH_PFC_FUNCTION(msiof1),
4120         SH_PFC_FUNCTION(msiof2),
4121         SH_PFC_FUNCTION(qspi),
4122         SH_PFC_FUNCTION(scif0),
4123         SH_PFC_FUNCTION(scif1),
4124         SH_PFC_FUNCTION(scif2),
4125         SH_PFC_FUNCTION(scif3),
4126         SH_PFC_FUNCTION(scif4),
4127         SH_PFC_FUNCTION(scif5),
4128         SH_PFC_FUNCTION(scifa0),
4129         SH_PFC_FUNCTION(scifa1),
4130         SH_PFC_FUNCTION(scifa2),
4131         SH_PFC_FUNCTION(scifa3),
4132         SH_PFC_FUNCTION(scifa4),
4133         SH_PFC_FUNCTION(scifa5),
4134         SH_PFC_FUNCTION(scifb0),
4135         SH_PFC_FUNCTION(scifb1),
4136         SH_PFC_FUNCTION(scifb2),
4137         SH_PFC_FUNCTION(scif_clk),
4138         SH_PFC_FUNCTION(sdhi0),
4139         SH_PFC_FUNCTION(sdhi1),
4140         SH_PFC_FUNCTION(sdhi2),
4141         SH_PFC_FUNCTION(ssi),
4142         SH_PFC_FUNCTION(usb0),
4143         SH_PFC_FUNCTION(usb1),
4144         SH_PFC_FUNCTION(vin0),
4145         SH_PFC_FUNCTION(vin1),
4146 };
4147
4148 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4149         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4150                 GP_0_31_FN, FN_IP2_17_16,
4151                 GP_0_30_FN, FN_IP2_15_14,
4152                 GP_0_29_FN, FN_IP2_13_12,
4153                 GP_0_28_FN, FN_IP2_11_10,
4154                 GP_0_27_FN, FN_IP2_9_8,
4155                 GP_0_26_FN, FN_IP2_7_6,
4156                 GP_0_25_FN, FN_IP2_5_4,
4157                 GP_0_24_FN, FN_IP2_3_2,
4158                 GP_0_23_FN, FN_IP2_1_0,
4159                 GP_0_22_FN, FN_IP1_31_30,
4160                 GP_0_21_FN, FN_IP1_29_28,
4161                 GP_0_20_FN, FN_IP1_27,
4162                 GP_0_19_FN, FN_IP1_26,
4163                 GP_0_18_FN, FN_A2,
4164                 GP_0_17_FN, FN_IP1_24,
4165                 GP_0_16_FN, FN_IP1_23_22,
4166                 GP_0_15_FN, FN_IP1_21_20,
4167                 GP_0_14_FN, FN_IP1_19_18,
4168                 GP_0_13_FN, FN_IP1_17_15,
4169                 GP_0_12_FN, FN_IP1_14_13,
4170                 GP_0_11_FN, FN_IP1_12_11,
4171                 GP_0_10_FN, FN_IP1_10_8,
4172                 GP_0_9_FN, FN_IP1_7_6,
4173                 GP_0_8_FN, FN_IP1_5_4,
4174                 GP_0_7_FN, FN_IP1_3_2,
4175                 GP_0_6_FN, FN_IP1_1_0,
4176                 GP_0_5_FN, FN_IP0_31_30,
4177                 GP_0_4_FN, FN_IP0_29_28,
4178                 GP_0_3_FN, FN_IP0_27_26,
4179                 GP_0_2_FN, FN_IP0_25,
4180                 GP_0_1_FN, FN_IP0_24,
4181                 GP_0_0_FN, FN_IP0_23_22, }
4182         },
4183         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
4184                 0, 0,
4185                 0, 0,
4186                 0, 0,
4187                 0, 0,
4188                 0, 0,
4189                 0, 0,
4190                 GP_1_25_FN, FN_DACK0,
4191                 GP_1_24_FN, FN_IP7_31,
4192                 GP_1_23_FN, FN_IP4_1_0,
4193                 GP_1_22_FN, FN_WE1_N,
4194                 GP_1_21_FN, FN_WE0_N,
4195                 GP_1_20_FN, FN_IP3_31,
4196                 GP_1_19_FN, FN_IP3_30,
4197                 GP_1_18_FN, FN_IP3_29_27,
4198                 GP_1_17_FN, FN_IP3_26_24,
4199                 GP_1_16_FN, FN_IP3_23_21,
4200                 GP_1_15_FN, FN_IP3_20_18,
4201                 GP_1_14_FN, FN_IP3_17_15,
4202                 GP_1_13_FN, FN_IP3_14_13,
4203                 GP_1_12_FN, FN_IP3_12,
4204                 GP_1_11_FN, FN_IP3_11,
4205                 GP_1_10_FN, FN_IP3_10,
4206                 GP_1_9_FN, FN_IP3_9_8,
4207                 GP_1_8_FN, FN_IP3_7_6,
4208                 GP_1_7_FN, FN_IP3_5_4,
4209                 GP_1_6_FN, FN_IP3_3_2,
4210                 GP_1_5_FN, FN_IP3_1_0,
4211                 GP_1_4_FN, FN_IP2_31_30,
4212                 GP_1_3_FN, FN_IP2_29_27,
4213                 GP_1_2_FN, FN_IP2_26_24,
4214                 GP_1_1_FN, FN_IP2_23_21,
4215                 GP_1_0_FN, FN_IP2_20_18, }
4216         },
4217         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
4218                 GP_2_31_FN, FN_IP6_7_6,
4219                 GP_2_30_FN, FN_IP6_5_4,
4220                 GP_2_29_FN, FN_IP6_3_2,
4221                 GP_2_28_FN, FN_IP6_1_0,
4222                 GP_2_27_FN, FN_IP5_31_30,
4223                 GP_2_26_FN, FN_IP5_29_28,
4224                 GP_2_25_FN, FN_IP5_27_26,
4225                 GP_2_24_FN, FN_IP5_25_24,
4226                 GP_2_23_FN, FN_IP5_23_22,
4227                 GP_2_22_FN, FN_IP5_21_20,
4228                 GP_2_21_FN, FN_IP5_19_18,
4229                 GP_2_20_FN, FN_IP5_17_16,
4230                 GP_2_19_FN, FN_IP5_15_14,
4231                 GP_2_18_FN, FN_IP5_13_12,
4232                 GP_2_17_FN, FN_IP5_11_9,
4233                 GP_2_16_FN, FN_IP5_8_6,
4234                 GP_2_15_FN, FN_IP5_5_4,
4235                 GP_2_14_FN, FN_IP5_3_2,
4236                 GP_2_13_FN, FN_IP5_1_0,
4237                 GP_2_12_FN, FN_IP4_31_30,
4238                 GP_2_11_FN, FN_IP4_29_28,
4239                 GP_2_10_FN, FN_IP4_27_26,
4240                 GP_2_9_FN, FN_IP4_25_23,
4241                 GP_2_8_FN, FN_IP4_22_20,
4242                 GP_2_7_FN, FN_IP4_19_18,
4243                 GP_2_6_FN, FN_IP4_17_16,
4244                 GP_2_5_FN, FN_IP4_15_14,
4245                 GP_2_4_FN, FN_IP4_13_12,
4246                 GP_2_3_FN, FN_IP4_11_10,
4247                 GP_2_2_FN, FN_IP4_9_8,
4248                 GP_2_1_FN, FN_IP4_7_5,
4249                 GP_2_0_FN, FN_IP4_4_2 }
4250         },
4251         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
4252                 GP_3_31_FN, FN_IP8_22_20,
4253                 GP_3_30_FN, FN_IP8_19_17,
4254                 GP_3_29_FN, FN_IP8_16_15,
4255                 GP_3_28_FN, FN_IP8_14_12,
4256                 GP_3_27_FN, FN_IP8_11_9,
4257                 GP_3_26_FN, FN_IP8_8_6,
4258                 GP_3_25_FN, FN_IP8_5_3,
4259                 GP_3_24_FN, FN_IP8_2_0,
4260                 GP_3_23_FN, FN_IP7_29_27,
4261                 GP_3_22_FN, FN_IP7_26_24,
4262                 GP_3_21_FN, FN_IP7_23_21,
4263                 GP_3_20_FN, FN_IP7_20_18,
4264                 GP_3_19_FN, FN_IP7_17_15,
4265                 GP_3_18_FN, FN_IP7_14_12,
4266                 GP_3_17_FN, FN_IP7_11_9,
4267                 GP_3_16_FN, FN_IP7_8_6,
4268                 GP_3_15_FN, FN_IP7_5_3,
4269                 GP_3_14_FN, FN_IP7_2_0,
4270                 GP_3_13_FN, FN_IP6_31_29,
4271                 GP_3_12_FN, FN_IP6_28_26,
4272                 GP_3_11_FN, FN_IP6_25_23,
4273                 GP_3_10_FN, FN_IP6_22_20,
4274                 GP_3_9_FN, FN_IP6_19_17,
4275                 GP_3_8_FN, FN_IP6_16,
4276                 GP_3_7_FN, FN_IP6_15,
4277                 GP_3_6_FN, FN_IP6_14,
4278                 GP_3_5_FN, FN_IP6_13,
4279                 GP_3_4_FN, FN_IP6_12,
4280                 GP_3_3_FN, FN_IP6_11,
4281                 GP_3_2_FN, FN_IP6_10,
4282                 GP_3_1_FN, FN_IP6_9,
4283                 GP_3_0_FN, FN_IP6_8 }
4284         },
4285         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
4286                 GP_4_31_FN, FN_IP11_17_16,
4287                 GP_4_30_FN, FN_IP11_15_14,
4288                 GP_4_29_FN, FN_IP11_13_11,
4289                 GP_4_28_FN, FN_IP11_10_8,
4290                 GP_4_27_FN, FN_IP11_7_6,
4291                 GP_4_26_FN, FN_IP11_5_3,
4292                 GP_4_25_FN, FN_IP11_2_0,
4293                 GP_4_24_FN, FN_IP10_31_30,
4294                 GP_4_23_FN, FN_IP10_29_27,
4295                 GP_4_22_FN, FN_IP10_26_24,
4296                 GP_4_21_FN, FN_IP10_23_21,
4297                 GP_4_20_FN, FN_IP10_20_18,
4298                 GP_4_19_FN, FN_IP10_17_15,
4299                 GP_4_18_FN, FN_IP10_14_12,
4300                 GP_4_17_FN, FN_IP10_11_9,
4301                 GP_4_16_FN, FN_IP10_8_6,
4302                 GP_4_15_FN, FN_IP10_5_3,
4303                 GP_4_14_FN, FN_IP10_2_0,
4304                 GP_4_13_FN, FN_IP9_30_28,
4305                 GP_4_12_FN, FN_IP9_27_25,
4306                 GP_4_11_FN, FN_IP9_24_22,
4307                 GP_4_10_FN, FN_IP9_21_19,
4308                 GP_4_9_FN, FN_IP9_18_17,
4309                 GP_4_8_FN, FN_IP9_16_15,
4310                 GP_4_7_FN, FN_IP9_14_12,
4311                 GP_4_6_FN, FN_IP9_11_9,
4312                 GP_4_5_FN, FN_IP9_8_6,
4313                 GP_4_4_FN, FN_IP9_5_3,
4314                 GP_4_3_FN, FN_IP9_2_0,
4315                 GP_4_2_FN, FN_IP8_31_29,
4316                 GP_4_1_FN, FN_IP8_28_26,
4317                 GP_4_0_FN, FN_IP8_25_23 }
4318         },
4319         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
4320                 0, 0,
4321                 0, 0,
4322                 0, 0,
4323                 0, 0,
4324                 GP_5_27_FN, FN_USB1_OVC,
4325                 GP_5_26_FN, FN_USB1_PWEN,
4326                 GP_5_25_FN, FN_USB0_OVC,
4327                 GP_5_24_FN, FN_USB0_PWEN,
4328                 GP_5_23_FN, FN_IP13_26_24,
4329                 GP_5_22_FN, FN_IP13_23_21,
4330                 GP_5_21_FN, FN_IP13_20_18,
4331                 GP_5_20_FN, FN_IP13_17_15,
4332                 GP_5_19_FN, FN_IP13_14_12,
4333                 GP_5_18_FN, FN_IP13_11_9,
4334                 GP_5_17_FN, FN_IP13_8_6,
4335                 GP_5_16_FN, FN_IP13_5_3,
4336                 GP_5_15_FN, FN_IP13_2_0,
4337                 GP_5_14_FN, FN_IP12_29_27,
4338                 GP_5_13_FN, FN_IP12_26_24,
4339                 GP_5_12_FN, FN_IP12_23_21,
4340                 GP_5_11_FN, FN_IP12_20_18,
4341                 GP_5_10_FN, FN_IP12_17_15,
4342                 GP_5_9_FN, FN_IP12_14_13,
4343                 GP_5_8_FN, FN_IP12_12_11,
4344                 GP_5_7_FN, FN_IP12_10_9,
4345                 GP_5_6_FN, FN_IP12_8_6,
4346                 GP_5_5_FN, FN_IP12_5_3,
4347                 GP_5_4_FN, FN_IP12_2_0,
4348                 GP_5_3_FN, FN_IP11_29_27,
4349                 GP_5_2_FN, FN_IP11_26_24,
4350                 GP_5_1_FN, FN_IP11_23_21,
4351                 GP_5_0_FN, FN_IP11_20_18 }
4352         },
4353         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
4354                 0, 0,
4355                 0, 0,
4356                 0, 0,
4357                 0, 0,
4358                 0, 0,
4359                 0, 0,
4360                 GP_6_25_FN, FN_IP0_21_20,
4361                 GP_6_24_FN, FN_IP0_19_18,
4362                 GP_6_23_FN, FN_IP0_17,
4363                 GP_6_22_FN, FN_IP0_16,
4364                 GP_6_21_FN, FN_IP0_15,
4365                 GP_6_20_FN, FN_IP0_14,
4366                 GP_6_19_FN, FN_IP0_13,
4367                 GP_6_18_FN, FN_IP0_12,
4368                 GP_6_17_FN, FN_IP0_11,
4369                 GP_6_16_FN, FN_IP0_10,
4370                 GP_6_15_FN, FN_IP0_9_8,
4371                 GP_6_14_FN, FN_IP0_0,
4372                 GP_6_13_FN, FN_SD1_DATA3,
4373                 GP_6_12_FN, FN_SD1_DATA2,
4374                 GP_6_11_FN, FN_SD1_DATA1,
4375                 GP_6_10_FN, FN_SD1_DATA0,
4376                 GP_6_9_FN, FN_SD1_CMD,
4377                 GP_6_8_FN, FN_SD1_CLK,
4378                 GP_6_7_FN, FN_SD0_WP,
4379                 GP_6_6_FN, FN_SD0_CD,
4380                 GP_6_5_FN, FN_SD0_DATA3,
4381                 GP_6_4_FN, FN_SD0_DATA2,
4382                 GP_6_3_FN, FN_SD0_DATA1,
4383                 GP_6_2_FN, FN_SD0_DATA0,
4384                 GP_6_1_FN, FN_SD0_CMD,
4385                 GP_6_0_FN, FN_SD0_CLK }
4386         },
4387         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4388                              2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
4389                              2, 1, 1, 1, 1, 1, 1, 1, 1) {
4390                 /* IP0_31_30 [2] */
4391                 FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
4392                 /* IP0_29_28 [2] */
4393                 FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
4394                 /* IP0_27_26 [2] */
4395                 FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
4396                 /* IP0_25 [1] */
4397                 FN_D2, FN_SCIFA3_TXD_B,
4398                 /* IP0_24 [1] */
4399                 FN_D1, FN_SCIFA3_RXD_B,
4400                 /* IP0_23_22 [2] */
4401                 FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
4402                 /* IP0_21_20 [2] */
4403                 FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
4404                 /* IP0_19_18 [2] */
4405                 FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
4406                 /* IP0_17 [1] */
4407                 FN_MMC_D5, FN_SD2_WP,
4408                 /* IP0_16 [1] */
4409                 FN_MMC_D4, FN_SD2_CD,
4410                 /* IP0_15 [1] */
4411                 FN_MMC_D3, FN_SD2_DATA3,
4412                 /* IP0_14 [1] */
4413                 FN_MMC_D2, FN_SD2_DATA2,
4414                 /* IP0_13 [1] */
4415                 FN_MMC_D1, FN_SD2_DATA1,
4416                 /* IP0_12 [1] */
4417                 FN_MMC_D0, FN_SD2_DATA0,
4418                 /* IP0_11 [1] */
4419                 FN_MMC_CMD, FN_SD2_CMD,
4420                 /* IP0_10 [1] */
4421                 FN_MMC_CLK, FN_SD2_CLK,
4422                 /* IP0_9_8 [2] */
4423                 FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
4424                 /* IP0_7 [1] */
4425                 0, 0,
4426                 /* IP0_6 [1] */
4427                 0, 0,
4428                 /* IP0_5 [1] */
4429                 0, 0,
4430                 /* IP0_4 [1] */
4431                 0, 0,
4432                 /* IP0_3 [1] */
4433                 0, 0,
4434                 /* IP0_2 [1] */
4435                 0, 0,
4436                 /* IP0_1 [1] */
4437                 0, 0,
4438                 /* IP0_0 [1] */
4439                 FN_SD1_CD, FN_CAN0_RX, }
4440         },
4441         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4442                              2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2,
4443                              2, 2) {
4444                 /* IP1_31_30 [2] */
4445                 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
4446                 /* IP1_29_28 [2] */
4447                 FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
4448                 /* IP1_27 [1] */
4449                 FN_A4, FN_SCIFB0_TXD,
4450                 /* IP1_26 [1] */
4451                 FN_A3, FN_SCIFB0_SCK,
4452                 /* IP1_25 [1] */
4453                 0, 0,
4454                 /* IP1_24 [1] */
4455                 FN_A1, FN_SCIFB1_TXD,
4456                 /* IP1_23_22 [2] */
4457                 FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0,
4458                 /* IP1_21_20 [2] */
4459                 FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, 0,
4460                 /* IP1_19_18 [2] */
4461                 FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 0,
4462                 /* IP1_17_15 [3] */
4463                 FN_D13, FN_SCIFA1_SCK, 0, FN_PWM2_C, FN_TCLK2_B,
4464                 0, 0, 0,
4465                 /* IP1_14_13 [2] */
4466                 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
4467                 /* IP1_12_11 [2] */
4468                 FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
4469                 /* IP1_10_8 [3] */
4470                 FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
4471                 0, 0, 0,
4472                 /* IP1_7_6 [2] */
4473                 FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0,
4474                 /* IP1_5_4 [2] */
4475                 FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0,
4476                 /* IP1_3_2 [2] */
4477                 FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
4478                 /* IP1_1_0 [2] */
4479                 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, }
4480         },
4481         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4482                              2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
4483                 /* IP2_31_30 [2] */
4484                 FN_A20, FN_SPCLK, 0, 0,
4485                 /* IP2_29_27 [3] */
4486                 FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
4487                 0, 0, 0, 0,
4488                 /* IP2_26_24 [3] */
4489                 FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
4490                 0, 0, 0, 0,
4491                 /* IP2_23_21 [3] */
4492                 FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
4493                 0, 0, 0, 0,
4494                 /* IP2_20_18 [3] */
4495                 FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN,
4496                 0, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
4497                 /* IP2_17_16 [2] */
4498                 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
4499                 /* IP2_15_14 [2] */
4500                 FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
4501                 /* IP2_13_12 [2] */
4502                 FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0,
4503                 /* IP2_11_10 [2] */
4504                 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0,
4505                 /* IP2_9_8 [2] */
4506                 FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B, 0,
4507                 /* IP2_7_6 [2] */
4508                 FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B, 0,
4509                 /* IP2_5_4 [2] */
4510                 FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0,
4511                 /* IP2_3_2 [2] */
4512                 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
4513                 /* IP2_1_0 [2] */
4514                 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, }
4515         },
4516         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4517                              1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) {
4518                 /* IP3_31 [1] */
4519                 FN_RD_WR_N, FN_ATAG1_N,
4520                 /* IP3_30 [1] */
4521                 FN_RD_N, FN_ATACS11_N,
4522                 /* IP3_29_27 [3] */
4523                 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
4524                 0, 0, 0,
4525                 /* IP3_26_24 [3] */
4526                 FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B,
4527                 0, FN_FMIN, FN_SCIFB2_RTS_N, 0,
4528                 /* IP3_23_21 [3] */
4529                 FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B,
4530                 0, FN_FMCLK, FN_SCIFB2_CTS_N, 0,
4531                 /* IP3_20_18 [3] */
4532                 FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
4533                 0, FN_BPFCLK, FN_SCIFB2_SCK, 0,
4534                 /* IP3_17_15 [3] */
4535                 FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B,
4536                 0, FN_TPUTO3, FN_SCIFB2_TXD, 0,
4537                 /* IP3_14_13 [2] */
4538                 FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
4539                 /* IP3_12 [1] */
4540                 FN_EX_CS0_N, FN_VI1_DATA10,
4541                 /* IP3_11 [1] */
4542                 FN_CS1_N_A26, FN_VI1_DATA9,
4543                 /* IP3_10 [1] */
4544                 FN_CS0_N, FN_VI1_DATA8,
4545                 /* IP3_9_8 [2] */
4546                 FN_A25, FN_SSL, FN_ATARD1_N, 0,
4547                 /* IP3_7_6 [2] */
4548                 FN_A24, FN_IO3, FN_EX_WAIT2, 0,
4549                 /* IP3_5_4 [2] */
4550                 FN_A23, FN_IO2, 0, FN_ATAWR1_N,
4551                 /* IP3_3_2 [2] */
4552                 FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N,
4553                 /* IP3_1_0 [2] */
4554                 FN_A21, FN_MOSI_IO0, 0, 0, }
4555         },
4556         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
4557                              2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) {
4558                 /* IP4_31_30 [2] */
4559                 FN_DU0_DG4, FN_LCDOUT12, 0, 0,
4560                 /* IP4_29_28 [2] */
4561                 FN_DU0_DG3, FN_LCDOUT11, 0, 0,
4562                 /* IP4_27_26 [2] */
4563                 FN_DU0_DG2, FN_LCDOUT10, 0, 0,
4564                 /* IP4_25_23 [3] */
4565                 FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
4566                 0, 0, 0, 0,
4567                 /* IP4_22_20 [3] */
4568                 FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
4569                 0, 0, 0, 0,
4570                 /* IP4_19_18 [2] */
4571                 FN_DU0_DR7, FN_LCDOUT23, 0, 0,
4572                 /* IP4_17_16 [2] */
4573                 FN_DU0_DR6, FN_LCDOUT22, 0, 0,
4574                 /* IP4_15_14 [2] */
4575                 FN_DU0_DR5, FN_LCDOUT21, 0, 0,
4576                 /* IP4_13_12 [2] */
4577                 FN_DU0_DR4, FN_LCDOUT20, 0, 0,
4578                 /* IP4_11_10 [2] */
4579                 FN_DU0_DR3, FN_LCDOUT19, 0, 0,
4580                 /* IP4_9_8 [2] */
4581                 FN_DU0_DR2, FN_LCDOUT18, 0, 0,
4582                 /* IP4_7_5 [3] */
4583                 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
4584                 0, 0, 0, 0,
4585                 /* IP4_4_2 [3] */
4586                 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
4587                 0, 0, 0, 0,
4588                 /* IP4_1_0 [2] */
4589                 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, }
4590         },
4591         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
4592                              2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) {
4593                 /* IP5_31_30 [2] */
4594                 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0,
4595                 /* IP5_29_28 [2] */
4596                 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, 0, 0,
4597                 /* IP5_27_26 [2] */
4598                 FN_DU0_DOTCLKOUT0, FN_QCLK, 0, 0,
4599                 /* IP5_25_24 [2] */
4600                 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 0, 0,
4601                 /* IP5_23_22 [2] */
4602                 FN_DU0_DB7, FN_LCDOUT7, 0, 0,
4603                 /* IP5_21_20 [2] */
4604                 FN_DU0_DB6, FN_LCDOUT6, 0, 0,
4605                 /* IP5_19_18 [2] */
4606                 FN_DU0_DB5, FN_LCDOUT5, 0, 0,
4607                 /* IP5_17_16 [2] */
4608                 FN_DU0_DB4, FN_LCDOUT4, 0, 0,
4609                 /* IP5_15_14 [2] */
4610                 FN_DU0_DB3, FN_LCDOUT3, 0, 0,
4611                 /* IP5_13_12 [2] */
4612                 FN_DU0_DB2, FN_LCDOUT2, 0, 0,
4613                 /* IP5_11_9 [3] */
4614                 FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
4615                 FN_CAN0_TX_C, 0, 0, 0,
4616                 /* IP5_8_6 [3] */
4617                 FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D,
4618                 FN_CAN0_RX_C, 0, 0, 0,
4619                 /* IP5_5_4 [2] */
4620                 FN_DU0_DG7, FN_LCDOUT15, 0, 0,
4621                 /* IP5_3_2 [2] */
4622                 FN_DU0_DG6, FN_LCDOUT14, 0, 0,
4623                 /* IP5_1_0 [2] */
4624                 FN_DU0_DG5, FN_LCDOUT13, 0, 0, }
4625         },
4626         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
4627                              3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
4628                              2, 2) {
4629                 /* IP6_31_29 [3] */
4630                 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D,
4631                 FN_AVB_TX_CLK, FN_ADIDATA, 0, 0,
4632                 /* IP6_28_26 [3] */
4633                 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
4634                 FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
4635                 /* IP6_25_23 [3] */
4636                 FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
4637                 FN_AVB_COL, 0, 0, 0,
4638                 /* IP6_22_20 [3] */
4639                 FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
4640                 FN_AVB_RX_ER, 0, 0, 0,
4641                 /* IP6_19_17 [3] */
4642                 FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
4643                 FN_AVB_RXD7, 0, 0, 0,
4644                 /* IP6_16 [1] */
4645                 FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
4646                 /* IP6_15 [1] */
4647                 FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
4648                 /* IP6_14 [1] */
4649                 FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
4650                 /* IP6_13 [1] */
4651                 FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
4652                 /* IP6_12 [1] */
4653                 FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
4654                 /* IP6_11 [1] */
4655                 FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
4656                 /* IP6_10 [1] */
4657                 FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
4658                 /* IP6_9 [1] */
4659                 FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
4660                 /* IP6_8 [1] */
4661                 FN_VI0_CLK, FN_AVB_RX_CLK,
4662                 /* IP6_7_6 [2] */
4663                 FN_DU0_CDE, FN_QPOLB, 0, 0,
4664                 /* IP6_5_4 [2] */
4665                 FN_DU0_DISP, FN_QPOLA, 0, 0,
4666                 /* IP6_3_2 [2] */
4667                 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0,
4668                 0,
4669                 /* IP6_1_0 [2] */
4670                 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, }
4671         },
4672         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
4673                              1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
4674                 /* IP7_31 [1] */
4675                 FN_DREQ0_N, FN_SCIFB1_RXD,
4676                 /* IP7_30 [1] */
4677                 0, 0,
4678                 /* IP7_29_27 [3] */
4679                 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
4680                 FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
4681                 /* IP7_26_24 [3] */
4682                 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
4683                 FN_SSI_SCK6_B, 0, 0, 0,
4684                 /* IP7_23_21 [3] */
4685                 FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D,
4686                 FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
4687                 /* IP7_20_18 [3] */
4688                 FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D,
4689                 FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
4690                 /* IP7_17_15 [3] */
4691                 FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
4692                 FN_SSI_SCK5_B, 0, 0, 0,
4693                 /* IP7_14_12 [3] */
4694                 FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
4695                 FN_AVB_TXD4, FN_ADICHS2, 0, 0,
4696                 /* IP7_11_9 [3] */
4697                 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
4698                 FN_AVB_TXD3, FN_ADICHS1, 0, 0,
4699                 /* IP7_8_6 [3] */
4700                 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
4701                 FN_AVB_TXD2, FN_ADICHS0, 0, 0,
4702                 /* IP7_5_3 [3] */
4703                 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
4704                 FN_AVB_TXD1, FN_ADICLK, 0, 0,
4705                 /* IP7_2_0 [3] */
4706                 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D,
4707                 FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, }
4708         },
4709         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
4710                              3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
4711                 /* IP8_31_29 [3] */
4712                 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
4713                 0, FN_TS_SDEN_D, FN_FMCLK_C, 0,
4714                 /* IP8_28_26 [3] */
4715                 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
4716                 0, FN_TS_SCK_D, FN_BPFCLK_C, 0,
4717                 /* IP8_25_23 [3] */
4718                 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
4719                 0, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
4720                 /* IP8_22_20 [3] */
4721                 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
4722                 FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
4723                 /* IP8_19_17 [3] */
4724                 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
4725                 FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
4726                 /* IP8_16_15 [2] */
4727                 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
4728                 /* IP8_14_12 [3] */
4729                 FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
4730                 FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
4731                 /* IP8_11_9 [3] */
4732                 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
4733                 FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
4734                 /* IP8_8_6 [3] */
4735                 FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
4736                 FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
4737                 /* IP8_5_3 [3] */
4738                 FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
4739                 FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
4740                 /* IP8_2_0 [3] */
4741                 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
4742                 FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
4743         },
4744         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
4745                              1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3, 3) {
4746                 /* IP9_31 [1] */
4747                 0, 0,
4748                 /* IP9_30_28 [3] */
4749                 FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
4750                 FN_SSI_SDATA1_B, 0, 0, 0,
4751                 /* IP9_27_25 [3] */
4752                 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4,
4753                 FN_SSI_WS1_B, 0, 0, 0,
4754                 /* IP9_24_22 [3] */
4755                 FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3,
4756                 FN_SSI_SCK1_B, 0, 0, 0,
4757                 /* IP9_21_19 [3] */
4758                 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2,
4759                 FN_REMOCON_B, FN_SPEEDIN_B, 0, 0,
4760                 /* IP9_18_17 [2] */
4761                 FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
4762                 /* IP9_16_15 [2] */
4763                 FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
4764                 /* IP9_14_12 [3] */
4765                 FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
4766                 0, FN_FMIN_B, 0, 0,
4767                 /* IP9_11_9 [3] */
4768                 FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6,
4769                 0, FN_FMCLK_B, 0, 0,
4770                 /* IP9_8_6 [3] */
4771                 FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5,
4772                 0, FN_BPFCLK_B, 0, 0,
4773                 /* IP9_5_3 [3] */
4774                 FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4,
4775                 0, FN_TPUTO1_C, 0, 0,
4776                 /* IP9_2_0 [3] */
4777                 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
4778                 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, }
4779         },
4780         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
4781                              2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
4782                 /* IP10_31_30 [2] */
4783                 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0,
4784                 /* IP10_29_27 [3] */
4785                 FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
4786                 0, 0, 0, 0,
4787                 /* IP10_26_24 [3] */
4788                 FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
4789                 FN_SSI_SDATA4_B, 0, 0, 0,
4790                 /* IP10_23_21 [3] */
4791                 FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5,
4792                 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0,
4793                 /* IP10_20_18 [3] */
4794                 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4,
4795                 FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, 0, 0,
4796                 /* IP10_17_15 [3] */
4797                 FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
4798                 FN_SSI_SDATA9_B, 0, 0, 0,
4799                 /* IP10_14_12 [3] */
4800                 FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
4801                 0, 0, 0, 0,
4802                 /* IP10_11_9 [3] */
4803                 FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
4804                 0, 0, 0, 0,
4805                 /* IP10_8_6 [3] */
4806                 FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
4807                 0, 0, 0, 0,
4808                 /* IP10_5_3 [3] */
4809                 FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
4810                 0, 0, 0, 0,
4811                 /* IP10_2_0 [3] */
4812                 FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
4813                 0, 0, 0, 0, }
4814         },
4815         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
4816                              2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
4817                 /* IP11_31_30 [2] */
4818                 0, 0, 0, 0,
4819                 /* IP11_29_27 [3] */
4820                 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
4821                 0, 0, 0, 0,
4822                 /* IP11_26_24 [3] */
4823                 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
4824                 0, 0, 0, 0,
4825                 /* IP11_23_21 [3] */
4826                 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
4827                 0, 0, 0, 0,
4828                 /* IP11_20_18 [3] */
4829                 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
4830                 FN_CAN_CLK_D, 0, 0, 0,
4831                 /* IP11_17_16 [2] */
4832                 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
4833                 /* IP11_15_14 [2] */
4834                 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
4835                 /* IP11_13_11 [3] */
4836                 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
4837                 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0, 0, 0,
4838                 /* IP11_10_8 [3] */
4839                 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
4840                 FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0, 0, 0,
4841                 /* IP11_7_6 [2] */
4842                 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, 0,
4843                 /* IP11_5_3 [3] */
4844                 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
4845                 0, 0, 0, 0,
4846                 /* IP11_2_0 [3] */
4847                 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
4848                 0, 0, 0, 0, }
4849         },
4850         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
4851                              2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) {
4852                 /* IP12_31_30 [2] */
4853                 0, 0, 0, 0,
4854                 /* IP12_29_27 [3] */
4855                 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0,
4856                 FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0,
4857                 /* IP12_26_24 [3] */
4858                 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, 0,
4859                 FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0,
4860                 /* IP12_23_21 [3] */
4861                 FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0,
4862                 FN_CAN0_TX_D, 0, FN_ETH_RX_ER_B, 0,
4863                 /* IP12_20_18 [3] */
4864                 FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK,
4865                 FN_CAN0_RX_D, 0, FN_ETH_CRS_DV_B, 0,
4866                 /* IP12_17_15 [3] */
4867                 FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
4868                 FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0,
4869                 /* IP12_14_13 [2] */
4870                 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, 0,
4871                 /* IP12_12_11 [2] */
4872                 FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, 0,
4873                 /* IP12_10_9 [2] */
4874                 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, 0,
4875                 /* IP12_8_6 [3] */
4876                 FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
4877                 FN_CAN1_TX_C, FN_DREQ2_N, 0, 0,
4878                 /* IP12_5_3 [3] */
4879                 FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
4880                 FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
4881                 /* IP12_2_0 [3] */
4882                 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
4883                 0, FN_DREQ1_N_B, 0, 0, }
4884         },
4885         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
4886                              1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
4887                 /* IP13_31 [1] */
4888                 0, 0,
4889                 /* IP13_30 [1] */
4890                 0, 0,
4891                 /* IP13_29 [1] */
4892                 0, 0,
4893                 /* IP13_28 [1] */
4894                 0, 0,
4895                 /* IP13_27 [1] */
4896                 0, 0,
4897                 /* IP13_26_24 [3] */
4898                 FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
4899                 FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0,
4900                 /* IP13_23_21 [3] */
4901                 FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
4902                 FN_TS_SDEN_C, 0, FN_FMCLK_E, 0,
4903                 /* IP13_20_18 [3] */
4904                 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
4905                 FN_TS_SCK_C, 0, FN_BPFCLK_E, FN_ETH_MDC_B,
4906                 /* IP13_17_15 [3] */
4907                 FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
4908                 FN_TS_SDATA_C, 0, FN_ETH_TXD0_B, 0,
4909                 /* IP13_14_12 [3] */
4910                 FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
4911                 FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0,
4912                 /* IP13_11_9 [3] */
4913                 FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6,
4914                 FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0,
4915                 /* IP13_8_6 [3] */
4916                 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
4917                 0, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
4918                 /* IP13_5_3 [2] */
4919                 FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D,
4920                 FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
4921                 /* IP13_2_0 [3] */
4922                 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
4923                 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, }
4924         },
4925         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
4926                              2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3,
4927                              2, 1) {
4928                 /* SEL_ADG [2] */
4929                 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
4930                 /* RESERVED [1] */
4931                 0, 0,
4932                 /* SEL_CAN [2] */
4933                 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
4934                 /* SEL_DARC [3] */
4935                 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
4936                 FN_SEL_DARC_4, 0, 0, 0,
4937                 /* RESERVED [4] */
4938                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4939                 /* SEL_ETH [1] */
4940                 FN_SEL_ETH_0, FN_SEL_ETH_1,
4941                 /* RESERVED [1] */
4942                 0, 0,
4943                 /* SEL_IC200 [3] */
4944                 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
4945                 FN_SEL_I2C00_4, 0, 0, 0,
4946                 /* SEL_I2C01 [3] */
4947                 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
4948                 FN_SEL_I2C01_4, 0, 0, 0,
4949                 /* SEL_I2C02 [3] */
4950                 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
4951                 FN_SEL_I2C02_4, 0, 0, 0,
4952                 /* SEL_I2C03 [3] */
4953                 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
4954                 FN_SEL_I2C03_4, 0, 0, 0,
4955                 /* SEL_I2C04 [3] */
4956                 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
4957                 FN_SEL_I2C04_4, 0, 0, 0,
4958                 /* SEL_I2C05 [2] */
4959                 FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
4960                 /* RESERVED [1] */
4961                 0, 0, }
4962         },
4963         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
4964                              2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
4965                              2, 2, 2, 1, 1, 2) {
4966                 /* SEL_IEB [2] */
4967                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
4968                 /* SEL_IIC0 [2] */
4969                 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
4970                 /* SEL_LBS [1] */
4971                 FN_SEL_LBS_0, FN_SEL_LBS_1,
4972                 /* SEL_MSI1 [1] */
4973                 FN_SEL_MSI1_0, FN_SEL_MSI1_1,
4974                 /* SEL_MSI2 [1] */
4975                 FN_SEL_MSI2_0, FN_SEL_MSI2_1,
4976                 /* SEL_RAD [1] */
4977                 FN_SEL_RAD_0, FN_SEL_RAD_1,
4978                 /* SEL_RCN [1] */
4979                 FN_SEL_RCN_0, FN_SEL_RCN_1,
4980                 /* SEL_RSP [1] */
4981                 FN_SEL_RSP_0, FN_SEL_RSP_1,
4982                 /* SEL_SCIFA0 [2] */
4983                 FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
4984                 FN_SEL_SCIFA0_3,
4985                 /* SEL_SCIFA1 [2] */
4986                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
4987                 /* SEL_SCIFA2 [1] */
4988                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
4989                 /* SEL_SCIFA3 [1] */
4990                 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
4991                 /* SEL_SCIFA4 [2] */
4992                 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
4993                 FN_SEL_SCIFA4_3,
4994                 /* SEL_SCIFA5 [2] */
4995                 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
4996                 FN_SEL_SCIFA5_3,
4997                 /* RESERVED [1] */
4998                 0, 0,
4999                 /* SEL_TMU [1] */
5000                 FN_SEL_TMU_0, FN_SEL_TMU_1,
5001                 /* SEL_TSIF0 [2] */
5002                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5003                 /* SEL_CAN0 [2] */
5004                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5005                 /* SEL_CAN1 [2] */
5006                 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
5007                 /* SEL_HSCIF0 [1] */
5008                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
5009                 /* SEL_HSCIF1 [1] */
5010                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5011                 /* RESERVED [2] */
5012                 0, 0, 0, 0, }
5013         },
5014         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5015                              2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
5016                              1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
5017                 /* SEL_SCIF0 [2] */
5018                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
5019                 /* SEL_SCIF1 [2] */
5020                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
5021                 /* SEL_SCIF2 [2] */
5022                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
5023                 /* SEL_SCIF3 [1] */
5024                 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
5025                 /* SEL_SCIF4 [3] */
5026                 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
5027                 FN_SEL_SCIF4_4, 0, 0, 0,
5028                 /* SEL_SCIF5 [2] */
5029                 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
5030                 /* SEL_SSI1 [1] */
5031                 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
5032                 /* SEL_SSI2 [1] */
5033                 FN_SEL_SSI2_0, FN_SEL_SSI2_1,
5034                 /* SEL_SSI4 [1] */
5035                 FN_SEL_SSI4_0, FN_SEL_SSI4_1,
5036                 /* SEL_SSI5 [1] */
5037                 FN_SEL_SSI5_0, FN_SEL_SSI5_1,
5038                 /* SEL_SSI6 [1] */
5039                 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
5040                 /* SEL_SSI7 [1] */
5041                 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
5042                 /* SEL_SSI8 [1] */
5043                 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
5044                 /* SEL_SSI9 [1] */
5045                 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
5046                 /* RESERVED [1] */
5047                 0, 0,
5048                 /* RESERVED [1] */
5049                 0, 0,
5050                 /* RESERVED [1] */
5051                 0, 0,
5052                 /* RESERVED [1] */
5053                 0, 0,
5054                 /* RESERVED [1] */
5055                 0, 0,
5056                 /* RESERVED [1] */
5057                 0, 0,
5058                 /* RESERVED [1] */
5059                 0, 0,
5060                 /* RESERVED [1] */
5061                 0, 0,
5062                 /* RESERVED [1] */
5063                 0, 0,
5064                 /* RESERVED [1] */
5065                 0, 0,
5066                 /* RESERVED [1] */
5067                 0, 0,
5068                 /* RESERVED [1] */
5069                 0, 0, }
5070         },
5071         { },
5072 };
5073
5074 static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5075 {
5076         *pocctrl = 0xe606006c;
5077
5078         switch (pin & 0x1f) {
5079         case 6: return 23;
5080         case 7: return 16;
5081         case 14: return 15;
5082         case 15: return 8;
5083         case 0 ... 5:
5084         case 8 ... 13:
5085                 return 22 - (pin & 0x1f);
5086         case 16 ... 23:
5087                 return 47 - (pin & 0x1f);
5088         }
5089
5090         return -EINVAL;
5091 }
5092
5093 static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
5094         .pin_to_pocctrl = r8a7794_pin_to_pocctrl,
5095 };
5096
5097 #ifdef CONFIG_PINCTRL_PFC_R8A7745
5098 const struct sh_pfc_soc_info r8a7745_pinmux_info = {
5099         .name = "r8a77450_pfc",
5100         .unlock_reg = 0xe6060000, /* PMMR */
5101
5102         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5103
5104         .pins = pinmux_pins,
5105         .nr_pins = ARRAY_SIZE(pinmux_pins),
5106         .groups = pinmux_groups,
5107         .nr_groups = ARRAY_SIZE(pinmux_groups),
5108         .functions = pinmux_functions,
5109         .nr_functions = ARRAY_SIZE(pinmux_functions),
5110
5111         .cfg_regs = pinmux_config_regs,
5112
5113         .pinmux_data = pinmux_data,
5114         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5115 };
5116 #endif
5117
5118 #ifdef CONFIG_PINCTRL_PFC_R8A7794
5119 const struct sh_pfc_soc_info r8a7794_pinmux_info = {
5120         .name = "r8a77940_pfc",
5121         .ops = &r8a7794_pinmux_ops,
5122         .unlock_reg = 0xe6060000, /* PMMR */
5123
5124         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5125
5126         .pins = pinmux_pins,
5127         .nr_pins = ARRAY_SIZE(pinmux_pins),
5128         .groups = pinmux_groups,
5129         .nr_groups = ARRAY_SIZE(pinmux_groups),
5130         .functions = pinmux_functions,
5131         .nr_functions = ARRAY_SIZE(pinmux_functions),
5132
5133         .cfg_regs = pinmux_config_regs,
5134
5135         .pinmux_data = pinmux_data,
5136         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5137 };
5138 #endif