1 * NAND chip and NAND controller generic binding
3 NAND controller/NAND chip representation:
5 The NAND controller should be represented with its own DT node, and all
6 NAND chips attached to this controller should be defined as children nodes
7 of the NAND controller. This representation should be enforced even for
8 simple controllers supporting only one chip.
10 Mandatory NAND controller properties:
11 - #address-cells: depends on your controller. Should at least be 1 to
12 encode the CS line id.
13 - #size-cells: depends on your controller. Put zero unless you need a
14 mapping between CS lines and dedicated memory regions
16 Optional NAND controller properties
17 - ranges: only needed if you need to define a mapping between CS lines and
20 Optional NAND chip properties:
22 - nand-ecc-mode : String, operation mode of the NAND ecc mode.
23 Supported values are: "none", "soft", "hw", "hw_syndrome",
26 "soft_bch": use "soft" and nand-ecc-algo instead
27 - nand-ecc-algo: string, algorithm of NAND ECC.
28 Supported values are: "hamming", "bch".
29 - nand-bus-width : 8 or 16 bus width if not present 8
30 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
32 - nand-ecc-strength: integer representing the number of bits to correct
35 - nand-ecc-step-size: integer representing the number of data bytes
36 that are covered by a single ECC step.
38 The ECC strength and ECC step size properties define the correction capability
39 of a controller. Together, they say a controller can correct "{strength} bit
40 errors per {size} bytes".
42 The interpretation of these parameters is implementation-defined, so not all
43 implementations must support all possible combinations. However, implementations
44 are encouraged to further specify the value(s) they support.
52 /* controller specific properties */
56 nand-ecc-mode = "soft";
57 nand-ecc-algo = "bch";
59 /* controller specific properties */