arch/mips/boot/dts/pic32/pic32mzda.dtsi

   1 /*
   2  * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  */
   9 #include <dt-bindings/clock/microchip,pic32-clock.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11
  12 / {
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15         interrupt-parent = <&evic>;
  16
  17         aliases {
  18                 gpio0 = &gpio0;
  19                 gpio1 = &gpio1;
  20                 gpio2 = &gpio2;
  21                 gpio3 = &gpio3;
  22                 gpio4 = &gpio4;
  23                 gpio5 = &gpio5;
  24                 gpio6 = &gpio6;
  25                 gpio7 = &gpio7;
  26                 gpio8 = &gpio8;
  27                 gpio9 = &gpio9;
  28                 serial0 = &uart1;
  29                 serial1 = &uart2;
  30                 serial2 = &uart3;
  31                 serial3 = &uart4;
  32                 serial4 = &uart5;
  33                 serial5 = &uart6;
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 cpu@0 {
  41                         compatible = "mti,mips14KEc";
  42                         device_type = "cpu";
  43                 };
  44         };
  45
  46         soc {
  47                 compatible = "microchip,pic32mzda-infra";
  48                 interrupts = <0 IRQ_TYPE_EDGE_RISING>;
  49         };
  50
  51         /* external clock input on TxCLKI pin */
  52         txcki: txcki_clk {
  53                 #clock-cells = <0>;
  54                 compatible = "fixed-clock";
  55                 clock-frequency = <4000000>;
  56                 status = "disabled";
  57         };
  58
  59         /* external input on REFCLKIx pin */
  60         refix: refix_clk {
  61                 #clock-cells = <0>;
  62                 compatible = "fixed-clock";
  63                 clock-frequency = <24000000>;
  64                 status = "disabled";
  65         };
  66
  67         rootclk: clock-controller@1f801200 {
  68                 compatible = "microchip,pic32mzda-clk";
  69                 reg = <0x1f801200 0x200>;
  70                 #clock-cells = <1>;
  71                 microchip,pic32mzda-sosc;
  72         };
  73
  74         evic: interrupt-controller@1f810000 {
  75                 compatible = "microchip,pic32mzda-evic";
  76                 interrupt-controller;
  77                 #interrupt-cells = <2>;
  78                 reg = <0x1f810000 0x1000>;
  79                 microchip,external-irqs = <3 8 13 18 23>;
  80         };
  81
  82         pic32_pinctrl: pinctrl@1f801400{
  83                 #address-cells = <1>;
  84                 #size-cells = <1>;
  85                 compatible = "microchip,pic32mzda-pinctrl";
  86                 reg = <0x1f801400 0x400>;
  87                 clocks = <&rootclk PB1CLK>;
  88         };
  89
  90         /* PORTA */
  91         gpio0: gpio0@1f860000 {
  92                 compatible = "microchip,pic32mzda-gpio";
  93                 reg = <0x1f860000 0x100>;
  94                 interrupts = <118 IRQ_TYPE_LEVEL_HIGH>;
  95                 #gpio-cells = <2>;
  96                 gpio-controller;
  97                 interrupt-controller;
  98                 #interrupt-cells = <2>;
  99                 clocks = <&rootclk PB4CLK>;
 100                 microchip,gpio-bank = <0>;
 101                 gpio-ranges = <&pic32_pinctrl 0 0 16>;
 102         };
 103
 104         /* PORTB */
 105         gpio1: gpio1@1f860100 {
 106                 compatible = "microchip,pic32mzda-gpio";
 107                 reg = <0x1f860100 0x100>;
 108                 interrupts = <119 IRQ_TYPE_LEVEL_HIGH>;
 109                 #gpio-cells = <2>;
 110                 gpio-controller;
 111                 interrupt-controller;
 112                 #interrupt-cells = <2>;
 113                 clocks = <&rootclk PB4CLK>;
 114                 microchip,gpio-bank = <1>;
 115                 gpio-ranges = <&pic32_pinctrl 0 16 16>;
 116         };
 117
 118         /* PORTC */
 119         gpio2: gpio2@1f860200 {
 120                 compatible = "microchip,pic32mzda-gpio";
 121                 reg = <0x1f860200 0x100>;
 122                 interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
 123                 #gpio-cells = <2>;
 124                 gpio-controller;
 125                 interrupt-controller;
 126                 #interrupt-cells = <2>;
 127                 clocks = <&rootclk PB4CLK>;
 128                 microchip,gpio-bank = <2>;
 129                 gpio-ranges = <&pic32_pinctrl 0 32 16>;
 130         };
 131
 132         /* PORTD */
 133         gpio3: gpio3@1f860300 {
 134                 compatible = "microchip,pic32mzda-gpio";
 135                 reg = <0x1f860300 0x100>;
 136                 interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
 137                 #gpio-cells = <2>;
 138                 gpio-controller;
 139                 interrupt-controller;
 140                 #interrupt-cells = <2>;
 141                 clocks = <&rootclk PB4CLK>;
 142                 microchip,gpio-bank = <3>;
 143                 gpio-ranges = <&pic32_pinctrl 0 48 16>;
 144         };
 145
 146         /* PORTE */
 147         gpio4: gpio4@1f860400 {
 148                 compatible = "microchip,pic32mzda-gpio";
 149                 reg = <0x1f860400 0x100>;
 150                 interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
 151                 #gpio-cells = <2>;
 152                 gpio-controller;
 153                 interrupt-controller;
 154                 #interrupt-cells = <2>;
 155                 clocks = <&rootclk PB4CLK>;
 156                 microchip,gpio-bank = <4>;
 157                 gpio-ranges = <&pic32_pinctrl 0 64 16>;
 158         };
 159
 160         /* PORTF */
 161         gpio5: gpio5@1f860500 {
 162                 compatible = "microchip,pic32mzda-gpio";
 163                 reg = <0x1f860500 0x100>;
 164                 interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
 165                 #gpio-cells = <2>;
 166                 gpio-controller;
 167                 interrupt-controller;
 168                 #interrupt-cells = <2>;
 169                 clocks = <&rootclk PB4CLK>;
 170                 microchip,gpio-bank = <5>;
 171                 gpio-ranges = <&pic32_pinctrl 0 80 16>;
 172         };
 173
 174         /* PORTG */
 175         gpio6: gpio6@1f860600 {
 176                 compatible = "microchip,pic32mzda-gpio";
 177                 reg = <0x1f860600 0x100>;
 178                 interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
 179                 #gpio-cells = <2>;
 180                 gpio-controller;
 181                 interrupt-controller;
 182                 #interrupt-cells = <2>;
 183                 clocks = <&rootclk PB4CLK>;
 184                 microchip,gpio-bank = <6>;
 185                 gpio-ranges = <&pic32_pinctrl 0 96 16>;
 186         };
 187
 188         /* PORTH */
 189         gpio7: gpio7@1f860700 {
 190                 compatible = "microchip,pic32mzda-gpio";
 191                 reg = <0x1f860700 0x100>;
 192                 interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
 193                 #gpio-cells = <2>;
 194                 gpio-controller;
 195                 interrupt-controller;
 196                 #interrupt-cells = <2>;
 197                 clocks = <&rootclk PB4CLK>;
 198                 microchip,gpio-bank = <7>;
 199                 gpio-ranges = <&pic32_pinctrl 0 112 16>;
 200         };
 201
 202         /* PORTI does not exist */
 203
 204         /* PORTJ */
 205         gpio8: gpio8@1f860800 {
 206                 compatible = "microchip,pic32mzda-gpio";
 207                 reg = <0x1f860800 0x100>;
 208                 interrupts = <126 IRQ_TYPE_LEVEL_HIGH>;
 209                 #gpio-cells = <2>;
 210                 gpio-controller;
 211                 interrupt-controller;
 212                 #interrupt-cells = <2>;
 213                 clocks = <&rootclk PB4CLK>;
 214                 microchip,gpio-bank = <8>;
 215                 gpio-ranges = <&pic32_pinctrl 0 128 16>;
 216         };
 217
 218         /* PORTK */
 219         gpio9: gpio9@1f860900 {
 220                 compatible = "microchip,pic32mzda-gpio";
 221                 reg = <0x1f860900 0x100>;
 222                 interrupts = <127 IRQ_TYPE_LEVEL_HIGH>;
 223                 #gpio-cells = <2>;
 224                 gpio-controller;
 225                 interrupt-controller;
 226                 #interrupt-cells = <2>;
 227                 clocks = <&rootclk PB4CLK>;
 228                 microchip,gpio-bank = <9>;
 229                 gpio-ranges = <&pic32_pinctrl 0 144 16>;
 230         };
 231
 232         sdhci: sdhci@1f8ec000 {
 233                 compatible = "microchip,pic32mzda-sdhci";
 234                 reg = <0x1f8ec000 0x100>;
 235                 interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
 236                 clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>;
 237                 clock-names = "base_clk", "sys_clk";
 238                 bus-width = <4>;
 239                 cap-sd-highspeed;
 240                 status = "disabled";
 241         };
 242
 243         uart1: serial@1f822000 {
 244                 compatible = "microchip,pic32mzda-uart";
 245                 reg = <0x1f822000 0x50>;
 246                 interrupts = <112 IRQ_TYPE_LEVEL_HIGH>,
 247                         <113 IRQ_TYPE_LEVEL_HIGH>,
 248                         <114 IRQ_TYPE_LEVEL_HIGH>;
 249                 clocks = <&rootclk PB2CLK>;
 250                 status = "disabled";
 251         };
 252
 253         uart2: serial@1f822200 {
 254                 compatible = "microchip,pic32mzda-uart";
 255                 reg = <0x1f822200 0x50>;
 256                 interrupts = <145 IRQ_TYPE_LEVEL_HIGH>,
 257                         <146 IRQ_TYPE_LEVEL_HIGH>,
 258                         <147 IRQ_TYPE_LEVEL_HIGH>;
 259                 clocks = <&rootclk PB2CLK>;
 260                 status = "disabled";
 261         };
 262
 263         uart3: serial@1f822400 {
 264                 compatible = "microchip,pic32mzda-uart";
 265                 reg = <0x1f822400 0x50>;
 266                 interrupts = <157 IRQ_TYPE_LEVEL_HIGH>,
 267                         <158 IRQ_TYPE_LEVEL_HIGH>,
 268                         <159 IRQ_TYPE_LEVEL_HIGH>;
 269                 clocks = <&rootclk PB2CLK>;
 270                 status = "disabled";
 271         };
 272
 273         uart4: serial@1f822600 {
 274                 compatible = "microchip,pic32mzda-uart";
 275                 reg = <0x1f822600 0x50>;
 276                 interrupts = <170 IRQ_TYPE_LEVEL_HIGH>,
 277                         <171 IRQ_TYPE_LEVEL_HIGH>,
 278                         <172 IRQ_TYPE_LEVEL_HIGH>;
 279                 clocks = <&rootclk PB2CLK>;
 280                 status = "disabled";
 281         };
 282
 283         uart5: serial@1f822800 {
 284                 compatible = "microchip,pic32mzda-uart";
 285                 reg = <0x1f822800 0x50>;
 286                 interrupts = <179 IRQ_TYPE_LEVEL_HIGH>,
 287                         <180 IRQ_TYPE_LEVEL_HIGH>,
 288                         <181 IRQ_TYPE_LEVEL_HIGH>;
 289                 clocks = <&rootclk PB2CLK>;
 290                 status = "disabled";
 291         };
 292
 293         uart6: serial@1f822A00 {
 294                 compatible = "microchip,pic32mzda-uart";
 295                 reg = <0x1f822A00 0x50>;
 296                 interrupts = <188 IRQ_TYPE_LEVEL_HIGH>,
 297                         <189 IRQ_TYPE_LEVEL_HIGH>,
 298                         <190 IRQ_TYPE_LEVEL_HIGH>;
 299                 clocks = <&rootclk PB2CLK>;
 300                 status = "disabled";
 301         };
 302 };