?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[cris-mirror.git] / arch / mips / cavium-octeon / octeon-platform.c
blobb31fbc9d6eae23ea37e07591f5c664e3f9346903
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2016 Cavium Networks
7 * Copyright (C) 2008 Wind River Systems
8 */
9
10 #include <linux/init.h>
11 #include <linux/delay.h>
12 #include <linux/etherdevice.h>
13 #include <linux/of_platform.h>
14 #include <linux/of_fdt.h>
15 #include <linux/libfdt.h>
16 #include <linux/usb/ehci_def.h>
17 #include <linux/usb/ehci_pdriver.h>
18 #include <linux/usb/ohci_pdriver.h>
19
20 #include <asm/octeon/octeon.h>
21 #include <asm/octeon/cvmx-helper-board.h>
22 #include <asm/octeon/cvmx-uctlx-defs.h>
23
24 #define CVMX_UAHCX_EHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000010ull))
25 #define CVMX_UAHCX_OHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000408ull))
26
27 /* Octeon Random Number Generator. */
28 static int __init octeon_rng_device_init(void)
29 {
30 struct platform_device *pd;
31 int ret = 0;
32
33 struct resource rng_resources[] = {
34 {
35 .flags = IORESOURCE_MEM,
36 .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
37 .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
38 }, {
39 .flags = IORESOURCE_MEM,
40 .start = cvmx_build_io_address(8, 0),
41 .end = cvmx_build_io_address(8, 0) + 0x7
42 }
43 };
44
45 pd = platform_device_alloc("octeon_rng", -1);
46 if (!pd) {
47 ret = -ENOMEM;
48 goto out;
49 }
50
51 ret = platform_device_add_resources(pd, rng_resources,
52 ARRAY_SIZE(rng_resources));
53 if (ret)
54 goto fail;
55
56 ret = platform_device_add(pd);
57 if (ret)
58 goto fail;
59
60 return ret;
61 fail:
62 platform_device_put(pd);
63
64 out:
65 return ret;
66 }
67 device_initcall(octeon_rng_device_init);
68
69 #ifdef CONFIG_USB
70
71 static DEFINE_MUTEX(octeon2_usb_clocks_mutex);
72
73 static int octeon2_usb_clock_start_cnt;
74
75 static int __init octeon2_usb_reset(void)
76 {
77 union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
78 u32 ucmd;
79
80 if (!OCTEON_IS_OCTEON2())
81 return 0;
82
83 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
84 if (clk_rst_ctl.s.hrst) {
85 ucmd = cvmx_read64_uint32(CVMX_UAHCX_EHCI_USBCMD);
86 ucmd &= ~CMD_RUN;
87 cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd);
88 mdelay(2);
89 ucmd |= CMD_RESET;
90 cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd);
91 ucmd = cvmx_read64_uint32(CVMX_UAHCX_OHCI_USBCMD);
92 ucmd |= CMD_RUN;
93 cvmx_write64_uint32(CVMX_UAHCX_OHCI_USBCMD, ucmd);
94 }
95
96 return 0;
97 }
98 arch_initcall(octeon2_usb_reset);
99
100 static void octeon2_usb_clocks_start(struct device *dev)
101 {
102 u64 div;
103 union cvmx_uctlx_if_ena if_ena;
104 union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
105 union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
106 int i;
107 unsigned long io_clk_64_to_ns;
108 u32 clock_rate = 12000000;
109 bool is_crystal_clock = false;
110
111
112 mutex_lock(&octeon2_usb_clocks_mutex);
113
114 octeon2_usb_clock_start_cnt++;
115 if (octeon2_usb_clock_start_cnt != 1)
116 goto exit;
117
118 io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
119
120 if (dev->of_node) {
121 struct device_node *uctl_node;
122 const char *clock_type;
123
124 uctl_node = of_get_parent(dev->of_node);
125 if (!uctl_node) {
126 dev_err(dev, "No UCTL device node\n");
127 goto exit;
128 }
129 i = of_property_read_u32(uctl_node,
130 "refclk-frequency", &clock_rate);
131 if (i) {
132 dev_err(dev, "No UCTL \"refclk-frequency\"\n");
133 goto exit;
134 }
135 i = of_property_read_string(uctl_node,
136 "refclk-type", &clock_type);
137
138 if (!i && strcmp("crystal", clock_type) == 0)
139 is_crystal_clock = true;
140 }
141
142 /*
143 * Step 1: Wait for voltages stable. That surely happened
144 * before starting the kernel.
145 *
146 * Step 2: Enable SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1
147 */
148 if_ena.u64 = 0;
149 if_ena.s.en = 1;
150 cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
151
152 for (i = 0; i <= 1; i++) {
153 port_ctl_status.u64 =
154 cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
155 /* Set txvreftune to 15 to obtain compliant 'eye' diagram. */
156 port_ctl_status.s.txvreftune = 15;
157 port_ctl_status.s.txrisetune = 1;
158 port_ctl_status.s.txpreemphasistune = 1;
159 cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
160 port_ctl_status.u64);
161 }
162
163 /* Step 3: Configure the reference clock, PHY, and HCLK */
164 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
165
166 /*
167 * If the UCTL looks like it has already been started, skip
168 * the initialization, otherwise bus errors are obtained.
169 */
170 if (clk_rst_ctl.s.hrst)
171 goto end_clock;
172 /* 3a */
173 clk_rst_ctl.s.p_por = 1;
174 clk_rst_ctl.s.hrst = 0;
175 clk_rst_ctl.s.p_prst = 0;
176 clk_rst_ctl.s.h_clkdiv_rst = 0;
177 clk_rst_ctl.s.o_clkdiv_rst = 0;
178 clk_rst_ctl.s.h_clkdiv_en = 0;
179 clk_rst_ctl.s.o_clkdiv_en = 0;
180 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
181
182 /* 3b */
183 clk_rst_ctl.s.p_refclk_sel = is_crystal_clock ? 0 : 1;
184 switch (clock_rate) {
185 default:
186 pr_err("Invalid UCTL clock rate of %u, using 12000000 instead\n",
187 clock_rate);
188 /* Fall through */
189 case 12000000:
190 clk_rst_ctl.s.p_refclk_div = 0;
191 break;
192 case 24000000:
193 clk_rst_ctl.s.p_refclk_div = 1;
194 break;
195 case 48000000:
196 clk_rst_ctl.s.p_refclk_div = 2;
197 break;
198 }
199 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
200
201 /* 3c */
202 div = octeon_get_io_clock_rate() / 130000000ull;
203
204 switch (div) {
205 case 0:
206 div = 1;
207 break;
208 case 1:
209 case 2:
210 case 3:
211 case 4:
212 break;
213 case 5:
214 div = 4;
215 break;
216 case 6:
217 case 7:
218 div = 6;
219 break;
220 case 8:
221 case 9:
222 case 10:
223 case 11:
224 div = 8;
225 break;
226 default:
227 div = 12;
228 break;
229 }
230 clk_rst_ctl.s.h_div = div;
231 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
232 /* Read it back, */
233 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
234 clk_rst_ctl.s.h_clkdiv_en = 1;
235 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
236 /* 3d */
237 clk_rst_ctl.s.h_clkdiv_rst = 1;
238 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
239
240 /* 3e: delay 64 io clocks */
241 ndelay(io_clk_64_to_ns);
242
243 /*
244 * Step 4: Program the power-on reset field in the UCTL
245 * clock-reset-control register.
246 */
247 clk_rst_ctl.s.p_por = 0;
248 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
249
250 /* Step 5: Wait 3 ms for the PHY clock to start. */
251 mdelay(3);
252
253 /* Steps 6..9 for ATE only, are skipped. */
254
255 /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */
256 /* 10a */
257 clk_rst_ctl.s.o_clkdiv_rst = 1;
258 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
259
260 /* 10b */
261 clk_rst_ctl.s.o_clkdiv_en = 1;
262 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
263
264 /* 10c */
265 ndelay(io_clk_64_to_ns);
266
267 /*
268 * Step 11: Program the PHY reset field:
269 * UCTL0_CLK_RST_CTL[P_PRST] = 1
270 */
271 clk_rst_ctl.s.p_prst = 1;
272 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
273
274 /* Step 11b */
275 udelay(1);
276
277 /* Step 11c */
278 clk_rst_ctl.s.p_prst = 0;
279 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
280
281 /* Step 11d */
282 mdelay(1);
283
284 /* Step 11e */
285 clk_rst_ctl.s.p_prst = 1;
286 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
287
288 /* Step 12: Wait 1 uS. */
289 udelay(1);
290
291 /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */
292 clk_rst_ctl.s.hrst = 1;
293 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
294
295 end_clock:
296 /* Set uSOF cycle period to 60,000 bits. */
297 cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull);
298
299 exit:
300 mutex_unlock(&octeon2_usb_clocks_mutex);
301 }
302
303 static void octeon2_usb_clocks_stop(void)
304 {
305 mutex_lock(&octeon2_usb_clocks_mutex);
306 octeon2_usb_clock_start_cnt--;
307 mutex_unlock(&octeon2_usb_clocks_mutex);
308 }
309
310 static int octeon_ehci_power_on(struct platform_device *pdev)
311 {
312 octeon2_usb_clocks_start(&pdev->dev);
313 return 0;
314 }
315
316 static void octeon_ehci_power_off(struct platform_device *pdev)
317 {
318 octeon2_usb_clocks_stop();
319 }
320
321 static struct usb_ehci_pdata octeon_ehci_pdata = {
322 /* Octeon EHCI matches CPU endianness. */
323 #ifdef __BIG_ENDIAN
324 .big_endian_mmio = 1,
325 #endif
326 /*
327 * We can DMA from anywhere. But the descriptors must be in
328 * the lower 4GB.
329 */
330 .dma_mask_64 = 0,
331 .power_on = octeon_ehci_power_on,
332 .power_off = octeon_ehci_power_off,
333 };
334
335 static void __init octeon_ehci_hw_start(struct device *dev)
336 {
337 union cvmx_uctlx_ehci_ctl ehci_ctl;
338
339 octeon2_usb_clocks_start(dev);
340
341 ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0));
342 /* Use 64-bit addressing. */
343 ehci_ctl.s.ehci_64b_addr_en = 1;
344 ehci_ctl.s.l2c_addr_msb = 0;
345 #ifdef __BIG_ENDIAN
346 ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
347 ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
348 #else
349 ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
350 ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
351 ehci_ctl.s.inv_reg_a2 = 1;
352 #endif
353 cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);
354
355 octeon2_usb_clocks_stop();
356 }
357
358 static int __init octeon_ehci_device_init(void)
359 {
360 struct platform_device *pd;
361 struct device_node *ehci_node;
362 int ret = 0;
363
364 ehci_node = of_find_node_by_name(NULL, "ehci");
365 if (!ehci_node)
366 return 0;
367
368 pd = of_find_device_by_node(ehci_node);
369 if (!pd)
370 return 0;
371
372 pd->dev.platform_data = &octeon_ehci_pdata;
373 octeon_ehci_hw_start(&pd->dev);
374
375 return ret;
376 }
377 device_initcall(octeon_ehci_device_init);
378
379 static int octeon_ohci_power_on(struct platform_device *pdev)
380 {
381 octeon2_usb_clocks_start(&pdev->dev);
382 return 0;
383 }
384
385 static void octeon_ohci_power_off(struct platform_device *pdev)
386 {
387 octeon2_usb_clocks_stop();
388 }
389
390 static struct usb_ohci_pdata octeon_ohci_pdata = {
391 /* Octeon OHCI matches CPU endianness. */
392 #ifdef __BIG_ENDIAN
393 .big_endian_mmio = 1,
394 #endif
395 .power_on = octeon_ohci_power_on,
396 .power_off = octeon_ohci_power_off,
397 };
398
399 static void __init octeon_ohci_hw_start(struct device *dev)
400 {
401 union cvmx_uctlx_ohci_ctl ohci_ctl;
402
403 octeon2_usb_clocks_start(dev);
404
405 ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));
406 ohci_ctl.s.l2c_addr_msb = 0;
407 #ifdef __BIG_ENDIAN
408 ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
409 ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
410 #else
411 ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
412 ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
413 ohci_ctl.s.inv_reg_a2 = 1;
414 #endif
415 cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);
416
417 octeon2_usb_clocks_stop();
418 }
419
420 static int __init octeon_ohci_device_init(void)
421 {
422 struct platform_device *pd;
423 struct device_node *ohci_node;
424 int ret = 0;
425
426 ohci_node = of_find_node_by_name(NULL, "ohci");
427 if (!ohci_node)
428 return 0;
429
430 pd = of_find_device_by_node(ohci_node);
431 if (!pd)
432 return 0;
433
434 pd->dev.platform_data = &octeon_ohci_pdata;
435 octeon_ohci_hw_start(&pd->dev);
436
437 return ret;
438 }
439 device_initcall(octeon_ohci_device_init);
440
441 #endif /* CONFIG_USB */
442
443
444 static struct of_device_id __initdata octeon_ids[] = {
445 { .compatible = "simple-bus", },
446 { .compatible = "cavium,octeon-6335-uctl", },
447 { .compatible = "cavium,octeon-5750-usbn", },
448 { .compatible = "cavium,octeon-3860-bootbus", },
449 { .compatible = "cavium,mdio-mux", },
450 { .compatible = "gpio-leds", },
451 {},
452 };
453
454 static bool __init octeon_has_88e1145(void)
455 {
456 return !OCTEON_IS_MODEL(OCTEON_CN52XX) &&
457 !OCTEON_IS_MODEL(OCTEON_CN6XXX) &&
458 !OCTEON_IS_MODEL(OCTEON_CN56XX);
459 }
460
461 static void __init octeon_fdt_set_phy(int eth, int phy_addr)
462 {
463 const __be32 *phy_handle;
464 const __be32 *alt_phy_handle;
465 const __be32 *reg;
466 u32 phandle;
467 int phy;
468 int alt_phy;
469 const char *p;
470 int current_len;
471 char new_name[20];
472
473 phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL);
474 if (!phy_handle)
475 return;
476
477 phandle = be32_to_cpup(phy_handle);
478 phy = fdt_node_offset_by_phandle(initial_boot_params, phandle);
479
480 alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
481 if (alt_phy_handle) {
482 u32 alt_phandle = be32_to_cpup(alt_phy_handle);
483 alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
484 } else {
485 alt_phy = -1;
486 }
487
488 if (phy_addr < 0 || phy < 0) {
489 /* Delete the PHY things */
490 fdt_nop_property(initial_boot_params, eth, "phy-handle");
491 /* This one may fail */
492 fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle");
493 if (phy >= 0)
494 fdt_nop_node(initial_boot_params, phy);
495 if (alt_phy >= 0)
496 fdt_nop_node(initial_boot_params, alt_phy);
497 return;
498 }
499
500 if (phy_addr >= 256 && alt_phy > 0) {
501 const struct fdt_property *phy_prop;
502 struct fdt_property *alt_prop;
503 u32 phy_handle_name;
504
505 /* Use the alt phy node instead.*/
506 phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
507 phy_handle_name = phy_prop->nameoff;
508 fdt_nop_node(initial_boot_params, phy);
509 fdt_nop_property(initial_boot_params, eth, "phy-handle");
510 alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
511 alt_prop->nameoff = phy_handle_name;
512 phy = alt_phy;
513 }
514
515 phy_addr &= 0xff;
516
517 if (octeon_has_88e1145()) {
518 fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
519 memset(new_name, 0, sizeof(new_name));
520 strcpy(new_name, "marvell,88e1145");
521 p = fdt_getprop(initial_boot_params, phy, "compatible",
522 &current_len);
523 if (p && current_len >= strlen(new_name))
524 fdt_setprop_inplace(initial_boot_params, phy,
525 "compatible", new_name, current_len);
526 }
527
528 reg = fdt_getprop(initial_boot_params, phy, "reg", NULL);
529 if (phy_addr == be32_to_cpup(reg))
530 return;
531
532 fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr);
533
534 snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr);
535
536 p = fdt_get_name(initial_boot_params, phy, &current_len);
537 if (p && current_len == strlen(new_name))
538 fdt_set_name(initial_boot_params, phy, new_name);
539 else
540 pr_err("Error: could not rename ethernet phy: <%s>", p);
541 }
542
543 static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac)
544 {
545 const u8 *old_mac;
546 int old_len;
547 u8 new_mac[6];
548 u64 mac = *pmac;
549 int r;
550
551 old_mac = fdt_getprop(initial_boot_params, n, "local-mac-address",
552 &old_len);
553 if (!old_mac || old_len != 6 || is_valid_ether_addr(old_mac))
554 return;
555
556 new_mac[0] = (mac >> 40) & 0xff;
557 new_mac[1] = (mac >> 32) & 0xff;
558 new_mac[2] = (mac >> 24) & 0xff;
559 new_mac[3] = (mac >> 16) & 0xff;
560 new_mac[4] = (mac >> 8) & 0xff;
561 new_mac[5] = mac & 0xff;
562
563 r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address",
564 new_mac, sizeof(new_mac));
565
566 if (r) {
567 pr_err("Setting \"local-mac-address\" failed %d", r);
568 return;
569 }
570 *pmac = mac + 1;
571 }
572
573 static void __init octeon_fdt_rm_ethernet(int node)
574 {
575 const __be32 *phy_handle;
576
577 phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL);
578 if (phy_handle) {
579 u32 ph = be32_to_cpup(phy_handle);
580 int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
581 if (p >= 0)
582 fdt_nop_node(initial_boot_params, p);
583 }
584 fdt_nop_node(initial_boot_params, node);
585 }
586
587 static void __init octeon_fdt_pip_port(int iface, int i, int p, int max)
588 {
589 char name_buffer[20];
590 int eth;
591 int phy_addr;
592 int ipd_port;
593
594 snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
595 eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
596 if (eth < 0)
597 return;
598 if (p > max) {
599 pr_debug("Deleting port %x:%x\n", i, p);
600 octeon_fdt_rm_ethernet(eth);
601 return;
602 }
603 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
604 ipd_port = (0x100 * i) + (0x10 * p) + 0x800;
605 else
606 ipd_port = 16 * i + p;
607
608 phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
609 octeon_fdt_set_phy(eth, phy_addr);
610 }
611
612 static void __init octeon_fdt_pip_iface(int pip, int idx)
613 {
614 char name_buffer[20];
615 int iface;
616 int p;
617 int count = 0;
618
619 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
620 iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
621 if (iface < 0)
622 return;
623
624 if (cvmx_helper_interface_enumerate(idx) == 0)
625 count = cvmx_helper_ports_on_interface(idx);
626
627 for (p = 0; p < 16; p++)
628 octeon_fdt_pip_port(iface, idx, p, count - 1);
629 }
630
631 void __init octeon_fill_mac_addresses(void)
632 {
633 const char *alias_prop;
634 char name_buffer[20];
635 u64 mac_addr_base;
636 int aliases;
637 int pip;
638 int i;
639
640 aliases = fdt_path_offset(initial_boot_params, "/aliases");
641 if (aliases < 0)
642 return;
643
644 mac_addr_base =
645 ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 |
646 ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 |
647 ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 |
648 ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 |
649 ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 |
650 (octeon_bootinfo->mac_addr_base[5] & 0xffull);
651
652 for (i = 0; i < 2; i++) {
653 int mgmt;
654
655 snprintf(name_buffer, sizeof(name_buffer), "mix%d", i);
656 alias_prop = fdt_getprop(initial_boot_params, aliases,
657 name_buffer, NULL);
658 if (!alias_prop)
659 continue;
660 mgmt = fdt_path_offset(initial_boot_params, alias_prop);
661 if (mgmt < 0)
662 continue;
663 octeon_fdt_set_mac_addr(mgmt, &mac_addr_base);
664 }
665
666 alias_prop = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
667 if (!alias_prop)
668 return;
669
670 pip = fdt_path_offset(initial_boot_params, alias_prop);
671 if (pip < 0)
672 return;
673
674 for (i = 0; i <= 4; i++) {
675 int iface;
676 int p;
677
678 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", i);
679 iface = fdt_subnode_offset(initial_boot_params, pip,
680 name_buffer);
681 if (iface < 0)
682 continue;
683 for (p = 0; p < 16; p++) {
684 int eth;
685
686 snprintf(name_buffer, sizeof(name_buffer),
687 "ethernet@%x", p);
688 eth = fdt_subnode_offset(initial_boot_params, iface,
689 name_buffer);
690 if (eth < 0)
691 continue;
692 octeon_fdt_set_mac_addr(eth, &mac_addr_base);
693 }
694 }
695 }
696
697 int __init octeon_prune_device_tree(void)
698 {
699 int i, max_port, uart_mask;
700 const char *pip_path;
701 const char *alias_prop;
702 char name_buffer[20];
703 int aliases;
704
705 if (fdt_check_header(initial_boot_params))
706 panic("Corrupt Device Tree.");
707
708 WARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_CUST_DSR1000N,
709 "Built-in DTB booting is deprecated on %s. Please switch to use appended DTB.",
710 cvmx_board_type_to_string(octeon_bootinfo->board_type));
711
712 aliases = fdt_path_offset(initial_boot_params, "/aliases");
713 if (aliases < 0) {
714 pr_err("Error: No /aliases node in device tree.");
715 return -EINVAL;
716 }
717
718 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
719 max_port = 2;
720 else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
721 max_port = 1;
722 else
723 max_port = 0;
724
725 if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E)
726 max_port = 0;
727
728 for (i = 0; i < 2; i++) {
729 int mgmt;
730 snprintf(name_buffer, sizeof(name_buffer),
731 "mix%d", i);
732 alias_prop = fdt_getprop(initial_boot_params, aliases,
733 name_buffer, NULL);
734 if (alias_prop) {
735 mgmt = fdt_path_offset(initial_boot_params, alias_prop);
736 if (mgmt < 0)
737 continue;
738 if (i >= max_port) {
739 pr_debug("Deleting mix%d\n", i);
740 octeon_fdt_rm_ethernet(mgmt);
741 fdt_nop_property(initial_boot_params, aliases,
742 name_buffer);
743 } else {
744 int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
745 octeon_fdt_set_phy(mgmt, phy_addr);
746 }
747 }
748 }
749
750 pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
751 if (pip_path) {
752 int pip = fdt_path_offset(initial_boot_params, pip_path);
753 if (pip >= 0)
754 for (i = 0; i <= 4; i++)
755 octeon_fdt_pip_iface(pip, i);
756 }
757
758 /* I2C */
759 if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
760 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
761 OCTEON_IS_MODEL(OCTEON_CN68XX) ||
762 OCTEON_IS_MODEL(OCTEON_CN56XX))
763 max_port = 2;
764 else
765 max_port = 1;
766
767 for (i = 0; i < 2; i++) {
768 int i2c;
769 snprintf(name_buffer, sizeof(name_buffer),
770 "twsi%d", i);
771 alias_prop = fdt_getprop(initial_boot_params, aliases,
772 name_buffer, NULL);
773
774 if (alias_prop) {
775 i2c = fdt_path_offset(initial_boot_params, alias_prop);
776 if (i2c < 0)
777 continue;
778 if (i >= max_port) {
779 pr_debug("Deleting twsi%d\n", i);
780 fdt_nop_node(initial_boot_params, i2c);
781 fdt_nop_property(initial_boot_params, aliases,
782 name_buffer);
783 }
784 }
785 }
786
787 /* SMI/MDIO */
788 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
789 max_port = 4;
790 else if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
791 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
792 OCTEON_IS_MODEL(OCTEON_CN56XX))
793 max_port = 2;
794 else
795 max_port = 1;
796
797 for (i = 0; i < 2; i++) {
798 int i2c;
799 snprintf(name_buffer, sizeof(name_buffer),
800 "smi%d", i);
801 alias_prop = fdt_getprop(initial_boot_params, aliases,
802 name_buffer, NULL);
803
804 if (alias_prop) {
805 i2c = fdt_path_offset(initial_boot_params, alias_prop);
806 if (i2c < 0)
807 continue;
808 if (i >= max_port) {
809 pr_debug("Deleting smi%d\n", i);
810 fdt_nop_node(initial_boot_params, i2c);
811 fdt_nop_property(initial_boot_params, aliases,
812 name_buffer);
813 }
814 }
815 }
816
817 /* Serial */
818 uart_mask = 3;
819
820 /* Right now CN52XX is the only chip with a third uart */
821 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
822 uart_mask |= 4; /* uart2 */
823
824 for (i = 0; i < 3; i++) {
825 int uart;
826 snprintf(name_buffer, sizeof(name_buffer),
827 "uart%d", i);
828 alias_prop = fdt_getprop(initial_boot_params, aliases,
829 name_buffer, NULL);
830
831 if (alias_prop) {
832 uart = fdt_path_offset(initial_boot_params, alias_prop);
833 if (uart_mask & (1 << i)) {
834 __be32 f;
835
836 f = cpu_to_be32(octeon_get_io_clock_rate());
837 fdt_setprop_inplace(initial_boot_params,
838 uart, "clock-frequency",
839 &f, sizeof(f));
840 continue;
841 }
842 pr_debug("Deleting uart%d\n", i);
843 fdt_nop_node(initial_boot_params, uart);
844 fdt_nop_property(initial_boot_params, aliases,
845 name_buffer);
846 }
847 }
848
849 /* Compact Flash */
850 alias_prop = fdt_getprop(initial_boot_params, aliases,
851 "cf0", NULL);
852 if (alias_prop) {
853 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
854 unsigned long base_ptr, region_base, region_size;
855 unsigned long region1_base = 0;
856 unsigned long region1_size = 0;
857 int cs, bootbus;
858 bool is_16bit = false;
859 bool is_true_ide = false;
860 __be32 new_reg[6];
861 __be32 *ranges;
862 int len;
863
864 int cf = fdt_path_offset(initial_boot_params, alias_prop);
865 base_ptr = 0;
866 if (octeon_bootinfo->major_version == 1
867 && octeon_bootinfo->minor_version >= 1) {
868 if (octeon_bootinfo->compact_flash_common_base_addr)
869 base_ptr = octeon_bootinfo->compact_flash_common_base_addr;
870 } else {
871 base_ptr = 0x1d000800;
872 }
873
874 if (!base_ptr)
875 goto no_cf;
876
877 /* Find CS0 region. */
878 for (cs = 0; cs < 8; cs++) {
879 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
880 region_base = mio_boot_reg_cfg.s.base << 16;
881 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
882 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
883 && base_ptr < region_base + region_size) {
884 is_16bit = mio_boot_reg_cfg.s.width;
885 break;
886 }
887 }
888 if (cs >= 7) {
889 /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */
890 goto no_cf;
891 }
892
893 if (!(base_ptr & 0xfffful)) {
894 /*
895 * Boot loader signals availability of DMA (true_ide
896 * mode) by setting low order bits of base_ptr to
897 * zero.
898 */
899
900 /* Asume that CS1 immediately follows. */
901 mio_boot_reg_cfg.u64 =
902 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
903 region1_base = mio_boot_reg_cfg.s.base << 16;
904 region1_size = (mio_boot_reg_cfg.s.size + 1) << 16;
905 if (!mio_boot_reg_cfg.s.en)
906 goto no_cf;
907 is_true_ide = true;
908
909 } else {
910 fdt_nop_property(initial_boot_params, cf, "cavium,true-ide");
911 fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
912 if (!is_16bit) {
913 __be32 width = cpu_to_be32(8);
914 fdt_setprop_inplace(initial_boot_params, cf,
915 "cavium,bus-width", &width, sizeof(width));
916 }
917 }
918 new_reg[0] = cpu_to_be32(cs);
919 new_reg[1] = cpu_to_be32(0);
920 new_reg[2] = cpu_to_be32(0x10000);
921 new_reg[3] = cpu_to_be32(cs + 1);
922 new_reg[4] = cpu_to_be32(0);
923 new_reg[5] = cpu_to_be32(0x10000);
924 fdt_setprop_inplace(initial_boot_params, cf,
925 "reg", new_reg, sizeof(new_reg));
926
927 bootbus = fdt_parent_offset(initial_boot_params, cf);
928 if (bootbus < 0)
929 goto no_cf;
930 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
931 if (!ranges || len < (5 * 8 * sizeof(__be32)))
932 goto no_cf;
933
934 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
935 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
936 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
937 if (is_true_ide) {
938 cs++;
939 ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32);
940 ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff);
941 ranges[(cs * 5) + 4] = cpu_to_be32(region1_size);
942 }
943 goto end_cf;
944 no_cf:
945 fdt_nop_node(initial_boot_params, cf);
946
947 end_cf:
948 ;
949 }
950
951 /* 8 char LED */
952 alias_prop = fdt_getprop(initial_boot_params, aliases,
953 "led0", NULL);
954 if (alias_prop) {
955 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
956 unsigned long base_ptr, region_base, region_size;
957 int cs, bootbus;
958 __be32 new_reg[6];
959 __be32 *ranges;
960 int len;
961 int led = fdt_path_offset(initial_boot_params, alias_prop);
962
963 base_ptr = octeon_bootinfo->led_display_base_addr;
964 if (base_ptr == 0)
965 goto no_led;
966 /* Find CS0 region. */
967 for (cs = 0; cs < 8; cs++) {
968 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
969 region_base = mio_boot_reg_cfg.s.base << 16;
970 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
971 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
972 && base_ptr < region_base + region_size)
973 break;
974 }
975
976 if (cs > 7)
977 goto no_led;
978
979 new_reg[0] = cpu_to_be32(cs);
980 new_reg[1] = cpu_to_be32(0x20);
981 new_reg[2] = cpu_to_be32(0x20);
982 new_reg[3] = cpu_to_be32(cs);
983 new_reg[4] = cpu_to_be32(0);
984 new_reg[5] = cpu_to_be32(0x20);
985 fdt_setprop_inplace(initial_boot_params, led,
986 "reg", new_reg, sizeof(new_reg));
987
988 bootbus = fdt_parent_offset(initial_boot_params, led);
989 if (bootbus < 0)
990 goto no_led;
991 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
992 if (!ranges || len < (5 * 8 * sizeof(__be32)))
993 goto no_led;
994
995 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
996 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
997 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
998 goto end_led;
999
1000 no_led:
1001 fdt_nop_node(initial_boot_params, led);
1002 end_led:
1003 ;
1004 }
1005
1006 /* OHCI/UHCI USB */
1007 alias_prop = fdt_getprop(initial_boot_params, aliases,
1008 "uctl", NULL);
1009 if (alias_prop) {
1010 int uctl = fdt_path_offset(initial_boot_params, alias_prop);
1011
1012 if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
1013 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) {
1014 pr_debug("Deleting uctl\n");
1015 fdt_nop_node(initial_boot_params, uctl);
1016 fdt_nop_property(initial_boot_params, aliases, "uctl");
1017 } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E ||
1018 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) {
1019 /* Missing "refclk-type" defaults to crystal. */
1020 fdt_nop_property(initial_boot_params, uctl, "refclk-type");
1021 }
1022 }
1023
1024 /* DWC2 USB */
1025 alias_prop = fdt_getprop(initial_boot_params, aliases,
1026 "usbn", NULL);
1027 if (alias_prop) {
1028 int usbn = fdt_path_offset(initial_boot_params, alias_prop);
1029
1030 if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 ||
1031 !octeon_has_feature(OCTEON_FEATURE_USB))) {
1032 pr_debug("Deleting usbn\n");
1033 fdt_nop_node(initial_boot_params, usbn);
1034 fdt_nop_property(initial_boot_params, aliases, "usbn");
1035 } else {
1036 __be32 new_f[1];
1037 enum cvmx_helper_board_usb_clock_types c;
1038 c = __cvmx_helper_board_usb_get_clock_type();
1039 switch (c) {
1040 case USB_CLOCK_TYPE_REF_48:
1041 new_f[0] = cpu_to_be32(48000000);
1042 fdt_setprop_inplace(initial_boot_params, usbn,
1043 "refclk-frequency", new_f, sizeof(new_f));
1044 /* Fall through ...*/
1045 case USB_CLOCK_TYPE_REF_12:
1046 /* Missing "refclk-type" defaults to external. */
1047 fdt_nop_property(initial_boot_params, usbn, "refclk-type");
1048 break;
1049 default:
1050 break;
1051 }
1052 }
1053 }
1054
1055 return 0;
1056 }
1057
1058 static int __init octeon_publish_devices(void)
1059 {
1060 return of_platform_bus_probe(NULL, octeon_ids, NULL);
1061 }
1062 device_initcall(octeon_publish_devices);
1063
1064 MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
1065 MODULE_LICENSE("GPL");
1066 MODULE_DESCRIPTION("Platform driver for Octeon SOC");
CRIS linux kernel tree