arch/mips/include/asm/cpu-features.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003, 2004 Ralf Baechle
   7  * Copyright (C) 2004  Maciej W. Rozycki
   8  */
   9 #ifndef __ASM_CPU_FEATURES_H
  10 #define __ASM_CPU_FEATURES_H
  11
  12 #include <asm/cpu.h>
  13 #include <asm/cpu-info.h>
  14 #include <cpu-feature-overrides.h>
  15
  16 /*
  17  * SMP assumption: Options of CPU 0 are a superset of all processors.
  18  * This is true for all known MIPS systems.
  19  */
  20 #ifndef cpu_has_tlb
  21 #define cpu_has_tlb             (cpu_data[0].options & MIPS_CPU_TLB)
  22 #endif
  23 #ifndef cpu_has_ftlb
  24 #define cpu_has_ftlb            (cpu_data[0].options & MIPS_CPU_FTLB)
  25 #endif
  26 #ifndef cpu_has_tlbinv
  27 #define cpu_has_tlbinv          (cpu_data[0].options & MIPS_CPU_TLBINV)
  28 #endif
  29 #ifndef cpu_has_segments
  30 #define cpu_has_segments        (cpu_data[0].options & MIPS_CPU_SEGMENTS)
  31 #endif
  32 #ifndef cpu_has_eva
  33 #define cpu_has_eva             (cpu_data[0].options & MIPS_CPU_EVA)
  34 #endif
  35 #ifndef cpu_has_htw
  36 #define cpu_has_htw             (cpu_data[0].options & MIPS_CPU_HTW)
  37 #endif
  38 #ifndef cpu_has_ldpte
  39 #define cpu_has_ldpte           (cpu_data[0].options & MIPS_CPU_LDPTE)
  40 #endif
  41 #ifndef cpu_has_rixiex
  42 #define cpu_has_rixiex          (cpu_data[0].options & MIPS_CPU_RIXIEX)
  43 #endif
  44 #ifndef cpu_has_maar
  45 #define cpu_has_maar            (cpu_data[0].options & MIPS_CPU_MAAR)
  46 #endif
  47 #ifndef cpu_has_rw_llb
  48 #define cpu_has_rw_llb          (cpu_data[0].options & MIPS_CPU_RW_LLB)
  49 #endif
  50
  51 /*
  52  * For the moment we don't consider R6000 and R8000 so we can assume that
  53  * anything that doesn't support R4000-style exceptions and interrupts is
  54  * R3000-like.  Users should still treat these two macro definitions as
  55  * opaque.
  56  */
  57 #ifndef cpu_has_3kex
  58 #define cpu_has_3kex            (!cpu_has_4kex)
  59 #endif
  60 #ifndef cpu_has_4kex
  61 #define cpu_has_4kex            (cpu_data[0].options & MIPS_CPU_4KEX)
  62 #endif
  63 #ifndef cpu_has_3k_cache
  64 #define cpu_has_3k_cache        (cpu_data[0].options & MIPS_CPU_3K_CACHE)
  65 #endif
  66 #define cpu_has_6k_cache        0
  67 #define cpu_has_8k_cache        0
  68 #ifndef cpu_has_4k_cache
  69 #define cpu_has_4k_cache        (cpu_data[0].options & MIPS_CPU_4K_CACHE)
  70 #endif
  71 #ifndef cpu_has_tx39_cache
  72 #define cpu_has_tx39_cache      (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
  73 #endif
  74 #ifndef cpu_has_octeon_cache
  75 #define cpu_has_octeon_cache    0
  76 #endif
  77 /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work.  */
  78 #ifndef cpu_has_fpu
  79 #define cpu_has_fpu             (current_cpu_data.options & MIPS_CPU_FPU)
  80 #define raw_cpu_has_fpu         (raw_current_cpu_data.options & MIPS_CPU_FPU)
  81 #else
  82 #define raw_cpu_has_fpu         cpu_has_fpu
  83 #endif
  84 #ifndef cpu_has_32fpr
  85 #define cpu_has_32fpr           (cpu_data[0].options & MIPS_CPU_32FPR)
  86 #endif
  87 #ifndef cpu_has_counter
  88 #define cpu_has_counter         (cpu_data[0].options & MIPS_CPU_COUNTER)
  89 #endif
  90 #ifndef cpu_has_watch
  91 #define cpu_has_watch           (cpu_data[0].options & MIPS_CPU_WATCH)
  92 #endif
  93 #ifndef cpu_has_divec
  94 #define cpu_has_divec           (cpu_data[0].options & MIPS_CPU_DIVEC)
  95 #endif
  96 #ifndef cpu_has_vce
  97 #define cpu_has_vce             (cpu_data[0].options & MIPS_CPU_VCE)
  98 #endif
  99 #ifndef cpu_has_cache_cdex_p
 100 #define cpu_has_cache_cdex_p    (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
 101 #endif
 102 #ifndef cpu_has_cache_cdex_s
 103 #define cpu_has_cache_cdex_s    (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
 104 #endif
 105 #ifndef cpu_has_prefetch
 106 #define cpu_has_prefetch        (cpu_data[0].options & MIPS_CPU_PREFETCH)
 107 #endif
 108 #ifndef cpu_has_mcheck
 109 #define cpu_has_mcheck          (cpu_data[0].options & MIPS_CPU_MCHECK)
 110 #endif
 111 #ifndef cpu_has_ejtag
 112 #define cpu_has_ejtag           (cpu_data[0].options & MIPS_CPU_EJTAG)
 113 #endif
 114 #ifndef cpu_has_llsc
 115 #define cpu_has_llsc            (cpu_data[0].options & MIPS_CPU_LLSC)
 116 #endif
 117 #ifndef cpu_has_bp_ghist
 118 #define cpu_has_bp_ghist        (cpu_data[0].options & MIPS_CPU_BP_GHIST)
 119 #endif
 120 #ifndef kernel_uses_llsc
 121 #define kernel_uses_llsc        cpu_has_llsc
 122 #endif
 123 #ifndef cpu_has_guestctl0ext
 124 #define cpu_has_guestctl0ext    (cpu_data[0].options & MIPS_CPU_GUESTCTL0EXT)
 125 #endif
 126 #ifndef cpu_has_guestctl1
 127 #define cpu_has_guestctl1       (cpu_data[0].options & MIPS_CPU_GUESTCTL1)
 128 #endif
 129 #ifndef cpu_has_guestctl2
 130 #define cpu_has_guestctl2       (cpu_data[0].options & MIPS_CPU_GUESTCTL2)
 131 #endif
 132 #ifndef cpu_has_guestid
 133 #define cpu_has_guestid         (cpu_data[0].options & MIPS_CPU_GUESTID)
 134 #endif
 135 #ifndef cpu_has_drg
 136 #define cpu_has_drg             (cpu_data[0].options & MIPS_CPU_DRG)
 137 #endif
 138 #ifndef cpu_has_mips16
 139 #define cpu_has_mips16          (cpu_data[0].ases & MIPS_ASE_MIPS16)
 140 #endif
 141 #ifndef cpu_has_mdmx
 142 #define cpu_has_mdmx            (cpu_data[0].ases & MIPS_ASE_MDMX)
 143 #endif
 144 #ifndef cpu_has_mips3d
 145 #define cpu_has_mips3d          (cpu_data[0].ases & MIPS_ASE_MIPS3D)
 146 #endif
 147 #ifndef cpu_has_smartmips
 148 #define cpu_has_smartmips       (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
 149 #endif
 150
 151 #ifndef cpu_has_rixi
 152 #define cpu_has_rixi            (cpu_data[0].options & MIPS_CPU_RIXI)
 153 #endif
 154
 155 #ifndef cpu_has_mmips
 156 # ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
 157 #  define cpu_has_mmips         (cpu_data[0].options & MIPS_CPU_MICROMIPS)
 158 # else
 159 #  define cpu_has_mmips         0
 160 # endif
 161 #endif
 162
 163 #ifndef cpu_has_lpa
 164 #define cpu_has_lpa             (cpu_data[0].options & MIPS_CPU_LPA)
 165 #endif
 166 #ifndef cpu_has_mvh
 167 #define cpu_has_mvh             (cpu_data[0].options & MIPS_CPU_MVH)
 168 #endif
 169 #ifndef cpu_has_xpa
 170 #define cpu_has_xpa             (cpu_has_lpa && cpu_has_mvh)
 171 #endif
 172 #ifndef cpu_has_vtag_icache
 173 #define cpu_has_vtag_icache     (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
 174 #endif
 175 #ifndef cpu_has_dc_aliases
 176 #define cpu_has_dc_aliases      (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
 177 #endif
 178 #ifndef cpu_has_ic_fills_f_dc
 179 #define cpu_has_ic_fills_f_dc   (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
 180 #endif
 181 #ifndef cpu_has_pindexed_dcache
 182 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
 183 #endif
 184 #ifndef cpu_has_local_ebase
 185 #define cpu_has_local_ebase     1
 186 #endif
 187
 188 /*
 189  * I-Cache snoops remote store.  This only matters on SMP.  Some multiprocessors
 190  * such as the R10000 have I-Caches that snoop local stores; the embedded ones
 191  * don't.  For maintaining I-cache coherency this means we need to flush the
 192  * D-cache all the way back to whever the I-cache does refills from, so the
 193  * I-cache has a chance to see the new data at all.  Then we have to flush the
 194  * I-cache also.
 195  * Note we may have been rescheduled and may no longer be running on the CPU
 196  * that did the store so we can't optimize this into only doing the flush on
 197  * the local CPU.
 198  */
 199 #ifndef cpu_icache_snoops_remote_store
 200 #ifdef CONFIG_SMP
 201 #define cpu_icache_snoops_remote_store  (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
 202 #else
 203 #define cpu_icache_snoops_remote_store  1
 204 #endif
 205 #endif
 206
 207 /* __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r */
 208 #if !((defined(cpu_has_mips32r1) && cpu_has_mips32r1) || \
 209           (defined(cpu_has_mips32r2) && cpu_has_mips32r2) || \
 210           (defined(cpu_has_mips32r6) && cpu_has_mips32r6) || \
 211           (defined(cpu_has_mips64r1) && cpu_has_mips64r1) || \
 212           (defined(cpu_has_mips64r2) && cpu_has_mips64r2) || \
 213           (defined(cpu_has_mips64r6) && cpu_has_mips64r6))
 214 #define CPU_NO_EFFICIENT_FFS 1
 215 #endif
 216
 217 #ifndef cpu_has_mips_1
 218 # define cpu_has_mips_1         (!cpu_has_mips_r6)
 219 #endif
 220 #ifndef cpu_has_mips_2
 221 # define cpu_has_mips_2         (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
 222 #endif
 223 #ifndef cpu_has_mips_3
 224 # define cpu_has_mips_3         (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
 225 #endif
 226 #ifndef cpu_has_mips_4
 227 # define cpu_has_mips_4         (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
 228 #endif
 229 #ifndef cpu_has_mips_5
 230 # define cpu_has_mips_5         (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
 231 #endif
 232 #ifndef cpu_has_mips32r1
 233 # define cpu_has_mips32r1       (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
 234 #endif
 235 #ifndef cpu_has_mips32r2
 236 # define cpu_has_mips32r2       (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
 237 #endif
 238 #ifndef cpu_has_mips32r6
 239 # define cpu_has_mips32r6       (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
 240 #endif
 241 #ifndef cpu_has_mips64r1
 242 # define cpu_has_mips64r1       (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
 243 #endif
 244 #ifndef cpu_has_mips64r2
 245 # define cpu_has_mips64r2       (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
 246 #endif
 247 #ifndef cpu_has_mips64r6
 248 # define cpu_has_mips64r6       (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6)
 249 #endif
 250
 251 /*
 252  * Shortcuts ...
 253  */
 254 #define cpu_has_mips_2_3_4_5    (cpu_has_mips_2 | cpu_has_mips_3_4_5)
 255 #define cpu_has_mips_3_4_5      (cpu_has_mips_3 | cpu_has_mips_4_5)
 256 #define cpu_has_mips_4_5        (cpu_has_mips_4 | cpu_has_mips_5)
 257
 258 #define cpu_has_mips_2_3_4_5_r  (cpu_has_mips_2 | cpu_has_mips_3_4_5_r)
 259 #define cpu_has_mips_3_4_5_r    (cpu_has_mips_3 | cpu_has_mips_4_5_r)
 260 #define cpu_has_mips_4_5_r      (cpu_has_mips_4 | cpu_has_mips_5_r)
 261 #define cpu_has_mips_5_r        (cpu_has_mips_5 | cpu_has_mips_r)
 262
 263 #define cpu_has_mips_3_4_5_64_r2_r6                                     \
 264                                 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
 265 #define cpu_has_mips_4_5_64_r2_r6                                       \
 266                                 (cpu_has_mips_4_5 | cpu_has_mips64r1 |  \
 267                                  cpu_has_mips_r2 | cpu_has_mips_r6)
 268
 269 #define cpu_has_mips32  (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
 270 #define cpu_has_mips64  (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
 271 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
 272 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
 273 #define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6)
 274 #define cpu_has_mips_r  (cpu_has_mips32r1 | cpu_has_mips32r2 | \
 275                          cpu_has_mips32r6 | cpu_has_mips64r1 | \
 276                          cpu_has_mips64r2 | cpu_has_mips64r6)
 277
 278 /* MIPSR2 and MIPSR6 have a lot of similarities */
 279 #define cpu_has_mips_r2_r6      (cpu_has_mips_r2 | cpu_has_mips_r6)
 280
 281 /*
 282  * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
 283  *
 284  * Returns non-zero value if the current processor implementation requires
 285  * an IHB instruction to deal with an instruction hazard as per MIPS R2
 286  * architecture specification, zero otherwise.
 287  */
 288 #ifndef cpu_has_mips_r2_exec_hazard
 289 #define cpu_has_mips_r2_exec_hazard                                     \
 290 ({                                                                      \
 291         int __res;                                                      \
 292                                                                         \
 293         switch (current_cpu_type()) {                                   \
 294         case CPU_M14KC:                                                 \
 295         case CPU_74K:                                                   \
 296         case CPU_1074K:                                                 \
 297         case CPU_PROAPTIV:                                              \
 298         case CPU_P5600:                                                 \
 299         case CPU_M5150:                                                 \
 300         case CPU_QEMU_GENERIC:                                          \
 301         case CPU_CAVIUM_OCTEON:                                         \
 302         case CPU_CAVIUM_OCTEON_PLUS:                                    \
 303         case CPU_CAVIUM_OCTEON2:                                        \
 304         case CPU_CAVIUM_OCTEON3:                                        \
 305                 __res = 0;                                              \
 306                 break;                                                  \
 307                                                                         \
 308         default:                                                        \
 309                 __res = 1;                                              \
 310         }                                                               \
 311                                                                         \
 312         __res;                                                          \
 313 })
 314 #endif
 315
 316 /*
 317  * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
 318  * pre-MIPS32/MIPS64 processors have CLO, CLZ.  The IDT RC64574 is 64-bit and
 319  * has CLO and CLZ but not DCLO nor DCLZ.  For 64-bit kernels
 320  * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
 321  */
 322 #ifndef cpu_has_clo_clz
 323 #define cpu_has_clo_clz cpu_has_mips_r
 324 #endif
 325
 326 /*
 327  * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
 328  * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
 329  * This indicates the availability of WSBH and in case of 64 bit CPUs also
 330  * DSBH and DSHD.
 331  */
 332 #ifndef cpu_has_wsbh
 333 #define cpu_has_wsbh            cpu_has_mips_r2
 334 #endif
 335
 336 #ifndef cpu_has_dsp
 337 #define cpu_has_dsp             (cpu_data[0].ases & MIPS_ASE_DSP)
 338 #endif
 339
 340 #ifndef cpu_has_dsp2
 341 #define cpu_has_dsp2            (cpu_data[0].ases & MIPS_ASE_DSP2P)
 342 #endif
 343
 344 #ifndef cpu_has_dsp3
 345 #define cpu_has_dsp3            (cpu_data[0].ases & MIPS_ASE_DSP3)
 346 #endif
 347
 348 #ifndef cpu_has_mipsmt
 349 #define cpu_has_mipsmt          (cpu_data[0].ases & MIPS_ASE_MIPSMT)
 350 #endif
 351
 352 #ifndef cpu_has_vp
 353 #define cpu_has_vp              (cpu_data[0].options & MIPS_CPU_VP)
 354 #endif
 355
 356 #ifndef cpu_has_userlocal
 357 #define cpu_has_userlocal       (cpu_data[0].options & MIPS_CPU_ULRI)
 358 #endif
 359
 360 #ifdef CONFIG_32BIT
 361 # ifndef cpu_has_nofpuex
 362 # define cpu_has_nofpuex        (cpu_data[0].options & MIPS_CPU_NOFPUEX)
 363 # endif
 364 # ifndef cpu_has_64bits
 365 # define cpu_has_64bits         (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
 366 # endif
 367 # ifndef cpu_has_64bit_zero_reg
 368 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
 369 # endif
 370 # ifndef cpu_has_64bit_gp_regs
 371 # define cpu_has_64bit_gp_regs          0
 372 # endif
 373 # ifndef cpu_has_64bit_addresses
 374 # define cpu_has_64bit_addresses        0
 375 # endif
 376 # ifndef cpu_vmbits
 377 # define cpu_vmbits 31
 378 # endif
 379 #endif
 380
 381 #ifdef CONFIG_64BIT
 382 # ifndef cpu_has_nofpuex
 383 # define cpu_has_nofpuex                0
 384 # endif
 385 # ifndef cpu_has_64bits
 386 # define cpu_has_64bits                 1
 387 # endif
 388 # ifndef cpu_has_64bit_zero_reg
 389 # define cpu_has_64bit_zero_reg         1
 390 # endif
 391 # ifndef cpu_has_64bit_gp_regs
 392 # define cpu_has_64bit_gp_regs          1
 393 # endif
 394 # ifndef cpu_has_64bit_addresses
 395 # define cpu_has_64bit_addresses        1
 396 # endif
 397 # ifndef cpu_vmbits
 398 # define cpu_vmbits cpu_data[0].vmbits
 399 # define __NEED_VMBITS_PROBE
 400 # endif
 401 #endif
 402
 403 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
 404 # define cpu_has_vint           (cpu_data[0].options & MIPS_CPU_VINT)
 405 #elif !defined(cpu_has_vint)
 406 # define cpu_has_vint                   0
 407 #endif
 408
 409 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
 410 # define cpu_has_veic           (cpu_data[0].options & MIPS_CPU_VEIC)
 411 #elif !defined(cpu_has_veic)
 412 # define cpu_has_veic                   0
 413 #endif
 414
 415 #ifndef cpu_has_inclusive_pcaches
 416 #define cpu_has_inclusive_pcaches       (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
 417 #endif
 418
 419 #ifndef cpu_dcache_line_size
 420 #define cpu_dcache_line_size()  cpu_data[0].dcache.linesz
 421 #endif
 422 #ifndef cpu_icache_line_size
 423 #define cpu_icache_line_size()  cpu_data[0].icache.linesz
 424 #endif
 425 #ifndef cpu_scache_line_size
 426 #define cpu_scache_line_size()  cpu_data[0].scache.linesz
 427 #endif
 428
 429 #ifndef cpu_hwrena_impl_bits
 430 #define cpu_hwrena_impl_bits            0
 431 #endif
 432
 433 #ifndef cpu_has_perf_cntr_intr_bit
 434 #define cpu_has_perf_cntr_intr_bit      (cpu_data[0].options & MIPS_CPU_PCI)
 435 #endif
 436
 437 #ifndef cpu_has_vz
 438 #define cpu_has_vz              (cpu_data[0].ases & MIPS_ASE_VZ)
 439 #endif
 440
 441 #if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
 442 # define cpu_has_msa            (cpu_data[0].ases & MIPS_ASE_MSA)
 443 #elif !defined(cpu_has_msa)
 444 # define cpu_has_msa            0
 445 #endif
 446
 447 #ifndef cpu_has_fre
 448 # define cpu_has_fre            (cpu_data[0].options & MIPS_CPU_FRE)
 449 #endif
 450
 451 #ifndef cpu_has_cdmm
 452 # define cpu_has_cdmm           (cpu_data[0].options & MIPS_CPU_CDMM)
 453 #endif
 454
 455 #ifndef cpu_has_small_pages
 456 # define cpu_has_small_pages    (cpu_data[0].options & MIPS_CPU_SP)
 457 #endif
 458
 459 #ifndef cpu_has_nan_legacy
 460 #define cpu_has_nan_legacy      (cpu_data[0].options & MIPS_CPU_NAN_LEGACY)
 461 #endif
 462 #ifndef cpu_has_nan_2008
 463 #define cpu_has_nan_2008        (cpu_data[0].options & MIPS_CPU_NAN_2008)
 464 #endif
 465
 466 #ifndef cpu_has_ebase_wg
 467 # define cpu_has_ebase_wg       (cpu_data[0].options & MIPS_CPU_EBASE_WG)
 468 #endif
 469
 470 #ifndef cpu_has_badinstr
 471 # define cpu_has_badinstr       (cpu_data[0].options & MIPS_CPU_BADINSTR)
 472 #endif
 473
 474 #ifndef cpu_has_badinstrp
 475 # define cpu_has_badinstrp      (cpu_data[0].options & MIPS_CPU_BADINSTRP)
 476 #endif
 477
 478 #ifndef cpu_has_contextconfig
 479 # define cpu_has_contextconfig  (cpu_data[0].options & MIPS_CPU_CTXTC)
 480 #endif
 481
 482 #ifndef cpu_has_perf
 483 # define cpu_has_perf           (cpu_data[0].options & MIPS_CPU_PERF)
 484 #endif
 485
 486 /*
 487  * Guest capabilities
 488  */
 489 #ifndef cpu_guest_has_conf1
 490 #define cpu_guest_has_conf1     (cpu_data[0].guest.conf & (1 << 1))
 491 #endif
 492 #ifndef cpu_guest_has_conf2
 493 #define cpu_guest_has_conf2     (cpu_data[0].guest.conf & (1 << 2))
 494 #endif
 495 #ifndef cpu_guest_has_conf3
 496 #define cpu_guest_has_conf3     (cpu_data[0].guest.conf & (1 << 3))
 497 #endif
 498 #ifndef cpu_guest_has_conf4
 499 #define cpu_guest_has_conf4     (cpu_data[0].guest.conf & (1 << 4))
 500 #endif
 501 #ifndef cpu_guest_has_conf5
 502 #define cpu_guest_has_conf5     (cpu_data[0].guest.conf & (1 << 5))
 503 #endif
 504 #ifndef cpu_guest_has_conf6
 505 #define cpu_guest_has_conf6     (cpu_data[0].guest.conf & (1 << 6))
 506 #endif
 507 #ifndef cpu_guest_has_conf7
 508 #define cpu_guest_has_conf7     (cpu_data[0].guest.conf & (1 << 7))
 509 #endif
 510 #ifndef cpu_guest_has_fpu
 511 #define cpu_guest_has_fpu       (cpu_data[0].guest.options & MIPS_CPU_FPU)
 512 #endif
 513 #ifndef cpu_guest_has_watch
 514 #define cpu_guest_has_watch     (cpu_data[0].guest.options & MIPS_CPU_WATCH)
 515 #endif
 516 #ifndef cpu_guest_has_contextconfig
 517 #define cpu_guest_has_contextconfig (cpu_data[0].guest.options & MIPS_CPU_CTXTC)
 518 #endif
 519 #ifndef cpu_guest_has_segments
 520 #define cpu_guest_has_segments  (cpu_data[0].guest.options & MIPS_CPU_SEGMENTS)
 521 #endif
 522 #ifndef cpu_guest_has_badinstr
 523 #define cpu_guest_has_badinstr  (cpu_data[0].guest.options & MIPS_CPU_BADINSTR)
 524 #endif
 525 #ifndef cpu_guest_has_badinstrp
 526 #define cpu_guest_has_badinstrp (cpu_data[0].guest.options & MIPS_CPU_BADINSTRP)
 527 #endif
 528 #ifndef cpu_guest_has_htw
 529 #define cpu_guest_has_htw       (cpu_data[0].guest.options & MIPS_CPU_HTW)
 530 #endif
 531 #ifndef cpu_guest_has_msa
 532 #define cpu_guest_has_msa       (cpu_data[0].guest.ases & MIPS_ASE_MSA)
 533 #endif
 534 #ifndef cpu_guest_has_kscr
 535 #define cpu_guest_has_kscr(n)   (cpu_data[0].guest.kscratch_mask & (1u << (n)))
 536 #endif
 537 #ifndef cpu_guest_has_rw_llb
 538 #define cpu_guest_has_rw_llb    (cpu_has_mips_r6 || (cpu_data[0].guest.options & MIPS_CPU_RW_LLB))
 539 #endif
 540 #ifndef cpu_guest_has_perf
 541 #define cpu_guest_has_perf      (cpu_data[0].guest.options & MIPS_CPU_PERF)
 542 #endif
 543 #ifndef cpu_guest_has_maar
 544 #define cpu_guest_has_maar      (cpu_data[0].guest.options & MIPS_CPU_MAAR)
 545 #endif
 546
 547 /*
 548  * Guest dynamic capabilities
 549  */
 550 #ifndef cpu_guest_has_dyn_fpu
 551 #define cpu_guest_has_dyn_fpu   (cpu_data[0].guest.options_dyn & MIPS_CPU_FPU)
 552 #endif
 553 #ifndef cpu_guest_has_dyn_watch
 554 #define cpu_guest_has_dyn_watch (cpu_data[0].guest.options_dyn & MIPS_CPU_WATCH)
 555 #endif
 556 #ifndef cpu_guest_has_dyn_contextconfig
 557 #define cpu_guest_has_dyn_contextconfig (cpu_data[0].guest.options_dyn & MIPS_CPU_CTXTC)
 558 #endif
 559 #ifndef cpu_guest_has_dyn_perf
 560 #define cpu_guest_has_dyn_perf  (cpu_data[0].guest.options_dyn & MIPS_CPU_PERF)
 561 #endif
 562 #ifndef cpu_guest_has_dyn_msa
 563 #define cpu_guest_has_dyn_msa   (cpu_data[0].guest.ases_dyn & MIPS_ASE_MSA)
 564 #endif
 565 #ifndef cpu_guest_has_dyn_maar
 566 #define cpu_guest_has_dyn_maar  (cpu_data[0].guest.options_dyn & MIPS_CPU_MAAR)
 567 #endif
 568
 569 #endif /* __ASM_CPU_FEATURES_H */