arch/mips/pistachio/init.c

   1 /*
   2  * Pistachio platform setup
   3  *
   4  * Copyright (C) 2014 Google, Inc.
   5  * Copyright (C) 2016 Imagination Technologies
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_fdt.h>
  17
  18 #include <asm/cacheflush.h>
  19 #include <asm/dma-coherence.h>
  20 #include <asm/fw/fw.h>
  21 #include <asm/mips-boards/generic.h>
  22 #include <asm/mips-cm.h>
  23 #include <asm/mips-cpc.h>
  24 #include <asm/prom.h>
  25 #include <asm/smp-ops.h>
  26 #include <asm/traps.h>
  27
  28 /*
  29  * Core revision register decoding
  30  * Bits 23 to 20: Major rev
  31  * Bits 15 to 8: Minor rev
  32  * Bits 7 to 0: Maintenance rev
  33  */
  34 #define PISTACHIO_CORE_REV_REG  0xB81483D0
  35 #define PISTACHIO_CORE_REV_A1   0x00100006
  36 #define PISTACHIO_CORE_REV_B0   0x00100106
  37
  38 const char *get_system_type(void)
  39 {
  40         u32 core_rev;
  41         const char *sys_type;
  42
  43         core_rev = __raw_readl((const void *)PISTACHIO_CORE_REV_REG);
  44
  45         switch (core_rev) {
  46         case PISTACHIO_CORE_REV_B0:
  47                 sys_type = "IMG Pistachio SoC (B0)";
  48                 break;
  49
  50         case PISTACHIO_CORE_REV_A1:
  51                 sys_type = "IMG Pistachio SoC (A1)";
  52                 break;
  53
  54         default:
  55                 sys_type = "IMG Pistachio SoC";
  56                 break;
  57         }
  58
  59         return sys_type;
  60 }
  61
  62 void __init *plat_get_fdt(void)
  63 {
  64         if (fw_arg0 != -2)
  65                 panic("Device-tree not present");
  66         return (void *)fw_arg1;
  67 }
  68
  69 void __init plat_mem_setup(void)
  70 {
  71         __dt_setup_arch(plat_get_fdt());
  72 }
  73
  74 #define DEFAULT_CPC_BASE_ADDR   0x1bde0000
  75 #define DEFAULT_CDMM_BASE_ADDR  0x1bdd0000
  76
  77 phys_addr_t mips_cpc_default_phys_base(void)
  78 {
  79         return DEFAULT_CPC_BASE_ADDR;
  80 }
  81
  82 phys_addr_t mips_cdmm_phys_base(void)
  83 {
  84         return DEFAULT_CDMM_BASE_ADDR;
  85 }
  86
  87 static void __init mips_nmi_setup(void)
  88 {
  89         void *base;
  90         extern char except_vec_nmi;
  91
  92         base = cpu_has_veic ?
  93                 (void *)(CAC_BASE + 0xa80) :
  94                 (void *)(CAC_BASE + 0x380);
  95         memcpy(base, &except_vec_nmi, 0x80);
  96         flush_icache_range((unsigned long)base,
  97                            (unsigned long)base + 0x80);
  98 }
  99
 100 static void __init mips_ejtag_setup(void)
 101 {
 102         void *base;
 103         extern char except_vec_ejtag_debug;
 104
 105         base = cpu_has_veic ?
 106                 (void *)(CAC_BASE + 0xa00) :
 107                 (void *)(CAC_BASE + 0x300);
 108         memcpy(base, &except_vec_ejtag_debug, 0x80);
 109         flush_icache_range((unsigned long)base,
 110                            (unsigned long)base + 0x80);
 111 }
 112
 113 void __init prom_init(void)
 114 {
 115         board_nmi_handler_setup = mips_nmi_setup;
 116         board_ejtag_handler_setup = mips_ejtag_setup;
 117
 118         mips_cm_probe();
 119         mips_cpc_probe();
 120         register_cps_smp_ops();
 121
 122         pr_info("SoC Type: %s\n", get_system_type());
 123 }
 124
 125 void __init prom_free_prom_memory(void)
 126 {
 127 }
 128
 129 void __init device_tree_init(void)
 130 {
 131         if (!initial_boot_params)
 132                 return;
 133
 134         unflatten_and_copy_device_tree();
 135 }