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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[cris-mirror.git] / arch / mips / ralink / mt7620.c
blob3c7c9bf57bf36cac56de4c7d9e8df527f0acac88
1 /*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Parts of this file are based on Ralink's 2.6.21 BSP
7 *
8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
10 * Copyright (C) 2013 John Crispin <john@phrozen.org>
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/module.h>
16
17 #include <asm/mipsregs.h>
18 #include <asm/mach-ralink/ralink_regs.h>
19 #include <asm/mach-ralink/mt7620.h>
20 #include <asm/mach-ralink/pinmux.h>
21
22 #include "common.h"
23
24 /* analog */
25 #define PMU0_CFG 0x88
26 #define PMU_SW_SET BIT(28)
27 #define A_DCDC_EN BIT(24)
28 #define A_SSC_PERI BIT(19)
29 #define A_SSC_GEN BIT(18)
30 #define A_SSC_M 0x3
31 #define A_SSC_S 16
32 #define A_DLY_M 0x7
33 #define A_DLY_S 8
34 #define A_VTUNE_M 0xff
35
36 /* digital */
37 #define PMU1_CFG 0x8C
38 #define DIG_SW_SEL BIT(25)
39
40 /* clock scaling */
41 #define CLKCFG_FDIV_MASK 0x1f00
42 #define CLKCFG_FDIV_USB_VAL 0x0300
43 #define CLKCFG_FFRAC_MASK 0x001f
44 #define CLKCFG_FFRAC_USB_VAL 0x0003
45
46 /* EFUSE bits */
47 #define EFUSE_MT7688 0x100000
48
49 /* DRAM type bit */
50 #define DRAM_TYPE_MT7628_MASK 0x1
51
52 /* does the board have sdram or ddram */
53 static int dram_type;
54
55 static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
56 static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
57 static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
58 static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
59 static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
60 static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
61 static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
62 static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
63 static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
64 static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
65 static struct rt2880_pmx_func uartf_grp[] = {
66 FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
67 FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
68 FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
69 FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
70 FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
71 FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
72 FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
73 };
74 static struct rt2880_pmx_func wdt_grp[] = {
75 FUNC("wdt rst", 0, 17, 1),
76 FUNC("wdt refclk", 0, 17, 1),
77 };
78 static struct rt2880_pmx_func pcie_rst_grp[] = {
79 FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
80 FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
81 };
82 static struct rt2880_pmx_func nd_sd_grp[] = {
83 FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
84 FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15)
85 };
86
87 static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
88 GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
89 GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
90 MT7620_GPIO_MODE_UART0_SHIFT),
91 GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
92 GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
93 GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
94 MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
95 GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
96 GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
97 GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
98 GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
99 MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
100 GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
101 MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
102 GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
103 GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
104 GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
105 GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
106 { 0 }
107 };
108
109 static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
110 FUNC("sdxc d6", 3, 19, 1),
111 FUNC("utif", 2, 19, 1),
112 FUNC("gpio", 1, 19, 1),
113 FUNC("pwm1", 0, 19, 1),
114 };
115
116 static struct rt2880_pmx_func pwm0_grp_mt7628[] = {
117 FUNC("sdxc d7", 3, 18, 1),
118 FUNC("utif", 2, 18, 1),
119 FUNC("gpio", 1, 18, 1),
120 FUNC("pwm0", 0, 18, 1),
121 };
122
123 static struct rt2880_pmx_func uart2_grp_mt7628[] = {
124 FUNC("sdxc d5 d4", 3, 20, 2),
125 FUNC("pwm", 2, 20, 2),
126 FUNC("gpio", 1, 20, 2),
127 FUNC("uart2", 0, 20, 2),
128 };
129
130 static struct rt2880_pmx_func uart1_grp_mt7628[] = {
131 FUNC("sw_r", 3, 45, 2),
132 FUNC("pwm", 2, 45, 2),
133 FUNC("gpio", 1, 45, 2),
134 FUNC("uart1", 0, 45, 2),
135 };
136
137 static struct rt2880_pmx_func i2c_grp_mt7628[] = {
138 FUNC("-", 3, 4, 2),
139 FUNC("debug", 2, 4, 2),
140 FUNC("gpio", 1, 4, 2),
141 FUNC("i2c", 0, 4, 2),
142 };
143
144 static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("reclk", 0, 36, 1) };
145 static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 37, 1) };
146 static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 38, 1) };
147 static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) };
148
149 static struct rt2880_pmx_func sd_mode_grp_mt7628[] = {
150 FUNC("jtag", 3, 22, 8),
151 FUNC("utif", 2, 22, 8),
152 FUNC("gpio", 1, 22, 8),
153 FUNC("sdxc", 0, 22, 8),
154 };
155
156 static struct rt2880_pmx_func uart0_grp_mt7628[] = {
157 FUNC("-", 3, 12, 2),
158 FUNC("-", 2, 12, 2),
159 FUNC("gpio", 1, 12, 2),
160 FUNC("uart0", 0, 12, 2),
161 };
162
163 static struct rt2880_pmx_func i2s_grp_mt7628[] = {
164 FUNC("antenna", 3, 0, 4),
165 FUNC("pcm", 2, 0, 4),
166 FUNC("gpio", 1, 0, 4),
167 FUNC("i2s", 0, 0, 4),
168 };
169
170 static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = {
171 FUNC("-", 3, 6, 1),
172 FUNC("refclk", 2, 6, 1),
173 FUNC("gpio", 1, 6, 1),
174 FUNC("spi cs1", 0, 6, 1),
175 };
176
177 static struct rt2880_pmx_func spis_grp_mt7628[] = {
178 FUNC("pwm_uart2", 3, 14, 4),
179 FUNC("util", 2, 14, 4),
180 FUNC("gpio", 1, 14, 4),
181 FUNC("spis", 0, 14, 4),
182 };
183
184 static struct rt2880_pmx_func gpio_grp_mt7628[] = {
185 FUNC("pcie", 3, 11, 1),
186 FUNC("refclk", 2, 11, 1),
187 FUNC("gpio", 1, 11, 1),
188 FUNC("gpio", 0, 11, 1),
189 };
190
191 static struct rt2880_pmx_func p4led_kn_grp_mt7628[] = {
192 FUNC("jtag", 3, 30, 1),
193 FUNC("util", 2, 30, 1),
194 FUNC("gpio", 1, 30, 1),
195 FUNC("p4led_kn", 0, 30, 1),
196 };
197
198 static struct rt2880_pmx_func p3led_kn_grp_mt7628[] = {
199 FUNC("jtag", 3, 31, 1),
200 FUNC("util", 2, 31, 1),
201 FUNC("gpio", 1, 31, 1),
202 FUNC("p3led_kn", 0, 31, 1),
203 };
204
205 static struct rt2880_pmx_func p2led_kn_grp_mt7628[] = {
206 FUNC("jtag", 3, 32, 1),
207 FUNC("util", 2, 32, 1),
208 FUNC("gpio", 1, 32, 1),
209 FUNC("p2led_kn", 0, 32, 1),
210 };
211
212 static struct rt2880_pmx_func p1led_kn_grp_mt7628[] = {
213 FUNC("jtag", 3, 33, 1),
214 FUNC("util", 2, 33, 1),
215 FUNC("gpio", 1, 33, 1),
216 FUNC("p1led_kn", 0, 33, 1),
217 };
218
219 static struct rt2880_pmx_func p0led_kn_grp_mt7628[] = {
220 FUNC("jtag", 3, 34, 1),
221 FUNC("rsvd", 2, 34, 1),
222 FUNC("gpio", 1, 34, 1),
223 FUNC("p0led_kn", 0, 34, 1),
224 };
225
226 static struct rt2880_pmx_func wled_kn_grp_mt7628[] = {
227 FUNC("rsvd", 3, 35, 1),
228 FUNC("rsvd", 2, 35, 1),
229 FUNC("gpio", 1, 35, 1),
230 FUNC("wled_kn", 0, 35, 1),
231 };
232
233 static struct rt2880_pmx_func p4led_an_grp_mt7628[] = {
234 FUNC("jtag", 3, 39, 1),
235 FUNC("util", 2, 39, 1),
236 FUNC("gpio", 1, 39, 1),
237 FUNC("p4led_an", 0, 39, 1),
238 };
239
240 static struct rt2880_pmx_func p3led_an_grp_mt7628[] = {
241 FUNC("jtag", 3, 40, 1),
242 FUNC("util", 2, 40, 1),
243 FUNC("gpio", 1, 40, 1),
244 FUNC("p3led_an", 0, 40, 1),
245 };
246
247 static struct rt2880_pmx_func p2led_an_grp_mt7628[] = {
248 FUNC("jtag", 3, 41, 1),
249 FUNC("util", 2, 41, 1),
250 FUNC("gpio", 1, 41, 1),
251 FUNC("p2led_an", 0, 41, 1),
252 };
253
254 static struct rt2880_pmx_func p1led_an_grp_mt7628[] = {
255 FUNC("jtag", 3, 42, 1),
256 FUNC("util", 2, 42, 1),
257 FUNC("gpio", 1, 42, 1),
258 FUNC("p1led_an", 0, 42, 1),
259 };
260
261 static struct rt2880_pmx_func p0led_an_grp_mt7628[] = {
262 FUNC("jtag", 3, 43, 1),
263 FUNC("rsvd", 2, 43, 1),
264 FUNC("gpio", 1, 43, 1),
265 FUNC("p0led_an", 0, 43, 1),
266 };
267
268 static struct rt2880_pmx_func wled_an_grp_mt7628[] = {
269 FUNC("rsvd", 3, 44, 1),
270 FUNC("rsvd", 2, 44, 1),
271 FUNC("gpio", 1, 44, 1),
272 FUNC("wled_an", 0, 44, 1),
273 };
274
275 #define MT7628_GPIO_MODE_MASK 0x3
276
277 #define MT7628_GPIO_MODE_P4LED_KN 58
278 #define MT7628_GPIO_MODE_P3LED_KN 56
279 #define MT7628_GPIO_MODE_P2LED_KN 54
280 #define MT7628_GPIO_MODE_P1LED_KN 52
281 #define MT7628_GPIO_MODE_P0LED_KN 50
282 #define MT7628_GPIO_MODE_WLED_KN 48
283 #define MT7628_GPIO_MODE_P4LED_AN 42
284 #define MT7628_GPIO_MODE_P3LED_AN 40
285 #define MT7628_GPIO_MODE_P2LED_AN 38
286 #define MT7628_GPIO_MODE_P1LED_AN 36
287 #define MT7628_GPIO_MODE_P0LED_AN 34
288 #define MT7628_GPIO_MODE_WLED_AN 32
289 #define MT7628_GPIO_MODE_PWM1 30
290 #define MT7628_GPIO_MODE_PWM0 28
291 #define MT7628_GPIO_MODE_UART2 26
292 #define MT7628_GPIO_MODE_UART1 24
293 #define MT7628_GPIO_MODE_I2C 20
294 #define MT7628_GPIO_MODE_REFCLK 18
295 #define MT7628_GPIO_MODE_PERST 16
296 #define MT7628_GPIO_MODE_WDT 14
297 #define MT7628_GPIO_MODE_SPI 12
298 #define MT7628_GPIO_MODE_SDMODE 10
299 #define MT7628_GPIO_MODE_UART0 8
300 #define MT7628_GPIO_MODE_I2S 6
301 #define MT7628_GPIO_MODE_CS1 4
302 #define MT7628_GPIO_MODE_SPIS 2
303 #define MT7628_GPIO_MODE_GPIO 0
304
305 static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
306 GRP_G("pwm1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK,
307 1, MT7628_GPIO_MODE_PWM1),
308 GRP_G("pwm0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK,
309 1, MT7628_GPIO_MODE_PWM0),
310 GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK,
311 1, MT7628_GPIO_MODE_UART2),
312 GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK,
313 1, MT7628_GPIO_MODE_UART1),
314 GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK,
315 1, MT7628_GPIO_MODE_I2C),
316 GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK),
317 GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST),
318 GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT),
319 GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI),
320 GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK,
321 1, MT7628_GPIO_MODE_SDMODE),
322 GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK,
323 1, MT7628_GPIO_MODE_UART0),
324 GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK,
325 1, MT7628_GPIO_MODE_I2S),
326 GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK,
327 1, MT7628_GPIO_MODE_CS1),
328 GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK,
329 1, MT7628_GPIO_MODE_SPIS),
330 GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK,
331 1, MT7628_GPIO_MODE_GPIO),
332 GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
333 1, MT7628_GPIO_MODE_WLED_AN),
334 GRP_G("p0led_an", p0led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
335 1, MT7628_GPIO_MODE_P0LED_AN),
336 GRP_G("p1led_an", p1led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
337 1, MT7628_GPIO_MODE_P1LED_AN),
338 GRP_G("p2led_an", p2led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
339 1, MT7628_GPIO_MODE_P2LED_AN),
340 GRP_G("p3led_an", p3led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
341 1, MT7628_GPIO_MODE_P3LED_AN),
342 GRP_G("p4led_an", p4led_an_grp_mt7628, MT7628_GPIO_MODE_MASK,
343 1, MT7628_GPIO_MODE_P4LED_AN),
344 GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
345 1, MT7628_GPIO_MODE_WLED_KN),
346 GRP_G("p0led_kn", p0led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
347 1, MT7628_GPIO_MODE_P0LED_KN),
348 GRP_G("p1led_kn", p1led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
349 1, MT7628_GPIO_MODE_P1LED_KN),
350 GRP_G("p2led_kn", p2led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
351 1, MT7628_GPIO_MODE_P2LED_KN),
352 GRP_G("p3led_kn", p3led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
353 1, MT7628_GPIO_MODE_P3LED_KN),
354 GRP_G("p4led_kn", p4led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK,
355 1, MT7628_GPIO_MODE_P4LED_KN),
356 { 0 }
357 };
358
359 static inline int is_mt76x8(void)
360 {
361 return ralink_soc == MT762X_SOC_MT7628AN ||
362 ralink_soc == MT762X_SOC_MT7688;
363 }
364
365 static __init u32
366 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
367 {
368 u64 t;
369
370 t = ref_rate;
371 t *= mul;
372 do_div(t, div);
373
374 return t;
375 }
376
377 #define MHZ(x) ((x) * 1000 * 1000)
378
379 static __init unsigned long
380 mt7620_get_xtal_rate(void)
381 {
382 u32 reg;
383
384 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
385 if (reg & SYSCFG0_XTAL_FREQ_SEL)
386 return MHZ(40);
387
388 return MHZ(20);
389 }
390
391 static __init unsigned long
392 mt7620_get_periph_rate(unsigned long xtal_rate)
393 {
394 u32 reg;
395
396 reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
397 if (reg & CLKCFG0_PERI_CLK_SEL)
398 return xtal_rate;
399
400 return MHZ(40);
401 }
402
403 static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
404
405 static __init unsigned long
406 mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
407 {
408 u32 reg;
409 u32 mul;
410 u32 div;
411
412 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
413 if (reg & CPLL_CFG0_BYPASS_REF_CLK)
414 return xtal_rate;
415
416 if ((reg & CPLL_CFG0_SW_CFG) == 0)
417 return MHZ(600);
418
419 mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
420 CPLL_CFG0_PLL_MULT_RATIO_MASK;
421 mul += 24;
422 if (reg & CPLL_CFG0_LC_CURFCK)
423 mul *= 2;
424
425 div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
426 CPLL_CFG0_PLL_DIV_RATIO_MASK;
427
428 WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
429
430 return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
431 }
432
433 static __init unsigned long
434 mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
435 {
436 u32 reg;
437
438 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
439 if (reg & CPLL_CFG1_CPU_AUX1)
440 return xtal_rate;
441
442 if (reg & CPLL_CFG1_CPU_AUX0)
443 return MHZ(480);
444
445 return cpu_pll_rate;
446 }
447
448 static __init unsigned long
449 mt7620_get_cpu_rate(unsigned long pll_rate)
450 {
451 u32 reg;
452 u32 mul;
453 u32 div;
454
455 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
456
457 mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
458 div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
459 CPU_SYS_CLKCFG_CPU_FDIV_MASK;
460
461 return mt7620_calc_rate(pll_rate, mul, div);
462 }
463
464 static const u32 mt7620_ocp_dividers[16] __initconst = {
465 [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
466 [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
467 [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
468 [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
469 [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
470 };
471
472 static __init unsigned long
473 mt7620_get_dram_rate(unsigned long pll_rate)
474 {
475 if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
476 return pll_rate / 4;
477
478 return pll_rate / 3;
479 }
480
481 static __init unsigned long
482 mt7620_get_sys_rate(unsigned long cpu_rate)
483 {
484 u32 reg;
485 u32 ocp_ratio;
486 u32 div;
487
488 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
489
490 ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
491 CPU_SYS_CLKCFG_OCP_RATIO_MASK;
492
493 if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
494 return cpu_rate;
495
496 div = mt7620_ocp_dividers[ocp_ratio];
497 if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
498 return cpu_rate;
499
500 return cpu_rate / div;
501 }
502
503 void __init ralink_clk_init(void)
504 {
505 unsigned long xtal_rate;
506 unsigned long cpu_pll_rate;
507 unsigned long pll_rate;
508 unsigned long cpu_rate;
509 unsigned long sys_rate;
510 unsigned long dram_rate;
511 unsigned long periph_rate;
512
513 xtal_rate = mt7620_get_xtal_rate();
514
515 #define RFMT(label) label ":%lu.%03luMHz "
516 #define RINT(x) ((x) / 1000000)
517 #define RFRAC(x) (((x) / 1000) % 1000)
518
519 if (is_mt76x8()) {
520 if (xtal_rate == MHZ(40))
521 cpu_rate = MHZ(580);
522 else
523 cpu_rate = MHZ(575);
524 dram_rate = sys_rate = cpu_rate / 3;
525 periph_rate = MHZ(40);
526
527 ralink_clk_add("10000d00.uartlite", periph_rate);
528 ralink_clk_add("10000e00.uartlite", periph_rate);
529 } else {
530 cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
531 pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
532
533 cpu_rate = mt7620_get_cpu_rate(pll_rate);
534 dram_rate = mt7620_get_dram_rate(pll_rate);
535 sys_rate = mt7620_get_sys_rate(cpu_rate);
536 periph_rate = mt7620_get_periph_rate(xtal_rate);
537
538 pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
539 RINT(xtal_rate), RFRAC(xtal_rate),
540 RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
541 RINT(pll_rate), RFRAC(pll_rate));
542
543 ralink_clk_add("10000500.uart", periph_rate);
544 }
545
546 pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
547 RINT(cpu_rate), RFRAC(cpu_rate),
548 RINT(dram_rate), RFRAC(dram_rate),
549 RINT(sys_rate), RFRAC(sys_rate),
550 RINT(periph_rate), RFRAC(periph_rate));
551 #undef RFRAC
552 #undef RINT
553 #undef RFMT
554
555 ralink_clk_add("cpu", cpu_rate);
556 ralink_clk_add("10000100.timer", periph_rate);
557 ralink_clk_add("10000120.watchdog", periph_rate);
558 ralink_clk_add("10000b00.spi", sys_rate);
559 ralink_clk_add("10000b40.spi", sys_rate);
560 ralink_clk_add("10000c00.uartlite", periph_rate);
561 ralink_clk_add("10000d00.uart1", periph_rate);
562 ralink_clk_add("10000e00.uart2", periph_rate);
563 ralink_clk_add("10180000.wmac", xtal_rate);
564
565 if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
566 /*
567 * When the CPU goes into sleep mode, the BUS clock will be
568 * too low for USB to function properly. Adjust the busses
569 * fractional divider to fix this
570 */
571 u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
572
573 val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
574 val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
575
576 rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
577 }
578 }
579
580 void __init ralink_of_remap(void)
581 {
582 rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
583 rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
584
585 if (!rt_sysc_membase || !rt_memc_membase)
586 panic("Failed to remap core resources");
587 }
588
589 static __init void
590 mt7620_dram_init(struct ralink_soc_info *soc_info)
591 {
592 switch (dram_type) {
593 case SYSCFG0_DRAM_TYPE_SDRAM:
594 pr_info("Board has SDRAM\n");
595 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
596 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
597 break;
598
599 case SYSCFG0_DRAM_TYPE_DDR1:
600 pr_info("Board has DDR1\n");
601 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
602 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
603 break;
604
605 case SYSCFG0_DRAM_TYPE_DDR2:
606 pr_info("Board has DDR2\n");
607 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
608 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
609 break;
610 default:
611 BUG();
612 }
613 }
614
615 static __init void
616 mt7628_dram_init(struct ralink_soc_info *soc_info)
617 {
618 switch (dram_type) {
619 case SYSCFG0_DRAM_TYPE_DDR1_MT7628:
620 pr_info("Board has DDR1\n");
621 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
622 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
623 break;
624
625 case SYSCFG0_DRAM_TYPE_DDR2_MT7628:
626 pr_info("Board has DDR2\n");
627 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
628 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
629 break;
630 default:
631 BUG();
632 }
633 }
634
635 void prom_soc_init(struct ralink_soc_info *soc_info)
636 {
637 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
638 unsigned char *name = NULL;
639 u32 n0;
640 u32 n1;
641 u32 rev;
642 u32 cfg0;
643 u32 pmu0;
644 u32 pmu1;
645 u32 bga;
646
647 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
648 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
649 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
650 bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
651
652 if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
653 if (bga) {
654 ralink_soc = MT762X_SOC_MT7620A;
655 name = "MT7620A";
656 soc_info->compatible = "ralink,mt7620a-soc";
657 } else {
658 ralink_soc = MT762X_SOC_MT7620N;
659 name = "MT7620N";
660 soc_info->compatible = "ralink,mt7620n-soc";
661 }
662 } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
663 u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
664
665 if (efuse & EFUSE_MT7688) {
666 ralink_soc = MT762X_SOC_MT7688;
667 name = "MT7688";
668 } else {
669 ralink_soc = MT762X_SOC_MT7628AN;
670 name = "MT7628AN";
671 }
672 soc_info->compatible = "ralink,mt7628an-soc";
673 } else {
674 panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
675 }
676
677 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
678 "MediaTek %s ver:%u eco:%u",
679 name,
680 (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
681 (rev & CHIP_REV_ECO_MASK));
682
683 cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
684 if (is_mt76x8()) {
685 dram_type = cfg0 & DRAM_TYPE_MT7628_MASK;
686 } else {
687 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) &
688 SYSCFG0_DRAM_TYPE_MASK;
689 if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN)
690 dram_type = SYSCFG0_DRAM_TYPE_SDRAM;
691 }
692
693 soc_info->mem_base = MT7620_DRAM_BASE;
694 if (is_mt76x8())
695 mt7628_dram_init(soc_info);
696 else
697 mt7620_dram_init(soc_info);
698
699 pmu0 = __raw_readl(sysc + PMU0_CFG);
700 pmu1 = __raw_readl(sysc + PMU1_CFG);
701
702 pr_info("Analog PMU set to %s control\n",
703 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
704 pr_info("Digital PMU set to %s control\n",
705 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
706
707 if (is_mt76x8())
708 rt2880_pinmux_data = mt7628an_pinmux_data;
709 else
710 rt2880_pinmux_data = mt7620a_pinmux_data;
711 }
CRIS linux kernel tree