drivers/mmc/host/dw_mmc-exynos.c

   1 /*
   2  * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
   3  *
   4  * Copyright (C) 2012, Samsung Electronics Co., Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/mmc/host.h>
  16 #include <linux/mmc/dw_mmc.h>
  17 #include <linux/mmc/mmc.h>
  18 #include <linux/of.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/slab.h>
  21
  22 #include "dw_mmc.h"
  23 #include "dw_mmc-pltfm.h"
  24 #include "dw_mmc-exynos.h"
  25
  26 /* Variations in Exynos specific dw-mshc controller */
  27 enum dw_mci_exynos_type {
  28         DW_MCI_TYPE_EXYNOS4210,
  29         DW_MCI_TYPE_EXYNOS4412,
  30         DW_MCI_TYPE_EXYNOS5250,
  31         DW_MCI_TYPE_EXYNOS5420,
  32         DW_MCI_TYPE_EXYNOS5420_SMU,
  33         DW_MCI_TYPE_EXYNOS7,
  34         DW_MCI_TYPE_EXYNOS7_SMU,
  35 };
  36
  37 /* Exynos implementation specific driver private data */
  38 struct dw_mci_exynos_priv_data {
  39         enum dw_mci_exynos_type         ctrl_type;
  40         u8                              ciu_div;
  41         u32                             sdr_timing;
  42         u32                             ddr_timing;
  43         u32                             hs400_timing;
  44         u32                             tuned_sample;
  45         u32                             cur_speed;
  46         u32                             dqs_delay;
  47         u32                             saved_dqs_en;
  48         u32                             saved_strobe_ctrl;
  49 };
  50
  51 static struct dw_mci_exynos_compatible {
  52         char                            *compatible;
  53         enum dw_mci_exynos_type         ctrl_type;
  54 } exynos_compat[] = {
  55         {
  56                 .compatible     = "samsung,exynos4210-dw-mshc",
  57                 .ctrl_type      = DW_MCI_TYPE_EXYNOS4210,
  58         }, {
  59                 .compatible     = "samsung,exynos4412-dw-mshc",
  60                 .ctrl_type      = DW_MCI_TYPE_EXYNOS4412,
  61         }, {
  62                 .compatible     = "samsung,exynos5250-dw-mshc",
  63                 .ctrl_type      = DW_MCI_TYPE_EXYNOS5250,
  64         }, {
  65                 .compatible     = "samsung,exynos5420-dw-mshc",
  66                 .ctrl_type      = DW_MCI_TYPE_EXYNOS5420,
  67         }, {
  68                 .compatible     = "samsung,exynos5420-dw-mshc-smu",
  69                 .ctrl_type      = DW_MCI_TYPE_EXYNOS5420_SMU,
  70         }, {
  71                 .compatible     = "samsung,exynos7-dw-mshc",
  72                 .ctrl_type      = DW_MCI_TYPE_EXYNOS7,
  73         }, {
  74                 .compatible     = "samsung,exynos7-dw-mshc-smu",
  75                 .ctrl_type      = DW_MCI_TYPE_EXYNOS7_SMU,
  76         },
  77 };
  78
  79 static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host)
  80 {
  81         struct dw_mci_exynos_priv_data *priv = host->priv;
  82
  83         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
  84                 return EXYNOS4412_FIXED_CIU_CLK_DIV;
  85         else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
  86                 return EXYNOS4210_FIXED_CIU_CLK_DIV;
  87         else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
  88                         priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
  89                 return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1;
  90         else
  91                 return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1;
  92 }
  93
  94 static void dw_mci_exynos_config_smu(struct dw_mci *host)
  95 {
  96         struct dw_mci_exynos_priv_data *priv = host->priv;
  97
  98         /*
  99          * If Exynos is provided the Security management,
 100          * set for non-ecryption mode at this time.
 101          */
 102         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU ||
 103                 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
 104                 mci_writel(host, MPSBEGIN0, 0);
 105                 mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX);
 106                 mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT |
 107                            SDMMC_MPSCTRL_NON_SECURE_READ_BIT |
 108                            SDMMC_MPSCTRL_VALID |
 109                            SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT);
 110         }
 111 }
 112
 113 static int dw_mci_exynos_priv_init(struct dw_mci *host)
 114 {
 115         struct dw_mci_exynos_priv_data *priv = host->priv;
 116
 117         dw_mci_exynos_config_smu(host);
 118
 119         if (priv->ctrl_type >= DW_MCI_TYPE_EXYNOS5420) {
 120                 priv->saved_strobe_ctrl = mci_readl(host, HS400_DLINE_CTRL);
 121                 priv->saved_dqs_en = mci_readl(host, HS400_DQS_EN);
 122                 priv->saved_dqs_en |= AXI_NON_BLOCKING_WR;
 123                 mci_writel(host, HS400_DQS_EN, priv->saved_dqs_en);
 124                 if (!priv->dqs_delay)
 125                         priv->dqs_delay =
 126                                 DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl);
 127         }
 128
 129         host->bus_hz /= (priv->ciu_div + 1);
 130
 131         return 0;
 132 }
 133
 134 static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing)
 135 {
 136         struct dw_mci_exynos_priv_data *priv = host->priv;
 137         u32 clksel;
 138
 139         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 140                 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 141                 clksel = mci_readl(host, CLKSEL64);
 142         else
 143                 clksel = mci_readl(host, CLKSEL);
 144
 145         clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing;
 146
 147         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 148                 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 149                 mci_writel(host, CLKSEL64, clksel);
 150         else
 151                 mci_writel(host, CLKSEL, clksel);
 152
 153         /*
 154          * Exynos4412 and Exynos5250 extends the use of CMD register with the
 155          * use of bit 29 (which is reserved on standard MSHC controllers) for
 156          * optionally bypassing the HOLD register for command and data. The
 157          * HOLD register should be bypassed in case there is no phase shift
 158          * applied on CMD/DATA that is sent to the card.
 159          */
 160         if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->cur_slot)
 161                 set_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags);
 162 }
 163
 164 #ifdef CONFIG_PM_SLEEP
 165 static int dw_mci_exynos_suspend(struct device *dev)
 166 {
 167         struct dw_mci *host = dev_get_drvdata(dev);
 168
 169         return dw_mci_suspend(host);
 170 }
 171
 172 static int dw_mci_exynos_resume(struct device *dev)
 173 {
 174         struct dw_mci *host = dev_get_drvdata(dev);
 175
 176         dw_mci_exynos_config_smu(host);
 177         return dw_mci_resume(host);
 178 }
 179
 180 /**
 181  * dw_mci_exynos_resume_noirq - Exynos-specific resume code
 182  *
 183  * On exynos5420 there is a silicon errata that will sometimes leave the
 184  * WAKEUP_INT bit in the CLKSEL register asserted.  This bit is 1 to indicate
 185  * that it fired and we can clear it by writing a 1 back.  Clear it to prevent
 186  * interrupts from going off constantly.
 187  *
 188  * We run this code on all exynos variants because it doesn't hurt.
 189  */
 190
 191 static int dw_mci_exynos_resume_noirq(struct device *dev)
 192 {
 193         struct dw_mci *host = dev_get_drvdata(dev);
 194         struct dw_mci_exynos_priv_data *priv = host->priv;
 195         u32 clksel;
 196
 197         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 198                 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 199                 clksel = mci_readl(host, CLKSEL64);
 200         else
 201                 clksel = mci_readl(host, CLKSEL);
 202
 203         if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
 204                 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 205                         priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 206                         mci_writel(host, CLKSEL64, clksel);
 207                 else
 208                         mci_writel(host, CLKSEL, clksel);
 209         }
 210
 211         return 0;
 212 }
 213 #else
 214 #define dw_mci_exynos_suspend           NULL
 215 #define dw_mci_exynos_resume            NULL
 216 #define dw_mci_exynos_resume_noirq      NULL
 217 #endif /* CONFIG_PM_SLEEP */
 218
 219 static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
 220 {
 221         struct dw_mci_exynos_priv_data *priv = host->priv;
 222         u32 dqs, strobe;
 223
 224         /*
 225          * Not supported to configure register
 226          * related to HS400
 227          */
 228         if (priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420)
 229                 return;
 230
 231         dqs = priv->saved_dqs_en;
 232         strobe = priv->saved_strobe_ctrl;
 233
 234         if (timing == MMC_TIMING_MMC_HS400) {
 235                 dqs |= DATA_STROBE_EN;
 236                 strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);
 237         } else {
 238                 dqs &= ~DATA_STROBE_EN;
 239         }
 240
 241         mci_writel(host, HS400_DQS_EN, dqs);
 242         mci_writel(host, HS400_DLINE_CTRL, strobe);
 243 }
 244
 245 static void dw_mci_exynos_adjust_clock(struct dw_mci *host, unsigned int wanted)
 246 {
 247         struct dw_mci_exynos_priv_data *priv = host->priv;
 248         unsigned long actual;
 249         u8 div;
 250         int ret;
 251         /*
 252          * Don't care if wanted clock is zero or
 253          * ciu clock is unavailable
 254          */
 255         if (!wanted || IS_ERR(host->ciu_clk))
 256                 return;
 257
 258         /* Guaranteed minimum frequency for cclkin */
 259         if (wanted < EXYNOS_CCLKIN_MIN)
 260                 wanted = EXYNOS_CCLKIN_MIN;
 261
 262         if (wanted == priv->cur_speed)
 263                 return;
 264
 265         div = dw_mci_exynos_get_ciu_div(host);
 266         ret = clk_set_rate(host->ciu_clk, wanted * div);
 267         if (ret)
 268                 dev_warn(host->dev,
 269                         "failed to set clk-rate %u error: %d\n",
 270                         wanted * div, ret);
 271         actual = clk_get_rate(host->ciu_clk);
 272         host->bus_hz = actual / div;
 273         priv->cur_speed = wanted;
 274         host->current_speed = 0;
 275 }
 276
 277 static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
 278 {
 279         struct dw_mci_exynos_priv_data *priv = host->priv;
 280         unsigned int wanted = ios->clock;
 281         u32 timing = ios->timing, clksel;
 282
 283         switch (timing) {
 284         case MMC_TIMING_MMC_HS400:
 285                 /* Update tuned sample timing */
 286                 clksel = SDMMC_CLKSEL_UP_SAMPLE(
 287                                 priv->hs400_timing, priv->tuned_sample);
 288                 wanted <<= 1;
 289                 break;
 290         case MMC_TIMING_MMC_DDR52:
 291                 clksel = priv->ddr_timing;
 292                 /* Should be double rate for DDR mode */
 293                 if (ios->bus_width == MMC_BUS_WIDTH_8)
 294                         wanted <<= 1;
 295                 break;
 296         default:
 297                 clksel = priv->sdr_timing;
 298         }
 299
 300         /* Set clock timing for the requested speed mode*/
 301         dw_mci_exynos_set_clksel_timing(host, clksel);
 302
 303         /* Configure setting for HS400 */
 304         dw_mci_exynos_config_hs400(host, timing);
 305
 306         /* Configure clock rate */
 307         dw_mci_exynos_adjust_clock(host, wanted);
 308 }
 309
 310 static int dw_mci_exynos_parse_dt(struct dw_mci *host)
 311 {
 312         struct dw_mci_exynos_priv_data *priv;
 313         struct device_node *np = host->dev->of_node;
 314         u32 timing[2];
 315         u32 div = 0;
 316         int idx;
 317         int ret;
 318
 319         priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
 320         if (!priv)
 321                 return -ENOMEM;
 322
 323         for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
 324                 if (of_device_is_compatible(np, exynos_compat[idx].compatible))
 325                         priv->ctrl_type = exynos_compat[idx].ctrl_type;
 326         }
 327
 328         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
 329                 priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1;
 330         else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
 331                 priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1;
 332         else {
 333                 of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
 334                 priv->ciu_div = div;
 335         }
 336
 337         ret = of_property_read_u32_array(np,
 338                         "samsung,dw-mshc-sdr-timing", timing, 2);
 339         if (ret)
 340                 return ret;
 341
 342         priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
 343
 344         ret = of_property_read_u32_array(np,
 345                         "samsung,dw-mshc-ddr-timing", timing, 2);
 346         if (ret)
 347                 return ret;
 348
 349         priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
 350
 351         ret = of_property_read_u32_array(np,
 352                         "samsung,dw-mshc-hs400-timing", timing, 2);
 353         if (!ret && of_property_read_u32(np,
 354                                 "samsung,read-strobe-delay", &priv->dqs_delay))
 355                 dev_dbg(host->dev,
 356                         "read-strobe-delay is not found, assuming usage of default value\n");
 357
 358         priv->hs400_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1],
 359                                                 HS400_FIXED_CIU_CLK_DIV);
 360         host->priv = priv;
 361         return 0;
 362 }
 363
 364 static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
 365 {
 366         struct dw_mci_exynos_priv_data *priv = host->priv;
 367
 368         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 369                 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 370                 return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
 371         else
 372                 return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
 373 }
 374
 375 static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
 376 {
 377         u32 clksel;
 378         struct dw_mci_exynos_priv_data *priv = host->priv;
 379
 380         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 381                 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 382                 clksel = mci_readl(host, CLKSEL64);
 383         else
 384                 clksel = mci_readl(host, CLKSEL);
 385         clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
 386         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 387                 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 388                 mci_writel(host, CLKSEL64, clksel);
 389         else
 390                 mci_writel(host, CLKSEL, clksel);
 391 }
 392
 393 static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
 394 {
 395         struct dw_mci_exynos_priv_data *priv = host->priv;
 396         u32 clksel;
 397         u8 sample;
 398
 399         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 400                 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 401                 clksel = mci_readl(host, CLKSEL64);
 402         else
 403                 clksel = mci_readl(host, CLKSEL);
 404
 405         sample = (clksel + 1) & 0x7;
 406         clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
 407
 408         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
 409                 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
 410                 mci_writel(host, CLKSEL64, clksel);
 411         else
 412                 mci_writel(host, CLKSEL, clksel);
 413
 414         return sample;
 415 }
 416
 417 static s8 dw_mci_exynos_get_best_clksmpl(u8 candiates)
 418 {
 419         const u8 iter = 8;
 420         u8 __c;
 421         s8 i, loc = -1;
 422
 423         for (i = 0; i < iter; i++) {
 424                 __c = ror8(candiates, i);
 425                 if ((__c & 0xc7) == 0xc7) {
 426                         loc = i;
 427                         goto out;
 428                 }
 429         }
 430
 431         for (i = 0; i < iter; i++) {
 432                 __c = ror8(candiates, i);
 433                 if ((__c & 0x83) == 0x83) {
 434                         loc = i;
 435                         goto out;
 436                 }
 437         }
 438
 439 out:
 440         return loc;
 441 }
 442
 443 static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
 444 {
 445         struct dw_mci *host = slot->host;
 446         struct dw_mci_exynos_priv_data *priv = host->priv;
 447         struct mmc_host *mmc = slot->mmc;
 448         u8 start_smpl, smpl, candiates = 0;
 449         s8 found = -1;
 450         int ret = 0;
 451
 452         start_smpl = dw_mci_exynos_get_clksmpl(host);
 453
 454         do {
 455                 mci_writel(host, TMOUT, ~0);
 456                 smpl = dw_mci_exynos_move_next_clksmpl(host);
 457
 458                 if (!mmc_send_tuning(mmc, opcode, NULL))
 459                         candiates |= (1 << smpl);
 460
 461         } while (start_smpl != smpl);
 462
 463         found = dw_mci_exynos_get_best_clksmpl(candiates);
 464         if (found >= 0) {
 465                 dw_mci_exynos_set_clksmpl(host, found);
 466                 priv->tuned_sample = found;
 467         } else {
 468                 ret = -EIO;
 469         }
 470
 471         return ret;
 472 }
 473
 474 static int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host,
 475                                         struct mmc_ios *ios)
 476 {
 477         struct dw_mci_exynos_priv_data *priv = host->priv;
 478
 479         dw_mci_exynos_set_clksel_timing(host, priv->hs400_timing);
 480         dw_mci_exynos_adjust_clock(host, (ios->clock) << 1);
 481
 482         return 0;
 483 }
 484
 485 /* Common capabilities of Exynos4/Exynos5 SoC */
 486 static unsigned long exynos_dwmmc_caps[4] = {
 487         MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
 488         MMC_CAP_CMD23,
 489         MMC_CAP_CMD23,
 490         MMC_CAP_CMD23,
 491 };
 492
 493 static const struct dw_mci_drv_data exynos_drv_data = {
 494         .caps                   = exynos_dwmmc_caps,
 495         .init                   = dw_mci_exynos_priv_init,
 496         .set_ios                = dw_mci_exynos_set_ios,
 497         .parse_dt               = dw_mci_exynos_parse_dt,
 498         .execute_tuning         = dw_mci_exynos_execute_tuning,
 499         .prepare_hs400_tuning   = dw_mci_exynos_prepare_hs400_tuning,
 500 };
 501
 502 static const struct of_device_id dw_mci_exynos_match[] = {
 503         { .compatible = "samsung,exynos4412-dw-mshc",
 504                         .data = &exynos_drv_data, },
 505         { .compatible = "samsung,exynos5250-dw-mshc",
 506                         .data = &exynos_drv_data, },
 507         { .compatible = "samsung,exynos5420-dw-mshc",
 508                         .data = &exynos_drv_data, },
 509         { .compatible = "samsung,exynos5420-dw-mshc-smu",
 510                         .data = &exynos_drv_data, },
 511         { .compatible = "samsung,exynos7-dw-mshc",
 512                         .data = &exynos_drv_data, },
 513         { .compatible = "samsung,exynos7-dw-mshc-smu",
 514                         .data = &exynos_drv_data, },
 515         {},
 516 };
 517 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
 518
 519 static int dw_mci_exynos_probe(struct platform_device *pdev)
 520 {
 521         const struct dw_mci_drv_data *drv_data;
 522         const struct of_device_id *match;
 523
 524         match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
 525         drv_data = match->data;
 526         return dw_mci_pltfm_register(pdev, drv_data);
 527 }
 528
 529 static const struct dev_pm_ops dw_mci_exynos_pmops = {
 530         SET_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend, dw_mci_exynos_resume)
 531         .resume_noirq = dw_mci_exynos_resume_noirq,
 532         .thaw_noirq = dw_mci_exynos_resume_noirq,
 533         .restore_noirq = dw_mci_exynos_resume_noirq,
 534 };
 535
 536 static struct platform_driver dw_mci_exynos_pltfm_driver = {
 537         .probe          = dw_mci_exynos_probe,
 538         .remove         = dw_mci_pltfm_remove,
 539         .driver         = {
 540                 .name           = "dwmmc_exynos",
 541                 .of_match_table = dw_mci_exynos_match,
 542                 .pm             = &dw_mci_exynos_pmops,
 543         },
 544 };
 545
 546 module_platform_driver(dw_mci_exynos_pltfm_driver);
 547
 548 MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
 549 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
 550 MODULE_LICENSE("GPL v2");
 551 MODULE_ALIAS("platform:dwmmc_exynos");