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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[cris-mirror.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_sriov.c
blob632daff117d305a822f95cc1bcd84b47437b2334
1 /* bnx2x_sriov.c: QLogic Everest network driver.
2 *
3 * Copyright 2009-2013 Broadcom Corporation
4 * Copyright 2014 QLogic Corporation
5 * All rights reserved
6 *
7 * Unless you and QLogic execute a separate written software license
8 * agreement governing use of this software, this software is licensed to you
9 * under the terms of the GNU General Public License version 2, available
10 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
11 *
12 * Notwithstanding the above, under no circumstances may you combine this
13 * software in any way with any other QLogic software provided under a
14 * license other than the GPL, without QLogic's express prior written
15 * consent.
16 *
17 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
18 * Written by: Shmulik Ravid
19 * Ariel Elior <ariel.elior@qlogic.com>
20 *
21 */
22 #include "bnx2x.h"
23 #include "bnx2x_init.h"
24 #include "bnx2x_cmn.h"
25 #include "bnx2x_sp.h"
26 #include <linux/crc32.h>
27 #include <linux/if_vlan.h>
28
29 static int bnx2x_vf_op_prep(struct bnx2x *bp, int vfidx,
30 struct bnx2x_virtf **vf,
31 struct pf_vf_bulletin_content **bulletin,
32 bool test_queue);
33
34 /* General service functions */
35 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
36 u16 pf_id)
37 {
38 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
39 pf_id);
40 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
41 pf_id);
42 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
43 pf_id);
44 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
45 pf_id);
46 }
47
48 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
49 u8 enable)
50 {
51 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
52 enable);
53 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
54 enable);
55 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
56 enable);
57 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
58 enable);
59 }
60
61 int bnx2x_vf_idx_by_abs_fid(struct bnx2x *bp, u16 abs_vfid)
62 {
63 int idx;
64
65 for_each_vf(bp, idx)
66 if (bnx2x_vf(bp, idx, abs_vfid) == abs_vfid)
67 break;
68 return idx;
69 }
70
71 static
72 struct bnx2x_virtf *bnx2x_vf_by_abs_fid(struct bnx2x *bp, u16 abs_vfid)
73 {
74 u16 idx = (u16)bnx2x_vf_idx_by_abs_fid(bp, abs_vfid);
75 return (idx < BNX2X_NR_VIRTFN(bp)) ? BP_VF(bp, idx) : NULL;
76 }
77
78 static void bnx2x_vf_igu_ack_sb(struct bnx2x *bp, struct bnx2x_virtf *vf,
79 u8 igu_sb_id, u8 segment, u16 index, u8 op,
80 u8 update)
81 {
82 /* acking a VF sb through the PF - use the GRC */
83 u32 ctl;
84 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
85 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
86 u32 func_encode = vf->abs_vfid;
87 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + igu_sb_id;
88 struct igu_regular cmd_data = {0};
89
90 cmd_data.sb_id_and_flags =
91 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
92 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
93 (update << IGU_REGULAR_BUPDATE_SHIFT) |
94 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
95
96 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
97 func_encode << IGU_CTRL_REG_FID_SHIFT |
98 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
99
100 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
101 cmd_data.sb_id_and_flags, igu_addr_data);
102 REG_WR(bp, igu_addr_data, cmd_data.sb_id_and_flags);
103 mmiowb();
104 barrier();
105
106 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
107 ctl, igu_addr_ctl);
108 REG_WR(bp, igu_addr_ctl, ctl);
109 mmiowb();
110 barrier();
111 }
112
113 static bool bnx2x_validate_vf_sp_objs(struct bnx2x *bp,
114 struct bnx2x_virtf *vf,
115 bool print_err)
116 {
117 if (!bnx2x_leading_vfq(vf, sp_initialized)) {
118 if (print_err)
119 BNX2X_ERR("Slowpath objects not yet initialized!\n");
120 else
121 DP(BNX2X_MSG_IOV, "Slowpath objects not yet initialized!\n");
122 return false;
123 }
124 return true;
125 }
126
127 /* VFOP operations states */
128 void bnx2x_vfop_qctor_dump_tx(struct bnx2x *bp, struct bnx2x_virtf *vf,
129 struct bnx2x_queue_init_params *init_params,
130 struct bnx2x_queue_setup_params *setup_params,
131 u16 q_idx, u16 sb_idx)
132 {
133 DP(BNX2X_MSG_IOV,
134 "VF[%d] Q_SETUP: txq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, flags=0x%lx, traffic-type=%d",
135 vf->abs_vfid,
136 q_idx,
137 sb_idx,
138 init_params->tx.sb_cq_index,
139 init_params->tx.hc_rate,
140 setup_params->flags,
141 setup_params->txq_params.traffic_type);
142 }
143
144 void bnx2x_vfop_qctor_dump_rx(struct bnx2x *bp, struct bnx2x_virtf *vf,
145 struct bnx2x_queue_init_params *init_params,
146 struct bnx2x_queue_setup_params *setup_params,
147 u16 q_idx, u16 sb_idx)
148 {
149 struct bnx2x_rxq_setup_params *rxq_params = &setup_params->rxq_params;
150
151 DP(BNX2X_MSG_IOV, "VF[%d] Q_SETUP: rxq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, mtu=%d, buf-size=%d\n"
152 "sge-size=%d, max_sge_pkt=%d, tpa-agg-size=%d, flags=0x%lx, drop-flags=0x%x, cache-log=%d\n",
153 vf->abs_vfid,
154 q_idx,
155 sb_idx,
156 init_params->rx.sb_cq_index,
157 init_params->rx.hc_rate,
158 setup_params->gen_params.mtu,
159 rxq_params->buf_sz,
160 rxq_params->sge_buf_sz,
161 rxq_params->max_sges_pkt,
162 rxq_params->tpa_agg_sz,
163 setup_params->flags,
164 rxq_params->drop_flags,
165 rxq_params->cache_line_log);
166 }
167
168 void bnx2x_vfop_qctor_prep(struct bnx2x *bp,
169 struct bnx2x_virtf *vf,
170 struct bnx2x_vf_queue *q,
171 struct bnx2x_vf_queue_construct_params *p,
172 unsigned long q_type)
173 {
174 struct bnx2x_queue_init_params *init_p = &p->qstate.params.init;
175 struct bnx2x_queue_setup_params *setup_p = &p->prep_qsetup;
176
177 /* INIT */
178
179 /* Enable host coalescing in the transition to INIT state */
180 if (test_bit(BNX2X_Q_FLG_HC, &init_p->rx.flags))
181 __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->rx.flags);
182
183 if (test_bit(BNX2X_Q_FLG_HC, &init_p->tx.flags))
184 __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->tx.flags);
185
186 /* FW SB ID */
187 init_p->rx.fw_sb_id = vf_igu_sb(vf, q->sb_idx);
188 init_p->tx.fw_sb_id = vf_igu_sb(vf, q->sb_idx);
189
190 /* context */
191 init_p->cxts[0] = q->cxt;
192
193 /* SETUP */
194
195 /* Setup-op general parameters */
196 setup_p->gen_params.spcl_id = vf->sp_cl_id;
197 setup_p->gen_params.stat_id = vfq_stat_id(vf, q);
198 setup_p->gen_params.fp_hsi = vf->fp_hsi;
199
200 /* Setup-op flags:
201 * collect statistics, zero statistics, local-switching, security,
202 * OV for Flex10, RSS and MCAST for leading
203 */
204 if (test_bit(BNX2X_Q_FLG_STATS, &setup_p->flags))
205 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &setup_p->flags);
206
207 /* for VFs, enable tx switching, bd coherency, and mac address
208 * anti-spoofing
209 */
210 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &setup_p->flags);
211 __set_bit(BNX2X_Q_FLG_TX_SEC, &setup_p->flags);
212 __set_bit(BNX2X_Q_FLG_ANTI_SPOOF, &setup_p->flags);
213
214 /* Setup-op rx parameters */
215 if (test_bit(BNX2X_Q_TYPE_HAS_RX, &q_type)) {
216 struct bnx2x_rxq_setup_params *rxq_p = &setup_p->rxq_params;
217
218 rxq_p->cl_qzone_id = vfq_qzone_id(vf, q);
219 rxq_p->fw_sb_id = vf_igu_sb(vf, q->sb_idx);
220 rxq_p->rss_engine_id = FW_VF_HANDLE(vf->abs_vfid);
221
222 if (test_bit(BNX2X_Q_FLG_TPA, &setup_p->flags))
223 rxq_p->max_tpa_queues = BNX2X_VF_MAX_TPA_AGG_QUEUES;
224 }
225
226 /* Setup-op tx parameters */
227 if (test_bit(BNX2X_Q_TYPE_HAS_TX, &q_type)) {
228 setup_p->txq_params.tss_leading_cl_id = vf->leading_rss;
229 setup_p->txq_params.fw_sb_id = vf_igu_sb(vf, q->sb_idx);
230 }
231 }
232
233 static int bnx2x_vf_queue_create(struct bnx2x *bp,
234 struct bnx2x_virtf *vf, int qid,
235 struct bnx2x_vf_queue_construct_params *qctor)
236 {
237 struct bnx2x_queue_state_params *q_params;
238 int rc = 0;
239
240 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid);
241
242 /* Prepare ramrod information */
243 q_params = &qctor->qstate;
244 q_params->q_obj = &bnx2x_vfq(vf, qid, sp_obj);
245 set_bit(RAMROD_COMP_WAIT, &q_params->ramrod_flags);
246
247 if (bnx2x_get_q_logical_state(bp, q_params->q_obj) ==
248 BNX2X_Q_LOGICAL_STATE_ACTIVE) {
249 DP(BNX2X_MSG_IOV, "queue was already up. Aborting gracefully\n");
250 goto out;
251 }
252
253 /* Run Queue 'construction' ramrods */
254 q_params->cmd = BNX2X_Q_CMD_INIT;
255 rc = bnx2x_queue_state_change(bp, q_params);
256 if (rc)
257 goto out;
258
259 memcpy(&q_params->params.setup, &qctor->prep_qsetup,
260 sizeof(struct bnx2x_queue_setup_params));
261 q_params->cmd = BNX2X_Q_CMD_SETUP;
262 rc = bnx2x_queue_state_change(bp, q_params);
263 if (rc)
264 goto out;
265
266 /* enable interrupts */
267 bnx2x_vf_igu_ack_sb(bp, vf, vf_igu_sb(vf, bnx2x_vfq(vf, qid, sb_idx)),
268 USTORM_ID, 0, IGU_INT_ENABLE, 0);
269 out:
270 return rc;
271 }
272
273 static int bnx2x_vf_queue_destroy(struct bnx2x *bp, struct bnx2x_virtf *vf,
274 int qid)
275 {
276 enum bnx2x_queue_cmd cmds[] = {BNX2X_Q_CMD_HALT,
277 BNX2X_Q_CMD_TERMINATE,
278 BNX2X_Q_CMD_CFC_DEL};
279 struct bnx2x_queue_state_params q_params;
280 int rc, i;
281
282 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
283
284 /* Prepare ramrod information */
285 memset(&q_params, 0, sizeof(struct bnx2x_queue_state_params));
286 q_params.q_obj = &bnx2x_vfq(vf, qid, sp_obj);
287 set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
288
289 if (bnx2x_get_q_logical_state(bp, q_params.q_obj) ==
290 BNX2X_Q_LOGICAL_STATE_STOPPED) {
291 DP(BNX2X_MSG_IOV, "queue was already stopped. Aborting gracefully\n");
292 goto out;
293 }
294
295 /* Run Queue 'destruction' ramrods */
296 for (i = 0; i < ARRAY_SIZE(cmds); i++) {
297 q_params.cmd = cmds[i];
298 rc = bnx2x_queue_state_change(bp, &q_params);
299 if (rc) {
300 BNX2X_ERR("Failed to run Queue command %d\n", cmds[i]);
301 return rc;
302 }
303 }
304 out:
305 /* Clean Context */
306 if (bnx2x_vfq(vf, qid, cxt)) {
307 bnx2x_vfq(vf, qid, cxt)->ustorm_ag_context.cdu_usage = 0;
308 bnx2x_vfq(vf, qid, cxt)->xstorm_ag_context.cdu_reserved = 0;
309 }
310
311 return 0;
312 }
313
314 static void
315 bnx2x_vf_set_igu_info(struct bnx2x *bp, u8 igu_sb_id, u8 abs_vfid)
316 {
317 struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid);
318 if (vf) {
319 /* the first igu entry belonging to VFs of this PF */
320 if (!BP_VFDB(bp)->first_vf_igu_entry)
321 BP_VFDB(bp)->first_vf_igu_entry = igu_sb_id;
322
323 /* the first igu entry belonging to this VF */
324 if (!vf_sb_count(vf))
325 vf->igu_base_id = igu_sb_id;
326
327 ++vf_sb_count(vf);
328 ++vf->sb_count;
329 }
330 BP_VFDB(bp)->vf_sbs_pool++;
331 }
332
333 static inline void bnx2x_vf_vlan_credit(struct bnx2x *bp,
334 struct bnx2x_vlan_mac_obj *obj,
335 atomic_t *counter)
336 {
337 struct list_head *pos;
338 int read_lock;
339 int cnt = 0;
340
341 read_lock = bnx2x_vlan_mac_h_read_lock(bp, obj);
342 if (read_lock)
343 DP(BNX2X_MSG_SP, "Failed to take vlan mac read head; continuing anyway\n");
344
345 list_for_each(pos, &obj->head)
346 cnt++;
347
348 if (!read_lock)
349 bnx2x_vlan_mac_h_read_unlock(bp, obj);
350
351 atomic_set(counter, cnt);
352 }
353
354 static int bnx2x_vf_vlan_mac_clear(struct bnx2x *bp, struct bnx2x_virtf *vf,
355 int qid, bool drv_only, int type)
356 {
357 struct bnx2x_vlan_mac_ramrod_params ramrod;
358 int rc;
359
360 DP(BNX2X_MSG_IOV, "vf[%d] - deleting all %s\n", vf->abs_vfid,
361 (type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MACs" :
362 (type == BNX2X_VF_FILTER_MAC) ? "MACs" : "VLANs");
363
364 /* Prepare ramrod params */
365 memset(&ramrod, 0, sizeof(struct bnx2x_vlan_mac_ramrod_params));
366 if (type == BNX2X_VF_FILTER_VLAN_MAC) {
367 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags);
368 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_mac_obj);
369 } else if (type == BNX2X_VF_FILTER_MAC) {
370 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags);
371 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj);
372 } else {
373 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj);
374 }
375 ramrod.user_req.cmd = BNX2X_VLAN_MAC_DEL;
376
377 set_bit(RAMROD_EXEC, &ramrod.ramrod_flags);
378 if (drv_only)
379 set_bit(RAMROD_DRV_CLR_ONLY, &ramrod.ramrod_flags);
380 else
381 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags);
382
383 /* Start deleting */
384 rc = ramrod.vlan_mac_obj->delete_all(bp,
385 ramrod.vlan_mac_obj,
386 &ramrod.user_req.vlan_mac_flags,
387 &ramrod.ramrod_flags);
388 if (rc) {
389 BNX2X_ERR("Failed to delete all %s\n",
390 (type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MACs" :
391 (type == BNX2X_VF_FILTER_MAC) ? "MACs" : "VLANs");
392 return rc;
393 }
394
395 return 0;
396 }
397
398 static int bnx2x_vf_mac_vlan_config(struct bnx2x *bp,
399 struct bnx2x_virtf *vf, int qid,
400 struct bnx2x_vf_mac_vlan_filter *filter,
401 bool drv_only)
402 {
403 struct bnx2x_vlan_mac_ramrod_params ramrod;
404 int rc;
405
406 DP(BNX2X_MSG_IOV, "vf[%d] - %s a %s filter\n",
407 vf->abs_vfid, filter->add ? "Adding" : "Deleting",
408 (filter->type == BNX2X_VF_FILTER_VLAN_MAC) ? "VLAN-MAC" :
409 (filter->type == BNX2X_VF_FILTER_MAC) ? "MAC" : "VLAN");
410
411 /* Prepare ramrod params */
412 memset(&ramrod, 0, sizeof(struct bnx2x_vlan_mac_ramrod_params));
413 if (filter->type == BNX2X_VF_FILTER_VLAN_MAC) {
414 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_mac_obj);
415 ramrod.user_req.u.vlan.vlan = filter->vid;
416 memcpy(&ramrod.user_req.u.mac.mac, filter->mac, ETH_ALEN);
417 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags);
418 } else if (filter->type == BNX2X_VF_FILTER_VLAN) {
419 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj);
420 ramrod.user_req.u.vlan.vlan = filter->vid;
421 } else {
422 set_bit(BNX2X_ETH_MAC, &ramrod.user_req.vlan_mac_flags);
423 ramrod.vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj);
424 memcpy(&ramrod.user_req.u.mac.mac, filter->mac, ETH_ALEN);
425 }
426 ramrod.user_req.cmd = filter->add ? BNX2X_VLAN_MAC_ADD :
427 BNX2X_VLAN_MAC_DEL;
428
429 set_bit(RAMROD_EXEC, &ramrod.ramrod_flags);
430 if (drv_only)
431 set_bit(RAMROD_DRV_CLR_ONLY, &ramrod.ramrod_flags);
432 else
433 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags);
434
435 /* Add/Remove the filter */
436 rc = bnx2x_config_vlan_mac(bp, &ramrod);
437 if (rc && rc != -EEXIST) {
438 BNX2X_ERR("Failed to %s %s\n",
439 filter->add ? "add" : "delete",
440 (filter->type == BNX2X_VF_FILTER_VLAN_MAC) ?
441 "VLAN-MAC" :
442 (filter->type == BNX2X_VF_FILTER_MAC) ?
443 "MAC" : "VLAN");
444 return rc;
445 }
446
447 return 0;
448 }
449
450 int bnx2x_vf_mac_vlan_config_list(struct bnx2x *bp, struct bnx2x_virtf *vf,
451 struct bnx2x_vf_mac_vlan_filters *filters,
452 int qid, bool drv_only)
453 {
454 int rc = 0, i;
455
456 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
457
458 if (!bnx2x_validate_vf_sp_objs(bp, vf, true))
459 return -EINVAL;
460
461 /* Prepare ramrod params */
462 for (i = 0; i < filters->count; i++) {
463 rc = bnx2x_vf_mac_vlan_config(bp, vf, qid,
464 &filters->filters[i], drv_only);
465 if (rc)
466 break;
467 }
468
469 /* Rollback if needed */
470 if (i != filters->count) {
471 BNX2X_ERR("Managed only %d/%d filters - rolling back\n",
472 i, filters->count + 1);
473 while (--i >= 0) {
474 filters->filters[i].add = !filters->filters[i].add;
475 bnx2x_vf_mac_vlan_config(bp, vf, qid,
476 &filters->filters[i],
477 drv_only);
478 }
479 }
480
481 /* It's our responsibility to free the filters */
482 kfree(filters);
483
484 return rc;
485 }
486
487 int bnx2x_vf_queue_setup(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid,
488 struct bnx2x_vf_queue_construct_params *qctor)
489 {
490 int rc;
491
492 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid);
493
494 rc = bnx2x_vf_queue_create(bp, vf, qid, qctor);
495 if (rc)
496 goto op_err;
497
498 /* Schedule the configuration of any pending vlan filters */
499 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_HYPERVISOR_VLAN,
500 BNX2X_MSG_IOV);
501 return 0;
502 op_err:
503 BNX2X_ERR("QSETUP[%d:%d] error: rc %d\n", vf->abs_vfid, qid, rc);
504 return rc;
505 }
506
507 static int bnx2x_vf_queue_flr(struct bnx2x *bp, struct bnx2x_virtf *vf,
508 int qid)
509 {
510 int rc;
511
512 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid);
513
514 /* If needed, clean the filtering data base */
515 if ((qid == LEADING_IDX) &&
516 bnx2x_validate_vf_sp_objs(bp, vf, false)) {
517 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true,
518 BNX2X_VF_FILTER_VLAN_MAC);
519 if (rc)
520 goto op_err;
521 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true,
522 BNX2X_VF_FILTER_VLAN);
523 if (rc)
524 goto op_err;
525 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid, true,
526 BNX2X_VF_FILTER_MAC);
527 if (rc)
528 goto op_err;
529 }
530
531 /* Terminate queue */
532 if (bnx2x_vfq(vf, qid, sp_obj).state != BNX2X_Q_STATE_RESET) {
533 struct bnx2x_queue_state_params qstate;
534
535 memset(&qstate, 0, sizeof(struct bnx2x_queue_state_params));
536 qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj);
537 qstate.q_obj->state = BNX2X_Q_STATE_STOPPED;
538 qstate.cmd = BNX2X_Q_CMD_TERMINATE;
539 set_bit(RAMROD_COMP_WAIT, &qstate.ramrod_flags);
540 rc = bnx2x_queue_state_change(bp, &qstate);
541 if (rc)
542 goto op_err;
543 }
544
545 return 0;
546 op_err:
547 BNX2X_ERR("vf[%d:%d] error: rc %d\n", vf->abs_vfid, qid, rc);
548 return rc;
549 }
550
551 int bnx2x_vf_mcast(struct bnx2x *bp, struct bnx2x_virtf *vf,
552 bnx2x_mac_addr_t *mcasts, int mc_num, bool drv_only)
553 {
554 struct bnx2x_mcast_list_elem *mc = NULL;
555 struct bnx2x_mcast_ramrod_params mcast;
556 int rc, i;
557
558 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
559
560 /* Prepare Multicast command */
561 memset(&mcast, 0, sizeof(struct bnx2x_mcast_ramrod_params));
562 mcast.mcast_obj = &vf->mcast_obj;
563 if (drv_only)
564 set_bit(RAMROD_DRV_CLR_ONLY, &mcast.ramrod_flags);
565 else
566 set_bit(RAMROD_COMP_WAIT, &mcast.ramrod_flags);
567 if (mc_num) {
568 mc = kzalloc(mc_num * sizeof(struct bnx2x_mcast_list_elem),
569 GFP_KERNEL);
570 if (!mc) {
571 BNX2X_ERR("Cannot Configure multicasts due to lack of memory\n");
572 return -ENOMEM;
573 }
574 }
575
576 /* clear existing mcasts */
577 mcast.mcast_list_len = vf->mcast_list_len;
578 vf->mcast_list_len = mc_num;
579 rc = bnx2x_config_mcast(bp, &mcast, BNX2X_MCAST_CMD_DEL);
580 if (rc) {
581 BNX2X_ERR("Failed to remove multicasts\n");
582 kfree(mc);
583 return rc;
584 }
585
586 /* update mcast list on the ramrod params */
587 if (mc_num) {
588 INIT_LIST_HEAD(&mcast.mcast_list);
589 for (i = 0; i < mc_num; i++) {
590 mc[i].mac = mcasts[i];
591 list_add_tail(&mc[i].link,
592 &mcast.mcast_list);
593 }
594
595 /* add new mcasts */
596 mcast.mcast_list_len = mc_num;
597 rc = bnx2x_config_mcast(bp, &mcast, BNX2X_MCAST_CMD_ADD);
598 if (rc)
599 BNX2X_ERR("Faled to add multicasts\n");
600 kfree(mc);
601 }
602
603 return rc;
604 }
605
606 static void bnx2x_vf_prep_rx_mode(struct bnx2x *bp, u8 qid,
607 struct bnx2x_rx_mode_ramrod_params *ramrod,
608 struct bnx2x_virtf *vf,
609 unsigned long accept_flags)
610 {
611 struct bnx2x_vf_queue *vfq = vfq_get(vf, qid);
612
613 memset(ramrod, 0, sizeof(*ramrod));
614 ramrod->cid = vfq->cid;
615 ramrod->cl_id = vfq_cl_id(vf, vfq);
616 ramrod->rx_mode_obj = &bp->rx_mode_obj;
617 ramrod->func_id = FW_VF_HANDLE(vf->abs_vfid);
618 ramrod->rx_accept_flags = accept_flags;
619 ramrod->tx_accept_flags = accept_flags;
620 ramrod->pstate = &vf->filter_state;
621 ramrod->state = BNX2X_FILTER_RX_MODE_PENDING;
622
623 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state);
624 set_bit(RAMROD_RX, &ramrod->ramrod_flags);
625 set_bit(RAMROD_TX, &ramrod->ramrod_flags);
626
627 ramrod->rdata = bnx2x_vf_sp(bp, vf, rx_mode_rdata.e2);
628 ramrod->rdata_mapping = bnx2x_vf_sp_map(bp, vf, rx_mode_rdata.e2);
629 }
630
631 int bnx2x_vf_rxmode(struct bnx2x *bp, struct bnx2x_virtf *vf,
632 int qid, unsigned long accept_flags)
633 {
634 struct bnx2x_rx_mode_ramrod_params ramrod;
635
636 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
637
638 bnx2x_vf_prep_rx_mode(bp, qid, &ramrod, vf, accept_flags);
639 set_bit(RAMROD_COMP_WAIT, &ramrod.ramrod_flags);
640 vfq_get(vf, qid)->accept_flags = ramrod.rx_accept_flags;
641 return bnx2x_config_rx_mode(bp, &ramrod);
642 }
643
644 int bnx2x_vf_queue_teardown(struct bnx2x *bp, struct bnx2x_virtf *vf, int qid)
645 {
646 int rc;
647
648 DP(BNX2X_MSG_IOV, "vf[%d:%d]\n", vf->abs_vfid, qid);
649
650 /* Remove all classification configuration for leading queue */
651 if (qid == LEADING_IDX) {
652 rc = bnx2x_vf_rxmode(bp, vf, qid, 0);
653 if (rc)
654 goto op_err;
655
656 /* Remove filtering if feasible */
657 if (bnx2x_validate_vf_sp_objs(bp, vf, true)) {
658 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid,
659 false,
660 BNX2X_VF_FILTER_VLAN_MAC);
661 if (rc)
662 goto op_err;
663 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid,
664 false,
665 BNX2X_VF_FILTER_VLAN);
666 if (rc)
667 goto op_err;
668 rc = bnx2x_vf_vlan_mac_clear(bp, vf, qid,
669 false,
670 BNX2X_VF_FILTER_MAC);
671 if (rc)
672 goto op_err;
673 rc = bnx2x_vf_mcast(bp, vf, NULL, 0, false);
674 if (rc)
675 goto op_err;
676 }
677 }
678
679 /* Destroy queue */
680 rc = bnx2x_vf_queue_destroy(bp, vf, qid);
681 if (rc)
682 goto op_err;
683 return rc;
684 op_err:
685 BNX2X_ERR("vf[%d:%d] error: rc %d\n",
686 vf->abs_vfid, qid, rc);
687 return rc;
688 }
689
690 /* VF enable primitives
691 * when pretend is required the caller is responsible
692 * for calling pretend prior to calling these routines
693 */
694
695 /* internal vf enable - until vf is enabled internally all transactions
696 * are blocked. This routine should always be called last with pretend.
697 */
698 static void bnx2x_vf_enable_internal(struct bnx2x *bp, u8 enable)
699 {
700 REG_WR(bp, PGLUE_B_REG_INTERNAL_VFID_ENABLE, enable ? 1 : 0);
701 }
702
703 /* clears vf error in all semi blocks */
704 static void bnx2x_vf_semi_clear_err(struct bnx2x *bp, u8 abs_vfid)
705 {
706 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, abs_vfid);
707 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, abs_vfid);
708 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, abs_vfid);
709 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, abs_vfid);
710 }
711
712 static void bnx2x_vf_pglue_clear_err(struct bnx2x *bp, u8 abs_vfid)
713 {
714 u32 was_err_group = (2 * BP_PATH(bp) + abs_vfid) >> 5;
715 u32 was_err_reg = 0;
716
717 switch (was_err_group) {
718 case 0:
719 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR;
720 break;
721 case 1:
722 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR;
723 break;
724 case 2:
725 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR;
726 break;
727 case 3:
728 was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR;
729 break;
730 }
731 REG_WR(bp, was_err_reg, 1 << (abs_vfid & 0x1f));
732 }
733
734 static void bnx2x_vf_igu_reset(struct bnx2x *bp, struct bnx2x_virtf *vf)
735 {
736 int i;
737 u32 val;
738
739 /* Set VF masks and configuration - pretend */
740 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid));
741
742 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
743 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
744 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
745 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
746 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
747 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
748
749 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION);
750 val |= (IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_MSI_MSIX_EN);
751 val &= ~IGU_VF_CONF_PARENT_MASK;
752 val |= (BP_ABS_FUNC(bp) >> 1) << IGU_VF_CONF_PARENT_SHIFT;
753 REG_WR(bp, IGU_REG_VF_CONFIGURATION, val);
754
755 DP(BNX2X_MSG_IOV,
756 "value in IGU_REG_VF_CONFIGURATION of vf %d after write is 0x%08x\n",
757 vf->abs_vfid, val);
758
759 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
760
761 /* iterate over all queues, clear sb consumer */
762 for (i = 0; i < vf_sb_count(vf); i++) {
763 u8 igu_sb_id = vf_igu_sb(vf, i);
764
765 /* zero prod memory */
766 REG_WR(bp, IGU_REG_PROD_CONS_MEMORY + igu_sb_id * 4, 0);
767
768 /* clear sb state machine */
769 bnx2x_igu_clear_sb_gen(bp, vf->abs_vfid, igu_sb_id,
770 false /* VF */);
771
772 /* disable + update */
773 bnx2x_vf_igu_ack_sb(bp, vf, igu_sb_id, USTORM_ID, 0,
774 IGU_INT_DISABLE, 1);
775 }
776 }
777
778 void bnx2x_vf_enable_access(struct bnx2x *bp, u8 abs_vfid)
779 {
780 /* set the VF-PF association in the FW */
781 storm_memset_vf_to_pf(bp, FW_VF_HANDLE(abs_vfid), BP_FUNC(bp));
782 storm_memset_func_en(bp, FW_VF_HANDLE(abs_vfid), 1);
783
784 /* clear vf errors*/
785 bnx2x_vf_semi_clear_err(bp, abs_vfid);
786 bnx2x_vf_pglue_clear_err(bp, abs_vfid);
787
788 /* internal vf-enable - pretend */
789 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, abs_vfid));
790 DP(BNX2X_MSG_IOV, "enabling internal access for vf %x\n", abs_vfid);
791 bnx2x_vf_enable_internal(bp, true);
792 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
793 }
794
795 static void bnx2x_vf_enable_traffic(struct bnx2x *bp, struct bnx2x_virtf *vf)
796 {
797 /* Reset vf in IGU interrupts are still disabled */
798 bnx2x_vf_igu_reset(bp, vf);
799
800 /* pretend to enable the vf with the PBF */
801 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid));
802 REG_WR(bp, PBF_REG_DISABLE_VF, 0);
803 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
804 }
805
806 static u8 bnx2x_vf_is_pcie_pending(struct bnx2x *bp, u8 abs_vfid)
807 {
808 struct pci_dev *dev;
809 struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid);
810
811 if (!vf)
812 return false;
813
814 dev = pci_get_bus_and_slot(vf->bus, vf->devfn);
815 if (dev)
816 return bnx2x_is_pcie_pending(dev);
817 return false;
818 }
819
820 int bnx2x_vf_flr_clnup_epilog(struct bnx2x *bp, u8 abs_vfid)
821 {
822 /* Verify no pending pci transactions */
823 if (bnx2x_vf_is_pcie_pending(bp, abs_vfid))
824 BNX2X_ERR("PCIE Transactions still pending\n");
825
826 return 0;
827 }
828
829 /* must be called after the number of PF queues and the number of VFs are
830 * both known
831 */
832 static void
833 bnx2x_iov_static_resc(struct bnx2x *bp, struct bnx2x_virtf *vf)
834 {
835 struct vf_pf_resc_request *resc = &vf->alloc_resc;
836
837 /* will be set only during VF-ACQUIRE */
838 resc->num_rxqs = 0;
839 resc->num_txqs = 0;
840
841 resc->num_mac_filters = VF_MAC_CREDIT_CNT;
842 resc->num_vlan_filters = VF_VLAN_CREDIT_CNT;
843
844 /* no real limitation */
845 resc->num_mc_filters = 0;
846
847 /* num_sbs already set */
848 resc->num_sbs = vf->sb_count;
849 }
850
851 /* FLR routines: */
852 static void bnx2x_vf_free_resc(struct bnx2x *bp, struct bnx2x_virtf *vf)
853 {
854 /* reset the state variables */
855 bnx2x_iov_static_resc(bp, vf);
856 vf->state = VF_FREE;
857 }
858
859 static void bnx2x_vf_flr_clnup_hw(struct bnx2x *bp, struct bnx2x_virtf *vf)
860 {
861 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
862
863 /* DQ usage counter */
864 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid));
865 bnx2x_flr_clnup_poll_hw_counter(bp, DORQ_REG_VF_USAGE_CNT,
866 "DQ VF usage counter timed out",
867 poll_cnt);
868 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
869
870 /* FW cleanup command - poll for the results */
871 if (bnx2x_send_final_clnup(bp, (u8)FW_VF_HANDLE(vf->abs_vfid),
872 poll_cnt))
873 BNX2X_ERR("VF[%d] Final cleanup timed-out\n", vf->abs_vfid);
874
875 /* verify TX hw is flushed */
876 bnx2x_tx_hw_flushed(bp, poll_cnt);
877 }
878
879 static void bnx2x_vf_flr(struct bnx2x *bp, struct bnx2x_virtf *vf)
880 {
881 int rc, i;
882
883 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
884
885 /* the cleanup operations are valid if and only if the VF
886 * was first acquired.
887 */
888 for (i = 0; i < vf_rxq_count(vf); i++) {
889 rc = bnx2x_vf_queue_flr(bp, vf, i);
890 if (rc)
891 goto out;
892 }
893
894 /* remove multicasts */
895 bnx2x_vf_mcast(bp, vf, NULL, 0, true);
896
897 /* dispatch final cleanup and wait for HW queues to flush */
898 bnx2x_vf_flr_clnup_hw(bp, vf);
899
900 /* release VF resources */
901 bnx2x_vf_free_resc(bp, vf);
902
903 /* re-open the mailbox */
904 bnx2x_vf_enable_mbx(bp, vf->abs_vfid);
905 return;
906 out:
907 BNX2X_ERR("vf[%d:%d] failed flr: rc %d\n",
908 vf->abs_vfid, i, rc);
909 }
910
911 static void bnx2x_vf_flr_clnup(struct bnx2x *bp)
912 {
913 struct bnx2x_virtf *vf;
914 int i;
915
916 for (i = 0; i < BNX2X_NR_VIRTFN(bp); i++) {
917 /* VF should be RESET & in FLR cleanup states */
918 if (bnx2x_vf(bp, i, state) != VF_RESET ||
919 !bnx2x_vf(bp, i, flr_clnup_stage))
920 continue;
921
922 DP(BNX2X_MSG_IOV, "next vf to cleanup: %d. Num of vfs: %d\n",
923 i, BNX2X_NR_VIRTFN(bp));
924
925 vf = BP_VF(bp, i);
926
927 /* lock the vf pf channel */
928 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR);
929
930 /* invoke the VF FLR SM */
931 bnx2x_vf_flr(bp, vf);
932
933 /* mark the VF to be ACKED and continue */
934 vf->flr_clnup_stage = false;
935 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR);
936 }
937
938 /* Acknowledge the handled VFs.
939 * we are acknowledge all the vfs which an flr was requested for, even
940 * if amongst them there are such that we never opened, since the mcp
941 * will interrupt us immediately again if we only ack some of the bits,
942 * resulting in an endless loop. This can happen for example in KVM
943 * where an 'all ones' flr request is sometimes given by hyper visor
944 */
945 DP(BNX2X_MSG_MCP, "DRV_STATUS_VF_DISABLED ACK for vfs 0x%x 0x%x\n",
946 bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]);
947 for (i = 0; i < FLRD_VFS_DWORDS; i++)
948 SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i],
949 bp->vfdb->flrd_vfs[i]);
950
951 bnx2x_fw_command(bp, DRV_MSG_CODE_VF_DISABLED_DONE, 0);
952
953 /* clear the acked bits - better yet if the MCP implemented
954 * write to clear semantics
955 */
956 for (i = 0; i < FLRD_VFS_DWORDS; i++)
957 SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i], 0);
958 }
959
960 void bnx2x_vf_handle_flr_event(struct bnx2x *bp)
961 {
962 int i;
963
964 /* Read FLR'd VFs */
965 for (i = 0; i < FLRD_VFS_DWORDS; i++)
966 bp->vfdb->flrd_vfs[i] = SHMEM2_RD(bp, mcp_vf_disabled[i]);
967
968 DP(BNX2X_MSG_MCP,
969 "DRV_STATUS_VF_DISABLED received for vfs 0x%x 0x%x\n",
970 bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]);
971
972 for_each_vf(bp, i) {
973 struct bnx2x_virtf *vf = BP_VF(bp, i);
974 u32 reset = 0;
975
976 if (vf->abs_vfid < 32)
977 reset = bp->vfdb->flrd_vfs[0] & (1 << vf->abs_vfid);
978 else
979 reset = bp->vfdb->flrd_vfs[1] &
980 (1 << (vf->abs_vfid - 32));
981
982 if (reset) {
983 /* set as reset and ready for cleanup */
984 vf->state = VF_RESET;
985 vf->flr_clnup_stage = true;
986
987 DP(BNX2X_MSG_IOV,
988 "Initiating Final cleanup for VF %d\n",
989 vf->abs_vfid);
990 }
991 }
992
993 /* do the FLR cleanup for all marked VFs*/
994 bnx2x_vf_flr_clnup(bp);
995 }
996
997 /* IOV global initialization routines */
998 void bnx2x_iov_init_dq(struct bnx2x *bp)
999 {
1000 if (!IS_SRIOV(bp))
1001 return;
1002
1003 /* Set the DQ such that the CID reflect the abs_vfid */
1004 REG_WR(bp, DORQ_REG_VF_NORM_VF_BASE, 0);
1005 REG_WR(bp, DORQ_REG_MAX_RVFID_SIZE, ilog2(BNX2X_MAX_NUM_OF_VFS));
1006
1007 /* Set VFs starting CID. If its > 0 the preceding CIDs are belong to
1008 * the PF L2 queues
1009 */
1010 REG_WR(bp, DORQ_REG_VF_NORM_CID_BASE, BNX2X_FIRST_VF_CID);
1011
1012 /* The VF window size is the log2 of the max number of CIDs per VF */
1013 REG_WR(bp, DORQ_REG_VF_NORM_CID_WND_SIZE, BNX2X_VF_CID_WND);
1014
1015 /* The VF doorbell size 0 - *B, 4 - 128B. We set it here to match
1016 * the Pf doorbell size although the 2 are independent.
1017 */
1018 REG_WR(bp, DORQ_REG_VF_NORM_CID_OFST, 3);
1019
1020 /* No security checks for now -
1021 * configure single rule (out of 16) mask = 0x1, value = 0x0,
1022 * CID range 0 - 0x1ffff
1023 */
1024 REG_WR(bp, DORQ_REG_VF_TYPE_MASK_0, 1);
1025 REG_WR(bp, DORQ_REG_VF_TYPE_VALUE_0, 0);
1026 REG_WR(bp, DORQ_REG_VF_TYPE_MIN_MCID_0, 0);
1027 REG_WR(bp, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff);
1028
1029 /* set the VF doorbell threshold. This threshold represents the amount
1030 * of doorbells allowed in the main DORQ fifo for a specific VF.
1031 */
1032 REG_WR(bp, DORQ_REG_VF_USAGE_CT_LIMIT, 64);
1033 }
1034
1035 void bnx2x_iov_init_dmae(struct bnx2x *bp)
1036 {
1037 if (pci_find_ext_capability(bp->pdev, PCI_EXT_CAP_ID_SRIOV))
1038 REG_WR(bp, DMAE_REG_BACKWARD_COMP_EN, 0);
1039 }
1040
1041 static int bnx2x_vf_bus(struct bnx2x *bp, int vfid)
1042 {
1043 struct pci_dev *dev = bp->pdev;
1044 struct bnx2x_sriov *iov = &bp->vfdb->sriov;
1045
1046 return dev->bus->number + ((dev->devfn + iov->offset +
1047 iov->stride * vfid) >> 8);
1048 }
1049
1050 static int bnx2x_vf_devfn(struct bnx2x *bp, int vfid)
1051 {
1052 struct pci_dev *dev = bp->pdev;
1053 struct bnx2x_sriov *iov = &bp->vfdb->sriov;
1054
1055 return (dev->devfn + iov->offset + iov->stride * vfid) & 0xff;
1056 }
1057
1058 static void bnx2x_vf_set_bars(struct bnx2x *bp, struct bnx2x_virtf *vf)
1059 {
1060 int i, n;
1061 struct pci_dev *dev = bp->pdev;
1062 struct bnx2x_sriov *iov = &bp->vfdb->sriov;
1063
1064 for (i = 0, n = 0; i < PCI_SRIOV_NUM_BARS; i += 2, n++) {
1065 u64 start = pci_resource_start(dev, PCI_IOV_RESOURCES + i);
1066 u32 size = pci_resource_len(dev, PCI_IOV_RESOURCES + i);
1067
1068 size /= iov->total;
1069 vf->bars[n].bar = start + size * vf->abs_vfid;
1070 vf->bars[n].size = size;
1071 }
1072 }
1073
1074 static int bnx2x_ari_enabled(struct pci_dev *dev)
1075 {
1076 return dev->bus->self && dev->bus->self->ari_enabled;
1077 }
1078
1079 static int
1080 bnx2x_get_vf_igu_cam_info(struct bnx2x *bp)
1081 {
1082 int sb_id;
1083 u32 val;
1084 u8 fid, current_pf = 0;
1085
1086 /* IGU in normal mode - read CAM */
1087 for (sb_id = 0; sb_id < IGU_REG_MAPPING_MEMORY_SIZE; sb_id++) {
1088 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + sb_id * 4);
1089 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
1090 continue;
1091 fid = GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID);
1092 if (fid & IGU_FID_ENCODE_IS_PF)
1093 current_pf = fid & IGU_FID_PF_NUM_MASK;
1094 else if (current_pf == BP_FUNC(bp))
1095 bnx2x_vf_set_igu_info(bp, sb_id,
1096 (fid & IGU_FID_VF_NUM_MASK));
1097 DP(BNX2X_MSG_IOV, "%s[%d], igu_sb_id=%d, msix=%d\n",
1098 ((fid & IGU_FID_ENCODE_IS_PF) ? "PF" : "VF"),
1099 ((fid & IGU_FID_ENCODE_IS_PF) ? (fid & IGU_FID_PF_NUM_MASK) :
1100 (fid & IGU_FID_VF_NUM_MASK)), sb_id,
1101 GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR));
1102 }
1103 DP(BNX2X_MSG_IOV, "vf_sbs_pool is %d\n", BP_VFDB(bp)->vf_sbs_pool);
1104 return BP_VFDB(bp)->vf_sbs_pool;
1105 }
1106
1107 static void __bnx2x_iov_free_vfdb(struct bnx2x *bp)
1108 {
1109 if (bp->vfdb) {
1110 kfree(bp->vfdb->vfqs);
1111 kfree(bp->vfdb->vfs);
1112 kfree(bp->vfdb);
1113 }
1114 bp->vfdb = NULL;
1115 }
1116
1117 static int bnx2x_sriov_pci_cfg_info(struct bnx2x *bp, struct bnx2x_sriov *iov)
1118 {
1119 int pos;
1120 struct pci_dev *dev = bp->pdev;
1121
1122 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
1123 if (!pos) {
1124 BNX2X_ERR("failed to find SRIOV capability in device\n");
1125 return -ENODEV;
1126 }
1127
1128 iov->pos = pos;
1129 DP(BNX2X_MSG_IOV, "sriov ext pos %d\n", pos);
1130 pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &iov->ctrl);
1131 pci_read_config_word(dev, pos + PCI_SRIOV_TOTAL_VF, &iov->total);
1132 pci_read_config_word(dev, pos + PCI_SRIOV_INITIAL_VF, &iov->initial);
1133 pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &iov->offset);
1134 pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &iov->stride);
1135 pci_read_config_dword(dev, pos + PCI_SRIOV_SUP_PGSIZE, &iov->pgsz);
1136 pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap);
1137 pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);
1138
1139 return 0;
1140 }
1141
1142 static int bnx2x_sriov_info(struct bnx2x *bp, struct bnx2x_sriov *iov)
1143 {
1144 u32 val;
1145
1146 /* read the SRIOV capability structure
1147 * The fields can be read via configuration read or
1148 * directly from the device (starting at offset PCICFG_OFFSET)
1149 */
1150 if (bnx2x_sriov_pci_cfg_info(bp, iov))
1151 return -ENODEV;
1152
1153 /* get the number of SRIOV bars */
1154 iov->nres = 0;
1155
1156 /* read the first_vfid */
1157 val = REG_RD(bp, PCICFG_OFFSET + GRC_CONFIG_REG_PF_INIT_VF);
1158 iov->first_vf_in_pf = ((val & GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK)
1159 * 8) - (BNX2X_MAX_NUM_OF_VFS * BP_PATH(bp));
1160
1161 DP(BNX2X_MSG_IOV,
1162 "IOV info[%d]: first vf %d, nres %d, cap 0x%x, ctrl 0x%x, total %d, initial %d, num vfs %d, offset %d, stride %d, page size 0x%x\n",
1163 BP_FUNC(bp),
1164 iov->first_vf_in_pf, iov->nres, iov->cap, iov->ctrl, iov->total,
1165 iov->initial, iov->nr_virtfn, iov->offset, iov->stride, iov->pgsz);
1166
1167 return 0;
1168 }
1169
1170 /* must be called after PF bars are mapped */
1171 int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param,
1172 int num_vfs_param)
1173 {
1174 int err, i;
1175 struct bnx2x_sriov *iov;
1176 struct pci_dev *dev = bp->pdev;
1177
1178 bp->vfdb = NULL;
1179
1180 /* verify is pf */
1181 if (IS_VF(bp))
1182 return 0;
1183
1184 /* verify sriov capability is present in configuration space */
1185 if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV))
1186 return 0;
1187
1188 /* verify chip revision */
1189 if (CHIP_IS_E1x(bp))
1190 return 0;
1191
1192 /* check if SRIOV support is turned off */
1193 if (!num_vfs_param)
1194 return 0;
1195
1196 /* SRIOV assumes that num of PF CIDs < BNX2X_FIRST_VF_CID */
1197 if (BNX2X_L2_MAX_CID(bp) >= BNX2X_FIRST_VF_CID) {
1198 BNX2X_ERR("PF cids %d are overspilling into vf space (starts at %d). Abort SRIOV\n",
1199 BNX2X_L2_MAX_CID(bp), BNX2X_FIRST_VF_CID);
1200 return 0;
1201 }
1202
1203 /* SRIOV can be enabled only with MSIX */
1204 if (int_mode_param == BNX2X_INT_MODE_MSI ||
1205 int_mode_param == BNX2X_INT_MODE_INTX) {
1206 BNX2X_ERR("Forced MSI/INTx mode is incompatible with SRIOV\n");
1207 return 0;
1208 }
1209
1210 err = -EIO;
1211 /* verify ari is enabled */
1212 if (!bnx2x_ari_enabled(bp->pdev)) {
1213 BNX2X_ERR("ARI not supported (check pci bridge ARI forwarding), SRIOV can not be enabled\n");
1214 return 0;
1215 }
1216
1217 /* verify igu is in normal mode */
1218 if (CHIP_INT_MODE_IS_BC(bp)) {
1219 BNX2X_ERR("IGU not normal mode, SRIOV can not be enabled\n");
1220 return 0;
1221 }
1222
1223 /* allocate the vfs database */
1224 bp->vfdb = kzalloc(sizeof(*(bp->vfdb)), GFP_KERNEL);
1225 if (!bp->vfdb) {
1226 BNX2X_ERR("failed to allocate vf database\n");
1227 err = -ENOMEM;
1228 goto failed;
1229 }
1230
1231 /* get the sriov info - Linux already collected all the pertinent
1232 * information, however the sriov structure is for the private use
1233 * of the pci module. Also we want this information regardless
1234 * of the hyper-visor.
1235 */
1236 iov = &(bp->vfdb->sriov);
1237 err = bnx2x_sriov_info(bp, iov);
1238 if (err)
1239 goto failed;
1240
1241 /* SR-IOV capability was enabled but there are no VFs*/
1242 if (iov->total == 0)
1243 goto failed;
1244
1245 iov->nr_virtfn = min_t(u16, iov->total, num_vfs_param);
1246
1247 DP(BNX2X_MSG_IOV, "num_vfs_param was %d, nr_virtfn was %d\n",
1248 num_vfs_param, iov->nr_virtfn);
1249
1250 /* allocate the vf array */
1251 bp->vfdb->vfs = kzalloc(sizeof(struct bnx2x_virtf) *
1252 BNX2X_NR_VIRTFN(bp), GFP_KERNEL);
1253 if (!bp->vfdb->vfs) {
1254 BNX2X_ERR("failed to allocate vf array\n");
1255 err = -ENOMEM;
1256 goto failed;
1257 }
1258
1259 /* Initial VF init - index and abs_vfid - nr_virtfn must be set */
1260 for_each_vf(bp, i) {
1261 bnx2x_vf(bp, i, index) = i;
1262 bnx2x_vf(bp, i, abs_vfid) = iov->first_vf_in_pf + i;
1263 bnx2x_vf(bp, i, state) = VF_FREE;
1264 mutex_init(&bnx2x_vf(bp, i, op_mutex));
1265 bnx2x_vf(bp, i, op_current) = CHANNEL_TLV_NONE;
1266 }
1267
1268 /* re-read the IGU CAM for VFs - index and abs_vfid must be set */
1269 if (!bnx2x_get_vf_igu_cam_info(bp)) {
1270 BNX2X_ERR("No entries in IGU CAM for vfs\n");
1271 err = -EINVAL;
1272 goto failed;
1273 }
1274
1275 /* allocate the queue arrays for all VFs */
1276 bp->vfdb->vfqs = kzalloc(
1277 BNX2X_MAX_NUM_VF_QUEUES * sizeof(struct bnx2x_vf_queue),
1278 GFP_KERNEL);
1279
1280 if (!bp->vfdb->vfqs) {
1281 BNX2X_ERR("failed to allocate vf queue array\n");
1282 err = -ENOMEM;
1283 goto failed;
1284 }
1285
1286 /* Prepare the VFs event synchronization mechanism */
1287 mutex_init(&bp->vfdb->event_mutex);
1288
1289 mutex_init(&bp->vfdb->bulletin_mutex);
1290
1291 if (SHMEM2_HAS(bp, sriov_switch_mode))
1292 SHMEM2_WR(bp, sriov_switch_mode, SRIOV_SWITCH_MODE_VEB);
1293
1294 return 0;
1295 failed:
1296 DP(BNX2X_MSG_IOV, "Failed err=%d\n", err);
1297 __bnx2x_iov_free_vfdb(bp);
1298 return err;
1299 }
1300
1301 void bnx2x_iov_remove_one(struct bnx2x *bp)
1302 {
1303 int vf_idx;
1304
1305 /* if SRIOV is not enabled there's nothing to do */
1306 if (!IS_SRIOV(bp))
1307 return;
1308
1309 bnx2x_disable_sriov(bp);
1310
1311 /* disable access to all VFs */
1312 for (vf_idx = 0; vf_idx < bp->vfdb->sriov.total; vf_idx++) {
1313 bnx2x_pretend_func(bp,
1314 HW_VF_HANDLE(bp,
1315 bp->vfdb->sriov.first_vf_in_pf +
1316 vf_idx));
1317 DP(BNX2X_MSG_IOV, "disabling internal access for vf %d\n",
1318 bp->vfdb->sriov.first_vf_in_pf + vf_idx);
1319 bnx2x_vf_enable_internal(bp, 0);
1320 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1321 }
1322
1323 /* free vf database */
1324 __bnx2x_iov_free_vfdb(bp);
1325 }
1326
1327 void bnx2x_iov_free_mem(struct bnx2x *bp)
1328 {
1329 int i;
1330
1331 if (!IS_SRIOV(bp))
1332 return;
1333
1334 /* free vfs hw contexts */
1335 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) {
1336 struct hw_dma *cxt = &bp->vfdb->context[i];
1337 BNX2X_PCI_FREE(cxt->addr, cxt->mapping, cxt->size);
1338 }
1339
1340 BNX2X_PCI_FREE(BP_VFDB(bp)->sp_dma.addr,
1341 BP_VFDB(bp)->sp_dma.mapping,
1342 BP_VFDB(bp)->sp_dma.size);
1343
1344 BNX2X_PCI_FREE(BP_VF_MBX_DMA(bp)->addr,
1345 BP_VF_MBX_DMA(bp)->mapping,
1346 BP_VF_MBX_DMA(bp)->size);
1347
1348 BNX2X_PCI_FREE(BP_VF_BULLETIN_DMA(bp)->addr,
1349 BP_VF_BULLETIN_DMA(bp)->mapping,
1350 BP_VF_BULLETIN_DMA(bp)->size);
1351 }
1352
1353 int bnx2x_iov_alloc_mem(struct bnx2x *bp)
1354 {
1355 size_t tot_size;
1356 int i, rc = 0;
1357
1358 if (!IS_SRIOV(bp))
1359 return rc;
1360
1361 /* allocate vfs hw contexts */
1362 tot_size = (BP_VFDB(bp)->sriov.first_vf_in_pf + BNX2X_NR_VIRTFN(bp)) *
1363 BNX2X_CIDS_PER_VF * sizeof(union cdu_context);
1364
1365 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) {
1366 struct hw_dma *cxt = BP_VF_CXT_PAGE(bp, i);
1367 cxt->size = min_t(size_t, tot_size, CDU_ILT_PAGE_SZ);
1368
1369 if (cxt->size) {
1370 cxt->addr = BNX2X_PCI_ALLOC(&cxt->mapping, cxt->size);
1371 if (!cxt->addr)
1372 goto alloc_mem_err;
1373 } else {
1374 cxt->addr = NULL;
1375 cxt->mapping = 0;
1376 }
1377 tot_size -= cxt->size;
1378 }
1379
1380 /* allocate vfs ramrods dma memory - client_init and set_mac */
1381 tot_size = BNX2X_NR_VIRTFN(bp) * sizeof(struct bnx2x_vf_sp);
1382 BP_VFDB(bp)->sp_dma.addr = BNX2X_PCI_ALLOC(&BP_VFDB(bp)->sp_dma.mapping,
1383 tot_size);
1384 if (!BP_VFDB(bp)->sp_dma.addr)
1385 goto alloc_mem_err;
1386 BP_VFDB(bp)->sp_dma.size = tot_size;
1387
1388 /* allocate mailboxes */
1389 tot_size = BNX2X_NR_VIRTFN(bp) * MBX_MSG_ALIGNED_SIZE;
1390 BP_VF_MBX_DMA(bp)->addr = BNX2X_PCI_ALLOC(&BP_VF_MBX_DMA(bp)->mapping,
1391 tot_size);
1392 if (!BP_VF_MBX_DMA(bp)->addr)
1393 goto alloc_mem_err;
1394
1395 BP_VF_MBX_DMA(bp)->size = tot_size;
1396
1397 /* allocate local bulletin boards */
1398 tot_size = BNX2X_NR_VIRTFN(bp) * BULLETIN_CONTENT_SIZE;
1399 BP_VF_BULLETIN_DMA(bp)->addr = BNX2X_PCI_ALLOC(&BP_VF_BULLETIN_DMA(bp)->mapping,
1400 tot_size);
1401 if (!BP_VF_BULLETIN_DMA(bp)->addr)
1402 goto alloc_mem_err;
1403
1404 BP_VF_BULLETIN_DMA(bp)->size = tot_size;
1405
1406 return 0;
1407
1408 alloc_mem_err:
1409 return -ENOMEM;
1410 }
1411
1412 static void bnx2x_vfq_init(struct bnx2x *bp, struct bnx2x_virtf *vf,
1413 struct bnx2x_vf_queue *q)
1414 {
1415 u8 cl_id = vfq_cl_id(vf, q);
1416 u8 func_id = FW_VF_HANDLE(vf->abs_vfid);
1417 unsigned long q_type = 0;
1418
1419 set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
1420 set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
1421
1422 /* Queue State object */
1423 bnx2x_init_queue_obj(bp, &q->sp_obj,
1424 cl_id, &q->cid, 1, func_id,
1425 bnx2x_vf_sp(bp, vf, q_data),
1426 bnx2x_vf_sp_map(bp, vf, q_data),
1427 q_type);
1428
1429 /* sp indication is set only when vlan/mac/etc. are initialized */
1430 q->sp_initialized = false;
1431
1432 DP(BNX2X_MSG_IOV,
1433 "initialized vf %d's queue object. func id set to %d. cid set to 0x%x\n",
1434 vf->abs_vfid, q->sp_obj.func_id, q->cid);
1435 }
1436
1437 static int bnx2x_max_speed_cap(struct bnx2x *bp)
1438 {
1439 u32 supported = bp->port.supported[bnx2x_get_link_cfg_idx(bp)];
1440
1441 if (supported &
1442 (SUPPORTED_20000baseMLD2_Full | SUPPORTED_20000baseKR2_Full))
1443 return 20000;
1444
1445 return 10000; /* assume lowest supported speed is 10G */
1446 }
1447
1448 int bnx2x_iov_link_update_vf(struct bnx2x *bp, int idx)
1449 {
1450 struct bnx2x_link_report_data *state = &bp->last_reported_link;
1451 struct pf_vf_bulletin_content *bulletin;
1452 struct bnx2x_virtf *vf;
1453 bool update = true;
1454 int rc = 0;
1455
1456 /* sanity and init */
1457 rc = bnx2x_vf_op_prep(bp, idx, &vf, &bulletin, false);
1458 if (rc)
1459 return rc;
1460
1461 mutex_lock(&bp->vfdb->bulletin_mutex);
1462
1463 if (vf->link_cfg == IFLA_VF_LINK_STATE_AUTO) {
1464 bulletin->valid_bitmap |= 1 << LINK_VALID;
1465
1466 bulletin->link_speed = state->line_speed;
1467 bulletin->link_flags = 0;
1468 if (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1469 &state->link_report_flags))
1470 bulletin->link_flags |= VFPF_LINK_REPORT_LINK_DOWN;
1471 if (test_bit(BNX2X_LINK_REPORT_FD,
1472 &state->link_report_flags))
1473 bulletin->link_flags |= VFPF_LINK_REPORT_FULL_DUPLEX;
1474 if (test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
1475 &state->link_report_flags))
1476 bulletin->link_flags |= VFPF_LINK_REPORT_RX_FC_ON;
1477 if (test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
1478 &state->link_report_flags))
1479 bulletin->link_flags |= VFPF_LINK_REPORT_TX_FC_ON;
1480 } else if (vf->link_cfg == IFLA_VF_LINK_STATE_DISABLE &&
1481 !(bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)) {
1482 bulletin->valid_bitmap |= 1 << LINK_VALID;
1483 bulletin->link_flags |= VFPF_LINK_REPORT_LINK_DOWN;
1484 } else if (vf->link_cfg == IFLA_VF_LINK_STATE_ENABLE &&
1485 (bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)) {
1486 bulletin->valid_bitmap |= 1 << LINK_VALID;
1487 bulletin->link_speed = bnx2x_max_speed_cap(bp);
1488 bulletin->link_flags &= ~VFPF_LINK_REPORT_LINK_DOWN;
1489 } else {
1490 update = false;
1491 }
1492
1493 if (update) {
1494 DP(NETIF_MSG_LINK | BNX2X_MSG_IOV,
1495 "vf %d mode %u speed %d flags %x\n", idx,
1496 vf->link_cfg, bulletin->link_speed, bulletin->link_flags);
1497
1498 /* Post update on VF's bulletin board */
1499 rc = bnx2x_post_vf_bulletin(bp, idx);
1500 if (rc) {
1501 BNX2X_ERR("failed to update VF[%d] bulletin\n", idx);
1502 goto out;
1503 }
1504 }
1505
1506 out:
1507 mutex_unlock(&bp->vfdb->bulletin_mutex);
1508 return rc;
1509 }
1510
1511 int bnx2x_set_vf_link_state(struct net_device *dev, int idx, int link_state)
1512 {
1513 struct bnx2x *bp = netdev_priv(dev);
1514 struct bnx2x_virtf *vf = BP_VF(bp, idx);
1515
1516 if (!vf)
1517 return -EINVAL;
1518
1519 if (vf->link_cfg == link_state)
1520 return 0; /* nothing todo */
1521
1522 vf->link_cfg = link_state;
1523
1524 return bnx2x_iov_link_update_vf(bp, idx);
1525 }
1526
1527 void bnx2x_iov_link_update(struct bnx2x *bp)
1528 {
1529 int vfid;
1530
1531 if (!IS_SRIOV(bp))
1532 return;
1533
1534 for_each_vf(bp, vfid)
1535 bnx2x_iov_link_update_vf(bp, vfid);
1536 }
1537
1538 /* called by bnx2x_nic_load */
1539 int bnx2x_iov_nic_init(struct bnx2x *bp)
1540 {
1541 int vfid;
1542
1543 if (!IS_SRIOV(bp)) {
1544 DP(BNX2X_MSG_IOV, "vfdb was not allocated\n");
1545 return 0;
1546 }
1547
1548 DP(BNX2X_MSG_IOV, "num of vfs: %d\n", (bp)->vfdb->sriov.nr_virtfn);
1549
1550 /* let FLR complete ... */
1551 msleep(100);
1552
1553 /* initialize vf database */
1554 for_each_vf(bp, vfid) {
1555 struct bnx2x_virtf *vf = BP_VF(bp, vfid);
1556
1557 int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vfid) *
1558 BNX2X_CIDS_PER_VF;
1559
1560 union cdu_context *base_cxt = (union cdu_context *)
1561 BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr +
1562 (base_vf_cid & (ILT_PAGE_CIDS-1));
1563
1564 DP(BNX2X_MSG_IOV,
1565 "VF[%d] Max IGU SBs: %d, base vf cid 0x%x, base cid 0x%x, base cxt %p\n",
1566 vf->abs_vfid, vf_sb_count(vf), base_vf_cid,
1567 BNX2X_FIRST_VF_CID + base_vf_cid, base_cxt);
1568
1569 /* init statically provisioned resources */
1570 bnx2x_iov_static_resc(bp, vf);
1571
1572 /* queues are initialized during VF-ACQUIRE */
1573 vf->filter_state = 0;
1574 vf->sp_cl_id = bnx2x_fp(bp, 0, cl_id);
1575
1576 bnx2x_init_credit_pool(&vf->vf_vlans_pool, 0,
1577 vf_vlan_rules_cnt(vf));
1578 bnx2x_init_credit_pool(&vf->vf_macs_pool, 0,
1579 vf_mac_rules_cnt(vf));
1580
1581 /* init mcast object - This object will be re-initialized
1582 * during VF-ACQUIRE with the proper cl_id and cid.
1583 * It needs to be initialized here so that it can be safely
1584 * handled by a subsequent FLR flow.
1585 */
1586 vf->mcast_list_len = 0;
1587 bnx2x_init_mcast_obj(bp, &vf->mcast_obj, 0xFF,
1588 0xFF, 0xFF, 0xFF,
1589 bnx2x_vf_sp(bp, vf, mcast_rdata),
1590 bnx2x_vf_sp_map(bp, vf, mcast_rdata),
1591 BNX2X_FILTER_MCAST_PENDING,
1592 &vf->filter_state,
1593 BNX2X_OBJ_TYPE_RX_TX);
1594
1595 /* set the mailbox message addresses */
1596 BP_VF_MBX(bp, vfid)->msg = (struct bnx2x_vf_mbx_msg *)
1597 (((u8 *)BP_VF_MBX_DMA(bp)->addr) + vfid *
1598 MBX_MSG_ALIGNED_SIZE);
1599
1600 BP_VF_MBX(bp, vfid)->msg_mapping = BP_VF_MBX_DMA(bp)->mapping +
1601 vfid * MBX_MSG_ALIGNED_SIZE;
1602
1603 /* Enable vf mailbox */
1604 bnx2x_vf_enable_mbx(bp, vf->abs_vfid);
1605 }
1606
1607 /* Final VF init */
1608 for_each_vf(bp, vfid) {
1609 struct bnx2x_virtf *vf = BP_VF(bp, vfid);
1610
1611 /* fill in the BDF and bars */
1612 vf->bus = bnx2x_vf_bus(bp, vfid);
1613 vf->devfn = bnx2x_vf_devfn(bp, vfid);
1614 bnx2x_vf_set_bars(bp, vf);
1615
1616 DP(BNX2X_MSG_IOV,
1617 "VF info[%d]: bus 0x%x, devfn 0x%x, bar0 [0x%x, %d], bar1 [0x%x, %d], bar2 [0x%x, %d]\n",
1618 vf->abs_vfid, vf->bus, vf->devfn,
1619 (unsigned)vf->bars[0].bar, vf->bars[0].size,
1620 (unsigned)vf->bars[1].bar, vf->bars[1].size,
1621 (unsigned)vf->bars[2].bar, vf->bars[2].size);
1622 }
1623
1624 return 0;
1625 }
1626
1627 /* called by bnx2x_chip_cleanup */
1628 int bnx2x_iov_chip_cleanup(struct bnx2x *bp)
1629 {
1630 int i;
1631
1632 if (!IS_SRIOV(bp))
1633 return 0;
1634
1635 /* release all the VFs */
1636 for_each_vf(bp, i)
1637 bnx2x_vf_release(bp, BP_VF(bp, i));
1638
1639 return 0;
1640 }
1641
1642 /* called by bnx2x_init_hw_func, returns the next ilt line */
1643 int bnx2x_iov_init_ilt(struct bnx2x *bp, u16 line)
1644 {
1645 int i;
1646 struct bnx2x_ilt *ilt = BP_ILT(bp);
1647
1648 if (!IS_SRIOV(bp))
1649 return line;
1650
1651 /* set vfs ilt lines */
1652 for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) {
1653 struct hw_dma *hw_cxt = BP_VF_CXT_PAGE(bp, i);
1654
1655 ilt->lines[line+i].page = hw_cxt->addr;
1656 ilt->lines[line+i].page_mapping = hw_cxt->mapping;
1657 ilt->lines[line+i].size = hw_cxt->size; /* doesn't matter */
1658 }
1659 return line + i;
1660 }
1661
1662 static u8 bnx2x_iov_is_vf_cid(struct bnx2x *bp, u16 cid)
1663 {
1664 return ((cid >= BNX2X_FIRST_VF_CID) &&
1665 ((cid - BNX2X_FIRST_VF_CID) < BNX2X_VF_CIDS));
1666 }
1667
1668 static
1669 void bnx2x_vf_handle_classification_eqe(struct bnx2x *bp,
1670 struct bnx2x_vf_queue *vfq,
1671 union event_ring_elem *elem)
1672 {
1673 unsigned long ramrod_flags = 0;
1674 int rc = 0;
1675 u32 echo = le32_to_cpu(elem->message.data.eth_event.echo);
1676
1677 /* Always push next commands out, don't wait here */
1678 set_bit(RAMROD_CONT, &ramrod_flags);
1679
1680 switch (echo >> BNX2X_SWCID_SHIFT) {
1681 case BNX2X_FILTER_MAC_PENDING:
1682 rc = vfq->mac_obj.complete(bp, &vfq->mac_obj, elem,
1683 &ramrod_flags);
1684 break;
1685 case BNX2X_FILTER_VLAN_PENDING:
1686 rc = vfq->vlan_obj.complete(bp, &vfq->vlan_obj, elem,
1687 &ramrod_flags);
1688 break;
1689 default:
1690 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo);
1691 return;
1692 }
1693 if (rc < 0)
1694 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
1695 else if (rc > 0)
1696 DP(BNX2X_MSG_IOV, "Scheduled next pending commands...\n");
1697 }
1698
1699 static
1700 void bnx2x_vf_handle_mcast_eqe(struct bnx2x *bp,
1701 struct bnx2x_virtf *vf)
1702 {
1703 struct bnx2x_mcast_ramrod_params rparam = {NULL};
1704 int rc;
1705
1706 rparam.mcast_obj = &vf->mcast_obj;
1707 vf->mcast_obj.raw.clear_pending(&vf->mcast_obj.raw);
1708
1709 /* If there are pending mcast commands - send them */
1710 if (vf->mcast_obj.check_pending(&vf->mcast_obj)) {
1711 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
1712 if (rc < 0)
1713 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
1714 rc);
1715 }
1716 }
1717
1718 static
1719 void bnx2x_vf_handle_filters_eqe(struct bnx2x *bp,
1720 struct bnx2x_virtf *vf)
1721 {
1722 smp_mb__before_atomic();
1723 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state);
1724 smp_mb__after_atomic();
1725 }
1726
1727 static void bnx2x_vf_handle_rss_update_eqe(struct bnx2x *bp,
1728 struct bnx2x_virtf *vf)
1729 {
1730 vf->rss_conf_obj.raw.clear_pending(&vf->rss_conf_obj.raw);
1731 }
1732
1733 int bnx2x_iov_eq_sp_event(struct bnx2x *bp, union event_ring_elem *elem)
1734 {
1735 struct bnx2x_virtf *vf;
1736 int qidx = 0, abs_vfid;
1737 u8 opcode;
1738 u16 cid = 0xffff;
1739
1740 if (!IS_SRIOV(bp))
1741 return 1;
1742
1743 /* first get the cid - the only events we handle here are cfc-delete
1744 * and set-mac completion
1745 */
1746 opcode = elem->message.opcode;
1747
1748 switch (opcode) {
1749 case EVENT_RING_OPCODE_CFC_DEL:
1750 cid = SW_CID(elem->message.data.cfc_del_event.cid);
1751 DP(BNX2X_MSG_IOV, "checking cfc-del comp cid=%d\n", cid);
1752 break;
1753 case EVENT_RING_OPCODE_CLASSIFICATION_RULES:
1754 case EVENT_RING_OPCODE_MULTICAST_RULES:
1755 case EVENT_RING_OPCODE_FILTERS_RULES:
1756 case EVENT_RING_OPCODE_RSS_UPDATE_RULES:
1757 cid = SW_CID(elem->message.data.eth_event.echo);
1758 DP(BNX2X_MSG_IOV, "checking filtering comp cid=%d\n", cid);
1759 break;
1760 case EVENT_RING_OPCODE_VF_FLR:
1761 abs_vfid = elem->message.data.vf_flr_event.vf_id;
1762 DP(BNX2X_MSG_IOV, "Got VF FLR notification abs_vfid=%d\n",
1763 abs_vfid);
1764 goto get_vf;
1765 case EVENT_RING_OPCODE_MALICIOUS_VF:
1766 abs_vfid = elem->message.data.malicious_vf_event.vf_id;
1767 BNX2X_ERR("Got VF MALICIOUS notification abs_vfid=%d err_id=0x%x\n",
1768 abs_vfid,
1769 elem->message.data.malicious_vf_event.err_id);
1770 goto get_vf;
1771 default:
1772 return 1;
1773 }
1774
1775 /* check if the cid is the VF range */
1776 if (!bnx2x_iov_is_vf_cid(bp, cid)) {
1777 DP(BNX2X_MSG_IOV, "cid is outside vf range: %d\n", cid);
1778 return 1;
1779 }
1780
1781 /* extract vf and rxq index from vf_cid - relies on the following:
1782 * 1. vfid on cid reflects the true abs_vfid
1783 * 2. The max number of VFs (per path) is 64
1784 */
1785 qidx = cid & ((1 << BNX2X_VF_CID_WND)-1);
1786 abs_vfid = (cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1);
1787 get_vf:
1788 vf = bnx2x_vf_by_abs_fid(bp, abs_vfid);
1789
1790 if (!vf) {
1791 BNX2X_ERR("EQ completion for unknown VF, cid %d, abs_vfid %d\n",
1792 cid, abs_vfid);
1793 return 0;
1794 }
1795
1796 switch (opcode) {
1797 case EVENT_RING_OPCODE_CFC_DEL:
1798 DP(BNX2X_MSG_IOV, "got VF [%d:%d] cfc delete ramrod\n",
1799 vf->abs_vfid, qidx);
1800 vfq_get(vf, qidx)->sp_obj.complete_cmd(bp,
1801 &vfq_get(vf,
1802 qidx)->sp_obj,
1803 BNX2X_Q_CMD_CFC_DEL);
1804 break;
1805 case EVENT_RING_OPCODE_CLASSIFICATION_RULES:
1806 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mac/vlan ramrod\n",
1807 vf->abs_vfid, qidx);
1808 bnx2x_vf_handle_classification_eqe(bp, vfq_get(vf, qidx), elem);
1809 break;
1810 case EVENT_RING_OPCODE_MULTICAST_RULES:
1811 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mcast ramrod\n",
1812 vf->abs_vfid, qidx);
1813 bnx2x_vf_handle_mcast_eqe(bp, vf);
1814 break;
1815 case EVENT_RING_OPCODE_FILTERS_RULES:
1816 DP(BNX2X_MSG_IOV, "got VF [%d:%d] set rx-mode ramrod\n",
1817 vf->abs_vfid, qidx);
1818 bnx2x_vf_handle_filters_eqe(bp, vf);
1819 break;
1820 case EVENT_RING_OPCODE_RSS_UPDATE_RULES:
1821 DP(BNX2X_MSG_IOV, "got VF [%d:%d] RSS update ramrod\n",
1822 vf->abs_vfid, qidx);
1823 bnx2x_vf_handle_rss_update_eqe(bp, vf);
1824 case EVENT_RING_OPCODE_VF_FLR:
1825 case EVENT_RING_OPCODE_MALICIOUS_VF:
1826 /* Do nothing for now */
1827 return 0;
1828 }
1829
1830 return 0;
1831 }
1832
1833 static struct bnx2x_virtf *bnx2x_vf_by_cid(struct bnx2x *bp, int vf_cid)
1834 {
1835 /* extract the vf from vf_cid - relies on the following:
1836 * 1. vfid on cid reflects the true abs_vfid
1837 * 2. The max number of VFs (per path) is 64
1838 */
1839 int abs_vfid = (vf_cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1);
1840 return bnx2x_vf_by_abs_fid(bp, abs_vfid);
1841 }
1842
1843 void bnx2x_iov_set_queue_sp_obj(struct bnx2x *bp, int vf_cid,
1844 struct bnx2x_queue_sp_obj **q_obj)
1845 {
1846 struct bnx2x_virtf *vf;
1847
1848 if (!IS_SRIOV(bp))
1849 return;
1850
1851 vf = bnx2x_vf_by_cid(bp, vf_cid);
1852
1853 if (vf) {
1854 /* extract queue index from vf_cid - relies on the following:
1855 * 1. vfid on cid reflects the true abs_vfid
1856 * 2. The max number of VFs (per path) is 64
1857 */
1858 int q_index = vf_cid & ((1 << BNX2X_VF_CID_WND)-1);
1859 *q_obj = &bnx2x_vfq(vf, q_index, sp_obj);
1860 } else {
1861 BNX2X_ERR("No vf matching cid %d\n", vf_cid);
1862 }
1863 }
1864
1865 void bnx2x_iov_adjust_stats_req(struct bnx2x *bp)
1866 {
1867 int i;
1868 int first_queue_query_index, num_queues_req;
1869 dma_addr_t cur_data_offset;
1870 struct stats_query_entry *cur_query_entry;
1871 u8 stats_count = 0;
1872 bool is_fcoe = false;
1873
1874 if (!IS_SRIOV(bp))
1875 return;
1876
1877 if (!NO_FCOE(bp))
1878 is_fcoe = true;
1879
1880 /* fcoe adds one global request and one queue request */
1881 num_queues_req = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe;
1882 first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX -
1883 (is_fcoe ? 0 : 1);
1884
1885 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS),
1886 "BNX2X_NUM_ETH_QUEUES %d, is_fcoe %d, first_queue_query_index %d => determined the last non virtual statistics query index is %d. Will add queries on top of that\n",
1887 BNX2X_NUM_ETH_QUEUES(bp), is_fcoe, first_queue_query_index,
1888 first_queue_query_index + num_queues_req);
1889
1890 cur_data_offset = bp->fw_stats_data_mapping +
1891 offsetof(struct bnx2x_fw_stats_data, queue_stats) +
1892 num_queues_req * sizeof(struct per_queue_stats);
1893
1894 cur_query_entry = &bp->fw_stats_req->
1895 query[first_queue_query_index + num_queues_req];
1896
1897 for_each_vf(bp, i) {
1898 int j;
1899 struct bnx2x_virtf *vf = BP_VF(bp, i);
1900
1901 if (vf->state != VF_ENABLED) {
1902 DP_AND((BNX2X_MSG_IOV | BNX2X_MSG_STATS),
1903 "vf %d not enabled so no stats for it\n",
1904 vf->abs_vfid);
1905 continue;
1906 }
1907
1908 DP(BNX2X_MSG_IOV, "add addresses for vf %d\n", vf->abs_vfid);
1909 for_each_vfq(vf, j) {
1910 struct bnx2x_vf_queue *rxq = vfq_get(vf, j);
1911
1912 dma_addr_t q_stats_addr =
1913 vf->fw_stat_map + j * vf->stats_stride;
1914
1915 /* collect stats fro active queues only */
1916 if (bnx2x_get_q_logical_state(bp, &rxq->sp_obj) ==
1917 BNX2X_Q_LOGICAL_STATE_STOPPED)
1918 continue;
1919
1920 /* create stats query entry for this queue */
1921 cur_query_entry->kind = STATS_TYPE_QUEUE;
1922 cur_query_entry->index = vfq_stat_id(vf, rxq);
1923 cur_query_entry->funcID =
1924 cpu_to_le16(FW_VF_HANDLE(vf->abs_vfid));
1925 cur_query_entry->address.hi =
1926 cpu_to_le32(U64_HI(q_stats_addr));
1927 cur_query_entry->address.lo =
1928 cpu_to_le32(U64_LO(q_stats_addr));
1929 DP(BNX2X_MSG_IOV,
1930 "added address %x %x for vf %d queue %d client %d\n",
1931 cur_query_entry->address.hi,
1932 cur_query_entry->address.lo, cur_query_entry->funcID,
1933 j, cur_query_entry->index);
1934 cur_query_entry++;
1935 cur_data_offset += sizeof(struct per_queue_stats);
1936 stats_count++;
1937
1938 /* all stats are coalesced to the leading queue */
1939 if (vf->cfg_flags & VF_CFG_STATS_COALESCE)
1940 break;
1941 }
1942 }
1943 bp->fw_stats_req->hdr.cmd_num = bp->fw_stats_num + stats_count;
1944 }
1945
1946 /* VF API helpers */
1947 static void bnx2x_vf_qtbl_set_q(struct bnx2x *bp, u8 abs_vfid, u8 qid,
1948 u8 enable)
1949 {
1950 u32 reg = PXP_REG_HST_ZONE_PERMISSION_TABLE + qid * 4;
1951 u32 val = enable ? (abs_vfid | (1 << 6)) : 0;
1952
1953 REG_WR(bp, reg, val);
1954 }
1955
1956 static void bnx2x_vf_clr_qtbl(struct bnx2x *bp, struct bnx2x_virtf *vf)
1957 {
1958 int i;
1959
1960 for_each_vfq(vf, i)
1961 bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid,
1962 vfq_qzone_id(vf, vfq_get(vf, i)), false);
1963 }
1964
1965 static void bnx2x_vf_igu_disable(struct bnx2x *bp, struct bnx2x_virtf *vf)
1966 {
1967 u32 val;
1968
1969 /* clear the VF configuration - pretend */
1970 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid));
1971 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION);
1972 val &= ~(IGU_VF_CONF_MSI_MSIX_EN | IGU_VF_CONF_SINGLE_ISR_EN |
1973 IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_PARENT_MASK);
1974 REG_WR(bp, IGU_REG_VF_CONFIGURATION, val);
1975 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1976 }
1977
1978 u8 bnx2x_vf_max_queue_cnt(struct bnx2x *bp, struct bnx2x_virtf *vf)
1979 {
1980 return min_t(u8, min_t(u8, vf_sb_count(vf), BNX2X_CIDS_PER_VF),
1981 BNX2X_VF_MAX_QUEUES);
1982 }
1983
1984 static
1985 int bnx2x_vf_chk_avail_resc(struct bnx2x *bp, struct bnx2x_virtf *vf,
1986 struct vf_pf_resc_request *req_resc)
1987 {
1988 u8 rxq_cnt = vf_rxq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf);
1989 u8 txq_cnt = vf_txq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf);
1990
1991 return ((req_resc->num_rxqs <= rxq_cnt) &&
1992 (req_resc->num_txqs <= txq_cnt) &&
1993 (req_resc->num_sbs <= vf_sb_count(vf)) &&
1994 (req_resc->num_mac_filters <= vf_mac_rules_cnt(vf)) &&
1995 (req_resc->num_vlan_filters <= vf_vlan_rules_cnt(vf)));
1996 }
1997
1998 /* CORE VF API */
1999 int bnx2x_vf_acquire(struct bnx2x *bp, struct bnx2x_virtf *vf,
2000 struct vf_pf_resc_request *resc)
2001 {
2002 int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vf->index) *
2003 BNX2X_CIDS_PER_VF;
2004
2005 union cdu_context *base_cxt = (union cdu_context *)
2006 BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr +
2007 (base_vf_cid & (ILT_PAGE_CIDS-1));
2008 int i;
2009
2010 /* if state is 'acquired' the VF was not released or FLR'd, in
2011 * this case the returned resources match the acquired already
2012 * acquired resources. Verify that the requested numbers do
2013 * not exceed the already acquired numbers.
2014 */
2015 if (vf->state == VF_ACQUIRED) {
2016 DP(BNX2X_MSG_IOV, "VF[%d] Trying to re-acquire resources (VF was not released or FLR'd)\n",
2017 vf->abs_vfid);
2018
2019 if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) {
2020 BNX2X_ERR("VF[%d] When re-acquiring resources, requested numbers must be <= then previously acquired numbers\n",
2021 vf->abs_vfid);
2022 return -EINVAL;
2023 }
2024 return 0;
2025 }
2026
2027 /* Otherwise vf state must be 'free' or 'reset' */
2028 if (vf->state != VF_FREE && vf->state != VF_RESET) {
2029 BNX2X_ERR("VF[%d] Can not acquire a VF with state %d\n",
2030 vf->abs_vfid, vf->state);
2031 return -EINVAL;
2032 }
2033
2034 /* static allocation:
2035 * the global maximum number are fixed per VF. Fail the request if
2036 * requested number exceed these globals
2037 */
2038 if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) {
2039 DP(BNX2X_MSG_IOV,
2040 "cannot fulfill vf resource request. Placing maximal available values in response\n");
2041 /* set the max resource in the vf */
2042 return -ENOMEM;
2043 }
2044
2045 /* Set resources counters - 0 request means max available */
2046 vf_sb_count(vf) = resc->num_sbs;
2047 vf_rxq_count(vf) = resc->num_rxqs ? : bnx2x_vf_max_queue_cnt(bp, vf);
2048 vf_txq_count(vf) = resc->num_txqs ? : bnx2x_vf_max_queue_cnt(bp, vf);
2049
2050 DP(BNX2X_MSG_IOV,
2051 "Fulfilling vf request: sb count %d, tx_count %d, rx_count %d, mac_rules_count %d, vlan_rules_count %d\n",
2052 vf_sb_count(vf), vf_rxq_count(vf),
2053 vf_txq_count(vf), vf_mac_rules_cnt(vf),
2054 vf_vlan_rules_cnt(vf));
2055
2056 /* Initialize the queues */
2057 if (!vf->vfqs) {
2058 DP(BNX2X_MSG_IOV, "vf->vfqs was not allocated\n");
2059 return -EINVAL;
2060 }
2061
2062 for_each_vfq(vf, i) {
2063 struct bnx2x_vf_queue *q = vfq_get(vf, i);
2064
2065 if (!q) {
2066 BNX2X_ERR("q number %d was not allocated\n", i);
2067 return -EINVAL;
2068 }
2069
2070 q->index = i;
2071 q->cxt = &((base_cxt + i)->eth);
2072 q->cid = BNX2X_FIRST_VF_CID + base_vf_cid + i;
2073
2074 DP(BNX2X_MSG_IOV, "VFQ[%d:%d]: index %d, cid 0x%x, cxt %p\n",
2075 vf->abs_vfid, i, q->index, q->cid, q->cxt);
2076
2077 /* init SP objects */
2078 bnx2x_vfq_init(bp, vf, q);
2079 }
2080 vf->state = VF_ACQUIRED;
2081 return 0;
2082 }
2083
2084 int bnx2x_vf_init(struct bnx2x *bp, struct bnx2x_virtf *vf, dma_addr_t *sb_map)
2085 {
2086 struct bnx2x_func_init_params func_init = {0};
2087 int i;
2088
2089 /* the sb resources are initialized at this point, do the
2090 * FW/HW initializations
2091 */
2092 for_each_vf_sb(vf, i)
2093 bnx2x_init_sb(bp, (dma_addr_t)sb_map[i], vf->abs_vfid, true,
2094 vf_igu_sb(vf, i), vf_igu_sb(vf, i));
2095
2096 /* Sanity checks */
2097 if (vf->state != VF_ACQUIRED) {
2098 DP(BNX2X_MSG_IOV, "VF[%d] is not in VF_ACQUIRED, but %d\n",
2099 vf->abs_vfid, vf->state);
2100 return -EINVAL;
2101 }
2102
2103 /* let FLR complete ... */
2104 msleep(100);
2105
2106 /* FLR cleanup epilogue */
2107 if (bnx2x_vf_flr_clnup_epilog(bp, vf->abs_vfid))
2108 return -EBUSY;
2109
2110 /* reset IGU VF statistics: MSIX */
2111 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + vf->abs_vfid * 4 , 0);
2112
2113 /* function setup */
2114 func_init.pf_id = BP_FUNC(bp);
2115 func_init.func_id = FW_VF_HANDLE(vf->abs_vfid);
2116 bnx2x_func_init(bp, &func_init);
2117
2118 /* Enable the vf */
2119 bnx2x_vf_enable_access(bp, vf->abs_vfid);
2120 bnx2x_vf_enable_traffic(bp, vf);
2121
2122 /* queue protection table */
2123 for_each_vfq(vf, i)
2124 bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid,
2125 vfq_qzone_id(vf, vfq_get(vf, i)), true);
2126
2127 vf->state = VF_ENABLED;
2128
2129 /* update vf bulletin board */
2130 bnx2x_post_vf_bulletin(bp, vf->index);
2131
2132 return 0;
2133 }
2134
2135 struct set_vf_state_cookie {
2136 struct bnx2x_virtf *vf;
2137 u8 state;
2138 };
2139
2140 static void bnx2x_set_vf_state(void *cookie)
2141 {
2142 struct set_vf_state_cookie *p = (struct set_vf_state_cookie *)cookie;
2143
2144 p->vf->state = p->state;
2145 }
2146
2147 int bnx2x_vf_close(struct bnx2x *bp, struct bnx2x_virtf *vf)
2148 {
2149 int rc = 0, i;
2150
2151 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
2152
2153 /* Close all queues */
2154 for (i = 0; i < vf_rxq_count(vf); i++) {
2155 rc = bnx2x_vf_queue_teardown(bp, vf, i);
2156 if (rc)
2157 goto op_err;
2158 }
2159
2160 /* disable the interrupts */
2161 DP(BNX2X_MSG_IOV, "disabling igu\n");
2162 bnx2x_vf_igu_disable(bp, vf);
2163
2164 /* disable the VF */
2165 DP(BNX2X_MSG_IOV, "clearing qtbl\n");
2166 bnx2x_vf_clr_qtbl(bp, vf);
2167
2168 /* need to make sure there are no outstanding stats ramrods which may
2169 * cause the device to access the VF's stats buffer which it will free
2170 * as soon as we return from the close flow.
2171 */
2172 {
2173 struct set_vf_state_cookie cookie;
2174
2175 cookie.vf = vf;
2176 cookie.state = VF_ACQUIRED;
2177 rc = bnx2x_stats_safe_exec(bp, bnx2x_set_vf_state, &cookie);
2178 if (rc)
2179 goto op_err;
2180 }
2181
2182 DP(BNX2X_MSG_IOV, "set state to acquired\n");
2183
2184 return 0;
2185 op_err:
2186 BNX2X_ERR("vf[%d] CLOSE error: rc %d\n", vf->abs_vfid, rc);
2187 return rc;
2188 }
2189
2190 /* VF release can be called either: 1. The VF was acquired but
2191 * not enabled 2. the vf was enabled or in the process of being
2192 * enabled
2193 */
2194 int bnx2x_vf_free(struct bnx2x *bp, struct bnx2x_virtf *vf)
2195 {
2196 int rc;
2197
2198 DP(BNX2X_MSG_IOV, "VF[%d] STATE: %s\n", vf->abs_vfid,
2199 vf->state == VF_FREE ? "Free" :
2200 vf->state == VF_ACQUIRED ? "Acquired" :
2201 vf->state == VF_ENABLED ? "Enabled" :
2202 vf->state == VF_RESET ? "Reset" :
2203 "Unknown");
2204
2205 switch (vf->state) {
2206 case VF_ENABLED:
2207 rc = bnx2x_vf_close(bp, vf);
2208 if (rc)
2209 goto op_err;
2210 /* Fallthrough to release resources */
2211 case VF_ACQUIRED:
2212 DP(BNX2X_MSG_IOV, "about to free resources\n");
2213 bnx2x_vf_free_resc(bp, vf);
2214 break;
2215
2216 case VF_FREE:
2217 case VF_RESET:
2218 default:
2219 break;
2220 }
2221 return 0;
2222 op_err:
2223 BNX2X_ERR("VF[%d] RELEASE error: rc %d\n", vf->abs_vfid, rc);
2224 return rc;
2225 }
2226
2227 int bnx2x_vf_rss_update(struct bnx2x *bp, struct bnx2x_virtf *vf,
2228 struct bnx2x_config_rss_params *rss)
2229 {
2230 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
2231 set_bit(RAMROD_COMP_WAIT, &rss->ramrod_flags);
2232 return bnx2x_config_rss(bp, rss);
2233 }
2234
2235 int bnx2x_vf_tpa_update(struct bnx2x *bp, struct bnx2x_virtf *vf,
2236 struct vfpf_tpa_tlv *tlv,
2237 struct bnx2x_queue_update_tpa_params *params)
2238 {
2239 aligned_u64 *sge_addr = tlv->tpa_client_info.sge_addr;
2240 struct bnx2x_queue_state_params qstate;
2241 int qid, rc = 0;
2242
2243 DP(BNX2X_MSG_IOV, "vf[%d]\n", vf->abs_vfid);
2244
2245 /* Set ramrod params */
2246 memset(&qstate, 0, sizeof(struct bnx2x_queue_state_params));
2247 memcpy(&qstate.params.update_tpa, params,
2248 sizeof(struct bnx2x_queue_update_tpa_params));
2249 qstate.cmd = BNX2X_Q_CMD_UPDATE_TPA;
2250 set_bit(RAMROD_COMP_WAIT, &qstate.ramrod_flags);
2251
2252 for (qid = 0; qid < vf_rxq_count(vf); qid++) {
2253 qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj);
2254 qstate.params.update_tpa.sge_map = sge_addr[qid];
2255 DP(BNX2X_MSG_IOV, "sge_addr[%d:%d] %08x:%08x\n",
2256 vf->abs_vfid, qid, U64_HI(sge_addr[qid]),
2257 U64_LO(sge_addr[qid]));
2258 rc = bnx2x_queue_state_change(bp, &qstate);
2259 if (rc) {
2260 BNX2X_ERR("Failed to configure sge_addr %08x:%08x for [%d:%d]\n",
2261 U64_HI(sge_addr[qid]), U64_LO(sge_addr[qid]),
2262 vf->abs_vfid, qid);
2263 return rc;
2264 }
2265 }
2266
2267 return rc;
2268 }
2269
2270 /* VF release ~ VF close + VF release-resources
2271 * Release is the ultimate SW shutdown and is called whenever an
2272 * irrecoverable error is encountered.
2273 */
2274 int bnx2x_vf_release(struct bnx2x *bp, struct bnx2x_virtf *vf)
2275 {
2276 int rc;
2277
2278 DP(BNX2X_MSG_IOV, "PF releasing vf %d\n", vf->abs_vfid);
2279 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF);
2280
2281 rc = bnx2x_vf_free(bp, vf);
2282 if (rc)
2283 WARN(rc,
2284 "VF[%d] Failed to allocate resources for release op- rc=%d\n",
2285 vf->abs_vfid, rc);
2286 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF);
2287 return rc;
2288 }
2289
2290 void bnx2x_lock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf,
2291 enum channel_tlvs tlv)
2292 {
2293 /* we don't lock the channel for unsupported tlvs */
2294 if (!bnx2x_tlv_supported(tlv)) {
2295 BNX2X_ERR("attempting to lock with unsupported tlv. Aborting\n");
2296 return;
2297 }
2298
2299 /* lock the channel */
2300 mutex_lock(&vf->op_mutex);
2301
2302 /* record the locking op */
2303 vf->op_current = tlv;
2304
2305 /* log the lock */
2306 DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel locked by %d\n",
2307 vf->abs_vfid, tlv);
2308 }
2309
2310 void bnx2x_unlock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf,
2311 enum channel_tlvs expected_tlv)
2312 {
2313 enum channel_tlvs current_tlv;
2314
2315 if (!vf) {
2316 BNX2X_ERR("VF was %p\n", vf);
2317 return;
2318 }
2319
2320 current_tlv = vf->op_current;
2321
2322 /* we don't unlock the channel for unsupported tlvs */
2323 if (!bnx2x_tlv_supported(expected_tlv))
2324 return;
2325
2326 WARN(expected_tlv != vf->op_current,
2327 "lock mismatch: expected %d found %d", expected_tlv,
2328 vf->op_current);
2329
2330 /* record the locking op */
2331 vf->op_current = CHANNEL_TLV_NONE;
2332
2333 /* lock the channel */
2334 mutex_unlock(&vf->op_mutex);
2335
2336 /* log the unlock */
2337 DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel unlocked by %d\n",
2338 vf->abs_vfid, current_tlv);
2339 }
2340
2341 static int bnx2x_set_pf_tx_switching(struct bnx2x *bp, bool enable)
2342 {
2343 struct bnx2x_queue_state_params q_params;
2344 u32 prev_flags;
2345 int i, rc;
2346
2347 /* Verify changes are needed and record current Tx switching state */
2348 prev_flags = bp->flags;
2349 if (enable)
2350 bp->flags |= TX_SWITCHING;
2351 else
2352 bp->flags &= ~TX_SWITCHING;
2353 if (prev_flags == bp->flags)
2354 return 0;
2355
2356 /* Verify state enables the sending of queue ramrods */
2357 if ((bp->state != BNX2X_STATE_OPEN) ||
2358 (bnx2x_get_q_logical_state(bp,
2359 &bnx2x_sp_obj(bp, &bp->fp[0]).q_obj) !=
2360 BNX2X_Q_LOGICAL_STATE_ACTIVE))
2361 return 0;
2362
2363 /* send q. update ramrod to configure Tx switching */
2364 memset(&q_params, 0, sizeof(q_params));
2365 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
2366 q_params.cmd = BNX2X_Q_CMD_UPDATE;
2367 __set_bit(BNX2X_Q_UPDATE_TX_SWITCHING_CHNG,
2368 &q_params.params.update.update_flags);
2369 if (enable)
2370 __set_bit(BNX2X_Q_UPDATE_TX_SWITCHING,
2371 &q_params.params.update.update_flags);
2372 else
2373 __clear_bit(BNX2X_Q_UPDATE_TX_SWITCHING,
2374 &q_params.params.update.update_flags);
2375
2376 /* send the ramrod on all the queues of the PF */
2377 for_each_eth_queue(bp, i) {
2378 struct bnx2x_fastpath *fp = &bp->fp[i];
2379
2380 /* Set the appropriate Queue object */
2381 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
2382
2383 /* Update the Queue state */
2384 rc = bnx2x_queue_state_change(bp, &q_params);
2385 if (rc) {
2386 BNX2X_ERR("Failed to configure Tx switching\n");
2387 return rc;
2388 }
2389 }
2390
2391 DP(BNX2X_MSG_IOV, "%s Tx Switching\n", enable ? "Enabled" : "Disabled");
2392 return 0;
2393 }
2394
2395 int bnx2x_sriov_configure(struct pci_dev *dev, int num_vfs_param)
2396 {
2397 struct bnx2x *bp = netdev_priv(pci_get_drvdata(dev));
2398
2399 if (!IS_SRIOV(bp)) {
2400 BNX2X_ERR("failed to configure SR-IOV since vfdb was not allocated. Check dmesg for errors in probe stage\n");
2401 return -EINVAL;
2402 }
2403
2404 DP(BNX2X_MSG_IOV, "bnx2x_sriov_configure called with %d, BNX2X_NR_VIRTFN(bp) was %d\n",
2405 num_vfs_param, BNX2X_NR_VIRTFN(bp));
2406
2407 /* HW channel is only operational when PF is up */
2408 if (bp->state != BNX2X_STATE_OPEN) {
2409 BNX2X_ERR("VF num configuration via sysfs not supported while PF is down\n");
2410 return -EINVAL;
2411 }
2412
2413 /* we are always bound by the total_vfs in the configuration space */
2414 if (num_vfs_param > BNX2X_NR_VIRTFN(bp)) {
2415 BNX2X_ERR("truncating requested number of VFs (%d) down to maximum allowed (%d)\n",
2416 num_vfs_param, BNX2X_NR_VIRTFN(bp));
2417 num_vfs_param = BNX2X_NR_VIRTFN(bp);
2418 }
2419
2420 bp->requested_nr_virtfn = num_vfs_param;
2421 if (num_vfs_param == 0) {
2422 bnx2x_set_pf_tx_switching(bp, false);
2423 bnx2x_disable_sriov(bp);
2424 return 0;
2425 } else {
2426 return bnx2x_enable_sriov(bp);
2427 }
2428 }
2429
2430 #define IGU_ENTRY_SIZE 4
2431
2432 int bnx2x_enable_sriov(struct bnx2x *bp)
2433 {
2434 int rc = 0, req_vfs = bp->requested_nr_virtfn;
2435 int vf_idx, sb_idx, vfq_idx, qcount, first_vf;
2436 u32 igu_entry, address;
2437 u16 num_vf_queues;
2438
2439 if (req_vfs == 0)
2440 return 0;
2441
2442 first_vf = bp->vfdb->sriov.first_vf_in_pf;
2443
2444 /* statically distribute vf sb pool between VFs */
2445 num_vf_queues = min_t(u16, BNX2X_VF_MAX_QUEUES,
2446 BP_VFDB(bp)->vf_sbs_pool / req_vfs);
2447
2448 /* zero previous values learned from igu cam */
2449 for (vf_idx = 0; vf_idx < req_vfs; vf_idx++) {
2450 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx);
2451
2452 vf->sb_count = 0;
2453 vf_sb_count(BP_VF(bp, vf_idx)) = 0;
2454 }
2455 bp->vfdb->vf_sbs_pool = 0;
2456
2457 /* prepare IGU cam */
2458 sb_idx = BP_VFDB(bp)->first_vf_igu_entry;
2459 address = IGU_REG_MAPPING_MEMORY + sb_idx * IGU_ENTRY_SIZE;
2460 for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) {
2461 for (vfq_idx = 0; vfq_idx < num_vf_queues; vfq_idx++) {
2462 igu_entry = vf_idx << IGU_REG_MAPPING_MEMORY_FID_SHIFT |
2463 vfq_idx << IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT |
2464 IGU_REG_MAPPING_MEMORY_VALID;
2465 DP(BNX2X_MSG_IOV, "assigning sb %d to vf %d\n",
2466 sb_idx, vf_idx);
2467 REG_WR(bp, address, igu_entry);
2468 sb_idx++;
2469 address += IGU_ENTRY_SIZE;
2470 }
2471 }
2472
2473 /* Reinitialize vf database according to igu cam */
2474 bnx2x_get_vf_igu_cam_info(bp);
2475
2476 DP(BNX2X_MSG_IOV, "vf_sbs_pool %d, num_vf_queues %d\n",
2477 BP_VFDB(bp)->vf_sbs_pool, num_vf_queues);
2478
2479 qcount = 0;
2480 for_each_vf(bp, vf_idx) {
2481 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx);
2482
2483 /* set local queue arrays */
2484 vf->vfqs = &bp->vfdb->vfqs[qcount];
2485 qcount += vf_sb_count(vf);
2486 bnx2x_iov_static_resc(bp, vf);
2487 }
2488
2489 /* prepare msix vectors in VF configuration space - the value in the
2490 * PCI configuration space should be the index of the last entry,
2491 * namely one less than the actual size of the table
2492 */
2493 for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) {
2494 bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf_idx));
2495 REG_WR(bp, PCICFG_OFFSET + GRC_CONFIG_REG_VF_MSIX_CONTROL,
2496 num_vf_queues - 1);
2497 DP(BNX2X_MSG_IOV, "set msix vec num in VF %d cfg space to %d\n",
2498 vf_idx, num_vf_queues - 1);
2499 }
2500 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
2501
2502 /* enable sriov. This will probe all the VFs, and consequentially cause
2503 * the "acquire" messages to appear on the VF PF channel.
2504 */
2505 DP(BNX2X_MSG_IOV, "about to call enable sriov\n");
2506 bnx2x_disable_sriov(bp);
2507
2508 rc = bnx2x_set_pf_tx_switching(bp, true);
2509 if (rc)
2510 return rc;
2511
2512 rc = pci_enable_sriov(bp->pdev, req_vfs);
2513 if (rc) {
2514 BNX2X_ERR("pci_enable_sriov failed with %d\n", rc);
2515 return rc;
2516 }
2517 DP(BNX2X_MSG_IOV, "sriov enabled (%d vfs)\n", req_vfs);
2518 return req_vfs;
2519 }
2520
2521 void bnx2x_pf_set_vfs_vlan(struct bnx2x *bp)
2522 {
2523 int vfidx;
2524 struct pf_vf_bulletin_content *bulletin;
2525
2526 DP(BNX2X_MSG_IOV, "configuring vlan for VFs from sp-task\n");
2527 for_each_vf(bp, vfidx) {
2528 bulletin = BP_VF_BULLETIN(bp, vfidx);
2529 if (bulletin->valid_bitmap & (1 << VLAN_VALID))
2530 bnx2x_set_vf_vlan(bp->dev, vfidx, bulletin->vlan, 0);
2531 }
2532 }
2533
2534 void bnx2x_disable_sriov(struct bnx2x *bp)
2535 {
2536 if (pci_vfs_assigned(bp->pdev)) {
2537 DP(BNX2X_MSG_IOV,
2538 "Unloading driver while VFs are assigned - VFs will not be deallocated\n");
2539 return;
2540 }
2541
2542 pci_disable_sriov(bp->pdev);
2543 }
2544
2545 static int bnx2x_vf_op_prep(struct bnx2x *bp, int vfidx,
2546 struct bnx2x_virtf **vf,
2547 struct pf_vf_bulletin_content **bulletin,
2548 bool test_queue)
2549 {
2550 if (bp->state != BNX2X_STATE_OPEN) {
2551 BNX2X_ERR("PF is down - can't utilize iov-related functionality\n");
2552 return -EINVAL;
2553 }
2554
2555 if (!IS_SRIOV(bp)) {
2556 BNX2X_ERR("sriov is disabled - can't utilize iov-related functionality\n");
2557 return -EINVAL;
2558 }
2559
2560 if (vfidx >= BNX2X_NR_VIRTFN(bp)) {
2561 BNX2X_ERR("VF is uninitialized - can't utilize iov-related functionality. vfidx was %d BNX2X_NR_VIRTFN was %d\n",
2562 vfidx, BNX2X_NR_VIRTFN(bp));
2563 return -EINVAL;
2564 }
2565
2566 /* init members */
2567 *vf = BP_VF(bp, vfidx);
2568 *bulletin = BP_VF_BULLETIN(bp, vfidx);
2569
2570 if (!*vf) {
2571 BNX2X_ERR("Unable to get VF structure for vfidx %d\n", vfidx);
2572 return -EINVAL;
2573 }
2574
2575 if (test_queue && !(*vf)->vfqs) {
2576 BNX2X_ERR("vfqs struct is null. Was this invoked before dynamically enabling SR-IOV? vfidx was %d\n",
2577 vfidx);
2578 return -EINVAL;
2579 }
2580
2581 if (!*bulletin) {
2582 BNX2X_ERR("Bulletin Board struct is null for vfidx %d\n",
2583 vfidx);
2584 return -EINVAL;
2585 }
2586
2587 return 0;
2588 }
2589
2590 int bnx2x_get_vf_config(struct net_device *dev, int vfidx,
2591 struct ifla_vf_info *ivi)
2592 {
2593 struct bnx2x *bp = netdev_priv(dev);
2594 struct bnx2x_virtf *vf = NULL;
2595 struct pf_vf_bulletin_content *bulletin = NULL;
2596 struct bnx2x_vlan_mac_obj *mac_obj;
2597 struct bnx2x_vlan_mac_obj *vlan_obj;
2598 int rc;
2599
2600 /* sanity and init */
2601 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true);
2602 if (rc)
2603 return rc;
2604
2605 mac_obj = &bnx2x_leading_vfq(vf, mac_obj);
2606 vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj);
2607 if (!mac_obj || !vlan_obj) {
2608 BNX2X_ERR("VF partially initialized\n");
2609 return -EINVAL;
2610 }
2611
2612 ivi->vf = vfidx;
2613 ivi->qos = 0;
2614 ivi->max_tx_rate = 10000; /* always 10G. TBA take from link struct */
2615 ivi->min_tx_rate = 0;
2616 ivi->spoofchk = 1; /*always enabled */
2617 if (vf->state == VF_ENABLED) {
2618 /* mac and vlan are in vlan_mac objects */
2619 if (bnx2x_validate_vf_sp_objs(bp, vf, false)) {
2620 mac_obj->get_n_elements(bp, mac_obj, 1, (u8 *)&ivi->mac,
2621 0, ETH_ALEN);
2622 vlan_obj->get_n_elements(bp, vlan_obj, 1,
2623 (u8 *)&ivi->vlan, 0,
2624 VLAN_HLEN);
2625 }
2626 } else {
2627 mutex_lock(&bp->vfdb->bulletin_mutex);
2628 /* mac */
2629 if (bulletin->valid_bitmap & (1 << MAC_ADDR_VALID))
2630 /* mac configured by ndo so its in bulletin board */
2631 memcpy(&ivi->mac, bulletin->mac, ETH_ALEN);
2632 else
2633 /* function has not been loaded yet. Show mac as 0s */
2634 eth_zero_addr(ivi->mac);
2635
2636 /* vlan */
2637 if (bulletin->valid_bitmap & (1 << VLAN_VALID))
2638 /* vlan configured by ndo so its in bulletin board */
2639 memcpy(&ivi->vlan, &bulletin->vlan, VLAN_HLEN);
2640 else
2641 /* function has not been loaded yet. Show vlans as 0s */
2642 memset(&ivi->vlan, 0, VLAN_HLEN);
2643
2644 mutex_unlock(&bp->vfdb->bulletin_mutex);
2645 }
2646
2647 return 0;
2648 }
2649
2650 /* New mac for VF. Consider these cases:
2651 * 1. VF hasn't been acquired yet - save the mac in local bulletin board and
2652 * supply at acquire.
2653 * 2. VF has already been acquired but has not yet initialized - store in local
2654 * bulletin board. mac will be posted on VF bulletin board after VF init. VF
2655 * will configure this mac when it is ready.
2656 * 3. VF has already initialized but has not yet setup a queue - post the new
2657 * mac on VF's bulletin board right now. VF will configure this mac when it
2658 * is ready.
2659 * 4. VF has already set a queue - delete any macs already configured for this
2660 * queue and manually config the new mac.
2661 * In any event, once this function has been called refuse any attempts by the
2662 * VF to configure any mac for itself except for this mac. In case of a race
2663 * where the VF fails to see the new post on its bulletin board before sending a
2664 * mac configuration request, the PF will simply fail the request and VF can try
2665 * again after consulting its bulletin board.
2666 */
2667 int bnx2x_set_vf_mac(struct net_device *dev, int vfidx, u8 *mac)
2668 {
2669 struct bnx2x *bp = netdev_priv(dev);
2670 int rc, q_logical_state;
2671 struct bnx2x_virtf *vf = NULL;
2672 struct pf_vf_bulletin_content *bulletin = NULL;
2673
2674 if (!is_valid_ether_addr(mac)) {
2675 BNX2X_ERR("mac address invalid\n");
2676 return -EINVAL;
2677 }
2678
2679 /* sanity and init */
2680 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true);
2681 if (rc)
2682 return rc;
2683
2684 mutex_lock(&bp->vfdb->bulletin_mutex);
2685
2686 /* update PF's copy of the VF's bulletin. Will no longer accept mac
2687 * configuration requests from vf unless match this mac
2688 */
2689 bulletin->valid_bitmap |= 1 << MAC_ADDR_VALID;
2690 memcpy(bulletin->mac, mac, ETH_ALEN);
2691
2692 /* Post update on VF's bulletin board */
2693 rc = bnx2x_post_vf_bulletin(bp, vfidx);
2694
2695 /* release lock before checking return code */
2696 mutex_unlock(&bp->vfdb->bulletin_mutex);
2697
2698 if (rc) {
2699 BNX2X_ERR("failed to update VF[%d] bulletin\n", vfidx);
2700 return rc;
2701 }
2702
2703 q_logical_state =
2704 bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj));
2705 if (vf->state == VF_ENABLED &&
2706 q_logical_state == BNX2X_Q_LOGICAL_STATE_ACTIVE) {
2707 /* configure the mac in device on this vf's queue */
2708 unsigned long ramrod_flags = 0;
2709 struct bnx2x_vlan_mac_obj *mac_obj;
2710
2711 /* User should be able to see failure reason in system logs */
2712 if (!bnx2x_validate_vf_sp_objs(bp, vf, true))
2713 return -EINVAL;
2714
2715 /* must lock vfpf channel to protect against vf flows */
2716 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC);
2717
2718 /* remove existing eth macs */
2719 mac_obj = &bnx2x_leading_vfq(vf, mac_obj);
2720 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_ETH_MAC, true);
2721 if (rc) {
2722 BNX2X_ERR("failed to delete eth macs\n");
2723 rc = -EINVAL;
2724 goto out;
2725 }
2726
2727 /* remove existing uc list macs */
2728 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, true);
2729 if (rc) {
2730 BNX2X_ERR("failed to delete uc_list macs\n");
2731 rc = -EINVAL;
2732 goto out;
2733 }
2734
2735 /* configure the new mac to device */
2736 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
2737 bnx2x_set_mac_one(bp, (u8 *)&bulletin->mac, mac_obj, true,
2738 BNX2X_ETH_MAC, &ramrod_flags);
2739
2740 out:
2741 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC);
2742 }
2743
2744 return rc;
2745 }
2746
2747 static void bnx2x_set_vf_vlan_acceptance(struct bnx2x *bp,
2748 struct bnx2x_virtf *vf, bool accept)
2749 {
2750 struct bnx2x_rx_mode_ramrod_params rx_ramrod;
2751 unsigned long accept_flags;
2752
2753 /* need to remove/add the VF's accept_any_vlan bit */
2754 accept_flags = bnx2x_leading_vfq(vf, accept_flags);
2755 if (accept)
2756 set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
2757 else
2758 clear_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
2759
2760 bnx2x_vf_prep_rx_mode(bp, LEADING_IDX, &rx_ramrod, vf,
2761 accept_flags);
2762 bnx2x_leading_vfq(vf, accept_flags) = accept_flags;
2763 bnx2x_config_rx_mode(bp, &rx_ramrod);
2764 }
2765
2766 static int bnx2x_set_vf_vlan_filter(struct bnx2x *bp, struct bnx2x_virtf *vf,
2767 u16 vlan, bool add)
2768 {
2769 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
2770 unsigned long ramrod_flags = 0;
2771 int rc = 0;
2772
2773 /* configure the new vlan to device */
2774 memset(&ramrod_param, 0, sizeof(ramrod_param));
2775 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
2776 ramrod_param.vlan_mac_obj = &bnx2x_leading_vfq(vf, vlan_obj);
2777 ramrod_param.ramrod_flags = ramrod_flags;
2778 ramrod_param.user_req.u.vlan.vlan = vlan;
2779 ramrod_param.user_req.cmd = add ? BNX2X_VLAN_MAC_ADD
2780 : BNX2X_VLAN_MAC_DEL;
2781 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
2782 if (rc) {
2783 BNX2X_ERR("failed to configure vlan\n");
2784 return -EINVAL;
2785 }
2786
2787 return 0;
2788 }
2789
2790 int bnx2x_set_vf_vlan(struct net_device *dev, int vfidx, u16 vlan, u8 qos)
2791 {
2792 struct pf_vf_bulletin_content *bulletin = NULL;
2793 struct bnx2x *bp = netdev_priv(dev);
2794 struct bnx2x_vlan_mac_obj *vlan_obj;
2795 unsigned long vlan_mac_flags = 0;
2796 unsigned long ramrod_flags = 0;
2797 struct bnx2x_virtf *vf = NULL;
2798 int i, rc;
2799
2800 if (vlan > 4095) {
2801 BNX2X_ERR("illegal vlan value %d\n", vlan);
2802 return -EINVAL;
2803 }
2804
2805 DP(BNX2X_MSG_IOV, "configuring VF %d with VLAN %d qos %d\n",
2806 vfidx, vlan, 0);
2807
2808 /* sanity and init */
2809 rc = bnx2x_vf_op_prep(bp, vfidx, &vf, &bulletin, true);
2810 if (rc)
2811 return rc;
2812
2813 /* update PF's copy of the VF's bulletin. No point in posting the vlan
2814 * to the VF since it doesn't have anything to do with it. But it useful
2815 * to store it here in case the VF is not up yet and we can only
2816 * configure the vlan later when it does. Treat vlan id 0 as remove the
2817 * Host tag.
2818 */
2819 mutex_lock(&bp->vfdb->bulletin_mutex);
2820
2821 if (vlan > 0)
2822 bulletin->valid_bitmap |= 1 << VLAN_VALID;
2823 else
2824 bulletin->valid_bitmap &= ~(1 << VLAN_VALID);
2825 bulletin->vlan = vlan;
2826
2827 /* Post update on VF's bulletin board */
2828 rc = bnx2x_post_vf_bulletin(bp, vfidx);
2829 if (rc)
2830 BNX2X_ERR("failed to update VF[%d] bulletin\n", vfidx);
2831 mutex_unlock(&bp->vfdb->bulletin_mutex);
2832
2833 /* is vf initialized and queue set up? */
2834 if (vf->state != VF_ENABLED ||
2835 bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj)) !=
2836 BNX2X_Q_LOGICAL_STATE_ACTIVE)
2837 return rc;
2838
2839 /* User should be able to see error in system logs */
2840 if (!bnx2x_validate_vf_sp_objs(bp, vf, true))
2841 return -EINVAL;
2842
2843 /* must lock vfpf channel to protect against vf flows */
2844 bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN);
2845
2846 /* remove existing vlans */
2847 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
2848 vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj);
2849 rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_mac_flags,
2850 &ramrod_flags);
2851 if (rc) {
2852 BNX2X_ERR("failed to delete vlans\n");
2853 rc = -EINVAL;
2854 goto out;
2855 }
2856
2857 /* clear accept_any_vlan when HV forces vlan, otherwise
2858 * according to VF capabilities
2859 */
2860 if (vlan || !(vf->cfg_flags & VF_CFG_VLAN_FILTER))
2861 bnx2x_set_vf_vlan_acceptance(bp, vf, !vlan);
2862
2863 rc = bnx2x_set_vf_vlan_filter(bp, vf, vlan, true);
2864 if (rc)
2865 goto out;
2866
2867 /* send queue update ramrods to configure default vlan and
2868 * silent vlan removal
2869 */
2870 for_each_vfq(vf, i) {
2871 struct bnx2x_queue_state_params q_params = {NULL};
2872 struct bnx2x_queue_update_params *update_params;
2873
2874 q_params.q_obj = &bnx2x_vfq(vf, i, sp_obj);
2875
2876 /* validate the Q is UP */
2877 if (bnx2x_get_q_logical_state(bp, q_params.q_obj) !=
2878 BNX2X_Q_LOGICAL_STATE_ACTIVE)
2879 continue;
2880
2881 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
2882 q_params.cmd = BNX2X_Q_CMD_UPDATE;
2883 update_params = &q_params.params.update;
2884 __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG,
2885 &update_params->update_flags);
2886 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
2887 &update_params->update_flags);
2888 if (vlan == 0) {
2889 /* if vlan is 0 then we want to leave the VF traffic
2890 * untagged, and leave the incoming traffic untouched
2891 * (i.e. do not remove any vlan tags).
2892 */
2893 __clear_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN,
2894 &update_params->update_flags);
2895 __clear_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
2896 &update_params->update_flags);
2897 } else {
2898 /* configure default vlan to vf queue and set silent
2899 * vlan removal (the vf remains unaware of this vlan).
2900 */
2901 __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN,
2902 &update_params->update_flags);
2903 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
2904 &update_params->update_flags);
2905 update_params->def_vlan = vlan;
2906 update_params->silent_removal_value =
2907 vlan & VLAN_VID_MASK;
2908 update_params->silent_removal_mask = VLAN_VID_MASK;
2909 }
2910
2911 /* Update the Queue state */
2912 rc = bnx2x_queue_state_change(bp, &q_params);
2913 if (rc) {
2914 BNX2X_ERR("Failed to configure default VLAN queue %d\n",
2915 i);
2916 goto out;
2917 }
2918 }
2919 out:
2920 bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN);
2921
2922 if (rc)
2923 DP(BNX2X_MSG_IOV,
2924 "updated VF[%d] vlan configuration (vlan = %d)\n",
2925 vfidx, vlan);
2926
2927 return rc;
2928 }
2929
2930 /* crc is the first field in the bulletin board. Compute the crc over the
2931 * entire bulletin board excluding the crc field itself. Use the length field
2932 * as the Bulletin Board was posted by a PF with possibly a different version
2933 * from the vf which will sample it. Therefore, the length is computed by the
2934 * PF and then used blindly by the VF.
2935 */
2936 u32 bnx2x_crc_vf_bulletin(struct pf_vf_bulletin_content *bulletin)
2937 {
2938 return crc32(BULLETIN_CRC_SEED,
2939 ((u8 *)bulletin) + sizeof(bulletin->crc),
2940 bulletin->length - sizeof(bulletin->crc));
2941 }
2942
2943 /* Check for new posts on the bulletin board */
2944 enum sample_bulletin_result bnx2x_sample_bulletin(struct bnx2x *bp)
2945 {
2946 struct pf_vf_bulletin_content *bulletin;
2947 int attempts;
2948
2949 /* sampling structure in mid post may result with corrupted data
2950 * validate crc to ensure coherency.
2951 */
2952 for (attempts = 0; attempts < BULLETIN_ATTEMPTS; attempts++) {
2953 u32 crc;
2954
2955 /* sample the bulletin board */
2956 memcpy(&bp->shadow_bulletin, bp->pf2vf_bulletin,
2957 sizeof(union pf_vf_bulletin));
2958
2959 crc = bnx2x_crc_vf_bulletin(&bp->shadow_bulletin.content);
2960
2961 if (bp->shadow_bulletin.content.crc == crc)
2962 break;
2963
2964 BNX2X_ERR("bad crc on bulletin board. Contained %x computed %x\n",
2965 bp->shadow_bulletin.content.crc, crc);
2966 }
2967
2968 if (attempts >= BULLETIN_ATTEMPTS) {
2969 BNX2X_ERR("pf to vf bulletin board crc was wrong %d consecutive times. Aborting\n",
2970 attempts);
2971 return PFVF_BULLETIN_CRC_ERR;
2972 }
2973 bulletin = &bp->shadow_bulletin.content;
2974
2975 /* bulletin board hasn't changed since last sample */
2976 if (bp->old_bulletin.version == bulletin->version)
2977 return PFVF_BULLETIN_UNCHANGED;
2978
2979 /* the mac address in bulletin board is valid and is new */
2980 if (bulletin->valid_bitmap & 1 << MAC_ADDR_VALID &&
2981 !ether_addr_equal(bulletin->mac, bp->old_bulletin.mac)) {
2982 /* update new mac to net device */
2983 memcpy(bp->dev->dev_addr, bulletin->mac, ETH_ALEN);
2984 }
2985
2986 if (bulletin->valid_bitmap & (1 << LINK_VALID)) {
2987 DP(BNX2X_MSG_IOV, "link update speed %d flags %x\n",
2988 bulletin->link_speed, bulletin->link_flags);
2989
2990 bp->vf_link_vars.line_speed = bulletin->link_speed;
2991 bp->vf_link_vars.link_report_flags = 0;
2992 /* Link is down */
2993 if (bulletin->link_flags & VFPF_LINK_REPORT_LINK_DOWN)
2994 __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
2995 &bp->vf_link_vars.link_report_flags);
2996 /* Full DUPLEX */
2997 if (bulletin->link_flags & VFPF_LINK_REPORT_FULL_DUPLEX)
2998 __set_bit(BNX2X_LINK_REPORT_FD,
2999 &bp->vf_link_vars.link_report_flags);
3000 /* Rx Flow Control is ON */
3001 if (bulletin->link_flags & VFPF_LINK_REPORT_RX_FC_ON)
3002 __set_bit(BNX2X_LINK_REPORT_RX_FC_ON,
3003 &bp->vf_link_vars.link_report_flags);
3004 /* Tx Flow Control is ON */
3005 if (bulletin->link_flags & VFPF_LINK_REPORT_TX_FC_ON)
3006 __set_bit(BNX2X_LINK_REPORT_TX_FC_ON,
3007 &bp->vf_link_vars.link_report_flags);
3008 __bnx2x_link_report(bp);
3009 }
3010
3011 /* copy new bulletin board to bp */
3012 memcpy(&bp->old_bulletin, bulletin,
3013 sizeof(struct pf_vf_bulletin_content));
3014
3015 return PFVF_BULLETIN_UPDATED;
3016 }
3017
3018 void bnx2x_timer_sriov(struct bnx2x *bp)
3019 {
3020 bnx2x_sample_bulletin(bp);
3021
3022 /* if channel is down we need to self destruct */
3023 if (bp->old_bulletin.valid_bitmap & 1 << CHANNEL_DOWN)
3024 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
3025 BNX2X_MSG_IOV);
3026 }
3027
3028 void __iomem *bnx2x_vf_doorbells(struct bnx2x *bp)
3029 {
3030 /* vf doorbells are embedded within the regview */
3031 return bp->regview + PXP_VF_ADDR_DB_START;
3032 }
3033
3034 void bnx2x_vf_pci_dealloc(struct bnx2x *bp)
3035 {
3036 BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->vf2pf_mbox_mapping,
3037 sizeof(struct bnx2x_vf_mbx_msg));
3038 BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->pf2vf_bulletin_mapping,
3039 sizeof(union pf_vf_bulletin));
3040 }
3041
3042 int bnx2x_vf_pci_alloc(struct bnx2x *bp)
3043 {
3044 mutex_init(&bp->vf2pf_mutex);
3045
3046 /* allocate vf2pf mailbox for vf to pf channel */
3047 bp->vf2pf_mbox = BNX2X_PCI_ALLOC(&bp->vf2pf_mbox_mapping,
3048 sizeof(struct bnx2x_vf_mbx_msg));
3049 if (!bp->vf2pf_mbox)
3050 goto alloc_mem_err;
3051
3052 /* allocate pf 2 vf bulletin board */
3053 bp->pf2vf_bulletin = BNX2X_PCI_ALLOC(&bp->pf2vf_bulletin_mapping,
3054 sizeof(union pf_vf_bulletin));
3055 if (!bp->pf2vf_bulletin)
3056 goto alloc_mem_err;
3057
3058 bnx2x_vf_bulletin_finalize(&bp->pf2vf_bulletin->content, true);
3059
3060 return 0;
3061
3062 alloc_mem_err:
3063 bnx2x_vf_pci_dealloc(bp);
3064 return -ENOMEM;
3065 }
3066
3067 void bnx2x_iov_channel_down(struct bnx2x *bp)
3068 {
3069 int vf_idx;
3070 struct pf_vf_bulletin_content *bulletin;
3071
3072 if (!IS_SRIOV(bp))
3073 return;
3074
3075 for_each_vf(bp, vf_idx) {
3076 /* locate this VFs bulletin board and update the channel down
3077 * bit
3078 */
3079 bulletin = BP_VF_BULLETIN(bp, vf_idx);
3080 bulletin->valid_bitmap |= 1 << CHANNEL_DOWN;
3081
3082 /* update vf bulletin board */
3083 bnx2x_post_vf_bulletin(bp, vf_idx);
3084 }
3085 }
3086
3087 void bnx2x_iov_task(struct work_struct *work)
3088 {
3089 struct bnx2x *bp = container_of(work, struct bnx2x, iov_task.work);
3090
3091 if (!netif_running(bp->dev))
3092 return;
3093
3094 if (test_and_clear_bit(BNX2X_IOV_HANDLE_FLR,
3095 &bp->iov_task_state))
3096 bnx2x_vf_handle_flr_event(bp);
3097
3098 if (test_and_clear_bit(BNX2X_IOV_HANDLE_VF_MSG,
3099 &bp->iov_task_state))
3100 bnx2x_vf_mbx(bp);
3101 }
3102
3103 void bnx2x_schedule_iov_task(struct bnx2x *bp, enum bnx2x_iov_flag flag)
3104 {
3105 smp_mb__before_atomic();
3106 set_bit(flag, &bp->iov_task_state);
3107 smp_mb__after_atomic();
3108 DP(BNX2X_MSG_IOV, "Scheduling iov task [Flag: %d]\n", flag);
3109 queue_delayed_work(bnx2x_iov_wq, &bp->iov_task, 0);
3110 }
CRIS linux kernel tree