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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[cris-mirror.git] / drivers / net / ethernet / broadcom / bnxt / bnxt_hsi.h
blob517567f6d6517cec763d3eb2c0f877066e2661c1
1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10 #ifndef BNXT_HSI_H
11 #define BNXT_HSI_H
12
13 /* per-context HW statistics -- chip view */
14 struct ctx_hw_stats {
15 __le64 rx_ucast_pkts;
16 __le64 rx_mcast_pkts;
17 __le64 rx_bcast_pkts;
18 __le64 rx_discard_pkts;
19 __le64 rx_drop_pkts;
20 __le64 rx_ucast_bytes;
21 __le64 rx_mcast_bytes;
22 __le64 rx_bcast_bytes;
23 __le64 tx_ucast_pkts;
24 __le64 tx_mcast_pkts;
25 __le64 tx_bcast_pkts;
26 __le64 tx_discard_pkts;
27 __le64 tx_drop_pkts;
28 __le64 tx_ucast_bytes;
29 __le64 tx_mcast_bytes;
30 __le64 tx_bcast_bytes;
31 __le64 tpa_pkts;
32 __le64 tpa_bytes;
33 __le64 tpa_events;
34 __le64 tpa_aborts;
35 };
36
37 /* Statistics Ejection Buffer Completion Record (16 bytes) */
38 struct eject_cmpl {
39 __le16 type;
40 #define EJECT_CMPL_TYPE_MASK 0x3fUL
41 #define EJECT_CMPL_TYPE_SFT 0
42 #define EJECT_CMPL_TYPE_STAT_EJECT (0x1aUL << 0)
43 __le16 len;
44 __le32 opaque;
45 __le32 v;
46 #define EJECT_CMPL_V 0x1UL
47 __le32 unused_2;
48 };
49
50 /* HWRM Completion Record (16 bytes) */
51 struct hwrm_cmpl {
52 __le16 type;
53 #define HWRM_CMPL_TYPE_MASK 0x3fUL
54 #define HWRM_CMPL_TYPE_SFT 0
55 #define HWRM_CMPL_TYPE_HWRM_DONE (0x20UL << 0)
56 __le16 sequence_id;
57 __le32 unused_1;
58 __le32 v;
59 #define HWRM_CMPL_V 0x1UL
60 __le32 unused_3;
61 };
62
63 /* HWRM Forwarded Request (16 bytes) */
64 struct hwrm_fwd_req_cmpl {
65 __le16 req_len_type;
66 #define HWRM_FWD_REQ_CMPL_TYPE_MASK 0x3fUL
67 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
68 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ (0x22UL << 0)
69 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL
70 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
71 __le16 source_id;
72 __le32 unused_0;
73 __le32 req_buf_addr_v[2];
74 #define HWRM_FWD_REQ_CMPL_V 0x1UL
75 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL
76 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
77 };
78
79 /* HWRM Forwarded Response (16 bytes) */
80 struct hwrm_fwd_resp_cmpl {
81 __le16 type;
82 #define HWRM_FWD_RESP_CMPL_TYPE_MASK 0x3fUL
83 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
84 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP (0x24UL << 0)
85 __le16 source_id;
86 __le16 resp_len;
87 __le16 unused_1;
88 __le32 resp_buf_addr_v[2];
89 #define HWRM_FWD_RESP_CMPL_V 0x1UL
90 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL
91 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
92 };
93
94 /* HWRM Asynchronous Event Completion Record (16 bytes) */
95 struct hwrm_async_event_cmpl {
96 __le16 type;
97 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL
98 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
99 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
100 __le16 event_id;
101 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE (0x0UL << 0)
102 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE (0x1UL << 0)
103 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE (0x2UL << 0)
104 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE (0x3UL << 0)
105 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED (0x4UL << 0)
106 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED (0x5UL << 0)
107 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE (0x6UL << 0)
108 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE (0x7UL << 0)
109 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD (0x10UL << 0)
110 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD (0x11UL << 0)
111 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD (0x20UL << 0)
112 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD (0x21UL << 0)
113 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR (0x30UL << 0)
114 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE (0x31UL << 0)
115 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE (0x32UL << 0)
116 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE (0x33UL << 0)
117 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR (0xffUL << 0)
118 __le32 event_data2;
119 u8 opaque_v;
120 #define HWRM_ASYNC_EVENT_CMPL_V 0x1UL
121 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL
122 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
123 u8 timestamp_lo;
124 __le16 timestamp_hi;
125 __le32 event_data1;
126 };
127
128 /* HWRM Asynchronous Event Completion Record for link status change (16 bytes) */
129 struct hwrm_async_event_cmpl_link_status_change {
130 __le16 type;
131 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL
132 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
133 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
134 __le16 event_id;
135 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE (0x0UL << 0)
136 __le32 event_data2;
137 u8 opaque_v;
138 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL
139 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
140 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
141 u8 timestamp_lo;
142 __le16 timestamp_hi;
143 __le32 event_data1;
144 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL
145 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN (0x0UL << 0)
146 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP (0x1UL << 0)
147 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
148 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL
149 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1
150 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL
151 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4
152 };
153
154 /* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */
155 struct hwrm_async_event_cmpl_link_mtu_change {
156 __le16 type;
157 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK 0x3fUL
158 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
159 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
160 __le16 event_id;
161 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE (0x1UL << 0)
162 __le32 event_data2;
163 u8 opaque_v;
164 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V 0x1UL
165 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL
166 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
167 u8 timestamp_lo;
168 __le16 timestamp_hi;
169 __le32 event_data1;
170 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL
171 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
172 };
173
174 /* HWRM Asynchronous Event Completion Record for link speed change (16 bytes) */
175 struct hwrm_async_event_cmpl_link_speed_change {
176 __le16 type;
177 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK 0x3fUL
178 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
179 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
180 __le16 event_id;
181 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE (0x2UL << 0)
182 __le32 event_data2;
183 u8 opaque_v;
184 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V 0x1UL
185 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL
186 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
187 u8 timestamp_lo;
188 __le16 timestamp_hi;
189 __le32 event_data1;
190 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL
191 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL
192 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1
193 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (0x1UL << 1)
194 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (0xaUL << 1)
195 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (0x14UL << 1)
196 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (0x19UL << 1)
197 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (0x64UL << 1)
198 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (0xc8UL << 1)
199 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (0xfaUL << 1)
200 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (0x190UL << 1)
201 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (0x1f4UL << 1)
202 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (0x3e8UL << 1)
203 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10MB (0xffffUL << 1)
204 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10MB
205 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0000UL
206 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16
207 };
208
209 /* HWRM Asynchronous Event Completion Record for DCB Config change (16 bytes) */
210 struct hwrm_async_event_cmpl_dcb_config_change {
211 __le16 type;
212 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK 0x3fUL
213 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
214 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
215 __le16 event_id;
216 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE (0x3UL << 0)
217 __le32 event_data2;
218 u8 opaque_v;
219 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V 0x1UL
220 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL
221 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
222 u8 timestamp_lo;
223 __le16 timestamp_hi;
224 __le32 event_data1;
225 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
226 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
227 };
228
229 /* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */
230 struct hwrm_async_event_cmpl_port_conn_not_allowed {
231 __le16 type;
232 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL
233 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0
234 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
235 __le16 event_id;
236 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED (0x4UL << 0)
237 __le32 event_data2;
238 u8 opaque_v;
239 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL
240 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
241 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
242 u8 timestamp_lo;
243 __le16 timestamp_hi;
244 __le32 event_data1;
245 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
246 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
247 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL
248 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16
249 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16)
250 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16)
251 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16)
252 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16)
253 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
254 };
255
256 /* HWRM Asynchronous Event Completion Record for link speed config not allowed (16 bytes) */
257 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
258 __le16 type;
259 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK 0x3fUL
260 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT 0
261 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
262 __le16 event_id;
263 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED (0x5UL << 0)
264 __le32 event_data2;
265 u8 opaque_v;
266 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V 0x1UL
267 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
268 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
269 u8 timestamp_lo;
270 __le16 timestamp_hi;
271 __le32 event_data1;
272 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
273 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
274 };
275
276 /* HWRM Asynchronous Event Completion Record for link speed configuration change (16 bytes) */
277 struct hwrm_async_event_cmpl_link_speed_cfg_change {
278 __le16 type;
279 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL
280 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0
281 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
282 __le16 event_id;
283 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE (0x6UL << 0)
284 __le32 event_data2;
285 u8 opaque_v;
286 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL
287 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL
288 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
289 u8 timestamp_lo;
290 __le16 timestamp_hi;
291 __le32 event_data1;
292 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
293 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
294 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL
295 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL
296 };
297
298 /* HWRM Asynchronous Event Completion Record for Function Driver Unload (16 bytes) */
299 struct hwrm_async_event_cmpl_func_drvr_unload {
300 __le16 type;
301 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK 0x3fUL
302 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
303 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
304 __le16 event_id;
305 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD (0x10UL << 0)
306 __le32 event_data2;
307 u8 opaque_v;
308 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V 0x1UL
309 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL
310 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
311 u8 timestamp_lo;
312 __le16 timestamp_hi;
313 __le32 event_data1;
314 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
315 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
316 };
317
318 /* HWRM Asynchronous Event Completion Record for Function Driver load (16 bytes) */
319 struct hwrm_async_event_cmpl_func_drvr_load {
320 __le16 type;
321 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK 0x3fUL
322 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
323 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
324 __le16 event_id;
325 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD (0x11UL << 0)
326 __le32 event_data2;
327 u8 opaque_v;
328 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V 0x1UL
329 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL
330 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
331 u8 timestamp_lo;
332 __le16 timestamp_hi;
333 __le32 event_data1;
334 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
335 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
336 };
337
338 /* HWRM Asynchronous Event Completion Record for PF Driver Unload (16 bytes) */
339 struct hwrm_async_event_cmpl_pf_drvr_unload {
340 __le16 type;
341 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK 0x3fUL
342 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
343 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
344 __le16 event_id;
345 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD (0x20UL << 0)
346 __le32 event_data2;
347 u8 opaque_v;
348 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL
349 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL
350 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
351 u8 timestamp_lo;
352 __le16 timestamp_hi;
353 __le32 event_data1;
354 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
355 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
356 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL
357 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
358 };
359
360 /* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */
361 struct hwrm_async_event_cmpl_pf_drvr_load {
362 __le16 type;
363 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK 0x3fUL
364 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
365 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
366 __le16 event_id;
367 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD (0x21UL << 0)
368 __le32 event_data2;
369 u8 opaque_v;
370 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V 0x1UL
371 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL
372 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
373 u8 timestamp_lo;
374 __le16 timestamp_hi;
375 __le32 event_data1;
376 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
377 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
378 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK 0x70000UL
379 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
380 };
381
382 /* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */
383 struct hwrm_async_event_cmpl_vf_flr {
384 __le16 type;
385 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK 0x3fUL
386 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
387 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
388 __le16 event_id;
389 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR (0x30UL << 0)
390 __le32 event_data2;
391 u8 opaque_v;
392 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V 0x1UL
393 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL
394 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
395 u8 timestamp_lo;
396 __le16 timestamp_hi;
397 __le32 event_data1;
398 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL
399 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
400 };
401
402 /* HWRM Asynchronous Event Completion Record for VF MAC Addr change (16 bytes) */
403 struct hwrm_async_event_cmpl_vf_mac_addr_change {
404 __le16 type;
405 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK 0x3fUL
406 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
407 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
408 __le16 event_id;
409 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE (0x31UL << 0)
410 __le32 event_data2;
411 u8 opaque_v;
412 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V 0x1UL
413 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL
414 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
415 u8 timestamp_lo;
416 __le16 timestamp_hi;
417 __le32 event_data1;
418 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL
419 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0
420 };
421
422 /* HWRM Asynchronous Event Completion Record for PF-VF communication status change (16 bytes) */
423 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
424 __le16 type;
425 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK 0x3fUL
426 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT 0
427 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
428 __le16 event_id;
429 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE (0x32UL << 0)
430 __le32 event_data2;
431 u8 opaque_v;
432 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V 0x1UL
433 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
434 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
435 u8 timestamp_lo;
436 __le16 timestamp_hi;
437 __le32 event_data1;
438 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED 0x1UL
439 };
440
441 /* HWRM Asynchronous Event Completion Record for VF configuration change (16 bytes) */
442 struct hwrm_async_event_cmpl_vf_cfg_change {
443 __le16 type;
444 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL
445 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
446 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
447 __le16 event_id;
448 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE (0x33UL << 0)
449 __le32 event_data2;
450 u8 opaque_v;
451 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL
452 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL
453 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
454 u8 timestamp_lo;
455 __le16 timestamp_hi;
456 __le32 event_data1;
457 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL
458 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL
459 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL
460 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL
461 };
462
463 /* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */
464 struct hwrm_async_event_cmpl_hwrm_error {
465 __le16 type;
466 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL
467 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
468 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
469 __le16 event_id;
470 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR (0xffUL << 0)
471 __le32 event_data2;
472 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL
473 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
474 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING (0x0UL << 0)
475 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL (0x1UL << 0)
476 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL (0x2UL << 0)
477 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
478 u8 opaque_v;
479 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL
480 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL
481 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
482 u8 timestamp_lo;
483 __le16 timestamp_hi;
484 __le32 event_data1;
485 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL
486 };
487
488 /* HW Resource Manager Specification 1.3.0 */
489 #define HWRM_VERSION_MAJOR 1
490 #define HWRM_VERSION_MINOR 3
491 #define HWRM_VERSION_UPDATE 0
492
493 #define HWRM_VERSION_STR "1.3.0"
494 /*
495 * Following is the signature for HWRM message field that indicates not
496 * applicable (All F's). Need to cast it the size of the field if needed.
497 */
498 #define HWRM_NA_SIGNATURE ((__le32)(-1))
499 #define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */
500 #define HWRM_MAX_RESP_LEN (176) /* hwrm_func_qstats */
501 #define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */
502 #define HW_HASH_KEY_SIZE 40
503 #define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */
504 /* Input (16 bytes) */
505 struct input {
506 __le16 req_type;
507 __le16 cmpl_ring;
508 __le16 seq_id;
509 __le16 target_id;
510 __le64 resp_addr;
511 };
512
513 /* Output (8 bytes) */
514 struct output {
515 __le16 error_code;
516 __le16 req_type;
517 __le16 seq_id;
518 __le16 resp_len;
519 };
520
521 /* Command numbering (8 bytes) */
522 struct cmd_nums {
523 __le16 req_type;
524 #define HWRM_VER_GET (0x0UL)
525 #define HWRM_FUNC_BUF_UNRGTR (0xeUL)
526 #define HWRM_FUNC_VF_CFG (0xfUL)
527 #define RESERVED1 (0x10UL)
528 #define HWRM_FUNC_RESET (0x11UL)
529 #define HWRM_FUNC_GETFID (0x12UL)
530 #define HWRM_FUNC_VF_ALLOC (0x13UL)
531 #define HWRM_FUNC_VF_FREE (0x14UL)
532 #define HWRM_FUNC_QCAPS (0x15UL)
533 #define HWRM_FUNC_QCFG (0x16UL)
534 #define HWRM_FUNC_CFG (0x17UL)
535 #define HWRM_FUNC_QSTATS (0x18UL)
536 #define HWRM_FUNC_CLR_STATS (0x19UL)
537 #define HWRM_FUNC_DRV_UNRGTR (0x1aUL)
538 #define HWRM_FUNC_VF_RESC_FREE (0x1bUL)
539 #define HWRM_FUNC_VF_VNIC_IDS_QUERY (0x1cUL)
540 #define HWRM_FUNC_DRV_RGTR (0x1dUL)
541 #define HWRM_FUNC_DRV_QVER (0x1eUL)
542 #define HWRM_FUNC_BUF_RGTR (0x1fUL)
543 #define HWRM_PORT_PHY_CFG (0x20UL)
544 #define HWRM_PORT_MAC_CFG (0x21UL)
545 #define HWRM_PORT_TS_QUERY (0x22UL)
546 #define HWRM_PORT_QSTATS (0x23UL)
547 #define HWRM_PORT_LPBK_QSTATS (0x24UL)
548 #define HWRM_PORT_CLR_STATS (0x25UL)
549 #define HWRM_PORT_LPBK_CLR_STATS (0x26UL)
550 #define HWRM_PORT_PHY_QCFG (0x27UL)
551 #define HWRM_PORT_MAC_QCFG (0x28UL)
552 #define HWRM_PORT_BLINK_LED (0x29UL)
553 #define HWRM_PORT_PHY_QCAPS (0x2aUL)
554 #define HWRM_PORT_PHY_I2C_WRITE (0x2bUL)
555 #define HWRM_PORT_PHY_I2C_READ (0x2cUL)
556 #define HWRM_QUEUE_QPORTCFG (0x30UL)
557 #define HWRM_QUEUE_QCFG (0x31UL)
558 #define HWRM_QUEUE_CFG (0x32UL)
559 #define HWRM_QUEUE_BUFFERS_QCFG (0x33UL)
560 #define HWRM_QUEUE_BUFFERS_CFG (0x34UL)
561 #define HWRM_QUEUE_PFCENABLE_QCFG (0x35UL)
562 #define HWRM_QUEUE_PFCENABLE_CFG (0x36UL)
563 #define HWRM_QUEUE_PRI2COS_QCFG (0x37UL)
564 #define HWRM_QUEUE_PRI2COS_CFG (0x38UL)
565 #define HWRM_QUEUE_COS2BW_QCFG (0x39UL)
566 #define HWRM_QUEUE_COS2BW_CFG (0x3aUL)
567 #define HWRM_VNIC_ALLOC (0x40UL)
568 #define HWRM_VNIC_FREE (0x41UL)
569 #define HWRM_VNIC_CFG (0x42UL)
570 #define HWRM_VNIC_QCFG (0x43UL)
571 #define HWRM_VNIC_TPA_CFG (0x44UL)
572 #define HWRM_VNIC_TPA_QCFG (0x45UL)
573 #define HWRM_VNIC_RSS_CFG (0x46UL)
574 #define HWRM_VNIC_RSS_QCFG (0x47UL)
575 #define HWRM_VNIC_PLCMODES_CFG (0x48UL)
576 #define HWRM_VNIC_PLCMODES_QCFG (0x49UL)
577 #define HWRM_RING_ALLOC (0x50UL)
578 #define HWRM_RING_FREE (0x51UL)
579 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (0x52UL)
580 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (0x53UL)
581 #define HWRM_RING_RESET (0x5eUL)
582 #define HWRM_RING_GRP_ALLOC (0x60UL)
583 #define HWRM_RING_GRP_FREE (0x61UL)
584 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (0x70UL)
585 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (0x71UL)
586 #define HWRM_CFA_L2_FILTER_ALLOC (0x90UL)
587 #define HWRM_CFA_L2_FILTER_FREE (0x91UL)
588 #define HWRM_CFA_L2_FILTER_CFG (0x92UL)
589 #define HWRM_CFA_L2_SET_RX_MASK (0x93UL)
590 #define RESERVED3 (0x94UL)
591 #define HWRM_CFA_TUNNEL_FILTER_ALLOC (0x95UL)
592 #define HWRM_CFA_TUNNEL_FILTER_FREE (0x96UL)
593 #define HWRM_CFA_ENCAP_RECORD_ALLOC (0x97UL)
594 #define HWRM_CFA_ENCAP_RECORD_FREE (0x98UL)
595 #define HWRM_CFA_NTUPLE_FILTER_ALLOC (0x99UL)
596 #define HWRM_CFA_NTUPLE_FILTER_FREE (0x9aUL)
597 #define HWRM_CFA_NTUPLE_FILTER_CFG (0x9bUL)
598 #define HWRM_CFA_EM_FLOW_ALLOC (0x9cUL)
599 #define HWRM_CFA_EM_FLOW_FREE (0x9dUL)
600 #define HWRM_CFA_EM_FLOW_CFG (0x9eUL)
601 #define HWRM_TUNNEL_DST_PORT_QUERY (0xa0UL)
602 #define HWRM_TUNNEL_DST_PORT_ALLOC (0xa1UL)
603 #define HWRM_TUNNEL_DST_PORT_FREE (0xa2UL)
604 #define HWRM_STAT_CTX_ALLOC (0xb0UL)
605 #define HWRM_STAT_CTX_FREE (0xb1UL)
606 #define HWRM_STAT_CTX_QUERY (0xb2UL)
607 #define HWRM_STAT_CTX_CLR_STATS (0xb3UL)
608 #define HWRM_FW_RESET (0xc0UL)
609 #define HWRM_FW_QSTATUS (0xc1UL)
610 #define HWRM_EXEC_FWD_RESP (0xd0UL)
611 #define HWRM_REJECT_FWD_RESP (0xd1UL)
612 #define HWRM_FWD_RESP (0xd2UL)
613 #define HWRM_FWD_ASYNC_EVENT_CMPL (0xd3UL)
614 #define HWRM_TEMP_MONITOR_QUERY (0xe0UL)
615 #define HWRM_WOL_FILTER_ALLOC (0xf0UL)
616 #define HWRM_WOL_FILTER_FREE (0xf1UL)
617 #define HWRM_WOL_FILTER_QCFG (0xf2UL)
618 #define HWRM_DBG_READ_DIRECT (0xff10UL)
619 #define HWRM_DBG_READ_INDIRECT (0xff11UL)
620 #define HWRM_DBG_WRITE_DIRECT (0xff12UL)
621 #define HWRM_DBG_WRITE_INDIRECT (0xff13UL)
622 #define HWRM_DBG_DUMP (0xff14UL)
623 #define HWRM_NVM_MODIFY (0xfff4UL)
624 #define HWRM_NVM_VERIFY_UPDATE (0xfff5UL)
625 #define HWRM_NVM_GET_DEV_INFO (0xfff6UL)
626 #define HWRM_NVM_ERASE_DIR_ENTRY (0xfff7UL)
627 #define HWRM_NVM_MOD_DIR_ENTRY (0xfff8UL)
628 #define HWRM_NVM_FIND_DIR_ENTRY (0xfff9UL)
629 #define HWRM_NVM_GET_DIR_ENTRIES (0xfffaUL)
630 #define HWRM_NVM_GET_DIR_INFO (0xfffbUL)
631 #define HWRM_NVM_RAW_DUMP (0xfffcUL)
632 #define HWRM_NVM_READ (0xfffdUL)
633 #define HWRM_NVM_WRITE (0xfffeUL)
634 #define HWRM_NVM_RAW_WRITE_BLK (0xffffUL)
635 __le16 unused_0[3];
636 };
637
638 /* Return Codes (8 bytes) */
639 struct ret_codes {
640 __le16 error_code;
641 #define HWRM_ERR_CODE_SUCCESS (0x0UL)
642 #define HWRM_ERR_CODE_FAIL (0x1UL)
643 #define HWRM_ERR_CODE_INVALID_PARAMS (0x2UL)
644 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (0x3UL)
645 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR (0x4UL)
646 #define HWRM_ERR_CODE_INVALID_FLAGS (0x5UL)
647 #define HWRM_ERR_CODE_INVALID_ENABLES (0x6UL)
648 #define HWRM_ERR_CODE_HWRM_ERROR (0xfUL)
649 #define HWRM_ERR_CODE_UNKNOWN_ERR (0xfffeUL)
650 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED (0xffffUL)
651 __le16 unused_0[3];
652 };
653
654 /* Output (16 bytes) */
655 struct hwrm_err_output {
656 __le16 error_code;
657 __le16 req_type;
658 __le16 seq_id;
659 __le16 resp_len;
660 __le32 opaque_0;
661 __le16 opaque_1;
662 u8 cmd_err;
663 u8 valid;
664 };
665
666 /* Port Tx Statistics Formats (408 bytes) */
667 struct tx_port_stats {
668 __le64 tx_64b_frames;
669 __le64 tx_65b_127b_frames;
670 __le64 tx_128b_255b_frames;
671 __le64 tx_256b_511b_frames;
672 __le64 tx_512b_1023b_frames;
673 __le64 tx_1024b_1518_frames;
674 __le64 tx_good_vlan_frames;
675 __le64 tx_1519b_2047_frames;
676 __le64 tx_2048b_4095b_frames;
677 __le64 tx_4096b_9216b_frames;
678 __le64 tx_9217b_16383b_frames;
679 __le64 tx_good_frames;
680 __le64 tx_total_frames;
681 __le64 tx_ucast_frames;
682 __le64 tx_mcast_frames;
683 __le64 tx_bcast_frames;
684 __le64 tx_pause_frames;
685 __le64 tx_pfc_frames;
686 __le64 tx_jabber_frames;
687 __le64 tx_fcs_err_frames;
688 __le64 tx_control_frames;
689 __le64 tx_oversz_frames;
690 __le64 tx_single_dfrl_frames;
691 __le64 tx_multi_dfrl_frames;
692 __le64 tx_single_coll_frames;
693 __le64 tx_multi_coll_frames;
694 __le64 tx_late_coll_frames;
695 __le64 tx_excessive_coll_frames;
696 __le64 tx_frag_frames;
697 __le64 tx_err;
698 __le64 tx_tagged_frames;
699 __le64 tx_dbl_tagged_frames;
700 __le64 tx_runt_frames;
701 __le64 tx_fifo_underruns;
702 __le64 tx_pfc_ena_frames_pri0;
703 __le64 tx_pfc_ena_frames_pri1;
704 __le64 tx_pfc_ena_frames_pri2;
705 __le64 tx_pfc_ena_frames_pri3;
706 __le64 tx_pfc_ena_frames_pri4;
707 __le64 tx_pfc_ena_frames_pri5;
708 __le64 tx_pfc_ena_frames_pri6;
709 __le64 tx_pfc_ena_frames_pri7;
710 __le64 tx_eee_lpi_events;
711 __le64 tx_eee_lpi_duration;
712 __le64 tx_llfc_logical_msgs;
713 __le64 tx_hcfc_msgs;
714 __le64 tx_total_collisions;
715 __le64 tx_bytes;
716 __le64 tx_xthol_frames;
717 __le64 tx_stat_discard;
718 __le64 tx_stat_error;
719 };
720
721 /* Port Rx Statistics Formats (528 bytes) */
722 struct rx_port_stats {
723 __le64 rx_64b_frames;
724 __le64 rx_65b_127b_frames;
725 __le64 rx_128b_255b_frames;
726 __le64 rx_256b_511b_frames;
727 __le64 rx_512b_1023b_frames;
728 __le64 rx_1024b_1518_frames;
729 __le64 rx_good_vlan_frames;
730 __le64 rx_1519b_2047b_frames;
731 __le64 rx_2048b_4095b_frames;
732 __le64 rx_4096b_9216b_frames;
733 __le64 rx_9217b_16383b_frames;
734 __le64 rx_total_frames;
735 __le64 rx_ucast_frames;
736 __le64 rx_mcast_frames;
737 __le64 rx_bcast_frames;
738 __le64 rx_fcs_err_frames;
739 __le64 rx_ctrl_frames;
740 __le64 rx_pause_frames;
741 __le64 rx_pfc_frames;
742 __le64 rx_unsupported_opcode_frames;
743 __le64 rx_unsupported_da_pausepfc_frames;
744 __le64 rx_wrong_sa_frames;
745 __le64 rx_align_err_frames;
746 __le64 rx_oor_len_frames;
747 __le64 rx_code_err_frames;
748 __le64 rx_false_carrier_frames;
749 __le64 rx_ovrsz_frames;
750 __le64 rx_jbr_frames;
751 __le64 rx_mtu_err_frames;
752 __le64 rx_match_crc_frames;
753 __le64 rx_promiscuous_frames;
754 __le64 rx_tagged_frames;
755 __le64 rx_double_tagged_frames;
756 __le64 rx_trunc_frames;
757 __le64 rx_good_frames;
758 __le64 rx_pfc_xon2xoff_frames_pri0;
759 __le64 rx_pfc_xon2xoff_frames_pri1;
760 __le64 rx_pfc_xon2xoff_frames_pri2;
761 __le64 rx_pfc_xon2xoff_frames_pri3;
762 __le64 rx_pfc_xon2xoff_frames_pri4;
763 __le64 rx_pfc_xon2xoff_frames_pri5;
764 __le64 rx_pfc_xon2xoff_frames_pri6;
765 __le64 rx_pfc_xon2xoff_frames_pri7;
766 __le64 rx_pfc_ena_frames_pri0;
767 __le64 rx_pfc_ena_frames_pri1;
768 __le64 rx_pfc_ena_frames_pri2;
769 __le64 rx_pfc_ena_frames_pri3;
770 __le64 rx_pfc_ena_frames_pri4;
771 __le64 rx_pfc_ena_frames_pri5;
772 __le64 rx_pfc_ena_frames_pri6;
773 __le64 rx_pfc_ena_frames_pri7;
774 __le64 rx_sch_crc_err_frames;
775 __le64 rx_undrsz_frames;
776 __le64 rx_frag_frames;
777 __le64 rx_eee_lpi_events;
778 __le64 rx_eee_lpi_duration;
779 __le64 rx_llfc_physical_msgs;
780 __le64 rx_llfc_logical_msgs;
781 __le64 rx_llfc_msgs_with_crc_err;
782 __le64 rx_hcfc_msgs;
783 __le64 rx_hcfc_msgs_with_crc_err;
784 __le64 rx_bytes;
785 __le64 rx_runt_bytes;
786 __le64 rx_runt_frames;
787 __le64 rx_stat_discard;
788 __le64 rx_stat_err;
789 };
790
791 /* hwrm_ver_get */
792 /* Input (24 bytes) */
793 struct hwrm_ver_get_input {
794 __le16 req_type;
795 __le16 cmpl_ring;
796 __le16 seq_id;
797 __le16 target_id;
798 __le64 resp_addr;
799 u8 hwrm_intf_maj;
800 u8 hwrm_intf_min;
801 u8 hwrm_intf_upd;
802 u8 unused_0[5];
803 };
804
805 /* Output (128 bytes) */
806 struct hwrm_ver_get_output {
807 __le16 error_code;
808 __le16 req_type;
809 __le16 seq_id;
810 __le16 resp_len;
811 u8 hwrm_intf_maj;
812 u8 hwrm_intf_min;
813 u8 hwrm_intf_upd;
814 u8 hwrm_intf_rsvd;
815 u8 hwrm_fw_maj;
816 u8 hwrm_fw_min;
817 u8 hwrm_fw_bld;
818 u8 hwrm_fw_rsvd;
819 u8 mgmt_fw_maj;
820 u8 mgmt_fw_min;
821 u8 mgmt_fw_bld;
822 u8 mgmt_fw_rsvd;
823 u8 netctrl_fw_maj;
824 u8 netctrl_fw_min;
825 u8 netctrl_fw_bld;
826 u8 netctrl_fw_rsvd;
827 __le32 reserved1;
828 u8 roce_fw_maj;
829 u8 roce_fw_min;
830 u8 roce_fw_bld;
831 u8 roce_fw_rsvd;
832 char hwrm_fw_name[16];
833 char mgmt_fw_name[16];
834 char netctrl_fw_name[16];
835 __le32 reserved2[4];
836 char roce_fw_name[16];
837 __le16 chip_num;
838 u8 chip_rev;
839 u8 chip_metal;
840 u8 chip_bond_id;
841 u8 chip_platform_type;
842 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC (0x0UL << 0)
843 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA (0x1UL << 0)
844 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM (0x2UL << 0)
845 __le16 max_req_win_len;
846 __le16 max_resp_len;
847 __le16 def_req_timeout;
848 u8 unused_0;
849 u8 unused_1;
850 u8 unused_2;
851 u8 valid;
852 };
853
854 /* hwrm_func_reset */
855 /* Input (24 bytes) */
856 struct hwrm_func_reset_input {
857 __le16 req_type;
858 __le16 cmpl_ring;
859 __le16 seq_id;
860 __le16 target_id;
861 __le64 resp_addr;
862 __le32 enables;
863 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL
864 __le16 vf_id;
865 u8 func_reset_level;
866 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL (0x0UL << 0)
867 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME (0x1UL << 0)
868 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN (0x2UL << 0)
869 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF (0x3UL << 0)
870 u8 unused_0;
871 };
872
873 /* Output (16 bytes) */
874 struct hwrm_func_reset_output {
875 __le16 error_code;
876 __le16 req_type;
877 __le16 seq_id;
878 __le16 resp_len;
879 __le32 unused_0;
880 u8 unused_1;
881 u8 unused_2;
882 u8 unused_3;
883 u8 valid;
884 };
885
886 /* hwrm_func_getfid */
887 /* Input (24 bytes) */
888 struct hwrm_func_getfid_input {
889 __le16 req_type;
890 __le16 cmpl_ring;
891 __le16 seq_id;
892 __le16 target_id;
893 __le64 resp_addr;
894 __le32 enables;
895 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL
896 __le16 pci_id;
897 __le16 unused_0;
898 };
899
900 /* Output (16 bytes) */
901 struct hwrm_func_getfid_output {
902 __le16 error_code;
903 __le16 req_type;
904 __le16 seq_id;
905 __le16 resp_len;
906 __le16 fid;
907 u8 unused_0;
908 u8 unused_1;
909 u8 unused_2;
910 u8 unused_3;
911 u8 unused_4;
912 u8 valid;
913 };
914
915 /* hwrm_func_vf_alloc */
916 /* Input (24 bytes) */
917 struct hwrm_func_vf_alloc_input {
918 __le16 req_type;
919 __le16 cmpl_ring;
920 __le16 seq_id;
921 __le16 target_id;
922 __le64 resp_addr;
923 __le32 enables;
924 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL
925 __le16 first_vf_id;
926 __le16 num_vfs;
927 };
928
929 /* Output (16 bytes) */
930 struct hwrm_func_vf_alloc_output {
931 __le16 error_code;
932 __le16 req_type;
933 __le16 seq_id;
934 __le16 resp_len;
935 __le16 first_vf_id;
936 u8 unused_0;
937 u8 unused_1;
938 u8 unused_2;
939 u8 unused_3;
940 u8 unused_4;
941 u8 valid;
942 };
943
944 /* hwrm_func_vf_free */
945 /* Input (24 bytes) */
946 struct hwrm_func_vf_free_input {
947 __le16 req_type;
948 __le16 cmpl_ring;
949 __le16 seq_id;
950 __le16 target_id;
951 __le64 resp_addr;
952 __le32 enables;
953 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL
954 __le16 first_vf_id;
955 __le16 num_vfs;
956 };
957
958 /* Output (16 bytes) */
959 struct hwrm_func_vf_free_output {
960 __le16 error_code;
961 __le16 req_type;
962 __le16 seq_id;
963 __le16 resp_len;
964 __le32 unused_0;
965 u8 unused_1;
966 u8 unused_2;
967 u8 unused_3;
968 u8 valid;
969 };
970
971 /* hwrm_func_vf_cfg */
972 /* Input (32 bytes) */
973 struct hwrm_func_vf_cfg_input {
974 __le16 req_type;
975 __le16 cmpl_ring;
976 __le16 seq_id;
977 __le16 target_id;
978 __le64 resp_addr;
979 __le32 enables;
980 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL
981 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL
982 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL
983 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL
984 __le16 mtu;
985 __le16 guest_vlan;
986 __le16 async_event_cr;
987 u8 dflt_mac_addr[6];
988 };
989
990 /* Output (16 bytes) */
991 struct hwrm_func_vf_cfg_output {
992 __le16 error_code;
993 __le16 req_type;
994 __le16 seq_id;
995 __le16 resp_len;
996 __le32 unused_0;
997 u8 unused_1;
998 u8 unused_2;
999 u8 unused_3;
1000 u8 valid;
1001 };
1002
1003 /* hwrm_func_qcaps */
1004 /* Input (24 bytes) */
1005 struct hwrm_func_qcaps_input {
1006 __le16 req_type;
1007 __le16 cmpl_ring;
1008 __le16 seq_id;
1009 __le16 target_id;
1010 __le64 resp_addr;
1011 __le16 fid;
1012 __le16 unused_0[3];
1013 };
1014
1015 /* Output (80 bytes) */
1016 struct hwrm_func_qcaps_output {
1017 __le16 error_code;
1018 __le16 req_type;
1019 __le16 seq_id;
1020 __le16 resp_len;
1021 __le16 fid;
1022 __le16 port_id;
1023 __le32 flags;
1024 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL
1025 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL
1026 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL
1027 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL
1028 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL
1029 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL
1030 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL
1031 u8 mac_address[6];
1032 __le16 max_rsscos_ctx;
1033 __le16 max_cmpl_rings;
1034 __le16 max_tx_rings;
1035 __le16 max_rx_rings;
1036 __le16 max_l2_ctxs;
1037 __le16 max_vnics;
1038 __le16 first_vf_id;
1039 __le16 max_vfs;
1040 __le16 max_stat_ctx;
1041 __le32 max_encap_records;
1042 __le32 max_decap_records;
1043 __le32 max_tx_em_flows;
1044 __le32 max_tx_wm_flows;
1045 __le32 max_rx_em_flows;
1046 __le32 max_rx_wm_flows;
1047 __le32 max_mcast_filters;
1048 __le32 max_flow_id;
1049 __le32 max_hw_ring_grps;
1050 u8 unused_0;
1051 u8 unused_1;
1052 u8 unused_2;
1053 u8 valid;
1054 };
1055
1056 /* hwrm_func_qcfg */
1057 /* Input (24 bytes) */
1058 struct hwrm_func_qcfg_input {
1059 __le16 req_type;
1060 __le16 cmpl_ring;
1061 __le16 seq_id;
1062 __le16 target_id;
1063 __le64 resp_addr;
1064 __le16 fid;
1065 __le16 unused_0[3];
1066 };
1067
1068 /* Output (72 bytes) */
1069 struct hwrm_func_qcfg_output {
1070 __le16 error_code;
1071 __le16 req_type;
1072 __le16 seq_id;
1073 __le16 resp_len;
1074 __le16 fid;
1075 __le16 port_id;
1076 __le16 vlan;
1077 __le16 flags;
1078 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL
1079 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL
1080 u8 mac_address[6];
1081 __le16 pci_id;
1082 __le16 alloc_rsscos_ctx;
1083 __le16 alloc_cmpl_rings;
1084 __le16 alloc_tx_rings;
1085 __le16 alloc_rx_rings;
1086 __le16 alloc_l2_ctx;
1087 __le16 alloc_vnics;
1088 __le16 mtu;
1089 __le16 mru;
1090 __le16 stat_ctx_id;
1091 u8 port_partition_type;
1092 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF (0x0UL << 0)
1093 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS (0x1UL << 0)
1094 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 (0x2UL << 0)
1095 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 (0x3UL << 0)
1096 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 (0x4UL << 0)
1097 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN (0xffUL << 0)
1098 u8 unused_0;
1099 __le16 dflt_vnic_id;
1100 u8 unused_1;
1101 u8 unused_2;
1102 __le32 min_bw;
1103 __le32 max_bw;
1104 u8 evb_mode;
1105 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB (0x0UL << 0)
1106 #define FUNC_QCFG_RESP_EVB_MODE_VEB (0x1UL << 0)
1107 #define FUNC_QCFG_RESP_EVB_MODE_VEPA (0x2UL << 0)
1108 u8 unused_3;
1109 __le16 unused_4;
1110 __le32 alloc_mcast_filters;
1111 __le32 alloc_hw_ring_grps;
1112 u8 unused_5;
1113 u8 unused_6;
1114 u8 unused_7;
1115 u8 valid;
1116 };
1117
1118 /* hwrm_func_cfg */
1119 /* Input (88 bytes) */
1120 struct hwrm_func_cfg_input {
1121 __le16 req_type;
1122 __le16 cmpl_ring;
1123 __le16 seq_id;
1124 __le16 target_id;
1125 __le64 resp_addr;
1126 __le16 fid;
1127 u8 unused_0;
1128 u8 unused_1;
1129 __le32 flags;
1130 #define FUNC_CFG_REQ_FLAGS_PROM_MODE 0x1UL
1131 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK 0x2UL
1132 #define FUNC_CFG_REQ_FLAGS_SRC_IP_ADDR_CHECK 0x4UL
1133 #define FUNC_CFG_REQ_FLAGS_VLAN_PRI_MATCH 0x8UL
1134 #define FUNC_CFG_REQ_FLAGS_DFLT_PRI_NOMATCH 0x10UL
1135 #define FUNC_CFG_REQ_FLAGS_DISABLE_PAUSE 0x20UL
1136 #define FUNC_CFG_REQ_FLAGS_DISABLE_STP 0x40UL
1137 #define FUNC_CFG_REQ_FLAGS_DISABLE_LLDP 0x80UL
1138 #define FUNC_CFG_REQ_FLAGS_DISABLE_PTPV2 0x100UL
1139 __le32 enables;
1140 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL
1141 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
1142 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL
1143 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL
1144 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL
1145 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL
1146 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL
1147 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL
1148 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL
1149 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL
1150 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL
1151 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL
1152 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL
1153 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL
1154 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL
1155 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL
1156 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL
1157 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL
1158 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL
1159 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL
1160 __le16 mtu;
1161 __le16 mru;
1162 __le16 num_rsscos_ctxs;
1163 __le16 num_cmpl_rings;
1164 __le16 num_tx_rings;
1165 __le16 num_rx_rings;
1166 __le16 num_l2_ctxs;
1167 __le16 num_vnics;
1168 __le16 num_stat_ctxs;
1169 __le16 num_hw_ring_grps;
1170 u8 dflt_mac_addr[6];
1171 __le16 dflt_vlan;
1172 __be32 dflt_ip_addr[4];
1173 __le32 min_bw;
1174 __le32 max_bw;
1175 __le16 async_event_cr;
1176 u8 vlan_antispoof_mode;
1177 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK (0x0UL << 0)
1178 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN (0x1UL << 0)
1179 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE (0x2UL << 0)
1180 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN (0x3UL << 0)
1181 u8 allowed_vlan_pris;
1182 u8 evb_mode;
1183 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB (0x0UL << 0)
1184 #define FUNC_CFG_REQ_EVB_MODE_VEB (0x1UL << 0)
1185 #define FUNC_CFG_REQ_EVB_MODE_VEPA (0x2UL << 0)
1186 u8 unused_2;
1187 __le16 num_mcast_filters;
1188 };
1189
1190 /* Output (16 bytes) */
1191 struct hwrm_func_cfg_output {
1192 __le16 error_code;
1193 __le16 req_type;
1194 __le16 seq_id;
1195 __le16 resp_len;
1196 __le32 unused_0;
1197 u8 unused_1;
1198 u8 unused_2;
1199 u8 unused_3;
1200 u8 valid;
1201 };
1202
1203 /* hwrm_func_qstats */
1204 /* Input (24 bytes) */
1205 struct hwrm_func_qstats_input {
1206 __le16 req_type;
1207 __le16 cmpl_ring;
1208 __le16 seq_id;
1209 __le16 target_id;
1210 __le64 resp_addr;
1211 __le16 fid;
1212 __le16 unused_0[3];
1213 };
1214
1215 /* Output (176 bytes) */
1216 struct hwrm_func_qstats_output {
1217 __le16 error_code;
1218 __le16 req_type;
1219 __le16 seq_id;
1220 __le16 resp_len;
1221 __le64 tx_ucast_pkts;
1222 __le64 tx_mcast_pkts;
1223 __le64 tx_bcast_pkts;
1224 __le64 tx_err_pkts;
1225 __le64 tx_drop_pkts;
1226 __le64 tx_ucast_bytes;
1227 __le64 tx_mcast_bytes;
1228 __le64 tx_bcast_bytes;
1229 __le64 rx_ucast_pkts;
1230 __le64 rx_mcast_pkts;
1231 __le64 rx_bcast_pkts;
1232 __le64 rx_err_pkts;
1233 __le64 rx_drop_pkts;
1234 __le64 rx_ucast_bytes;
1235 __le64 rx_mcast_bytes;
1236 __le64 rx_bcast_bytes;
1237 __le64 rx_agg_pkts;
1238 __le64 rx_agg_bytes;
1239 __le64 rx_agg_events;
1240 __le64 rx_agg_aborts;
1241 __le32 unused_0;
1242 u8 unused_1;
1243 u8 unused_2;
1244 u8 unused_3;
1245 u8 valid;
1246 };
1247
1248 /* hwrm_func_clr_stats */
1249 /* Input (24 bytes) */
1250 struct hwrm_func_clr_stats_input {
1251 __le16 req_type;
1252 __le16 cmpl_ring;
1253 __le16 seq_id;
1254 __le16 target_id;
1255 __le64 resp_addr;
1256 __le16 fid;
1257 __le16 unused_0[3];
1258 };
1259
1260 /* Output (16 bytes) */
1261 struct hwrm_func_clr_stats_output {
1262 __le16 error_code;
1263 __le16 req_type;
1264 __le16 seq_id;
1265 __le16 resp_len;
1266 __le32 unused_0;
1267 u8 unused_1;
1268 u8 unused_2;
1269 u8 unused_3;
1270 u8 valid;
1271 };
1272
1273 /* hwrm_func_vf_resc_free */
1274 /* Input (24 bytes) */
1275 struct hwrm_func_vf_resc_free_input {
1276 __le16 req_type;
1277 __le16 cmpl_ring;
1278 __le16 seq_id;
1279 __le16 target_id;
1280 __le64 resp_addr;
1281 __le16 vf_id;
1282 __le16 unused_0[3];
1283 };
1284
1285 /* Output (16 bytes) */
1286 struct hwrm_func_vf_resc_free_output {
1287 __le16 error_code;
1288 __le16 req_type;
1289 __le16 seq_id;
1290 __le16 resp_len;
1291 __le32 unused_0;
1292 u8 unused_1;
1293 u8 unused_2;
1294 u8 unused_3;
1295 u8 valid;
1296 };
1297
1298 /* hwrm_func_vf_vnic_ids_query */
1299 /* Input (32 bytes) */
1300 struct hwrm_func_vf_vnic_ids_query_input {
1301 __le16 req_type;
1302 __le16 cmpl_ring;
1303 __le16 seq_id;
1304 __le16 target_id;
1305 __le64 resp_addr;
1306 __le16 vf_id;
1307 u8 unused_0;
1308 u8 unused_1;
1309 __le32 max_vnic_id_cnt;
1310 __le64 vnic_id_tbl_addr;
1311 };
1312
1313 /* Output (16 bytes) */
1314 struct hwrm_func_vf_vnic_ids_query_output {
1315 __le16 error_code;
1316 __le16 req_type;
1317 __le16 seq_id;
1318 __le16 resp_len;
1319 __le32 vnic_id_cnt;
1320 u8 unused_0;
1321 u8 unused_1;
1322 u8 unused_2;
1323 u8 valid;
1324 };
1325
1326 /* hwrm_func_drv_rgtr */
1327 /* Input (80 bytes) */
1328 struct hwrm_func_drv_rgtr_input {
1329 __le16 req_type;
1330 __le16 cmpl_ring;
1331 __le16 seq_id;
1332 __le16 target_id;
1333 __le64 resp_addr;
1334 __le32 flags;
1335 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL
1336 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
1337 __le32 enables;
1338 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
1339 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
1340 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL
1341 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL
1342 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL
1343 __le16 os_type;
1344 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN (0x0UL << 0)
1345 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER (0x1UL << 0)
1346 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS (0xeUL << 0)
1347 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS (0x12UL << 0)
1348 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS (0x1dUL << 0)
1349 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX (0x24UL << 0)
1350 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD (0x2aUL << 0)
1351 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI (0x68UL << 0)
1352 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 (0x73UL << 0)
1353 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 (0x74UL << 0)
1354 u8 ver_maj;
1355 u8 ver_min;
1356 u8 ver_upd;
1357 u8 unused_0;
1358 __le16 unused_1;
1359 __le32 timestamp;
1360 __le32 unused_2;
1361 __le32 vf_req_fwd[8];
1362 __le32 async_event_fwd[8];
1363 };
1364
1365 /* Output (16 bytes) */
1366 struct hwrm_func_drv_rgtr_output {
1367 __le16 error_code;
1368 __le16 req_type;
1369 __le16 seq_id;
1370 __le16 resp_len;
1371 __le32 unused_0;
1372 u8 unused_1;
1373 u8 unused_2;
1374 u8 unused_3;
1375 u8 valid;
1376 };
1377
1378 /* hwrm_func_drv_unrgtr */
1379 /* Input (24 bytes) */
1380 struct hwrm_func_drv_unrgtr_input {
1381 __le16 req_type;
1382 __le16 cmpl_ring;
1383 __le16 seq_id;
1384 __le16 target_id;
1385 __le64 resp_addr;
1386 __le32 flags;
1387 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL
1388 __le32 unused_0;
1389 };
1390
1391 /* Output (16 bytes) */
1392 struct hwrm_func_drv_unrgtr_output {
1393 __le16 error_code;
1394 __le16 req_type;
1395 __le16 seq_id;
1396 __le16 resp_len;
1397 __le32 unused_0;
1398 u8 unused_1;
1399 u8 unused_2;
1400 u8 unused_3;
1401 u8 valid;
1402 };
1403
1404 /* hwrm_func_buf_rgtr */
1405 /* Input (128 bytes) */
1406 struct hwrm_func_buf_rgtr_input {
1407 __le16 req_type;
1408 __le16 cmpl_ring;
1409 __le16 seq_id;
1410 __le16 target_id;
1411 __le64 resp_addr;
1412 __le32 enables;
1413 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL
1414 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL
1415 __le16 vf_id;
1416 __le16 req_buf_num_pages;
1417 __le16 req_buf_page_size;
1418 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B (0x4UL << 0)
1419 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K (0xcUL << 0)
1420 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K (0xdUL << 0)
1421 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K (0x10UL << 0)
1422 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M (0x15UL << 0)
1423 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M (0x16UL << 0)
1424 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G (0x1eUL << 0)
1425 __le16 req_buf_len;
1426 __le16 resp_buf_len;
1427 u8 unused_0;
1428 u8 unused_1;
1429 __le64 req_buf_page_addr0;
1430 __le64 req_buf_page_addr1;
1431 __le64 req_buf_page_addr2;
1432 __le64 req_buf_page_addr3;
1433 __le64 req_buf_page_addr4;
1434 __le64 req_buf_page_addr5;
1435 __le64 req_buf_page_addr6;
1436 __le64 req_buf_page_addr7;
1437 __le64 req_buf_page_addr8;
1438 __le64 req_buf_page_addr9;
1439 __le64 error_buf_addr;
1440 __le64 resp_buf_addr;
1441 };
1442
1443 /* Output (16 bytes) */
1444 struct hwrm_func_buf_rgtr_output {
1445 __le16 error_code;
1446 __le16 req_type;
1447 __le16 seq_id;
1448 __le16 resp_len;
1449 __le32 unused_0;
1450 u8 unused_1;
1451 u8 unused_2;
1452 u8 unused_3;
1453 u8 valid;
1454 };
1455
1456 /* hwrm_func_drv_qver */
1457 /* Input (24 bytes) */
1458 struct hwrm_func_drv_qver_input {
1459 __le16 req_type;
1460 __le16 cmpl_ring;
1461 __le16 seq_id;
1462 __le16 target_id;
1463 __le64 resp_addr;
1464 __le32 reserved;
1465 __le16 fid;
1466 __le16 unused_0;
1467 };
1468
1469 /* Output (16 bytes) */
1470 struct hwrm_func_drv_qver_output {
1471 __le16 error_code;
1472 __le16 req_type;
1473 __le16 seq_id;
1474 __le16 resp_len;
1475 __le16 os_type;
1476 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN (0x0UL << 0)
1477 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER (0x1UL << 0)
1478 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS (0xeUL << 0)
1479 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS (0x12UL << 0)
1480 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS (0x1dUL << 0)
1481 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX (0x24UL << 0)
1482 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD (0x2aUL << 0)
1483 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI (0x68UL << 0)
1484 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 (0x73UL << 0)
1485 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 (0x74UL << 0)
1486 u8 ver_maj;
1487 u8 ver_min;
1488 u8 ver_upd;
1489 u8 unused_0;
1490 u8 unused_1;
1491 u8 valid;
1492 };
1493
1494 /* hwrm_port_phy_cfg */
1495 /* Input (56 bytes) */
1496 struct hwrm_port_phy_cfg_input {
1497 __le16 req_type;
1498 __le16 cmpl_ring;
1499 __le16 seq_id;
1500 __le16 target_id;
1501 __le64 resp_addr;
1502 __le32 flags;
1503 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL
1504 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN 0x2UL
1505 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL
1506 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL
1507 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL
1508 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL
1509 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL
1510 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL
1511 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL
1512 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL
1513 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL
1514 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL
1515 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL
1516 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL
1517 __le32 enables;
1518 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL
1519 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL
1520 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL
1521 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL
1522 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL
1523 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL
1524 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL
1525 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL
1526 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL
1527 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL
1528 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL
1529 __le16 port_id;
1530 __le16 force_link_speed;
1531 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB (0x1UL << 0)
1532 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB (0xaUL << 0)
1533 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB (0x14UL << 0)
1534 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB (0x19UL << 0)
1535 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB (0x64UL << 0)
1536 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB (0xc8UL << 0)
1537 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB (0xfaUL << 0)
1538 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB (0x190UL << 0)
1539 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB (0x1f4UL << 0)
1540 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB (0x3e8UL << 0)
1541 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB (0xffffUL << 0)
1542 u8 auto_mode;
1543 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE (0x0UL << 0)
1544 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS (0x1UL << 0)
1545 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED (0x2UL << 0)
1546 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0)
1547 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK (0x4UL << 0)
1548 u8 auto_duplex;
1549 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF (0x0UL << 0)
1550 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL (0x1UL << 0)
1551 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH (0x2UL << 0)
1552 u8 auto_pause;
1553 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL
1554 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL
1555 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
1556 u8 unused_0;
1557 __le16 auto_link_speed;
1558 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB (0x1UL << 0)
1559 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB (0xaUL << 0)
1560 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB (0x14UL << 0)
1561 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB (0x19UL << 0)
1562 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB (0x64UL << 0)
1563 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB (0xc8UL << 0)
1564 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB (0xfaUL << 0)
1565 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB (0x190UL << 0)
1566 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB (0x1f4UL << 0)
1567 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB (0x3e8UL << 0)
1568 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB (0xffffUL << 0)
1569 __le16 auto_link_speed_mask;
1570 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
1571 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL
1572 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
1573 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL
1574 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL
1575 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
1576 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL
1577 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL
1578 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL
1579 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL
1580 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL
1581 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL
1582 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
1583 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
1584 u8 wirespeed;
1585 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF (0x0UL << 0)
1586 #define PORT_PHY_CFG_REQ_WIRESPEED_ON (0x1UL << 0)
1587 u8 lpbk;
1588 #define PORT_PHY_CFG_REQ_LPBK_NONE (0x0UL << 0)
1589 #define PORT_PHY_CFG_REQ_LPBK_LOCAL (0x1UL << 0)
1590 #define PORT_PHY_CFG_REQ_LPBK_REMOTE (0x2UL << 0)
1591 u8 force_pause;
1592 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL
1593 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL
1594 u8 unused_1;
1595 __le32 preemphasis;
1596 __le16 eee_link_speed_mask;
1597 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
1598 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL
1599 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
1600 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL
1601 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
1602 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
1603 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL
1604 u8 unused_2;
1605 u8 unused_3;
1606 __le32 tx_lpi_timer;
1607 __le32 unused_4;
1608 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL
1609 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0
1610 };
1611
1612 /* Output (16 bytes) */
1613 struct hwrm_port_phy_cfg_output {
1614 __le16 error_code;
1615 __le16 req_type;
1616 __le16 seq_id;
1617 __le16 resp_len;
1618 __le32 unused_0;
1619 u8 unused_1;
1620 u8 unused_2;
1621 u8 unused_3;
1622 u8 valid;
1623 };
1624
1625 /* hwrm_port_phy_qcfg */
1626 /* Input (24 bytes) */
1627 struct hwrm_port_phy_qcfg_input {
1628 __le16 req_type;
1629 __le16 cmpl_ring;
1630 __le16 seq_id;
1631 __le16 target_id;
1632 __le64 resp_addr;
1633 __le16 port_id;
1634 __le16 unused_0[3];
1635 };
1636
1637 /* Output (96 bytes) */
1638 struct hwrm_port_phy_qcfg_output {
1639 __le16 error_code;
1640 __le16 req_type;
1641 __le16 seq_id;
1642 __le16 resp_len;
1643 u8 link;
1644 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK (0x0UL << 0)
1645 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL (0x1UL << 0)
1646 #define PORT_PHY_QCFG_RESP_LINK_LINK (0x2UL << 0)
1647 u8 unused_0;
1648 __le16 link_speed;
1649 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB (0x1UL << 0)
1650 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB (0xaUL << 0)
1651 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB (0x14UL << 0)
1652 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB (0x19UL << 0)
1653 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB (0x64UL << 0)
1654 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB (0xc8UL << 0)
1655 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB (0xfaUL << 0)
1656 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB (0x190UL << 0)
1657 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB (0x1f4UL << 0)
1658 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB (0x3e8UL << 0)
1659 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB (0xffffUL << 0)
1660 u8 duplex;
1661 #define PORT_PHY_QCFG_RESP_DUPLEX_HALF (0x0UL << 0)
1662 #define PORT_PHY_QCFG_RESP_DUPLEX_FULL (0x1UL << 0)
1663 u8 pause;
1664 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL
1665 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL
1666 __le16 support_speeds;
1667 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL
1668 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL
1669 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL
1670 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL
1671 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL
1672 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL
1673 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL
1674 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL
1675 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL
1676 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL
1677 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL
1678 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL
1679 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL
1680 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL
1681 __le16 force_link_speed;
1682 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB (0x1UL << 0)
1683 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB (0xaUL << 0)
1684 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB (0x14UL << 0)
1685 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB (0x19UL << 0)
1686 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB (0x64UL << 0)
1687 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB (0xc8UL << 0)
1688 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB (0xfaUL << 0)
1689 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB (0x190UL << 0)
1690 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB (0x1f4UL << 0)
1691 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB (0x3e8UL << 0)
1692 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB (0xffffUL << 0)
1693 u8 auto_mode;
1694 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE (0x0UL << 0)
1695 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS (0x1UL << 0)
1696 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED (0x2UL << 0)
1697 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0)
1698 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK (0x4UL << 0)
1699 u8 auto_pause;
1700 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL
1701 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL
1702 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
1703 __le16 auto_link_speed;
1704 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB (0x1UL << 0)
1705 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB (0xaUL << 0)
1706 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB (0x14UL << 0)
1707 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB (0x19UL << 0)
1708 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB (0x64UL << 0)
1709 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB (0xc8UL << 0)
1710 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB (0xfaUL << 0)
1711 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB (0x190UL << 0)
1712 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB (0x1f4UL << 0)
1713 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB (0x3e8UL << 0)
1714 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB (0xffffUL << 0)
1715 __le16 auto_link_speed_mask;
1716 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
1717 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL
1718 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
1719 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL
1720 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL
1721 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
1722 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL
1723 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL
1724 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL
1725 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL
1726 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL
1727 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL
1728 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
1729 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
1730 u8 wirespeed;
1731 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF (0x0UL << 0)
1732 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON (0x1UL << 0)
1733 u8 lpbk;
1734 #define PORT_PHY_QCFG_RESP_LPBK_NONE (0x0UL << 0)
1735 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL (0x1UL << 0)
1736 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE (0x2UL << 0)
1737 u8 force_pause;
1738 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL
1739 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL
1740 u8 module_status;
1741 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE (0x0UL << 0)
1742 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX (0x1UL << 0)
1743 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG (0x2UL << 0)
1744 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN (0x3UL << 0)
1745 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED (0x4UL << 0)
1746 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE (0xffUL << 0)
1747 __le32 preemphasis;
1748 u8 phy_maj;
1749 u8 phy_min;
1750 u8 phy_bld;
1751 u8 phy_type;
1752 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN (0x0UL << 0)
1753 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR (0x1UL << 0)
1754 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 (0x2UL << 0)
1755 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR (0x3UL << 0)
1756 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR (0x4UL << 0)
1757 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 (0x5UL << 0)
1758 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX (0x6UL << 0)
1759 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR (0x7UL << 0)
1760 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET (0x8UL << 0)
1761 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE (0x9UL << 0)
1762 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY (0xaUL << 0)
1763 u8 media_type;
1764 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN (0x0UL << 0)
1765 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP (0x1UL << 0)
1766 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC (0x2UL << 0)
1767 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE (0x3UL << 0)
1768 u8 xcvr_pkg_type;
1769 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL (0x1UL << 0)
1770 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL (0x2UL << 0)
1771 u8 eee_config_phy_addr;
1772 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL
1773 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0
1774 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL
1775 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL
1776 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL
1777 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL
1778 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5
1779 u8 parallel_detect;
1780 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL
1781 #define PORT_PHY_QCFG_RESP_RESERVED_MASK 0xfeUL
1782 #define PORT_PHY_QCFG_RESP_RESERVED_SFT 1
1783 __le16 link_partner_adv_speeds;
1784 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL
1785 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL
1786 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL
1787 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL
1788 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL
1789 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL
1790 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL
1791 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL
1792 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL
1793 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL
1794 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL
1795 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL
1796 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL
1797 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL
1798 u8 link_partner_adv_auto_mode;
1799 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE (0x0UL << 0)
1800 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS (0x1UL << 0)
1801 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED (0x2UL << 0)
1802 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0)
1803 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK (0x4UL << 0)
1804 u8 link_partner_adv_pause;
1805 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL
1806 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL
1807 __le16 adv_eee_link_speed_mask;
1808 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
1809 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
1810 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
1811 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
1812 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
1813 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
1814 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
1815 __le16 link_partner_adv_eee_link_speed_mask;
1816 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
1817 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
1818 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
1819 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
1820 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
1821 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
1822 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
1823 __le32 xcvr_identifier_type_tx_lpi_timer;
1824 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL
1825 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0
1826 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL
1827 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24
1828 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24)
1829 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24)
1830 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24)
1831 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24)
1832 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24)
1833 __le16 fec_cfg;
1834 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL
1835 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL
1836 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL
1837 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL
1838 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL
1839 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL
1840 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL
1841 u8 unused_1;
1842 u8 unused_2;
1843 char phy_vendor_name[16];
1844 char phy_vendor_partnumber[16];
1845 __le32 unused_3;
1846 u8 unused_4;
1847 u8 unused_5;
1848 u8 unused_6;
1849 u8 valid;
1850 };
1851
1852 /* hwrm_port_mac_cfg */
1853 /* Input (40 bytes) */
1854 struct hwrm_port_mac_cfg_input {
1855 __le16 req_type;
1856 __le16 cmpl_ring;
1857 __le16 seq_id;
1858 __le16 target_id;
1859 __le64 resp_addr;
1860 __le32 flags;
1861 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL
1862 #define PORT_MAC_CFG_REQ_FLAGS_COS_ASSIGNMENT_ENABLE 0x2UL
1863 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL
1864 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL
1865 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL
1866 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL
1867 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL
1868 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL
1869 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL
1870 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL
1871 __le32 enables;
1872 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL
1873 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL
1874 #define PORT_MAC_CFG_REQ_ENABLES_IVLAN_PRI2COS_MAP_PRI 0x4UL
1875 #define PORT_MAC_CFG_REQ_ENABLES_LCOS_MAP_PRI 0x8UL
1876 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL
1877 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL
1878 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL
1879 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL
1880 __le16 port_id;
1881 u8 ipg;
1882 u8 lpbk;
1883 #define PORT_MAC_CFG_REQ_LPBK_NONE (0x0UL << 0)
1884 #define PORT_MAC_CFG_REQ_LPBK_LOCAL (0x1UL << 0)
1885 #define PORT_MAC_CFG_REQ_LPBK_REMOTE (0x2UL << 0)
1886 u8 ivlan_pri2cos_map_pri;
1887 u8 lcos_map_pri;
1888 u8 tunnel_pri2cos_map_pri;
1889 u8 dscp2pri_map_pri;
1890 __le16 rx_ts_capture_ptp_msg_type;
1891 __le16 tx_ts_capture_ptp_msg_type;
1892 __le32 unused_0;
1893 };
1894
1895 /* Output (16 bytes) */
1896 struct hwrm_port_mac_cfg_output {
1897 __le16 error_code;
1898 __le16 req_type;
1899 __le16 seq_id;
1900 __le16 resp_len;
1901 __le16 mru;
1902 __le16 mtu;
1903 u8 ipg;
1904 u8 lpbk;
1905 #define PORT_MAC_CFG_RESP_LPBK_NONE (0x0UL << 0)
1906 #define PORT_MAC_CFG_RESP_LPBK_LOCAL (0x1UL << 0)
1907 #define PORT_MAC_CFG_RESP_LPBK_REMOTE (0x2UL << 0)
1908 u8 unused_0;
1909 u8 valid;
1910 };
1911
1912 /* hwrm_port_qstats */
1913 /* Input (40 bytes) */
1914 struct hwrm_port_qstats_input {
1915 __le16 req_type;
1916 __le16 cmpl_ring;
1917 __le16 seq_id;
1918 __le16 target_id;
1919 __le64 resp_addr;
1920 __le16 port_id;
1921 u8 unused_0;
1922 u8 unused_1;
1923 u8 unused_2[3];
1924 u8 unused_3;
1925 __le64 tx_stat_host_addr;
1926 __le64 rx_stat_host_addr;
1927 };
1928
1929 /* Output (16 bytes) */
1930 struct hwrm_port_qstats_output {
1931 __le16 error_code;
1932 __le16 req_type;
1933 __le16 seq_id;
1934 __le16 resp_len;
1935 __le16 tx_stat_size;
1936 __le16 rx_stat_size;
1937 u8 unused_0;
1938 u8 unused_1;
1939 u8 unused_2;
1940 u8 valid;
1941 };
1942
1943 /* hwrm_port_lpbk_qstats */
1944 /* Input (16 bytes) */
1945 struct hwrm_port_lpbk_qstats_input {
1946 __le16 req_type;
1947 __le16 cmpl_ring;
1948 __le16 seq_id;
1949 __le16 target_id;
1950 __le64 resp_addr;
1951 };
1952
1953 /* Output (96 bytes) */
1954 struct hwrm_port_lpbk_qstats_output {
1955 __le16 error_code;
1956 __le16 req_type;
1957 __le16 seq_id;
1958 __le16 resp_len;
1959 __le64 lpbk_ucast_frames;
1960 __le64 lpbk_mcast_frames;
1961 __le64 lpbk_bcast_frames;
1962 __le64 lpbk_ucast_bytes;
1963 __le64 lpbk_mcast_bytes;
1964 __le64 lpbk_bcast_bytes;
1965 __le64 tx_stat_discard;
1966 __le64 tx_stat_error;
1967 __le64 rx_stat_discard;
1968 __le64 rx_stat_error;
1969 __le32 unused_0;
1970 u8 unused_1;
1971 u8 unused_2;
1972 u8 unused_3;
1973 u8 valid;
1974 };
1975
1976 /* hwrm_port_clr_stats */
1977 /* Input (24 bytes) */
1978 struct hwrm_port_clr_stats_input {
1979 __le16 req_type;
1980 __le16 cmpl_ring;
1981 __le16 seq_id;
1982 __le16 target_id;
1983 __le64 resp_addr;
1984 __le16 port_id;
1985 __le16 unused_0[3];
1986 };
1987
1988 /* Output (16 bytes) */
1989 struct hwrm_port_clr_stats_output {
1990 __le16 error_code;
1991 __le16 req_type;
1992 __le16 seq_id;
1993 __le16 resp_len;
1994 __le32 unused_0;
1995 u8 unused_1;
1996 u8 unused_2;
1997 u8 unused_3;
1998 u8 valid;
1999 };
2000
2001 /* hwrm_port_lpbk_clr_stats */
2002 /* Input (16 bytes) */
2003 struct hwrm_port_lpbk_clr_stats_input {
2004 __le16 req_type;
2005 __le16 cmpl_ring;
2006 __le16 seq_id;
2007 __le16 target_id;
2008 __le64 resp_addr;
2009 };
2010
2011 /* Output (16 bytes) */
2012 struct hwrm_port_lpbk_clr_stats_output {
2013 __le16 error_code;
2014 __le16 req_type;
2015 __le16 seq_id;
2016 __le16 resp_len;
2017 __le32 unused_0;
2018 u8 unused_1;
2019 u8 unused_2;
2020 u8 unused_3;
2021 u8 valid;
2022 };
2023
2024 /* hwrm_port_blink_led */
2025 /* Input (24 bytes) */
2026 struct hwrm_port_blink_led_input {
2027 __le16 req_type;
2028 __le16 cmpl_ring;
2029 __le16 seq_id;
2030 __le16 target_id;
2031 __le64 resp_addr;
2032 __le32 num_blinks;
2033 __le32 unused_0;
2034 };
2035
2036 /* Output (16 bytes) */
2037 struct hwrm_port_blink_led_output {
2038 __le16 error_code;
2039 __le16 req_type;
2040 __le16 seq_id;
2041 __le16 resp_len;
2042 __le32 unused_0;
2043 u8 unused_1;
2044 u8 unused_2;
2045 u8 unused_3;
2046 u8 valid;
2047 };
2048
2049 /* hwrm_port_phy_qcaps */
2050 /* Input (24 bytes) */
2051 struct hwrm_port_phy_qcaps_input {
2052 __le16 req_type;
2053 __le16 cmpl_ring;
2054 __le16 seq_id;
2055 __le16 target_id;
2056 __le64 resp_addr;
2057 __le16 port_id;
2058 __le16 unused_0[3];
2059 };
2060
2061 /* Output (24 bytes) */
2062 struct hwrm_port_phy_qcaps_output {
2063 __le16 error_code;
2064 __le16 req_type;
2065 __le16 seq_id;
2066 __le16 resp_len;
2067 u8 eee_supported;
2068 #define PORT_PHY_QCAPS_RESP_EEE_SUPPORTED 0x1UL
2069 #define PORT_PHY_QCAPS_RESP_RSVD1_MASK 0xfeUL
2070 #define PORT_PHY_QCAPS_RESP_RSVD1_SFT 1
2071 u8 unused_0;
2072 __le16 supported_speeds_force_mode;
2073 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL
2074 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL
2075 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL
2076 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL
2077 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL
2078 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL
2079 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL
2080 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL
2081 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL
2082 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL
2083 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL
2084 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL
2085 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL
2086 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL
2087 __le16 supported_speeds_auto_mode;
2088 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL
2089 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL
2090 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL
2091 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL
2092 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL
2093 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL
2094 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL
2095 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL
2096 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL
2097 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL
2098 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL
2099 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL
2100 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL
2101 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL
2102 __le16 supported_speeds_eee_mode;
2103 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL
2104 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL
2105 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL
2106 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL
2107 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL
2108 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL
2109 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL
2110 __le32 tx_lpi_timer_low;
2111 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL
2112 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0
2113 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL
2114 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24
2115 __le32 valid_tx_lpi_timer_high;
2116 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL
2117 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0
2118 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL
2119 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24
2120 };
2121
2122 /* hwrm_port_phy_i2c_read */
2123 /* Input (40 bytes) */
2124 struct hwrm_port_phy_i2c_read_input {
2125 __le16 req_type;
2126 __le16 cmpl_ring;
2127 __le16 seq_id;
2128 __le16 target_id;
2129 __le64 resp_addr;
2130 __le32 flags;
2131 __le32 enables;
2132 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL
2133 __le16 port_id;
2134 u8 i2c_slave_addr;
2135 u8 unused_0;
2136 __le16 page_number;
2137 __le16 page_offset;
2138 u8 data_length;
2139 u8 unused_1[7];
2140 };
2141
2142 /* Output (80 bytes) */
2143 struct hwrm_port_phy_i2c_read_output {
2144 __le16 error_code;
2145 __le16 req_type;
2146 __le16 seq_id;
2147 __le16 resp_len;
2148 __le32 data[16];
2149 __le32 unused_0;
2150 u8 unused_1;
2151 u8 unused_2;
2152 u8 unused_3;
2153 u8 valid;
2154 };
2155
2156 /* hwrm_queue_qportcfg */
2157 /* Input (24 bytes) */
2158 struct hwrm_queue_qportcfg_input {
2159 __le16 req_type;
2160 __le16 cmpl_ring;
2161 __le16 seq_id;
2162 __le16 target_id;
2163 __le64 resp_addr;
2164 __le32 flags;
2165 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL
2166 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX (0x0UL << 0)
2167 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX (0x1UL << 0)
2168 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX
2169 __le16 port_id;
2170 __le16 unused_0;
2171 };
2172
2173 /* Output (32 bytes) */
2174 struct hwrm_queue_qportcfg_output {
2175 __le16 error_code;
2176 __le16 req_type;
2177 __le16 seq_id;
2178 __le16 resp_len;
2179 u8 max_configurable_queues;
2180 u8 max_configurable_lossless_queues;
2181 u8 queue_cfg_allowed;
2182 u8 queue_buffers_cfg_allowed;
2183 u8 queue_pfcenable_cfg_allowed;
2184 u8 queue_pri2cos_cfg_allowed;
2185 u8 queue_cos2bw_cfg_allowed;
2186 u8 queue_id0;
2187 u8 queue_id0_service_profile;
2188 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY (0x0UL << 0)
2189 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
2190 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
2191 u8 queue_id1;
2192 u8 queue_id1_service_profile;
2193 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY (0x0UL << 0)
2194 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
2195 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
2196 u8 queue_id2;
2197 u8 queue_id2_service_profile;
2198 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY (0x0UL << 0)
2199 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
2200 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
2201 u8 queue_id3;
2202 u8 queue_id3_service_profile;
2203 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY (0x0UL << 0)
2204 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
2205 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
2206 u8 queue_id4;
2207 u8 queue_id4_service_profile;
2208 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY (0x0UL << 0)
2209 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
2210 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
2211 u8 queue_id5;
2212 u8 queue_id5_service_profile;
2213 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY (0x0UL << 0)
2214 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
2215 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
2216 u8 queue_id6;
2217 u8 queue_id6_service_profile;
2218 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY (0x0UL << 0)
2219 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
2220 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
2221 u8 queue_id7;
2222 u8 queue_id7_service_profile;
2223 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY (0x0UL << 0)
2224 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
2225 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
2226 u8 valid;
2227 };
2228
2229 /* hwrm_queue_cfg */
2230 /* Input (40 bytes) */
2231 struct hwrm_queue_cfg_input {
2232 __le16 req_type;
2233 __le16 cmpl_ring;
2234 __le16 seq_id;
2235 __le16 target_id;
2236 __le64 resp_addr;
2237 __le32 flags;
2238 #define QUEUE_CFG_REQ_FLAGS_PATH 0x1UL
2239 #define QUEUE_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0)
2240 #define QUEUE_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0)
2241 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_RX
2242 __le32 enables;
2243 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL
2244 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL
2245 __le32 queue_id;
2246 __le32 dflt_len;
2247 u8 service_profile;
2248 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY (0x0UL << 0)
2249 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
2250 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
2251 u8 unused_0[7];
2252 };
2253
2254 /* Output (16 bytes) */
2255 struct hwrm_queue_cfg_output {
2256 __le16 error_code;
2257 __le16 req_type;
2258 __le16 seq_id;
2259 __le16 resp_len;
2260 __le32 unused_0;
2261 u8 unused_1;
2262 u8 unused_2;
2263 u8 unused_3;
2264 u8 valid;
2265 };
2266
2267 /* hwrm_queue_buffers_cfg */
2268 /* Input (56 bytes) */
2269 struct hwrm_queue_buffers_cfg_input {
2270 __le16 req_type;
2271 __le16 cmpl_ring;
2272 __le16 seq_id;
2273 __le16 target_id;
2274 __le64 resp_addr;
2275 __le32 flags;
2276 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH 0x1UL
2277 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0)
2278 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0)
2279 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_LAST QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_RX
2280 __le32 enables;
2281 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_RESERVED 0x1UL
2282 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_SHARED 0x2UL
2283 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_XOFF 0x4UL
2284 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_XON 0x8UL
2285 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_FULL 0x10UL
2286 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_NOTFULL 0x20UL
2287 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_MAX 0x40UL
2288 __le32 queue_id;
2289 __le32 reserved;
2290 __le32 shared;
2291 __le32 xoff;
2292 __le32 xon;
2293 __le32 full;
2294 __le32 notfull;
2295 __le32 max;
2296 };
2297
2298 /* Output (16 bytes) */
2299 struct hwrm_queue_buffers_cfg_output {
2300 __le16 error_code;
2301 __le16 req_type;
2302 __le16 seq_id;
2303 __le16 resp_len;
2304 __le32 unused_0;
2305 u8 unused_1;
2306 u8 unused_2;
2307 u8 unused_3;
2308 u8 valid;
2309 };
2310
2311 /* hwrm_queue_pfcenable_cfg */
2312 /* Input (24 bytes) */
2313 struct hwrm_queue_pfcenable_cfg_input {
2314 __le16 req_type;
2315 __le16 cmpl_ring;
2316 __le16 seq_id;
2317 __le16 target_id;
2318 __le64 resp_addr;
2319 __le32 flags;
2320 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL
2321 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL
2322 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL
2323 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL
2324 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL
2325 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL
2326 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL
2327 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL
2328 __le16 port_id;
2329 __le16 unused_0;
2330 };
2331
2332 /* Output (16 bytes) */
2333 struct hwrm_queue_pfcenable_cfg_output {
2334 __le16 error_code;
2335 __le16 req_type;
2336 __le16 seq_id;
2337 __le16 resp_len;
2338 __le32 unused_0;
2339 u8 unused_1;
2340 u8 unused_2;
2341 u8 unused_3;
2342 u8 valid;
2343 };
2344
2345 /* hwrm_queue_pri2cos_cfg */
2346 /* Input (40 bytes) */
2347 struct hwrm_queue_pri2cos_cfg_input {
2348 __le16 req_type;
2349 __le16 cmpl_ring;
2350 __le16 seq_id;
2351 __le16 target_id;
2352 __le64 resp_addr;
2353 __le32 flags;
2354 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH 0x1UL
2355 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0)
2356 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0)
2357 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX
2358 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x2UL
2359 __le32 enables;
2360 u8 port_id;
2361 u8 pri0_cos_queue_id;
2362 u8 pri1_cos_queue_id;
2363 u8 pri2_cos_queue_id;
2364 u8 pri3_cos_queue_id;
2365 u8 pri4_cos_queue_id;
2366 u8 pri5_cos_queue_id;
2367 u8 pri6_cos_queue_id;
2368 u8 pri7_cos_queue_id;
2369 u8 unused_0[7];
2370 };
2371
2372 /* Output (16 bytes) */
2373 struct hwrm_queue_pri2cos_cfg_output {
2374 __le16 error_code;
2375 __le16 req_type;
2376 __le16 seq_id;
2377 __le16 resp_len;
2378 __le32 unused_0;
2379 u8 unused_1;
2380 u8 unused_2;
2381 u8 unused_3;
2382 u8 valid;
2383 };
2384
2385 /* hwrm_queue_cos2bw_cfg */
2386 /* Input (128 bytes) */
2387 struct hwrm_queue_cos2bw_cfg_input {
2388 __le16 req_type;
2389 __le16 cmpl_ring;
2390 __le16 seq_id;
2391 __le16 target_id;
2392 __le64 resp_addr;
2393 __le32 flags;
2394 __le32 enables;
2395 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL
2396 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL
2397 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL
2398 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL
2399 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL
2400 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL
2401 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL
2402 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL
2403 __le16 port_id;
2404 u8 queue_id0;
2405 u8 unused_0;
2406 __le32 queue_id0_min_bw;
2407 __le32 queue_id0_max_bw;
2408 u8 queue_id0_tsa_assign;
2409 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP (0x0UL << 0)
2410 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS (0x1UL << 0)
2411 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2412 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST (0xffUL << 0)
2413 u8 queue_id0_pri_lvl;
2414 u8 queue_id0_bw_weight;
2415 u8 queue_id1;
2416 __le32 queue_id1_min_bw;
2417 __le32 queue_id1_max_bw;
2418 u8 queue_id1_tsa_assign;
2419 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP (0x0UL << 0)
2420 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS (0x1UL << 0)
2421 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2422 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST (0xffUL << 0)
2423 u8 queue_id1_pri_lvl;
2424 u8 queue_id1_bw_weight;
2425 u8 queue_id2;
2426 __le32 queue_id2_min_bw;
2427 __le32 queue_id2_max_bw;
2428 u8 queue_id2_tsa_assign;
2429 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP (0x0UL << 0)
2430 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS (0x1UL << 0)
2431 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2432 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST (0xffUL << 0)
2433 u8 queue_id2_pri_lvl;
2434 u8 queue_id2_bw_weight;
2435 u8 queue_id3;
2436 __le32 queue_id3_min_bw;
2437 __le32 queue_id3_max_bw;
2438 u8 queue_id3_tsa_assign;
2439 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP (0x0UL << 0)
2440 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS (0x1UL << 0)
2441 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2442 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST (0xffUL << 0)
2443 u8 queue_id3_pri_lvl;
2444 u8 queue_id3_bw_weight;
2445 u8 queue_id4;
2446 __le32 queue_id4_min_bw;
2447 __le32 queue_id4_max_bw;
2448 u8 queue_id4_tsa_assign;
2449 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP (0x0UL << 0)
2450 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS (0x1UL << 0)
2451 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2452 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST (0xffUL << 0)
2453 u8 queue_id4_pri_lvl;
2454 u8 queue_id4_bw_weight;
2455 u8 queue_id5;
2456 __le32 queue_id5_min_bw;
2457 __le32 queue_id5_max_bw;
2458 u8 queue_id5_tsa_assign;
2459 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP (0x0UL << 0)
2460 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS (0x1UL << 0)
2461 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2462 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST (0xffUL << 0)
2463 u8 queue_id5_pri_lvl;
2464 u8 queue_id5_bw_weight;
2465 u8 queue_id6;
2466 __le32 queue_id6_min_bw;
2467 __le32 queue_id6_max_bw;
2468 u8 queue_id6_tsa_assign;
2469 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP (0x0UL << 0)
2470 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS (0x1UL << 0)
2471 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2472 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST (0xffUL << 0)
2473 u8 queue_id6_pri_lvl;
2474 u8 queue_id6_bw_weight;
2475 u8 queue_id7;
2476 __le32 queue_id7_min_bw;
2477 __le32 queue_id7_max_bw;
2478 u8 queue_id7_tsa_assign;
2479 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP (0x0UL << 0)
2480 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS (0x1UL << 0)
2481 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2482 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST (0xffUL << 0)
2483 u8 queue_id7_pri_lvl;
2484 u8 queue_id7_bw_weight;
2485 u8 unused_1[5];
2486 };
2487
2488 /* Output (16 bytes) */
2489 struct hwrm_queue_cos2bw_cfg_output {
2490 __le16 error_code;
2491 __le16 req_type;
2492 __le16 seq_id;
2493 __le16 resp_len;
2494 __le32 unused_0;
2495 u8 unused_1;
2496 u8 unused_2;
2497 u8 unused_3;
2498 u8 valid;
2499 };
2500
2501 /* hwrm_vnic_alloc */
2502 /* Input (24 bytes) */
2503 struct hwrm_vnic_alloc_input {
2504 __le16 req_type;
2505 __le16 cmpl_ring;
2506 __le16 seq_id;
2507 __le16 target_id;
2508 __le64 resp_addr;
2509 __le32 flags;
2510 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL
2511 __le32 unused_0;
2512 };
2513
2514 /* Output (16 bytes) */
2515 struct hwrm_vnic_alloc_output {
2516 __le16 error_code;
2517 __le16 req_type;
2518 __le16 seq_id;
2519 __le16 resp_len;
2520 __le32 vnic_id;
2521 u8 unused_0;
2522 u8 unused_1;
2523 u8 unused_2;
2524 u8 valid;
2525 };
2526
2527 /* hwrm_vnic_free */
2528 /* Input (24 bytes) */
2529 struct hwrm_vnic_free_input {
2530 __le16 req_type;
2531 __le16 cmpl_ring;
2532 __le16 seq_id;
2533 __le16 target_id;
2534 __le64 resp_addr;
2535 __le32 vnic_id;
2536 __le32 unused_0;
2537 };
2538
2539 /* Output (16 bytes) */
2540 struct hwrm_vnic_free_output {
2541 __le16 error_code;
2542 __le16 req_type;
2543 __le16 seq_id;
2544 __le16 resp_len;
2545 __le32 unused_0;
2546 u8 unused_1;
2547 u8 unused_2;
2548 u8 unused_3;
2549 u8 valid;
2550 };
2551
2552 /* hwrm_vnic_cfg */
2553 /* Input (40 bytes) */
2554 struct hwrm_vnic_cfg_input {
2555 __le16 req_type;
2556 __le16 cmpl_ring;
2557 __le16 seq_id;
2558 __le16 target_id;
2559 __le64 resp_addr;
2560 __le32 flags;
2561 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL
2562 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL
2563 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL
2564 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL
2565 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL
2566 __le32 enables;
2567 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL
2568 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL
2569 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL
2570 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL
2571 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL
2572 __le16 vnic_id;
2573 __le16 dflt_ring_grp;
2574 __le16 rss_rule;
2575 __le16 cos_rule;
2576 __le16 lb_rule;
2577 __le16 mru;
2578 __le32 unused_0;
2579 };
2580
2581 /* Output (16 bytes) */
2582 struct hwrm_vnic_cfg_output {
2583 __le16 error_code;
2584 __le16 req_type;
2585 __le16 seq_id;
2586 __le16 resp_len;
2587 __le32 unused_0;
2588 u8 unused_1;
2589 u8 unused_2;
2590 u8 unused_3;
2591 u8 valid;
2592 };
2593
2594 /* hwrm_vnic_tpa_cfg */
2595 /* Input (40 bytes) */
2596 struct hwrm_vnic_tpa_cfg_input {
2597 __le16 req_type;
2598 __le16 cmpl_ring;
2599 __le16 seq_id;
2600 __le16 target_id;
2601 __le64 resp_addr;
2602 __le32 flags;
2603 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL
2604 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL
2605 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL
2606 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL
2607 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL
2608 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
2609 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL
2610 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL
2611 __le32 enables;
2612 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL
2613 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL
2614 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL
2615 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL
2616 __le16 vnic_id;
2617 __le16 max_agg_segs;
2618 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 (0x0UL << 0)
2619 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 (0x1UL << 0)
2620 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 (0x2UL << 0)
2621 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 (0x3UL << 0)
2622 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX (0x1fUL << 0)
2623 __le16 max_aggs;
2624 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 (0x0UL << 0)
2625 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 (0x1UL << 0)
2626 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 (0x2UL << 0)
2627 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 (0x3UL << 0)
2628 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 (0x4UL << 0)
2629 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX (0x7UL << 0)
2630 u8 unused_0;
2631 u8 unused_1;
2632 __le32 max_agg_timer;
2633 __le32 min_agg_len;
2634 };
2635
2636 /* Output (16 bytes) */
2637 struct hwrm_vnic_tpa_cfg_output {
2638 __le16 error_code;
2639 __le16 req_type;
2640 __le16 seq_id;
2641 __le16 resp_len;
2642 __le32 unused_0;
2643 u8 unused_1;
2644 u8 unused_2;
2645 u8 unused_3;
2646 u8 valid;
2647 };
2648
2649 /* hwrm_vnic_rss_cfg */
2650 /* Input (48 bytes) */
2651 struct hwrm_vnic_rss_cfg_input {
2652 __le16 req_type;
2653 __le16 cmpl_ring;
2654 __le16 seq_id;
2655 __le16 target_id;
2656 __le64 resp_addr;
2657 __le32 hash_type;
2658 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL
2659 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL
2660 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL
2661 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL
2662 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL
2663 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL
2664 __le32 unused_0;
2665 __le64 ring_grp_tbl_addr;
2666 __le64 hash_key_tbl_addr;
2667 __le16 rss_ctx_idx;
2668 __le16 unused_1[3];
2669 };
2670
2671 /* Output (16 bytes) */
2672 struct hwrm_vnic_rss_cfg_output {
2673 __le16 error_code;
2674 __le16 req_type;
2675 __le16 seq_id;
2676 __le16 resp_len;
2677 __le32 unused_0;
2678 u8 unused_1;
2679 u8 unused_2;
2680 u8 unused_3;
2681 u8 valid;
2682 };
2683
2684 /* hwrm_vnic_plcmodes_cfg */
2685 /* Input (40 bytes) */
2686 struct hwrm_vnic_plcmodes_cfg_input {
2687 __le16 req_type;
2688 __le16 cmpl_ring;
2689 __le16 seq_id;
2690 __le16 target_id;
2691 __le64 resp_addr;
2692 __le32 flags;
2693 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL
2694 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL
2695 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL
2696 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL
2697 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL
2698 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL
2699 __le32 enables;
2700 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL
2701 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL
2702 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL
2703 __le32 vnic_id;
2704 __le16 jumbo_thresh;
2705 __le16 hds_offset;
2706 __le16 hds_threshold;
2707 __le16 unused_0[3];
2708 };
2709
2710 /* Output (16 bytes) */
2711 struct hwrm_vnic_plcmodes_cfg_output {
2712 __le16 error_code;
2713 __le16 req_type;
2714 __le16 seq_id;
2715 __le16 resp_len;
2716 __le32 unused_0;
2717 u8 unused_1;
2718 u8 unused_2;
2719 u8 unused_3;
2720 u8 valid;
2721 };
2722
2723 /* hwrm_vnic_rss_cos_lb_ctx_alloc */
2724 /* Input (16 bytes) */
2725 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
2726 __le16 req_type;
2727 __le16 cmpl_ring;
2728 __le16 seq_id;
2729 __le16 target_id;
2730 __le64 resp_addr;
2731 };
2732
2733 /* Output (16 bytes) */
2734 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
2735 __le16 error_code;
2736 __le16 req_type;
2737 __le16 seq_id;
2738 __le16 resp_len;
2739 __le16 rss_cos_lb_ctx_id;
2740 u8 unused_0;
2741 u8 unused_1;
2742 u8 unused_2;
2743 u8 unused_3;
2744 u8 unused_4;
2745 u8 valid;
2746 };
2747
2748 /* hwrm_vnic_rss_cos_lb_ctx_free */
2749 /* Input (24 bytes) */
2750 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
2751 __le16 req_type;
2752 __le16 cmpl_ring;
2753 __le16 seq_id;
2754 __le16 target_id;
2755 __le64 resp_addr;
2756 __le16 rss_cos_lb_ctx_id;
2757 __le16 unused_0[3];
2758 };
2759
2760 /* Output (16 bytes) */
2761 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
2762 __le16 error_code;
2763 __le16 req_type;
2764 __le16 seq_id;
2765 __le16 resp_len;
2766 __le32 unused_0;
2767 u8 unused_1;
2768 u8 unused_2;
2769 u8 unused_3;
2770 u8 valid;
2771 };
2772
2773 /* hwrm_ring_alloc */
2774 /* Input (80 bytes) */
2775 struct hwrm_ring_alloc_input {
2776 __le16 req_type;
2777 __le16 cmpl_ring;
2778 __le16 seq_id;
2779 __le16 target_id;
2780 __le64 resp_addr;
2781 __le32 enables;
2782 #define RING_ALLOC_REQ_ENABLES_RESERVED1 0x1UL
2783 #define RING_ALLOC_REQ_ENABLES_RESERVED2 0x2UL
2784 #define RING_ALLOC_REQ_ENABLES_RESERVED3 0x4UL
2785 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL
2786 #define RING_ALLOC_REQ_ENABLES_RESERVED4 0x10UL
2787 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL
2788 u8 ring_type;
2789 #define RING_ALLOC_REQ_RING_TYPE_CMPL (0x0UL << 0)
2790 #define RING_ALLOC_REQ_RING_TYPE_TX (0x1UL << 0)
2791 #define RING_ALLOC_REQ_RING_TYPE_RX (0x2UL << 0)
2792 u8 unused_0;
2793 __le16 unused_1;
2794 __le64 page_tbl_addr;
2795 __le32 fbo;
2796 u8 page_size;
2797 u8 page_tbl_depth;
2798 u8 unused_2;
2799 u8 unused_3;
2800 __le32 length;
2801 __le16 logical_id;
2802 __le16 cmpl_ring_id;
2803 __le16 queue_id;
2804 u8 unused_4;
2805 u8 unused_5;
2806 __le32 reserved1;
2807 __le16 reserved2;
2808 u8 unused_6;
2809 u8 unused_7;
2810 __le32 reserved3;
2811 __le32 stat_ctx_id;
2812 __le32 reserved4;
2813 __le32 max_bw;
2814 u8 int_mode;
2815 #define RING_ALLOC_REQ_INT_MODE_LEGACY (0x0UL << 0)
2816 #define RING_ALLOC_REQ_INT_MODE_RSVD (0x1UL << 0)
2817 #define RING_ALLOC_REQ_INT_MODE_MSIX (0x2UL << 0)
2818 #define RING_ALLOC_REQ_INT_MODE_POLL (0x3UL << 0)
2819 u8 unused_8[3];
2820 };
2821
2822 /* Output (16 bytes) */
2823 struct hwrm_ring_alloc_output {
2824 __le16 error_code;
2825 __le16 req_type;
2826 __le16 seq_id;
2827 __le16 resp_len;
2828 __le16 ring_id;
2829 __le16 logical_ring_id;
2830 u8 unused_0;
2831 u8 unused_1;
2832 u8 unused_2;
2833 u8 valid;
2834 };
2835
2836 /* hwrm_ring_free */
2837 /* Input (24 bytes) */
2838 struct hwrm_ring_free_input {
2839 __le16 req_type;
2840 __le16 cmpl_ring;
2841 __le16 seq_id;
2842 __le16 target_id;
2843 __le64 resp_addr;
2844 u8 ring_type;
2845 #define RING_FREE_REQ_RING_TYPE_CMPL (0x0UL << 0)
2846 #define RING_FREE_REQ_RING_TYPE_TX (0x1UL << 0)
2847 #define RING_FREE_REQ_RING_TYPE_RX (0x2UL << 0)
2848 u8 unused_0;
2849 __le16 ring_id;
2850 __le32 unused_1;
2851 };
2852
2853 /* Output (16 bytes) */
2854 struct hwrm_ring_free_output {
2855 __le16 error_code;
2856 __le16 req_type;
2857 __le16 seq_id;
2858 __le16 resp_len;
2859 __le32 unused_0;
2860 u8 unused_1;
2861 u8 unused_2;
2862 u8 unused_3;
2863 u8 valid;
2864 };
2865
2866 /* hwrm_ring_cmpl_ring_qaggint_params */
2867 /* Input (24 bytes) */
2868 struct hwrm_ring_cmpl_ring_qaggint_params_input {
2869 __le16 req_type;
2870 __le16 cmpl_ring;
2871 __le16 seq_id;
2872 __le16 target_id;
2873 __le64 resp_addr;
2874 __le16 ring_id;
2875 __le16 unused_0[3];
2876 };
2877
2878 /* Output (32 bytes) */
2879 struct hwrm_ring_cmpl_ring_qaggint_params_output {
2880 __le16 error_code;
2881 __le16 req_type;
2882 __le16 seq_id;
2883 __le16 resp_len;
2884 __le16 flags;
2885 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL
2886 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL
2887 __le16 num_cmpl_dma_aggr;
2888 __le16 num_cmpl_dma_aggr_during_int;
2889 __le16 cmpl_aggr_dma_tmr;
2890 __le16 cmpl_aggr_dma_tmr_during_int;
2891 __le16 int_lat_tmr_min;
2892 __le16 int_lat_tmr_max;
2893 __le16 num_cmpl_aggr_int;
2894 __le32 unused_0;
2895 u8 unused_1;
2896 u8 unused_2;
2897 u8 unused_3;
2898 u8 valid;
2899 };
2900
2901 /* hwrm_ring_cmpl_ring_cfg_aggint_params */
2902 /* Input (40 bytes) */
2903 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
2904 __le16 req_type;
2905 __le16 cmpl_ring;
2906 __le16 seq_id;
2907 __le16 target_id;
2908 __le64 resp_addr;
2909 __le16 ring_id;
2910 __le16 flags;
2911 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL
2912 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL
2913 __le16 num_cmpl_dma_aggr;
2914 __le16 num_cmpl_dma_aggr_during_int;
2915 __le16 cmpl_aggr_dma_tmr;
2916 __le16 cmpl_aggr_dma_tmr_during_int;
2917 __le16 int_lat_tmr_min;
2918 __le16 int_lat_tmr_max;
2919 __le16 num_cmpl_aggr_int;
2920 __le16 unused_0[3];
2921 };
2922
2923 /* Output (16 bytes) */
2924 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
2925 __le16 error_code;
2926 __le16 req_type;
2927 __le16 seq_id;
2928 __le16 resp_len;
2929 __le32 unused_0;
2930 u8 unused_1;
2931 u8 unused_2;
2932 u8 unused_3;
2933 u8 valid;
2934 };
2935
2936 /* hwrm_ring_reset */
2937 /* Input (24 bytes) */
2938 struct hwrm_ring_reset_input {
2939 __le16 req_type;
2940 __le16 cmpl_ring;
2941 __le16 seq_id;
2942 __le16 target_id;
2943 __le64 resp_addr;
2944 u8 ring_type;
2945 #define RING_RESET_REQ_RING_TYPE_CMPL (0x0UL << 0)
2946 #define RING_RESET_REQ_RING_TYPE_TX (0x1UL << 0)
2947 #define RING_RESET_REQ_RING_TYPE_RX (0x2UL << 0)
2948 u8 unused_0;
2949 __le16 ring_id;
2950 __le32 unused_1;
2951 };
2952
2953 /* Output (16 bytes) */
2954 struct hwrm_ring_reset_output {
2955 __le16 error_code;
2956 __le16 req_type;
2957 __le16 seq_id;
2958 __le16 resp_len;
2959 __le32 unused_0;
2960 u8 unused_1;
2961 u8 unused_2;
2962 u8 unused_3;
2963 u8 valid;
2964 };
2965
2966 /* hwrm_ring_grp_alloc */
2967 /* Input (24 bytes) */
2968 struct hwrm_ring_grp_alloc_input {
2969 __le16 req_type;
2970 __le16 cmpl_ring;
2971 __le16 seq_id;
2972 __le16 target_id;
2973 __le64 resp_addr;
2974 __le16 cr;
2975 __le16 rr;
2976 __le16 ar;
2977 __le16 sc;
2978 };
2979
2980 /* Output (16 bytes) */
2981 struct hwrm_ring_grp_alloc_output {
2982 __le16 error_code;
2983 __le16 req_type;
2984 __le16 seq_id;
2985 __le16 resp_len;
2986 __le32 ring_group_id;
2987 u8 unused_0;
2988 u8 unused_1;
2989 u8 unused_2;
2990 u8 valid;
2991 };
2992
2993 /* hwrm_ring_grp_free */
2994 /* Input (24 bytes) */
2995 struct hwrm_ring_grp_free_input {
2996 __le16 req_type;
2997 __le16 cmpl_ring;
2998 __le16 seq_id;
2999 __le16 target_id;
3000 __le64 resp_addr;
3001 __le32 ring_group_id;
3002 __le32 unused_0;
3003 };
3004
3005 /* Output (16 bytes) */
3006 struct hwrm_ring_grp_free_output {
3007 __le16 error_code;
3008 __le16 req_type;
3009 __le16 seq_id;
3010 __le16 resp_len;
3011 __le32 unused_0;
3012 u8 unused_1;
3013 u8 unused_2;
3014 u8 unused_3;
3015 u8 valid;
3016 };
3017
3018 /* hwrm_cfa_l2_filter_alloc */
3019 /* Input (96 bytes) */
3020 struct hwrm_cfa_l2_filter_alloc_input {
3021 __le16 req_type;
3022 __le16 cmpl_ring;
3023 __le16 seq_id;
3024 __le16 target_id;
3025 __le64 resp_addr;
3026 __le32 flags;
3027 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL
3028 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX (0x0UL << 0)
3029 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX (0x1UL << 0)
3030 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
3031 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL
3032 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL
3033 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL
3034 __le32 enables;
3035 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL
3036 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL
3037 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL
3038 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL
3039 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL
3040 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL
3041 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL
3042 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL
3043 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL
3044 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL
3045 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL
3046 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL
3047 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL
3048 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL
3049 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL
3050 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
3051 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
3052 u8 l2_addr[6];
3053 u8 unused_0;
3054 u8 unused_1;
3055 u8 l2_addr_mask[6];
3056 __le16 l2_ovlan;
3057 __le16 l2_ovlan_mask;
3058 __le16 l2_ivlan;
3059 __le16 l2_ivlan_mask;
3060 u8 unused_2;
3061 u8 unused_3;
3062 u8 t_l2_addr[6];
3063 u8 unused_4;
3064 u8 unused_5;
3065 u8 t_l2_addr_mask[6];
3066 __le16 t_l2_ovlan;
3067 __le16 t_l2_ovlan_mask;
3068 __le16 t_l2_ivlan;
3069 __le16 t_l2_ivlan_mask;
3070 u8 src_type;
3071 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT (0x0UL << 0)
3072 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF (0x1UL << 0)
3073 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF (0x2UL << 0)
3074 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC (0x3UL << 0)
3075 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG (0x4UL << 0)
3076 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE (0x5UL << 0)
3077 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO (0x6UL << 0)
3078 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG (0x7UL << 0)
3079 u8 unused_6;
3080 __le32 src_id;
3081 u8 tunnel_type;
3082 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0)
3083 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
3084 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0)
3085 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0)
3086 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0)
3087 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
3088 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0)
3089 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0)
3090 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0)
3091 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0)
3092 u8 unused_7;
3093 __le16 dst_id;
3094 __le16 mirror_vnic_id;
3095 u8 pri_hint;
3096 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER (0x0UL << 0)
3097 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER (0x1UL << 0)
3098 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER (0x2UL << 0)
3099 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX (0x3UL << 0)
3100 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN (0x4UL << 0)
3101 u8 unused_8;
3102 __le32 unused_9;
3103 __le64 l2_filter_id_hint;
3104 };
3105
3106 /* Output (24 bytes) */
3107 struct hwrm_cfa_l2_filter_alloc_output {
3108 __le16 error_code;
3109 __le16 req_type;
3110 __le16 seq_id;
3111 __le16 resp_len;
3112 __le64 l2_filter_id;
3113 __le32 flow_id;
3114 u8 unused_0;
3115 u8 unused_1;
3116 u8 unused_2;
3117 u8 valid;
3118 };
3119
3120 /* hwrm_cfa_l2_filter_free */
3121 /* Input (24 bytes) */
3122 struct hwrm_cfa_l2_filter_free_input {
3123 __le16 req_type;
3124 __le16 cmpl_ring;
3125 __le16 seq_id;
3126 __le16 target_id;
3127 __le64 resp_addr;
3128 __le64 l2_filter_id;
3129 };
3130
3131 /* Output (16 bytes) */
3132 struct hwrm_cfa_l2_filter_free_output {
3133 __le16 error_code;
3134 __le16 req_type;
3135 __le16 seq_id;
3136 __le16 resp_len;
3137 __le32 unused_0;
3138 u8 unused_1;
3139 u8 unused_2;
3140 u8 unused_3;
3141 u8 valid;
3142 };
3143
3144 /* hwrm_cfa_l2_filter_cfg */
3145 /* Input (40 bytes) */
3146 struct hwrm_cfa_l2_filter_cfg_input {
3147 __le16 req_type;
3148 __le16 cmpl_ring;
3149 __le16 seq_id;
3150 __le16 target_id;
3151 __le64 resp_addr;
3152 __le32 flags;
3153 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL
3154 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0)
3155 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0)
3156 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX
3157 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL
3158 __le32 enables;
3159 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL
3160 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
3161 __le64 l2_filter_id;
3162 __le32 dst_id;
3163 __le32 new_mirror_vnic_id;
3164 };
3165
3166 /* Output (16 bytes) */
3167 struct hwrm_cfa_l2_filter_cfg_output {
3168 __le16 error_code;
3169 __le16 req_type;
3170 __le16 seq_id;
3171 __le16 resp_len;
3172 __le32 unused_0;
3173 u8 unused_1;
3174 u8 unused_2;
3175 u8 unused_3;
3176 u8 valid;
3177 };
3178
3179 /* hwrm_cfa_l2_set_rx_mask */
3180 /* Input (56 bytes) */
3181 struct hwrm_cfa_l2_set_rx_mask_input {
3182 __le16 req_type;
3183 __le16 cmpl_ring;
3184 __le16 seq_id;
3185 __le16 target_id;
3186 __le64 resp_addr;
3187 __le32 vnic_id;
3188 __le32 mask;
3189 #define CFA_L2_SET_RX_MASK_REQ_MASK_RESERVED 0x1UL
3190 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL
3191 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL
3192 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL
3193 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL
3194 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL
3195 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL
3196 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL
3197 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL
3198 __le64 mc_tbl_addr;
3199 __le32 num_mc_entries;
3200 __le32 unused_0;
3201 __le64 vlan_tag_tbl_addr;
3202 __le32 num_vlan_tags;
3203 __le32 unused_1;
3204 };
3205
3206 /* Output (16 bytes) */
3207 struct hwrm_cfa_l2_set_rx_mask_output {
3208 __le16 error_code;
3209 __le16 req_type;
3210 __le16 seq_id;
3211 __le16 resp_len;
3212 __le32 unused_0;
3213 u8 unused_1;
3214 u8 unused_2;
3215 u8 unused_3;
3216 u8 valid;
3217 };
3218
3219 /* hwrm_cfa_tunnel_filter_alloc */
3220 /* Input (88 bytes) */
3221 struct hwrm_cfa_tunnel_filter_alloc_input {
3222 __le16 req_type;
3223 __le16 cmpl_ring;
3224 __le16 seq_id;
3225 __le16 target_id;
3226 __le64 resp_addr;
3227 __le32 flags;
3228 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
3229 __le32 enables;
3230 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
3231 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL
3232 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL
3233 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL
3234 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL
3235 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL
3236 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL
3237 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL
3238 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL
3239 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL
3240 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL
3241 __le64 l2_filter_id;
3242 u8 l2_addr[6];
3243 __le16 l2_ivlan;
3244 __le32 l3_addr[4];
3245 __le32 t_l3_addr[4];
3246 u8 l3_addr_type;
3247 u8 t_l3_addr_type;
3248 u8 tunnel_type;
3249 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0)
3250 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
3251 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0)
3252 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0)
3253 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0)
3254 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
3255 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0)
3256 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0)
3257 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0)
3258 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0)
3259 u8 unused_0;
3260 __le32 vni;
3261 __le32 dst_vnic_id;
3262 __le32 mirror_vnic_id;
3263 };
3264
3265 /* Output (24 bytes) */
3266 struct hwrm_cfa_tunnel_filter_alloc_output {
3267 __le16 error_code;
3268 __le16 req_type;
3269 __le16 seq_id;
3270 __le16 resp_len;
3271 __le64 tunnel_filter_id;
3272 __le32 flow_id;
3273 u8 unused_0;
3274 u8 unused_1;
3275 u8 unused_2;
3276 u8 valid;
3277 };
3278
3279 /* hwrm_cfa_tunnel_filter_free */
3280 /* Input (24 bytes) */
3281 struct hwrm_cfa_tunnel_filter_free_input {
3282 __le16 req_type;
3283 __le16 cmpl_ring;
3284 __le16 seq_id;
3285 __le16 target_id;
3286 __le64 resp_addr;
3287 __le64 tunnel_filter_id;
3288 };
3289
3290 /* Output (16 bytes) */
3291 struct hwrm_cfa_tunnel_filter_free_output {
3292 __le16 error_code;
3293 __le16 req_type;
3294 __le16 seq_id;
3295 __le16 resp_len;
3296 __le32 unused_0;
3297 u8 unused_1;
3298 u8 unused_2;
3299 u8 unused_3;
3300 u8 valid;
3301 };
3302
3303 /* hwrm_cfa_encap_record_alloc */
3304 /* Input (32 bytes) */
3305 struct hwrm_cfa_encap_record_alloc_input {
3306 __le16 req_type;
3307 __le16 cmpl_ring;
3308 __le16 seq_id;
3309 __le16 target_id;
3310 __le64 resp_addr;
3311 __le32 flags;
3312 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
3313 u8 encap_type;
3314 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN (0x1UL << 0)
3315 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE (0x2UL << 0)
3316 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE (0x3UL << 0)
3317 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP (0x4UL << 0)
3318 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE (0x5UL << 0)
3319 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS (0x6UL << 0)
3320 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN (0x7UL << 0)
3321 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE (0x8UL << 0)
3322 u8 unused_0;
3323 __le16 unused_1;
3324 __le32 encap_data[16];
3325 };
3326
3327 /* Output (16 bytes) */
3328 struct hwrm_cfa_encap_record_alloc_output {
3329 __le16 error_code;
3330 __le16 req_type;
3331 __le16 seq_id;
3332 __le16 resp_len;
3333 __le32 encap_record_id;
3334 u8 unused_0;
3335 u8 unused_1;
3336 u8 unused_2;
3337 u8 valid;
3338 };
3339
3340 /* hwrm_cfa_encap_record_free */
3341 /* Input (24 bytes) */
3342 struct hwrm_cfa_encap_record_free_input {
3343 __le16 req_type;
3344 __le16 cmpl_ring;
3345 __le16 seq_id;
3346 __le16 target_id;
3347 __le64 resp_addr;
3348 __le32 encap_record_id;
3349 __le32 unused_0;
3350 };
3351
3352 /* Output (16 bytes) */
3353 struct hwrm_cfa_encap_record_free_output {
3354 __le16 error_code;
3355 __le16 req_type;
3356 __le16 seq_id;
3357 __le16 resp_len;
3358 __le32 unused_0;
3359 u8 unused_1;
3360 u8 unused_2;
3361 u8 unused_3;
3362 u8 valid;
3363 };
3364
3365 /* hwrm_cfa_ntuple_filter_alloc */
3366 /* Input (128 bytes) */
3367 struct hwrm_cfa_ntuple_filter_alloc_input {
3368 __le16 req_type;
3369 __le16 cmpl_ring;
3370 __le16 seq_id;
3371 __le16 target_id;
3372 __le64 resp_addr;
3373 __le32 flags;
3374 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
3375 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL
3376 __le32 enables;
3377 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
3378 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL
3379 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL
3380 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL
3381 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL
3382 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL
3383 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL
3384 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL
3385 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL
3386 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL
3387 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL
3388 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL
3389 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL
3390 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL
3391 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL
3392 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL
3393 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL
3394 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL
3395 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL
3396 __le64 l2_filter_id;
3397 u8 src_macaddr[6];
3398 __be16 ethertype;
3399 u8 ip_addr_type;
3400 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN (0x0UL << 0)
3401 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 (0x4UL << 0)
3402 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 (0x6UL << 0)
3403 u8 ip_protocol;
3404 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN (0x0UL << 0)
3405 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP (0x6UL << 0)
3406 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP (0x11UL << 0)
3407 __le16 dst_id;
3408 __le16 mirror_vnic_id;
3409 u8 tunnel_type;
3410 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0)
3411 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
3412 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0)
3413 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0)
3414 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0)
3415 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
3416 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0)
3417 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0)
3418 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0)
3419 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0)
3420 u8 pri_hint;
3421 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER (0x0UL << 0)
3422 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE (0x1UL << 0)
3423 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW (0x2UL << 0)
3424 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST (0x3UL << 0)
3425 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST (0x4UL << 0)
3426 __be32 src_ipaddr[4];
3427 __be32 src_ipaddr_mask[4];
3428 __be32 dst_ipaddr[4];
3429 __be32 dst_ipaddr_mask[4];
3430 __be16 src_port;
3431 __be16 src_port_mask;
3432 __be16 dst_port;
3433 __be16 dst_port_mask;
3434 __le64 ntuple_filter_id_hint;
3435 };
3436
3437 /* Output (24 bytes) */
3438 struct hwrm_cfa_ntuple_filter_alloc_output {
3439 __le16 error_code;
3440 __le16 req_type;
3441 __le16 seq_id;
3442 __le16 resp_len;
3443 __le64 ntuple_filter_id;
3444 __le32 flow_id;
3445 u8 unused_0;
3446 u8 unused_1;
3447 u8 unused_2;
3448 u8 valid;
3449 };
3450
3451 /* hwrm_cfa_ntuple_filter_free */
3452 /* Input (24 bytes) */
3453 struct hwrm_cfa_ntuple_filter_free_input {
3454 __le16 req_type;
3455 __le16 cmpl_ring;
3456 __le16 seq_id;
3457 __le16 target_id;
3458 __le64 resp_addr;
3459 __le64 ntuple_filter_id;
3460 };
3461
3462 /* Output (16 bytes) */
3463 struct hwrm_cfa_ntuple_filter_free_output {
3464 __le16 error_code;
3465 __le16 req_type;
3466 __le16 seq_id;
3467 __le16 resp_len;
3468 __le32 unused_0;
3469 u8 unused_1;
3470 u8 unused_2;
3471 u8 unused_3;
3472 u8 valid;
3473 };
3474
3475 /* hwrm_cfa_ntuple_filter_cfg */
3476 /* Input (40 bytes) */
3477 struct hwrm_cfa_ntuple_filter_cfg_input {
3478 __le16 req_type;
3479 __le16 cmpl_ring;
3480 __le16 seq_id;
3481 __le16 target_id;
3482 __le64 resp_addr;
3483 __le32 enables;
3484 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL
3485 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
3486 __le32 unused_0;
3487 __le64 ntuple_filter_id;
3488 __le32 new_dst_id;
3489 __le32 new_mirror_vnic_id;
3490 };
3491
3492 /* Output (16 bytes) */
3493 struct hwrm_cfa_ntuple_filter_cfg_output {
3494 __le16 error_code;
3495 __le16 req_type;
3496 __le16 seq_id;
3497 __le16 resp_len;
3498 __le32 unused_0;
3499 u8 unused_1;
3500 u8 unused_2;
3501 u8 unused_3;
3502 u8 valid;
3503 };
3504
3505 /* hwrm_tunnel_dst_port_query */
3506 /* Input (24 bytes) */
3507 struct hwrm_tunnel_dst_port_query_input {
3508 __le16 req_type;
3509 __le16 cmpl_ring;
3510 __le16 seq_id;
3511 __le16 target_id;
3512 __le64 resp_addr;
3513 u8 tunnel_type;
3514 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
3515 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
3516 u8 unused_0[7];
3517 };
3518
3519 /* Output (16 bytes) */
3520 struct hwrm_tunnel_dst_port_query_output {
3521 __le16 error_code;
3522 __le16 req_type;
3523 __le16 seq_id;
3524 __le16 resp_len;
3525 __le16 tunnel_dst_port_id;
3526 __be16 tunnel_dst_port_val;
3527 u8 unused_0;
3528 u8 unused_1;
3529 u8 unused_2;
3530 u8 valid;
3531 };
3532
3533 /* hwrm_tunnel_dst_port_alloc */
3534 /* Input (24 bytes) */
3535 struct hwrm_tunnel_dst_port_alloc_input {
3536 __le16 req_type;
3537 __le16 cmpl_ring;
3538 __le16 seq_id;
3539 __le16 target_id;
3540 __le64 resp_addr;
3541 u8 tunnel_type;
3542 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
3543 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
3544 u8 unused_0;
3545 __be16 tunnel_dst_port_val;
3546 __le32 unused_1;
3547 };
3548
3549 /* Output (16 bytes) */
3550 struct hwrm_tunnel_dst_port_alloc_output {
3551 __le16 error_code;
3552 __le16 req_type;
3553 __le16 seq_id;
3554 __le16 resp_len;
3555 __le16 tunnel_dst_port_id;
3556 u8 unused_0;
3557 u8 unused_1;
3558 u8 unused_2;
3559 u8 unused_3;
3560 u8 unused_4;
3561 u8 valid;
3562 };
3563
3564 /* hwrm_tunnel_dst_port_free */
3565 /* Input (24 bytes) */
3566 struct hwrm_tunnel_dst_port_free_input {
3567 __le16 req_type;
3568 __le16 cmpl_ring;
3569 __le16 seq_id;
3570 __le16 target_id;
3571 __le64 resp_addr;
3572 u8 tunnel_type;
3573 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
3574 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
3575 u8 unused_0;
3576 __le16 tunnel_dst_port_id;
3577 __le32 unused_1;
3578 };
3579
3580 /* Output (16 bytes) */
3581 struct hwrm_tunnel_dst_port_free_output {
3582 __le16 error_code;
3583 __le16 req_type;
3584 __le16 seq_id;
3585 __le16 resp_len;
3586 __le32 unused_0;
3587 u8 unused_1;
3588 u8 unused_2;
3589 u8 unused_3;
3590 u8 valid;
3591 };
3592
3593 /* hwrm_stat_ctx_alloc */
3594 /* Input (32 bytes) */
3595 struct hwrm_stat_ctx_alloc_input {
3596 __le16 req_type;
3597 __le16 cmpl_ring;
3598 __le16 seq_id;
3599 __le16 target_id;
3600 __le64 resp_addr;
3601 __le64 stats_dma_addr;
3602 __le32 update_period_ms;
3603 __le32 unused_0;
3604 };
3605
3606 /* Output (16 bytes) */
3607 struct hwrm_stat_ctx_alloc_output {
3608 __le16 error_code;
3609 __le16 req_type;
3610 __le16 seq_id;
3611 __le16 resp_len;
3612 __le32 stat_ctx_id;
3613 u8 unused_0;
3614 u8 unused_1;
3615 u8 unused_2;
3616 u8 valid;
3617 };
3618
3619 /* hwrm_stat_ctx_free */
3620 /* Input (24 bytes) */
3621 struct hwrm_stat_ctx_free_input {
3622 __le16 req_type;
3623 __le16 cmpl_ring;
3624 __le16 seq_id;
3625 __le16 target_id;
3626 __le64 resp_addr;
3627 __le32 stat_ctx_id;
3628 __le32 unused_0;
3629 };
3630
3631 /* Output (16 bytes) */
3632 struct hwrm_stat_ctx_free_output {
3633 __le16 error_code;
3634 __le16 req_type;
3635 __le16 seq_id;
3636 __le16 resp_len;
3637 __le32 stat_ctx_id;
3638 u8 unused_0;
3639 u8 unused_1;
3640 u8 unused_2;
3641 u8 valid;
3642 };
3643
3644 /* hwrm_stat_ctx_query */
3645 /* Input (24 bytes) */
3646 struct hwrm_stat_ctx_query_input {
3647 __le16 req_type;
3648 __le16 cmpl_ring;
3649 __le16 seq_id;
3650 __le16 target_id;
3651 __le64 resp_addr;
3652 __le32 stat_ctx_id;
3653 __le32 unused_0;
3654 };
3655
3656 /* Output (176 bytes) */
3657 struct hwrm_stat_ctx_query_output {
3658 __le16 error_code;
3659 __le16 req_type;
3660 __le16 seq_id;
3661 __le16 resp_len;
3662 __le64 tx_ucast_pkts;
3663 __le64 tx_mcast_pkts;
3664 __le64 tx_bcast_pkts;
3665 __le64 tx_err_pkts;
3666 __le64 tx_drop_pkts;
3667 __le64 tx_ucast_bytes;
3668 __le64 tx_mcast_bytes;
3669 __le64 tx_bcast_bytes;
3670 __le64 rx_ucast_pkts;
3671 __le64 rx_mcast_pkts;
3672 __le64 rx_bcast_pkts;
3673 __le64 rx_err_pkts;
3674 __le64 rx_drop_pkts;
3675 __le64 rx_ucast_bytes;
3676 __le64 rx_mcast_bytes;
3677 __le64 rx_bcast_bytes;
3678 __le64 rx_agg_pkts;
3679 __le64 rx_agg_bytes;
3680 __le64 rx_agg_events;
3681 __le64 rx_agg_aborts;
3682 __le32 unused_0;
3683 u8 unused_1;
3684 u8 unused_2;
3685 u8 unused_3;
3686 u8 valid;
3687 };
3688
3689 /* hwrm_stat_ctx_clr_stats */
3690 /* Input (24 bytes) */
3691 struct hwrm_stat_ctx_clr_stats_input {
3692 __le16 req_type;
3693 __le16 cmpl_ring;
3694 __le16 seq_id;
3695 __le16 target_id;
3696 __le64 resp_addr;
3697 __le32 stat_ctx_id;
3698 __le32 unused_0;
3699 };
3700
3701 /* Output (16 bytes) */
3702 struct hwrm_stat_ctx_clr_stats_output {
3703 __le16 error_code;
3704 __le16 req_type;
3705 __le16 seq_id;
3706 __le16 resp_len;
3707 __le32 unused_0;
3708 u8 unused_1;
3709 u8 unused_2;
3710 u8 unused_3;
3711 u8 valid;
3712 };
3713
3714 /* hwrm_fw_reset */
3715 /* Input (24 bytes) */
3716 struct hwrm_fw_reset_input {
3717 __le16 req_type;
3718 __le16 cmpl_ring;
3719 __le16 seq_id;
3720 __le16 target_id;
3721 __le64 resp_addr;
3722 u8 embedded_proc_type;
3723 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT (0x0UL << 0)
3724 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT (0x1UL << 0)
3725 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL (0x2UL << 0)
3726 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE (0x3UL << 0)
3727 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_RSVD (0x4UL << 0)
3728 u8 selfrst_status;
3729 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0)
3730 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0)
3731 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0)
3732 __le16 unused_0[3];
3733 };
3734
3735 /* Output (16 bytes) */
3736 struct hwrm_fw_reset_output {
3737 __le16 error_code;
3738 __le16 req_type;
3739 __le16 seq_id;
3740 __le16 resp_len;
3741 u8 selfrst_status;
3742 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0)
3743 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0)
3744 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0)
3745 u8 unused_0;
3746 __le16 unused_1;
3747 u8 unused_2;
3748 u8 unused_3;
3749 u8 unused_4;
3750 u8 valid;
3751 };
3752
3753 /* hwrm_fw_qstatus */
3754 /* Input (24 bytes) */
3755 struct hwrm_fw_qstatus_input {
3756 __le16 req_type;
3757 __le16 cmpl_ring;
3758 __le16 seq_id;
3759 __le16 target_id;
3760 __le64 resp_addr;
3761 u8 embedded_proc_type;
3762 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT (0x0UL << 0)
3763 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT (0x1UL << 0)
3764 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL (0x2UL << 0)
3765 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE (0x3UL << 0)
3766 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_RSVD (0x4UL << 0)
3767 u8 unused_0[7];
3768 };
3769
3770 /* Output (16 bytes) */
3771 struct hwrm_fw_qstatus_output {
3772 __le16 error_code;
3773 __le16 req_type;
3774 __le16 seq_id;
3775 __le16 resp_len;
3776 u8 selfrst_status;
3777 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0)
3778 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0)
3779 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0)
3780 u8 unused_0;
3781 __le16 unused_1;
3782 u8 unused_2;
3783 u8 unused_3;
3784 u8 unused_4;
3785 u8 valid;
3786 };
3787
3788 /* hwrm_exec_fwd_resp */
3789 /* Input (128 bytes) */
3790 struct hwrm_exec_fwd_resp_input {
3791 __le16 req_type;
3792 __le16 cmpl_ring;
3793 __le16 seq_id;
3794 __le16 target_id;
3795 __le64 resp_addr;
3796 __le32 encap_request[26];
3797 __le16 encap_resp_target_id;
3798 __le16 unused_0[3];
3799 };
3800
3801 /* Output (16 bytes) */
3802 struct hwrm_exec_fwd_resp_output {
3803 __le16 error_code;
3804 __le16 req_type;
3805 __le16 seq_id;
3806 __le16 resp_len;
3807 __le32 unused_0;
3808 u8 unused_1;
3809 u8 unused_2;
3810 u8 unused_3;
3811 u8 valid;
3812 };
3813
3814 /* hwrm_reject_fwd_resp */
3815 /* Input (128 bytes) */
3816 struct hwrm_reject_fwd_resp_input {
3817 __le16 req_type;
3818 __le16 cmpl_ring;
3819 __le16 seq_id;
3820 __le16 target_id;
3821 __le64 resp_addr;
3822 __le32 encap_request[26];
3823 __le16 encap_resp_target_id;
3824 __le16 unused_0[3];
3825 };
3826
3827 /* Output (16 bytes) */
3828 struct hwrm_reject_fwd_resp_output {
3829 __le16 error_code;
3830 __le16 req_type;
3831 __le16 seq_id;
3832 __le16 resp_len;
3833 __le32 unused_0;
3834 u8 unused_1;
3835 u8 unused_2;
3836 u8 unused_3;
3837 u8 valid;
3838 };
3839
3840 /* hwrm_fwd_resp */
3841 /* Input (40 bytes) */
3842 struct hwrm_fwd_resp_input {
3843 __le16 req_type;
3844 __le16 cmpl_ring;
3845 __le16 seq_id;
3846 __le16 target_id;
3847 __le64 resp_addr;
3848 __le16 encap_resp_target_id;
3849 __le16 encap_resp_cmpl_ring;
3850 __le16 encap_resp_len;
3851 u8 unused_0;
3852 u8 unused_1;
3853 __le64 encap_resp_addr;
3854 __le32 encap_resp[24];
3855 };
3856
3857 /* Output (16 bytes) */
3858 struct hwrm_fwd_resp_output {
3859 __le16 error_code;
3860 __le16 req_type;
3861 __le16 seq_id;
3862 __le16 resp_len;
3863 __le32 unused_0;
3864 u8 unused_1;
3865 u8 unused_2;
3866 u8 unused_3;
3867 u8 valid;
3868 };
3869
3870 /* hwrm_fwd_async_event_cmpl */
3871 /* Input (32 bytes) */
3872 struct hwrm_fwd_async_event_cmpl_input {
3873 __le16 req_type;
3874 __le16 cmpl_ring;
3875 __le16 seq_id;
3876 __le16 target_id;
3877 __le64 resp_addr;
3878 __le16 encap_async_event_target_id;
3879 u8 unused_0;
3880 u8 unused_1;
3881 u8 unused_2[3];
3882 u8 unused_3;
3883 __le32 encap_async_event_cmpl[4];
3884 };
3885
3886 /* Output (16 bytes) */
3887 struct hwrm_fwd_async_event_cmpl_output {
3888 __le16 error_code;
3889 __le16 req_type;
3890 __le16 seq_id;
3891 __le16 resp_len;
3892 __le32 unused_0;
3893 u8 unused_1;
3894 u8 unused_2;
3895 u8 unused_3;
3896 u8 valid;
3897 };
3898
3899 /* hwrm_temp_monitor_query */
3900 /* Input (16 bytes) */
3901 struct hwrm_temp_monitor_query_input {
3902 __le16 req_type;
3903 __le16 cmpl_ring;
3904 __le16 seq_id;
3905 __le16 target_id;
3906 __le64 resp_addr;
3907 };
3908
3909 /* Output (16 bytes) */
3910 struct hwrm_temp_monitor_query_output {
3911 __le16 error_code;
3912 __le16 req_type;
3913 __le16 seq_id;
3914 __le16 resp_len;
3915 u8 temp;
3916 u8 unused_0;
3917 __le16 unused_1;
3918 u8 unused_2;
3919 u8 unused_3;
3920 u8 unused_4;
3921 u8 valid;
3922 };
3923
3924 /* hwrm_nvm_raw_write_blk */
3925 /* Input (32 bytes) */
3926 struct hwrm_nvm_raw_write_blk_input {
3927 __le16 req_type;
3928 __le16 cmpl_ring;
3929 __le16 seq_id;
3930 __le16 target_id;
3931 __le64 resp_addr;
3932 __le64 host_src_addr;
3933 __le32 dest_addr;
3934 __le32 len;
3935 };
3936
3937 /* Output (16 bytes) */
3938 struct hwrm_nvm_raw_write_blk_output {
3939 __le16 error_code;
3940 __le16 req_type;
3941 __le16 seq_id;
3942 __le16 resp_len;
3943 __le32 unused_0;
3944 u8 unused_1;
3945 u8 unused_2;
3946 u8 unused_3;
3947 u8 valid;
3948 };
3949
3950 /* hwrm_nvm_read */
3951 /* Input (40 bytes) */
3952 struct hwrm_nvm_read_input {
3953 __le16 req_type;
3954 __le16 cmpl_ring;
3955 __le16 seq_id;
3956 __le16 target_id;
3957 __le64 resp_addr;
3958 __le64 host_dest_addr;
3959 __le16 dir_idx;
3960 u8 unused_0;
3961 u8 unused_1;
3962 __le32 offset;
3963 __le32 len;
3964 __le32 unused_2;
3965 };
3966
3967 /* Output (16 bytes) */
3968 struct hwrm_nvm_read_output {
3969 __le16 error_code;
3970 __le16 req_type;
3971 __le16 seq_id;
3972 __le16 resp_len;
3973 __le32 unused_0;
3974 u8 unused_1;
3975 u8 unused_2;
3976 u8 unused_3;
3977 u8 valid;
3978 };
3979
3980 /* hwrm_nvm_raw_dump */
3981 /* Input (32 bytes) */
3982 struct hwrm_nvm_raw_dump_input {
3983 __le16 req_type;
3984 __le16 cmpl_ring;
3985 __le16 seq_id;
3986 __le16 target_id;
3987 __le64 resp_addr;
3988 __le64 host_dest_addr;
3989 __le32 offset;
3990 __le32 len;
3991 };
3992
3993 /* Output (16 bytes) */
3994 struct hwrm_nvm_raw_dump_output {
3995 __le16 error_code;
3996 __le16 req_type;
3997 __le16 seq_id;
3998 __le16 resp_len;
3999 __le32 unused_0;
4000 u8 unused_1;
4001 u8 unused_2;
4002 u8 unused_3;
4003 u8 valid;
4004 };
4005
4006 /* hwrm_nvm_get_dir_entries */
4007 /* Input (24 bytes) */
4008 struct hwrm_nvm_get_dir_entries_input {
4009 __le16 req_type;
4010 __le16 cmpl_ring;
4011 __le16 seq_id;
4012 __le16 target_id;
4013 __le64 resp_addr;
4014 __le64 host_dest_addr;
4015 };
4016
4017 /* Output (16 bytes) */
4018 struct hwrm_nvm_get_dir_entries_output {
4019 __le16 error_code;
4020 __le16 req_type;
4021 __le16 seq_id;
4022 __le16 resp_len;
4023 __le32 unused_0;
4024 u8 unused_1;
4025 u8 unused_2;
4026 u8 unused_3;
4027 u8 valid;
4028 };
4029
4030 /* hwrm_nvm_get_dir_info */
4031 /* Input (16 bytes) */
4032 struct hwrm_nvm_get_dir_info_input {
4033 __le16 req_type;
4034 __le16 cmpl_ring;
4035 __le16 seq_id;
4036 __le16 target_id;
4037 __le64 resp_addr;
4038 };
4039
4040 /* Output (24 bytes) */
4041 struct hwrm_nvm_get_dir_info_output {
4042 __le16 error_code;
4043 __le16 req_type;
4044 __le16 seq_id;
4045 __le16 resp_len;
4046 __le32 entries;
4047 __le32 entry_length;
4048 __le32 unused_0;
4049 u8 unused_1;
4050 u8 unused_2;
4051 u8 unused_3;
4052 u8 valid;
4053 };
4054
4055 /* hwrm_nvm_write */
4056 /* Input (48 bytes) */
4057 struct hwrm_nvm_write_input {
4058 __le16 req_type;
4059 __le16 cmpl_ring;
4060 __le16 seq_id;
4061 __le16 target_id;
4062 __le64 resp_addr;
4063 __le64 host_src_addr;
4064 __le16 dir_type;
4065 __le16 dir_ordinal;
4066 __le16 dir_ext;
4067 __le16 dir_attr;
4068 __le32 dir_data_length;
4069 __le16 option;
4070 __le16 flags;
4071 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL
4072 __le32 dir_item_length;
4073 __le32 unused_0;
4074 };
4075
4076 /* Output (16 bytes) */
4077 struct hwrm_nvm_write_output {
4078 __le16 error_code;
4079 __le16 req_type;
4080 __le16 seq_id;
4081 __le16 resp_len;
4082 __le32 dir_item_length;
4083 __le16 dir_idx;
4084 u8 unused_0;
4085 u8 valid;
4086 };
4087
4088 /* hwrm_nvm_modify */
4089 /* Input (40 bytes) */
4090 struct hwrm_nvm_modify_input {
4091 __le16 req_type;
4092 __le16 cmpl_ring;
4093 __le16 seq_id;
4094 __le16 target_id;
4095 __le64 resp_addr;
4096 __le64 host_src_addr;
4097 __le16 dir_idx;
4098 u8 unused_0;
4099 u8 unused_1;
4100 __le32 offset;
4101 __le32 len;
4102 __le32 unused_2;
4103 };
4104
4105 /* Output (16 bytes) */
4106 struct hwrm_nvm_modify_output {
4107 __le16 error_code;
4108 __le16 req_type;
4109 __le16 seq_id;
4110 __le16 resp_len;
4111 __le32 unused_0;
4112 u8 unused_1;
4113 u8 unused_2;
4114 u8 unused_3;
4115 u8 valid;
4116 };
4117
4118 /* hwrm_nvm_find_dir_entry */
4119 /* Input (32 bytes) */
4120 struct hwrm_nvm_find_dir_entry_input {
4121 __le16 req_type;
4122 __le16 cmpl_ring;
4123 __le16 seq_id;
4124 __le16 target_id;
4125 __le64 resp_addr;
4126 __le32 enables;
4127 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL
4128 __le16 dir_idx;
4129 __le16 dir_type;
4130 __le16 dir_ordinal;
4131 __le16 dir_ext;
4132 u8 opt_ordinal;
4133 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL
4134 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0
4135 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ (0x0UL << 0)
4136 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE (0x1UL << 0)
4137 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT (0x2UL << 0)
4138 u8 unused_1[3];
4139 };
4140
4141 /* Output (32 bytes) */
4142 struct hwrm_nvm_find_dir_entry_output {
4143 __le16 error_code;
4144 __le16 req_type;
4145 __le16 seq_id;
4146 __le16 resp_len;
4147 __le32 dir_item_length;
4148 __le32 dir_data_length;
4149 __le32 fw_ver;
4150 __le16 dir_ordinal;
4151 __le16 dir_idx;
4152 __le32 unused_0;
4153 u8 unused_1;
4154 u8 unused_2;
4155 u8 unused_3;
4156 u8 valid;
4157 };
4158
4159 /* hwrm_nvm_erase_dir_entry */
4160 /* Input (24 bytes) */
4161 struct hwrm_nvm_erase_dir_entry_input {
4162 __le16 req_type;
4163 __le16 cmpl_ring;
4164 __le16 seq_id;
4165 __le16 target_id;
4166 __le64 resp_addr;
4167 __le16 dir_idx;
4168 __le16 unused_0[3];
4169 };
4170
4171 /* Output (16 bytes) */
4172 struct hwrm_nvm_erase_dir_entry_output {
4173 __le16 error_code;
4174 __le16 req_type;
4175 __le16 seq_id;
4176 __le16 resp_len;
4177 __le32 unused_0;
4178 u8 unused_1;
4179 u8 unused_2;
4180 u8 unused_3;
4181 u8 valid;
4182 };
4183
4184 /* hwrm_nvm_get_dev_info */
4185 /* Input (16 bytes) */
4186 struct hwrm_nvm_get_dev_info_input {
4187 __le16 req_type;
4188 __le16 cmpl_ring;
4189 __le16 seq_id;
4190 __le16 target_id;
4191 __le64 resp_addr;
4192 };
4193
4194 /* Output (32 bytes) */
4195 struct hwrm_nvm_get_dev_info_output {
4196 __le16 error_code;
4197 __le16 req_type;
4198 __le16 seq_id;
4199 __le16 resp_len;
4200 __le16 manufacturer_id;
4201 __le16 device_id;
4202 __le32 sector_size;
4203 __le32 nvram_size;
4204 __le32 reserved_size;
4205 __le32 available_size;
4206 u8 unused_0;
4207 u8 unused_1;
4208 u8 unused_2;
4209 u8 valid;
4210 };
4211
4212 /* hwrm_nvm_mod_dir_entry */
4213 /* Input (32 bytes) */
4214 struct hwrm_nvm_mod_dir_entry_input {
4215 __le16 req_type;
4216 __le16 cmpl_ring;
4217 __le16 seq_id;
4218 __le16 target_id;
4219 __le64 resp_addr;
4220 __le32 enables;
4221 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL
4222 __le16 dir_idx;
4223 __le16 dir_ordinal;
4224 __le16 dir_ext;
4225 __le16 dir_attr;
4226 __le32 checksum;
4227 };
4228
4229 /* Output (16 bytes) */
4230 struct hwrm_nvm_mod_dir_entry_output {
4231 __le16 error_code;
4232 __le16 req_type;
4233 __le16 seq_id;
4234 __le16 resp_len;
4235 __le32 unused_0;
4236 u8 unused_1;
4237 u8 unused_2;
4238 u8 unused_3;
4239 u8 valid;
4240 };
4241
4242 /* hwrm_nvm_verify_update */
4243 /* Input (24 bytes) */
4244 struct hwrm_nvm_verify_update_input {
4245 __le16 req_type;
4246 __le16 cmpl_ring;
4247 __le16 seq_id;
4248 __le16 target_id;
4249 __le64 resp_addr;
4250 __le16 dir_type;
4251 __le16 dir_ordinal;
4252 __le16 dir_ext;
4253 __le16 unused_0;
4254 };
4255
4256 /* Output (16 bytes) */
4257 struct hwrm_nvm_verify_update_output {
4258 __le16 error_code;
4259 __le16 req_type;
4260 __le16 seq_id;
4261 __le16 resp_len;
4262 __le32 unused_0;
4263 u8 unused_1;
4264 u8 unused_2;
4265 u8 unused_3;
4266 u8 valid;
4267 };
4268
4269 #endif
CRIS linux kernel tree