drivers/net/ethernet/cavium/liquidio/octeon_config.h

   1 /**********************************************************************
   2 * Author: Cavium, Inc.
   3 *
   4 * Contact: support@cavium.com
   5 *          Please include "LiquidIO" in the subject.
   6 *
   7 * Copyright (c) 2003-2015 Cavium, Inc.
   8 *
   9 * This file is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License, Version 2, as
  11 * published by the Free Software Foundation.
  12 *
  13 * This file is distributed in the hope that it will be useful, but
  14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16 * NONINFRINGEMENT.  See the GNU General Public License for more
  17 * details.
  18 *
  19 * This file may also be available under a different license from Cavium.
  20 * Contact Cavium, Inc. for more information
  21 **********************************************************************/
  22
  23 /*! \file  octeon_config.h
  24  *  \brief Host Driver: Configuration data structures for the host driver.
  25  */
  26
  27 #ifndef __OCTEON_CONFIG_H__
  28 #define __OCTEON_CONFIG_H__
  29
  30 /*--------------------------CONFIG VALUES------------------------*/
  31
  32 /* The following macros affect the way the driver data structures
  33  * are generated for Octeon devices.
  34  * They can be modified.
  35  */
  36
  37 /* Maximum octeon devices defined as MAX_OCTEON_NICIF to support
  38  * multiple(<= MAX_OCTEON_NICIF) Miniports
  39  */
  40 #define   MAX_OCTEON_NICIF             128
  41 #define   MAX_OCTEON_DEVICES           MAX_OCTEON_NICIF
  42 #define   MAX_OCTEON_LINKS             MAX_OCTEON_NICIF
  43 #define   MAX_OCTEON_MULTICAST_ADDR    32
  44
  45 /* CN6xxx IQ configuration macros */
  46 #define   CN6XXX_MAX_INPUT_QUEUES      32
  47 #define   CN6XXX_MAX_IQ_DESCRIPTORS    2048
  48 #define   CN6XXX_DB_MIN                1
  49 #define   CN6XXX_DB_MAX                8
  50 #define   CN6XXX_DB_TIMEOUT            1
  51
  52 /* CN6xxx OQ configuration macros */
  53 #define   CN6XXX_MAX_OUTPUT_QUEUES     32
  54 #define   CN6XXX_MAX_OQ_DESCRIPTORS    2048
  55 #define   CN6XXX_OQ_BUF_SIZE           1536
  56 #define   CN6XXX_OQ_PKTSPER_INTR       ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \
  57                                         (CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128)
  58 #define   CN6XXX_OQ_REFIL_THRESHOLD    ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \
  59                                         (CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128)
  60
  61 #define   CN6XXX_OQ_INTR_PKT           64
  62 #define   CN6XXX_OQ_INTR_TIME          100
  63 #define   DEFAULT_NUM_NIC_PORTS_66XX   2
  64 #define   DEFAULT_NUM_NIC_PORTS_68XX   4
  65 #define   DEFAULT_NUM_NIC_PORTS_68XX_210NV  2
  66
  67 /* common OCTEON configuration macros */
  68 #define   CN6XXX_CFG_IO_QUEUES         32
  69 #define   OCTEON_32BYTE_INSTR          32
  70 #define   OCTEON_64BYTE_INSTR          64
  71 #define   OCTEON_MAX_BASE_IOQ          4
  72 #define   OCTEON_OQ_BUFPTR_MODE        0
  73 #define   OCTEON_OQ_INFOPTR_MODE       1
  74
  75 #define   OCTEON_DMA_INTR_PKT          64
  76 #define   OCTEON_DMA_INTR_TIME         1000
  77
  78 #define MAX_TXQS_PER_INTF  8
  79 #define MAX_RXQS_PER_INTF  8
  80 #define DEF_TXQS_PER_INTF  4
  81 #define DEF_RXQS_PER_INTF  4
  82
  83 #define INVALID_IOQ_NO          0xff
  84
  85 #define   DEFAULT_POW_GRP       0
  86
  87 /* Macros to get octeon config params */
  88 #define CFG_GET_IQ_CFG(cfg)                      ((cfg)->iq)
  89 #define CFG_GET_IQ_MAX_Q(cfg)                    ((cfg)->iq.max_iqs)
  90 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg)        ((cfg)->iq.pending_list_size)
  91 #define CFG_GET_IQ_INSTR_TYPE(cfg)               ((cfg)->iq.instr_type)
  92 #define CFG_GET_IQ_DB_MIN(cfg)                   ((cfg)->iq.db_min)
  93 #define CFG_GET_IQ_DB_TIMEOUT(cfg)               ((cfg)->iq.db_timeout)
  94
  95 #define CFG_GET_OQ_MAX_Q(cfg)                    ((cfg)->oq.max_oqs)
  96 #define CFG_GET_OQ_INFO_PTR(cfg)                 ((cfg)->oq.info_ptr)
  97 #define CFG_GET_OQ_PKTS_PER_INTR(cfg)            ((cfg)->oq.pkts_per_intr)
  98 #define CFG_GET_OQ_REFILL_THRESHOLD(cfg)         ((cfg)->oq.refill_threshold)
  99 #define CFG_GET_OQ_INTR_PKT(cfg)                 ((cfg)->oq.oq_intr_pkt)
 100 #define CFG_GET_OQ_INTR_TIME(cfg)                ((cfg)->oq.oq_intr_time)
 101 #define CFG_SET_OQ_INTR_PKT(cfg, val)            (cfg)->oq.oq_intr_pkt = val
 102 #define CFG_SET_OQ_INTR_TIME(cfg, val)           (cfg)->oq.oq_intr_time = val
 103
 104 #define CFG_GET_DMA_INTR_PKT(cfg)                ((cfg)->dma.dma_intr_pkt)
 105 #define CFG_GET_DMA_INTR_TIME(cfg)               ((cfg)->dma.dma_intr_time)
 106 #define CFG_GET_NUM_NIC_PORTS(cfg)               ((cfg)->num_nic_ports)
 107 #define CFG_GET_NUM_DEF_TX_DESCS(cfg)            ((cfg)->num_def_tx_descs)
 108 #define CFG_GET_NUM_DEF_RX_DESCS(cfg)            ((cfg)->num_def_rx_descs)
 109 #define CFG_GET_DEF_RX_BUF_SIZE(cfg)             ((cfg)->def_rx_buf_size)
 110
 111 #define CFG_GET_MAX_TXQS_NIC_IF(cfg, idx) \
 112                                 ((cfg)->nic_if_cfg[idx].max_txqs)
 113 #define CFG_GET_NUM_TXQS_NIC_IF(cfg, idx) \
 114                                 ((cfg)->nic_if_cfg[idx].num_txqs)
 115 #define CFG_GET_MAX_RXQS_NIC_IF(cfg, idx) \
 116                                 ((cfg)->nic_if_cfg[idx].max_rxqs)
 117 #define CFG_GET_NUM_RXQS_NIC_IF(cfg, idx) \
 118                                 ((cfg)->nic_if_cfg[idx].num_rxqs)
 119 #define CFG_GET_NUM_RX_DESCS_NIC_IF(cfg, idx) \
 120                                 ((cfg)->nic_if_cfg[idx].num_rx_descs)
 121 #define CFG_GET_NUM_TX_DESCS_NIC_IF(cfg, idx) \
 122                                 ((cfg)->nic_if_cfg[idx].num_tx_descs)
 123 #define CFG_GET_NUM_RX_BUF_SIZE_NIC_IF(cfg, idx) \
 124                                 ((cfg)->nic_if_cfg[idx].rx_buf_size)
 125 #define CFG_GET_BASE_QUE_NIC_IF(cfg, idx) \
 126                                 ((cfg)->nic_if_cfg[idx].base_queue)
 127 #define CFG_GET_GMXID_NIC_IF(cfg, idx) \
 128                                 ((cfg)->nic_if_cfg[idx].gmx_port_id)
 129
 130 #define CFG_GET_CTRL_Q_GRP(cfg)                  ((cfg)->misc.ctrlq_grp)
 131 #define CFG_GET_HOST_LINK_QUERY_INTERVAL(cfg) \
 132                                 ((cfg)->misc.host_link_query_interval)
 133 #define CFG_GET_OCT_LINK_QUERY_INTERVAL(cfg) \
 134                                 ((cfg)->misc.oct_link_query_interval)
 135 #define CFG_GET_IS_SLI_BP_ON(cfg)                ((cfg)->misc.enable_sli_oq_bp)
 136
 137 /* Max IOQs per OCTEON Link */
 138 #define MAX_IOQS_PER_NICIF              64
 139
 140 enum lio_card_type {
 141         LIO_210SV = 0, /* Two port, 66xx */
 142         LIO_210NV,     /* Two port, 68xx */
 143         LIO_410NV      /* Four port, 68xx */
 144 };
 145
 146 #define LIO_210SV_NAME "210sv"
 147 #define LIO_210NV_NAME "210nv"
 148 #define LIO_410NV_NAME "410nv"
 149
 150 /** Structure to define the configuration attributes for each Input queue.
 151  *  Applicable to all Octeon processors
 152  **/
 153 struct octeon_iq_config {
 154 #ifdef __BIG_ENDIAN_BITFIELD
 155         u64 reserved:32;
 156
 157         /** Minimum ticks to wait before checking for pending instructions. */
 158         u64 db_timeout:16;
 159
 160         /** Minimum number of commands pending to be posted to Octeon
 161          *  before driver hits the Input queue doorbell.
 162          */
 163         u64 db_min:8;
 164
 165         /** Command size - 32 or 64 bytes */
 166         u64 instr_type:32;
 167
 168         /** Pending list size (usually set to the sum of the size of all Input
 169          *  queues)
 170          */
 171         u64 pending_list_size:32;
 172
 173         /* Max number of IQs available */
 174         u64 max_iqs:8;
 175 #else
 176         /* Max number of IQs available */
 177         u64 max_iqs:8;
 178
 179         /** Pending list size (usually set to the sum of the size of all Input
 180          *  queues)
 181          */
 182         u64 pending_list_size:32;
 183
 184         /** Command size - 32 or 64 bytes */
 185         u64 instr_type:32;
 186
 187         /** Minimum number of commands pending to be posted to Octeon
 188          *  before driver hits the Input queue doorbell.
 189          */
 190         u64 db_min:8;
 191
 192         /** Minimum ticks to wait before checking for pending instructions. */
 193         u64 db_timeout:16;
 194
 195         u64 reserved:32;
 196 #endif
 197 };
 198
 199 /** Structure to define the configuration attributes for each Output queue.
 200  *  Applicable to all Octeon processors
 201  **/
 202 struct octeon_oq_config {
 203 #ifdef __BIG_ENDIAN_BITFIELD
 204         u64 reserved:16;
 205
 206         u64 pkts_per_intr:16;
 207
 208         /** Interrupt Coalescing (Time Interval). Octeon will interrupt the
 209          *  host if atleast one packet was sent in the time interval specified
 210          *  by this field. The driver uses time interval interrupt coalescing
 211          *  by default. The time is specified in microseconds.
 212          */
 213         u64 oq_intr_time:16;
 214
 215         /** Interrupt Coalescing (Packet Count). Octeon will interrupt the host
 216          *  only if it sent as many packets as specified by this field.
 217          *  The driver
 218          *  usually does not use packet count interrupt coalescing.
 219          */
 220         u64 oq_intr_pkt:16;
 221
 222         /** The number of buffers that were consumed during packet processing by
 223          *   the driver on this Output queue before the driver attempts to
 224          *   replenish
 225          *   the descriptor ring with new buffers.
 226          */
 227         u64 refill_threshold:16;
 228
 229         /** If set, the Output queue uses info-pointer mode. (Default: 1) */
 230         u64 info_ptr:32;
 231
 232         /* Max number of OQs available */
 233         u64 max_oqs:8;
 234
 235 #else
 236         /* Max number of OQs available */
 237         u64 max_oqs:8;
 238
 239         /** If set, the Output queue uses info-pointer mode. (Default: 1) */
 240         u64 info_ptr:32;
 241
 242         /** The number of buffers that were consumed during packet processing by
 243          *   the driver on this Output queue before the driver attempts to
 244          *   replenish
 245          *   the descriptor ring with new buffers.
 246          */
 247         u64 refill_threshold:16;
 248
 249         /** Interrupt Coalescing (Packet Count). Octeon will interrupt the host
 250          *  only if it sent as many packets as specified by this field.
 251          *  The driver
 252          *  usually does not use packet count interrupt coalescing.
 253          */
 254         u64 oq_intr_pkt:16;
 255
 256         /** Interrupt Coalescing (Time Interval). Octeon will interrupt the
 257          *  host if atleast one packet was sent in the time interval specified
 258          *  by this field. The driver uses time interval interrupt coalescing
 259          *  by default.  The time is specified in microseconds.
 260          */
 261         u64 oq_intr_time:16;
 262
 263         u64 pkts_per_intr:16;
 264
 265         u64 reserved:16;
 266 #endif
 267
 268 };
 269
 270 /** This structure conatins the NIC link configuration attributes,
 271  *  common for all the OCTEON Modles.
 272  */
 273 struct octeon_nic_if_config {
 274 #ifdef __BIG_ENDIAN_BITFIELD
 275         u64 reserved:56;
 276
 277         u64 base_queue:16;
 278
 279         u64 gmx_port_id:8;
 280
 281         /* SKB size, We need not change buf size even for Jumbo frames.
 282          * Octeon can send jumbo frames in 4 consecutive descriptors,
 283          */
 284         u64 rx_buf_size:16;
 285
 286         /* Num of desc for tx rings */
 287         u64 num_tx_descs:16;
 288
 289         /* Num of desc for rx rings */
 290         u64 num_rx_descs:16;
 291
 292         /* Actual configured value. Range could be: 1...max_rxqs */
 293         u64 num_rxqs:16;
 294
 295         /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 296         u64 max_rxqs:16;
 297
 298         /* Actual configured value. Range could be: 1...max_txqs */
 299         u64 num_txqs:16;
 300
 301         /* Max Txqs: Half for each of the two ports :max_iq/2 */
 302         u64 max_txqs:16;
 303 #else
 304         /* Max Txqs: Half for each of the two ports :max_iq/2 */
 305         u64 max_txqs:16;
 306
 307         /* Actual configured value. Range could be: 1...max_txqs */
 308         u64 num_txqs:16;
 309
 310         /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 311         u64 max_rxqs:16;
 312
 313         /* Actual configured value. Range could be: 1...max_rxqs */
 314         u64 num_rxqs:16;
 315
 316         /* Num of desc for rx rings */
 317         u64 num_rx_descs:16;
 318
 319         /* Num of desc for tx rings */
 320         u64 num_tx_descs:16;
 321
 322         /* SKB size, We need not change buf size even for Jumbo frames.
 323          * Octeon can send jumbo frames in 4 consecutive descriptors,
 324          */
 325         u64 rx_buf_size:16;
 326
 327         u64 gmx_port_id:8;
 328
 329         u64 base_queue:16;
 330
 331         u64 reserved:56;
 332 #endif
 333
 334 };
 335
 336 /** Structure to define the configuration attributes for meta data.
 337  *  Applicable to all Octeon processors.
 338  */
 339
 340 struct octeon_misc_config {
 341 #ifdef __BIG_ENDIAN_BITFIELD
 342         /** Host link status polling period */
 343         u64 host_link_query_interval:32;
 344         /** Oct link status polling period */
 345         u64 oct_link_query_interval:32;
 346
 347         u64 enable_sli_oq_bp:1;
 348         /** Control IQ Group */
 349         u64 ctrlq_grp:4;
 350 #else
 351         /** Control IQ Group */
 352         u64 ctrlq_grp:4;
 353         /** BP for SLI OQ */
 354         u64 enable_sli_oq_bp:1;
 355         /** Host link status polling period */
 356         u64 oct_link_query_interval:32;
 357         /** Oct link status polling period */
 358         u64 host_link_query_interval:32;
 359 #endif
 360 };
 361
 362 /** Structure to define the configuration for all OCTEON processors. */
 363 struct octeon_config {
 364         u16 card_type;
 365         char *card_name;
 366
 367         /** Input Queue attributes. */
 368         struct octeon_iq_config iq;
 369
 370         /** Output Queue attributes. */
 371         struct octeon_oq_config oq;
 372
 373         /** NIC Port Configuration */
 374         struct octeon_nic_if_config nic_if_cfg[MAX_OCTEON_NICIF];
 375
 376         /** Miscellaneous attributes */
 377         struct octeon_misc_config misc;
 378
 379         int num_nic_ports;
 380
 381         int num_def_tx_descs;
 382
 383         /* Num of desc for rx rings */
 384         int num_def_rx_descs;
 385
 386         int def_rx_buf_size;
 387
 388 };
 389
 390 /* The following config values are fixed and should not be modified. */
 391
 392 /* Maximum address space to be mapped for Octeon's BAR1 index-based access. */
 393 #define  MAX_BAR1_MAP_INDEX                     2
 394 #define  OCTEON_BAR1_ENTRY_SIZE         (4 * 1024 * 1024)
 395
 396 /* BAR1 Index 0 to (MAX_BAR1_MAP_INDEX - 1) for normal mapped memory access.
 397  * Bar1 register at MAX_BAR1_MAP_INDEX used by driver for dynamic access.
 398  */
 399 #define  MAX_BAR1_IOREMAP_SIZE  ((MAX_BAR1_MAP_INDEX + 1) * \
 400                                  OCTEON_BAR1_ENTRY_SIZE)
 401
 402 /* Response lists - 1 ordered, 1 unordered-blocking, 1 unordered-nonblocking
 403  * NoResponse Lists are now maintained with each IQ. (Dec' 2007).
 404  */
 405 #define MAX_RESPONSE_LISTS           4
 406
 407 /* Opcode hash bits. The opcode is hashed on the lower 6-bits to lookup the
 408  * dispatch table.
 409  */
 410 #define OPCODE_MASK_BITS             6
 411
 412 /* Mask for the 6-bit lookup hash */
 413 #define OCTEON_OPCODE_MASK           0x3f
 414
 415 /* Size of the dispatch table. The 6-bit hash can index into 2^6 entries */
 416 #define DISPATCH_LIST_SIZE                      BIT(OPCODE_MASK_BITS)
 417
 418 /* Maximum number of Octeon Instruction (command) queues */
 419 #define MAX_OCTEON_INSTR_QUEUES(oct)         CN6XXX_MAX_INPUT_QUEUES
 420 /* Maximum number of Octeon Output queues */
 421 #define MAX_OCTEON_OUTPUT_QUEUES(oct)         CN6XXX_MAX_OUTPUT_QUEUES
 422
 423 #define MAX_POSSIBLE_OCTEON_INSTR_QUEUES       CN6XXX_MAX_INPUT_QUEUES
 424 #define MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES      CN6XXX_MAX_OUTPUT_QUEUES
 425
 426 #endif /* __OCTEON_CONFIG_H__  */