drivers/net/ethernet/cavium/liquidio/octeon_iq.h

   1 /**********************************************************************
   2  * Author: Cavium, Inc.
   3  *
   4  * Contact: support@cavium.com
   5  *          Please include "LiquidIO" in the subject.
   6  *
   7  * Copyright (c) 2003-2015 Cavium, Inc.
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * This file may also be available under a different license from Cavium.
  20  * Contact Cavium, Inc. for more information
  21  **********************************************************************/
  22
  23 /*!  \file  octeon_iq.h
  24  *   \brief Host Driver: Implementation of Octeon input queues. "Input" is
  25  *   with respect to the Octeon device on the NIC. From this driver's
  26  *   point of view they are egress queues.
  27  */
  28
  29 #ifndef __OCTEON_IQ_H__
  30 #define  __OCTEON_IQ_H__
  31
  32 #define IQ_STATUS_RUNNING   1
  33
  34 #define IQ_SEND_OK          0
  35 #define IQ_SEND_STOP        1
  36 #define IQ_SEND_FAILED     -1
  37
  38 /*-------------------------  INSTRUCTION QUEUE --------------------------*/
  39
  40 /* \cond */
  41
  42 #define REQTYPE_NONE                 0
  43 #define REQTYPE_NORESP_NET           1
  44 #define REQTYPE_NORESP_NET_SG        2
  45 #define REQTYPE_RESP_NET             3
  46 #define REQTYPE_RESP_NET_SG          4
  47 #define REQTYPE_SOFT_COMMAND         5
  48 #define REQTYPE_LAST                 5
  49
  50 struct octeon_request_list {
  51         u32 reqtype;
  52         void *buf;
  53 };
  54
  55 /* \endcond */
  56
  57 /** Input Queue statistics. Each input queue has four stats fields. */
  58 struct oct_iq_stats {
  59         u64 instr_posted; /**< Instructions posted to this queue. */
  60         u64 instr_processed; /**< Instructions processed in this queue. */
  61         u64 instr_dropped; /**< Instructions that could not be processed */
  62         u64 bytes_sent;  /**< Bytes sent through this queue. */
  63         u64 sgentry_sent;/**< Gather entries sent through this queue. */
  64         u64 tx_done;/**< Num of packets sent to network. */
  65         u64 tx_iq_busy;/**< Numof times this iq was found to be full. */
  66         u64 tx_dropped;/**< Numof pkts dropped dueto xmitpath errors. */
  67         u64 tx_tot_bytes;/**< Total count of bytes sento to network. */
  68         u64 tx_gso;  /* count of tso */
  69         u64 tx_vxlan; /* tunnel */
  70         u64 tx_dmamap_fail;
  71         u64 tx_restart;
  72         /*u64 tx_timeout_count;*/
  73 };
  74
  75 #define OCT_IQ_STATS_SIZE   (sizeof(struct oct_iq_stats))
  76
  77 /** The instruction (input) queue.
  78  *  The input queue is used to post raw (instruction) mode data or packet
  79  *  data to Octeon device from the host. Each input queue (upto 4) for
  80  *  a Octeon device has one such structure to represent it.
  81 */
  82 struct octeon_instr_queue {
  83         struct octeon_device *oct_dev;
  84
  85         /** A spinlock to protect access to the input ring.  */
  86         spinlock_t lock;
  87
  88         /** A spinlock to protect while posting on the ring.  */
  89         spinlock_t post_lock;
  90
  91         /** A spinlock to protect access to the input ring.*/
  92         spinlock_t iq_flush_running_lock;
  93
  94         /** Flag that indicates if the queue uses 64 byte commands. */
  95         u32 iqcmd_64B:1;
  96
  97         /** Queue info. */
  98         union oct_txpciq txpciq;
  99
 100         u32 rsvd:17;
 101
 102         /* Controls whether extra flushing of IQ is done on Tx */
 103         u32 do_auto_flush:1;
 104
 105         u32 status:8;
 106
 107         /** Maximum no. of instructions in this queue. */
 108         u32 max_count;
 109
 110         /** Index in input ring where the driver should write the next packet */
 111         u32 host_write_index;
 112
 113         /** Index in input ring where Octeon is expected to read the next
 114          * packet.
 115          */
 116         u32 octeon_read_index;
 117
 118         /** This index aids in finding the window in the queue where Octeon
 119           * has read the commands.
 120           */
 121         u32 flush_index;
 122
 123         /** This field keeps track of the instructions pending in this queue. */
 124         atomic_t instr_pending;
 125
 126         u32 reset_instr_cnt;
 127
 128         /** Pointer to the Virtual Base addr of the input ring. */
 129         u8 *base_addr;
 130
 131         struct octeon_request_list *request_list;
 132
 133         /** Octeon doorbell register for the ring. */
 134         void __iomem *doorbell_reg;
 135
 136         /** Octeon instruction count register for this ring. */
 137         void __iomem *inst_cnt_reg;
 138
 139         /** Number of instructions pending to be posted to Octeon. */
 140         u32 fill_cnt;
 141
 142         /** The max. number of instructions that can be held pending by the
 143          * driver.
 144          */
 145         u32 fill_threshold;
 146
 147         /** The last time that the doorbell was rung. */
 148         u64 last_db_time;
 149
 150         /** The doorbell timeout. If the doorbell was not rung for this time and
 151           * fill_cnt is non-zero, ring the doorbell again.
 152           */
 153         u32 db_timeout;
 154
 155         /** Statistics for this input queue. */
 156         struct oct_iq_stats stats;
 157
 158         /** DMA mapped base address of the input descriptor ring. */
 159         u64 base_addr_dma;
 160
 161         /** Application context */
 162         void *app_ctx;
 163
 164         /* network stack queue index */
 165         int q_index;
 166
 167         /*os ifidx associated with this queue */
 168         int ifidx;
 169
 170 };
 171
 172 /*----------------------  INSTRUCTION FORMAT ----------------------------*/
 173
 174 /** 32-byte instruction format.
 175  *  Format of instruction for a 32-byte mode input queue.
 176  */
 177 struct octeon_instr_32B {
 178         /** Pointer where the input data is available. */
 179         u64 dptr;
 180
 181         /** Instruction Header.  */
 182         u64 ih;
 183
 184         /** Pointer where the response for a RAW mode packet will be written
 185          * by Octeon.
 186          */
 187         u64 rptr;
 188
 189         /** Input Request Header. Additional info about the input. */
 190         u64 irh;
 191
 192 };
 193
 194 #define OCT_32B_INSTR_SIZE     (sizeof(struct octeon_instr_32B))
 195
 196 /** 64-byte instruction format.
 197  *  Format of instruction for a 64-byte mode input queue.
 198  */
 199 struct octeon_instr2_64B {
 200         /** Pointer where the input data is available. */
 201         u64 dptr;
 202
 203         /** Instruction Header. */
 204         u64 ih2;
 205
 206         /** Input Request Header. */
 207         u64 irh;
 208
 209         /** opcode/subcode specific parameters */
 210         u64 ossp[2];
 211
 212         /** Return Data Parameters */
 213         u64 rdp;
 214
 215         /** Pointer where the response for a RAW mode packet will be written
 216          * by Octeon.
 217          */
 218         u64 rptr;
 219
 220         u64 reserved;
 221 };
 222
 223 struct octeon_instr3_64B {
 224         /** Pointer where the input data is available. */
 225         u64 dptr;
 226
 227         /** Instruction Header. */
 228         u64 ih3;
 229
 230         /** Instruction Header. */
 231         u64 pki_ih3;
 232
 233         /** Input Request Header. */
 234         u64 irh;
 235
 236         /** opcode/subcode specific parameters */
 237         u64 ossp[2];
 238
 239         /** Return Data Parameters */
 240         u64 rdp;
 241
 242         /** Pointer where the response for a RAW mode packet will be written
 243          * by Octeon.
 244          */
 245         u64 rptr;
 246
 247 };
 248
 249 union octeon_instr_64B {
 250         struct octeon_instr2_64B cmd2;
 251         struct octeon_instr3_64B cmd3;
 252 };
 253
 254 #define OCT_64B_INSTR_SIZE     (sizeof(union octeon_instr_64B))
 255
 256 /** The size of each buffer in soft command buffer pool
 257  */
 258 #define  SOFT_COMMAND_BUFFER_SIZE       1536
 259
 260 struct octeon_soft_command {
 261         /** Soft command buffer info. */
 262         struct list_head node;
 263         u64 dma_addr;
 264         u32 size;
 265
 266         /** Command and return status */
 267         union octeon_instr_64B cmd;
 268
 269 #define COMPLETION_WORD_INIT    0xffffffffffffffffULL
 270         u64 *status_word;
 271
 272         /** Data buffer info */
 273         void *virtdptr;
 274         u64 dmadptr;
 275         u32 datasize;
 276
 277         /** Return buffer info */
 278         void *virtrptr;
 279         u64 dmarptr;
 280         u32 rdatasize;
 281
 282         /** Context buffer info */
 283         void *ctxptr;
 284         u32  ctxsize;
 285
 286         /** Time out and callback */
 287         size_t wait_time;
 288         size_t timeout;
 289         u32 iq_no;
 290         void (*callback)(struct octeon_device *, u32, void *);
 291         void *callback_arg;
 292 };
 293
 294 /** Maximum number of buffers to allocate into soft command buffer pool
 295  */
 296 #define  MAX_SOFT_COMMAND_BUFFERS       256
 297
 298 /** Head of a soft command buffer pool.
 299  */
 300 struct octeon_sc_buffer_pool {
 301         /** List structure to add delete pending entries to */
 302         struct list_head head;
 303
 304         /** A lock for this response list */
 305         spinlock_t lock;
 306
 307         atomic_t alloc_buf_count;
 308 };
 309
 310 int octeon_setup_sc_buffer_pool(struct octeon_device *oct);
 311 int octeon_free_sc_buffer_pool(struct octeon_device *oct);
 312 struct octeon_soft_command *
 313         octeon_alloc_soft_command(struct octeon_device *oct,
 314                                   u32 datasize, u32 rdatasize,
 315                                   u32 ctxsize);
 316 void octeon_free_soft_command(struct octeon_device *oct,
 317                               struct octeon_soft_command *sc);
 318
 319 /**
 320  *  octeon_init_instr_queue()
 321  *  @param octeon_dev      - pointer to the octeon device structure.
 322  *  @param txpciq          - queue to be initialized (0 <= q_no <= 3).
 323  *
 324  *  Called at driver init time for each input queue. iq_conf has the
 325  *  configuration parameters for the queue.
 326  *
 327  *  @return  Success: 0   Failure: 1
 328  */
 329 int octeon_init_instr_queue(struct octeon_device *octeon_dev,
 330                             union oct_txpciq txpciq,
 331                             u32 num_descs);
 332
 333 /**
 334  *  octeon_delete_instr_queue()
 335  *  @param octeon_dev      - pointer to the octeon device structure.
 336  *  @param iq_no           - queue to be deleted (0 <= q_no <= 3).
 337  *
 338  *  Called at driver unload time for each input queue. Deletes all
 339  *  allocated resources for the input queue.
 340  *
 341  *  @return  Success: 0   Failure: 1
 342  */
 343 int octeon_delete_instr_queue(struct octeon_device *octeon_dev, u32 iq_no);
 344
 345 int lio_wait_for_instr_fetch(struct octeon_device *oct);
 346
 347 int
 348 octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype,
 349                                 void (*fn)(void *));
 350
 351 int
 352 lio_process_iq_request_list(struct octeon_device *oct,
 353                             struct octeon_instr_queue *iq, u32 napi_budget);
 354
 355 int octeon_send_command(struct octeon_device *oct, u32 iq_no,
 356                         u32 force_db, void *cmd, void *buf,
 357                         u32 datasize, u32 reqtype);
 358
 359 void octeon_prepare_soft_command(struct octeon_device *oct,
 360                                  struct octeon_soft_command *sc,
 361                                  u8 opcode, u8 subcode,
 362                                  u32 irh_ossp, u64 ossp0,
 363                                  u64 ossp1);
 364
 365 int octeon_send_soft_command(struct octeon_device *oct,
 366                              struct octeon_soft_command *sc);
 367
 368 int octeon_setup_iq(struct octeon_device *oct, int ifidx,
 369                     int q_index, union oct_txpciq iq_no, u32 num_descs,
 370                     void *app_ctx);
 371 int
 372 octeon_flush_iq(struct octeon_device *oct, struct octeon_instr_queue *iq,
 373                 u32 pending_thresh, u32 napi_budget);
 374 #endif                          /* __OCTEON_IQ_H__ */